if_msk.c revision 1.73
1 /* $NetBSD: if_msk.c,v 1.73 2018/07/10 18:34:42 jdolecek Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.79 2009/10/15 17:54:56 deraadt Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.73 2018/07/10 18:34:42 jdolecek Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/mutex.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/device.h> 66 #include <sys/queue.h> 67 #include <sys/callout.h> 68 #include <sys/sysctl.h> 69 #include <sys/endian.h> 70 #ifdef __NetBSD__ 71 #define letoh16 htole16 72 #define letoh32 htole32 73 #endif 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #include <net/if_media.h> 80 81 #include <net/bpf.h> 82 #include <sys/rndsource.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 #include <dev/mii/brgphyreg.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 92 #include <dev/pci/if_skreg.h> 93 #include <dev/pci/if_mskvar.h> 94 95 int mskc_probe(device_t, cfdata_t, void *); 96 void mskc_attach(device_t, device_t, void *); 97 int mskc_detach(device_t, int); 98 void mskc_reset(struct sk_softc *); 99 static bool mskc_suspend(device_t, const pmf_qual_t *); 100 static bool mskc_resume(device_t, const pmf_qual_t *); 101 int msk_probe(device_t, cfdata_t, void *); 102 void msk_attach(device_t, device_t, void *); 103 int msk_detach(device_t, int); 104 void msk_reset(struct sk_if_softc *); 105 int mskcprint(void *, const char *); 106 int msk_intr(void *); 107 void msk_intr_yukon(struct sk_if_softc *); 108 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 109 void msk_txeof(struct sk_if_softc *); 110 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 111 void msk_start(struct ifnet *); 112 int msk_ioctl(struct ifnet *, u_long, void *); 113 int msk_init(struct ifnet *); 114 void msk_init_yukon(struct sk_if_softc *); 115 void msk_stop(struct ifnet *, int); 116 void msk_watchdog(struct ifnet *); 117 int msk_newbuf(struct sk_if_softc *, bus_dmamap_t); 118 int msk_alloc_jumbo_mem(struct sk_if_softc *); 119 void *msk_jalloc(struct sk_if_softc *); 120 void msk_jfree(struct mbuf *, void *, size_t, void *); 121 int msk_init_rx_ring(struct sk_if_softc *); 122 int msk_init_tx_ring(struct sk_if_softc *); 123 void msk_fill_rx_ring(struct sk_if_softc *); 124 125 void msk_update_int_mod(struct sk_softc *, int); 126 127 int msk_miibus_readreg(device_t, int, int); 128 void msk_miibus_writereg(device_t, int, int, int); 129 void msk_miibus_statchg(struct ifnet *); 130 131 void msk_setmulti(struct sk_if_softc *); 132 void msk_setpromisc(struct sk_if_softc *); 133 void msk_tick(void *); 134 static void msk_fill_rx_tick(void *); 135 136 /* #define MSK_DEBUG 1 */ 137 #ifdef MSK_DEBUG 138 #define DPRINTF(x) if (mskdebug) printf x 139 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 140 int mskdebug = MSK_DEBUG; 141 142 void msk_dump_txdesc(struct msk_tx_desc *, int); 143 void msk_dump_mbuf(struct mbuf *); 144 void msk_dump_bytes(const char *, int); 145 #else 146 #define DPRINTF(x) 147 #define DPRINTFN(n,x) 148 #endif 149 150 static int msk_sysctl_handler(SYSCTLFN_PROTO); 151 static int msk_root_num; 152 153 /* supported device vendors */ 154 static const struct msk_product { 155 pci_vendor_id_t msk_vendor; 156 pci_product_id_t msk_product; 157 } msk_products[] = { 158 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 159 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 160 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 162 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 163 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8079 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 197 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 198 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 } 199 }; 200 201 static inline u_int32_t 202 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 203 { 204 return CSR_READ_4(sc, reg); 205 } 206 207 static inline u_int16_t 208 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 209 { 210 return CSR_READ_2(sc, reg); 211 } 212 213 static inline u_int8_t 214 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 215 { 216 return CSR_READ_1(sc, reg); 217 } 218 219 static inline void 220 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 221 { 222 CSR_WRITE_4(sc, reg, x); 223 } 224 225 static inline void 226 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 227 { 228 CSR_WRITE_2(sc, reg, x); 229 } 230 231 static inline void 232 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 233 { 234 CSR_WRITE_1(sc, reg, x); 235 } 236 237 int 238 msk_miibus_readreg(device_t dev, int phy, int reg) 239 { 240 struct sk_if_softc *sc_if = device_private(dev); 241 u_int16_t val; 242 int i; 243 244 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 245 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 246 247 for (i = 0; i < SK_TIMEOUT; i++) { 248 DELAY(1); 249 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 250 if (val & YU_SMICR_READ_VALID) 251 break; 252 } 253 254 if (i == SK_TIMEOUT) { 255 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 256 return (0); 257 } 258 259 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 260 SK_TIMEOUT)); 261 262 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 263 264 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 265 phy, reg, val)); 266 267 return (val); 268 } 269 270 void 271 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 272 { 273 struct sk_if_softc *sc_if = device_private(dev); 274 int i; 275 276 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 277 phy, reg, val)); 278 279 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 280 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 281 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 282 283 for (i = 0; i < SK_TIMEOUT; i++) { 284 DELAY(1); 285 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 286 break; 287 } 288 289 if (i == SK_TIMEOUT) 290 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 291 } 292 293 void 294 msk_miibus_statchg(struct ifnet *ifp) 295 { 296 struct sk_if_softc *sc_if = ifp->if_softc; 297 struct mii_data *mii = &sc_if->sk_mii; 298 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 299 int gpcr; 300 301 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 302 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 303 304 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 305 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 306 /* Set speed. */ 307 gpcr |= YU_GPCR_SPEED_DIS; 308 switch (IFM_SUBTYPE(mii->mii_media_active)) { 309 case IFM_1000_SX: 310 case IFM_1000_LX: 311 case IFM_1000_CX: 312 case IFM_1000_T: 313 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 314 break; 315 case IFM_100_TX: 316 gpcr |= YU_GPCR_SPEED; 317 break; 318 } 319 320 /* Set duplex. */ 321 gpcr |= YU_GPCR_DPLX_DIS; 322 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 323 gpcr |= YU_GPCR_DUPLEX; 324 325 /* Disable flow control. */ 326 gpcr |= YU_GPCR_FCTL_DIS; 327 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 328 } 329 330 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 331 332 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 333 SK_YU_READ_2(sc_if, YUKON_GPCR))); 334 } 335 336 void 337 msk_setmulti(struct sk_if_softc *sc_if) 338 { 339 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 340 u_int32_t hashes[2] = { 0, 0 }; 341 int h; 342 struct ethercom *ec = &sc_if->sk_ethercom; 343 struct ether_multi *enm; 344 struct ether_multistep step; 345 u_int16_t reg; 346 347 /* First, zot all the existing filters. */ 348 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 349 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 350 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 351 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 352 353 354 /* Now program new ones. */ 355 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 356 reg |= YU_RCR_UFLEN; 357 allmulti: 358 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 359 if ((ifp->if_flags & IFF_PROMISC) != 0) 360 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 361 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 362 hashes[0] = 0xFFFFFFFF; 363 hashes[1] = 0xFFFFFFFF; 364 } 365 } else { 366 /* First find the tail of the list. */ 367 ETHER_FIRST_MULTI(step, ec, enm); 368 while (enm != NULL) { 369 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 370 ETHER_ADDR_LEN)) { 371 ifp->if_flags |= IFF_ALLMULTI; 372 goto allmulti; 373 } 374 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 375 ((1 << SK_HASH_BITS) - 1); 376 if (h < 32) 377 hashes[0] |= (1 << h); 378 else 379 hashes[1] |= (1 << (h - 32)); 380 381 ETHER_NEXT_MULTI(step, enm); 382 } 383 reg |= YU_RCR_MUFLEN; 384 } 385 386 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 387 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 388 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 389 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 390 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 391 } 392 393 void 394 msk_setpromisc(struct sk_if_softc *sc_if) 395 { 396 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 397 398 if (ifp->if_flags & IFF_PROMISC) 399 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 400 YU_RCR_UFLEN | YU_RCR_MUFLEN); 401 else 402 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 403 YU_RCR_UFLEN | YU_RCR_MUFLEN); 404 } 405 406 int 407 msk_init_rx_ring(struct sk_if_softc *sc_if) 408 { 409 struct msk_chain_data *cd = &sc_if->sk_cdata; 410 struct msk_ring_data *rd = sc_if->sk_rdata; 411 int i, nexti; 412 413 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 414 415 for (i = 0; i < MSK_RX_RING_CNT; i++) { 416 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 417 if (i == (MSK_RX_RING_CNT - 1)) 418 nexti = 0; 419 else 420 nexti = i + 1; 421 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 422 } 423 424 sc_if->sk_cdata.sk_rx_prod = 0; 425 sc_if->sk_cdata.sk_rx_cons = 0; 426 sc_if->sk_cdata.sk_rx_cnt = 0; 427 428 msk_fill_rx_ring(sc_if); 429 return (0); 430 } 431 432 int 433 msk_init_tx_ring(struct sk_if_softc *sc_if) 434 { 435 struct sk_softc *sc = sc_if->sk_softc; 436 struct msk_chain_data *cd = &sc_if->sk_cdata; 437 struct msk_ring_data *rd = sc_if->sk_rdata; 438 bus_dmamap_t dmamap; 439 struct sk_txmap_entry *entry; 440 int i, nexti; 441 442 memset(rd->sk_tx_ring, 0, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 443 444 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 445 for (i = 0; i < MSK_TX_RING_CNT; i++) { 446 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 447 if (i == (MSK_TX_RING_CNT - 1)) 448 nexti = 0; 449 else 450 nexti = i + 1; 451 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 452 453 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 454 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 455 return (ENOBUFS); 456 457 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 458 if (!entry) { 459 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 460 return (ENOBUFS); 461 } 462 entry->dmamap = dmamap; 463 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 464 } 465 466 sc_if->sk_cdata.sk_tx_prod = 0; 467 sc_if->sk_cdata.sk_tx_cons = 0; 468 sc_if->sk_cdata.sk_tx_cnt = 0; 469 470 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 471 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 472 473 return (0); 474 } 475 476 int 477 msk_newbuf(struct sk_if_softc *sc_if, bus_dmamap_t dmamap) 478 { 479 struct mbuf *m_new = NULL; 480 struct sk_chain *c; 481 struct msk_rx_desc *r; 482 void *buf = NULL; 483 484 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 485 if (m_new == NULL) 486 return (ENOBUFS); 487 488 /* Allocate the jumbo buffer */ 489 buf = msk_jalloc(sc_if); 490 if (buf == NULL) { 491 m_freem(m_new); 492 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 493 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 494 return (ENOBUFS); 495 } 496 497 /* Attach the buffer to the mbuf */ 498 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 499 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 500 501 m_adj(m_new, ETHER_ALIGN); 502 503 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 504 r = c->sk_le; 505 c->sk_mbuf = m_new; 506 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + 507 (((vaddr_t)m_new->m_data 508 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 509 r->sk_len = htole16(SK_JLEN); 510 r->sk_ctl = 0; 511 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 512 513 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 514 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 515 516 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 517 sc_if->sk_cdata.sk_rx_cnt++; 518 519 return (0); 520 } 521 522 /* 523 * Memory management for jumbo frames. 524 */ 525 526 int 527 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 528 { 529 struct sk_softc *sc = sc_if->sk_softc; 530 char *ptr, *kva; 531 int i, state, error; 532 struct sk_jpool_entry *entry; 533 534 state = error = 0; 535 536 /* Grab a big chunk o' storage. */ 537 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 538 &sc_if->sk_cdata.sk_jumbo_seg, 1, &sc_if->sk_cdata.sk_jumbo_nseg, 539 BUS_DMA_NOWAIT)) { 540 aprint_error(": can't alloc rx buffers"); 541 return (ENOBUFS); 542 } 543 544 state = 1; 545 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 546 sc_if->sk_cdata.sk_jumbo_nseg, MSK_JMEM, (void **)&kva, 547 BUS_DMA_NOWAIT)) { 548 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 549 error = ENOBUFS; 550 goto out; 551 } 552 553 state = 2; 554 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 555 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 556 aprint_error(": can't create dma map"); 557 error = ENOBUFS; 558 goto out; 559 } 560 561 state = 3; 562 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 563 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 564 aprint_error(": can't load dma map"); 565 error = ENOBUFS; 566 goto out; 567 } 568 569 state = 4; 570 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 571 DPRINTFN(1,("msk_jumbo_buf = %p\n", (void *)sc_if->sk_cdata.sk_jumbo_buf)); 572 573 LIST_INIT(&sc_if->sk_jfree_listhead); 574 LIST_INIT(&sc_if->sk_jinuse_listhead); 575 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 576 577 /* 578 * Now divide it up into 9K pieces and save the addresses 579 * in an array. 580 */ 581 ptr = sc_if->sk_cdata.sk_jumbo_buf; 582 for (i = 0; i < MSK_JSLOTS; i++) { 583 sc_if->sk_cdata.sk_jslots[i] = ptr; 584 ptr += SK_JLEN; 585 entry = malloc(sizeof(struct sk_jpool_entry), 586 M_DEVBUF, M_NOWAIT); 587 if (entry == NULL) { 588 sc_if->sk_cdata.sk_jumbo_buf = NULL; 589 aprint_error(": no memory for jumbo buffer queue!"); 590 error = ENOBUFS; 591 goto out; 592 } 593 entry->slot = i; 594 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 595 entry, jpool_entries); 596 } 597 out: 598 if (error != 0) { 599 switch (state) { 600 case 4: 601 bus_dmamap_unload(sc->sc_dmatag, 602 sc_if->sk_cdata.sk_rx_jumbo_map); 603 case 3: 604 bus_dmamap_destroy(sc->sc_dmatag, 605 sc_if->sk_cdata.sk_rx_jumbo_map); 606 case 2: 607 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 608 case 1: 609 bus_dmamem_free(sc->sc_dmatag, 610 &sc_if->sk_cdata.sk_jumbo_seg, 611 sc_if->sk_cdata.sk_jumbo_nseg); 612 break; 613 default: 614 break; 615 } 616 } 617 618 return error; 619 } 620 621 static void 622 msk_free_jumbo_mem(struct sk_if_softc *sc_if) 623 { 624 struct sk_softc *sc = sc_if->sk_softc; 625 626 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 627 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 628 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_cdata.sk_jumbo_buf, MSK_JMEM); 629 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 630 sc_if->sk_cdata.sk_jumbo_nseg); 631 } 632 633 /* 634 * Allocate a jumbo buffer. 635 */ 636 void * 637 msk_jalloc(struct sk_if_softc *sc_if) 638 { 639 struct sk_jpool_entry *entry; 640 641 mutex_enter(&sc_if->sk_jpool_mtx); 642 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 643 644 if (entry == NULL) { 645 mutex_exit(&sc_if->sk_jpool_mtx); 646 return NULL; 647 } 648 649 LIST_REMOVE(entry, jpool_entries); 650 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 651 mutex_exit(&sc_if->sk_jpool_mtx); 652 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 653 } 654 655 /* 656 * Release a jumbo buffer. 657 */ 658 void 659 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 660 { 661 struct sk_jpool_entry *entry; 662 struct sk_if_softc *sc; 663 int i; 664 665 /* Extract the softc struct pointer. */ 666 sc = (struct sk_if_softc *)arg; 667 668 if (sc == NULL) 669 panic("msk_jfree: can't find softc pointer!"); 670 671 /* calculate the slot this buffer belongs to */ 672 i = ((vaddr_t)buf 673 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 674 675 if ((i < 0) || (i >= MSK_JSLOTS)) 676 panic("msk_jfree: asked to free buffer that we don't manage!"); 677 678 mutex_enter(&sc->sk_jpool_mtx); 679 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 680 if (entry == NULL) 681 panic("msk_jfree: buffer not in use!"); 682 entry->slot = i; 683 LIST_REMOVE(entry, jpool_entries); 684 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 685 mutex_exit(&sc->sk_jpool_mtx); 686 687 if (__predict_true(m != NULL)) 688 pool_cache_put(mb_cache, m); 689 690 /* Now that we know we have a free RX buffer, refill if running out */ 691 if ((sc->sk_ethercom.ec_if.if_flags & IFF_RUNNING) != 0 692 && sc->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 693 callout_schedule(&sc->sk_tick_rx, 0); 694 } 695 696 int 697 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 698 { 699 struct sk_if_softc *sc = ifp->if_softc; 700 int s, error; 701 702 s = splnet(); 703 704 DPRINTFN(2, ("msk_ioctl ETHER\n")); 705 switch (cmd) { 706 case SIOCSIFFLAGS: 707 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 708 break; 709 710 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 711 case IFF_RUNNING: 712 msk_stop(ifp, 1); 713 break; 714 case IFF_UP: 715 msk_init(ifp); 716 break; 717 case IFF_UP | IFF_RUNNING: 718 if ((ifp->if_flags ^ sc->sk_if_flags) == IFF_PROMISC) { 719 msk_setpromisc(sc); 720 msk_setmulti(sc); 721 } else 722 msk_init(ifp); 723 break; 724 } 725 sc->sk_if_flags = ifp->if_flags; 726 break; 727 default: 728 error = ether_ioctl(ifp, cmd, data); 729 if (error == ENETRESET) { 730 error = 0; 731 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 732 ; 733 else if (ifp->if_flags & IFF_RUNNING) { 734 /* 735 * Multicast list has changed; set the hardware 736 * filter accordingly. 737 */ 738 msk_setmulti(sc); 739 } 740 } 741 break; 742 } 743 744 splx(s); 745 return error; 746 } 747 748 void 749 msk_update_int_mod(struct sk_softc *sc, int verbose) 750 { 751 u_int32_t imtimer_ticks; 752 753 /* 754 * Configure interrupt moderation. The moderation timer 755 * defers interrupts specified in the interrupt moderation 756 * timer mask based on the timeout specified in the interrupt 757 * moderation timer init register. Each bit in the timer 758 * register represents one tick, so to specify a timeout in 759 * microseconds, we have to multiply by the correct number of 760 * ticks-per-microsecond. 761 */ 762 switch (sc->sk_type) { 763 case SK_YUKON_EC: 764 case SK_YUKON_EC_U: 765 case SK_YUKON_EX: 766 case SK_YUKON_SUPR: 767 case SK_YUKON_ULTRA2: 768 case SK_YUKON_OPTIMA: 769 case SK_YUKON_PRM: 770 case SK_YUKON_OPTIMA2: 771 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 772 break; 773 case SK_YUKON_FE: 774 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 775 break; 776 case SK_YUKON_FE_P: 777 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 778 break; 779 case SK_YUKON_XL: 780 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 781 break; 782 default: 783 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 784 } 785 if (verbose) 786 aprint_verbose_dev(sc->sk_dev, 787 "interrupt moderation is %d us\n", sc->sk_int_mod); 788 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 789 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 790 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 791 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 792 sc->sk_int_mod_pending = 0; 793 } 794 795 static int 796 msk_lookup(const struct pci_attach_args *pa) 797 { 798 const struct msk_product *pmsk; 799 800 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 801 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 802 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 803 return 1; 804 } 805 return 0; 806 } 807 808 /* 809 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 810 * IDs against our list and return a device name if we find a match. 811 */ 812 int 813 mskc_probe(device_t parent, cfdata_t match, void *aux) 814 { 815 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 816 817 return msk_lookup(pa); 818 } 819 820 /* 821 * Force the GEnesis into reset, then bring it out of reset. 822 */ 823 void 824 mskc_reset(struct sk_softc *sc) 825 { 826 u_int32_t imtimer_ticks, reg1; 827 int reg; 828 829 DPRINTFN(2, ("mskc_reset\n")); 830 831 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 832 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 833 834 DELAY(1000); 835 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 836 DELAY(2); 837 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 838 sk_win_write_1(sc, SK_TESTCTL1, 2); 839 840 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 841 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 842 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 843 else 844 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 845 846 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 847 sc->sk_type >= SK_YUKON_FE_P) { 848 uint32_t our; 849 850 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 851 852 /* enable all clocks. */ 853 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 854 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 855 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST| 856 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN| 857 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY| 858 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 859 /* Set all bits to 0 except bits 15..12 */ 860 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 861 /* Set to default value */ 862 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 863 } 864 865 /* release PHY from PowerDown/Coma mode. */ 866 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 867 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 868 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 869 else 870 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 871 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 872 873 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 874 sk_win_write_1(sc, SK_Y2_CLKGATE, 875 SK_Y2_CLKGATE_LINK1_GATE_DIS | 876 SK_Y2_CLKGATE_LINK2_GATE_DIS | 877 SK_Y2_CLKGATE_LINK1_CORE_DIS | 878 SK_Y2_CLKGATE_LINK2_CORE_DIS | 879 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 880 else 881 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 882 883 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 884 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 885 DELAY(1000); 886 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 887 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 888 889 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 890 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 891 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 892 } 893 894 sk_win_write_1(sc, SK_TESTCTL1, 1); 895 896 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 897 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 898 CSR_READ_2(sc, SK_LINK_CTRL))); 899 900 /* Disable ASF */ 901 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 902 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 903 904 /* Clear I2C IRQ noise */ 905 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 906 907 /* Disable hardware timer */ 908 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 909 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 910 911 /* Disable descriptor polling */ 912 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 913 914 /* Disable time stamps */ 915 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 916 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 917 918 /* Enable RAM interface */ 919 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 920 for (reg = SK_TO0;reg <= SK_TO11; reg++) 921 sk_win_write_1(sc, reg, 36); 922 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 923 for (reg = SK_TO0;reg <= SK_TO11; reg++) 924 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 925 926 /* 927 * Configure interrupt moderation. The moderation timer 928 * defers interrupts specified in the interrupt moderation 929 * timer mask based on the timeout specified in the interrupt 930 * moderation timer init register. Each bit in the timer 931 * register represents one tick, so to specify a timeout in 932 * microseconds, we have to multiply by the correct number of 933 * ticks-per-microsecond. 934 */ 935 switch (sc->sk_type) { 936 case SK_YUKON_EC: 937 case SK_YUKON_EC_U: 938 case SK_YUKON_EX: 939 case SK_YUKON_SUPR: 940 case SK_YUKON_ULTRA2: 941 case SK_YUKON_OPTIMA: 942 case SK_YUKON_PRM: 943 case SK_YUKON_OPTIMA2: 944 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 945 break; 946 case SK_YUKON_FE: 947 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 948 break; 949 case SK_YUKON_FE_P: 950 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 951 break; 952 case SK_YUKON_XL: 953 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 954 break; 955 default: 956 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 957 break; 958 } 959 960 /* Reset status ring. */ 961 memset(sc->sk_status_ring, 0, 962 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 963 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 964 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 965 sc->sk_status_idx = 0; 966 sc->sk_status_own_idx = 0; 967 968 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 969 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 970 971 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 972 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 973 sc->sk_status_map->dm_segs[0].ds_addr); 974 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 975 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 976 if ((sc->sk_workaround & SK_STAT_BMU_FIFOIWM) != 0) { 977 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK); 978 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 979 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 980 } else { 981 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 982 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 983 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 984 ((sc->sk_workaround & SK_WA_4109) != 0) ? 0x10 : 0x04); 985 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 986 } 987 988 #if 0 989 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 990 #endif 991 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 992 993 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 994 995 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 996 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 997 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 998 999 msk_update_int_mod(sc, 0); 1000 } 1001 1002 int 1003 msk_probe(device_t parent, cfdata_t match, void *aux) 1004 { 1005 struct skc_attach_args *sa = aux; 1006 1007 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1008 return (0); 1009 1010 switch (sa->skc_type) { 1011 case SK_YUKON_XL: 1012 case SK_YUKON_EC_U: 1013 case SK_YUKON_EX: 1014 case SK_YUKON_EC: 1015 case SK_YUKON_FE: 1016 case SK_YUKON_FE_P: 1017 case SK_YUKON_SUPR: 1018 case SK_YUKON_ULTRA2: 1019 case SK_YUKON_OPTIMA: 1020 case SK_YUKON_PRM: 1021 case SK_YUKON_OPTIMA2: 1022 return (1); 1023 } 1024 1025 return (0); 1026 } 1027 1028 void 1029 msk_reset(struct sk_if_softc *sc_if) 1030 { 1031 /* GMAC and GPHY Reset */ 1032 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1033 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1034 DELAY(1000); 1035 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1036 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1037 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1038 } 1039 1040 static bool 1041 msk_resume(device_t dv, const pmf_qual_t *qual) 1042 { 1043 struct sk_if_softc *sc_if = device_private(dv); 1044 1045 msk_init_yukon(sc_if); 1046 return true; 1047 } 1048 1049 /* 1050 * Each XMAC chip is attached as a separate logical IP interface. 1051 * Single port cards will have only one logical interface of course. 1052 */ 1053 void 1054 msk_attach(device_t parent, device_t self, void *aux) 1055 { 1056 struct sk_if_softc *sc_if = device_private(self); 1057 struct sk_softc *sc = device_private(parent); 1058 struct skc_attach_args *sa = aux; 1059 struct ifnet *ifp; 1060 void *kva; 1061 int i; 1062 u_int32_t chunk; 1063 int mii_flags; 1064 1065 sc_if->sk_dev = self; 1066 sc_if->sk_port = sa->skc_port; 1067 sc_if->sk_softc = sc; 1068 sc->sk_if[sa->skc_port] = sc_if; 1069 1070 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1071 1072 /* 1073 * Get station address for this interface. Note that 1074 * dual port cards actually come with three station 1075 * addresses: one for each port, plus an extra. The 1076 * extra one is used by the SysKonnect driver software 1077 * as a 'virtual' station address for when both ports 1078 * are operating in failover mode. Currently we don't 1079 * use this extra address. 1080 */ 1081 for (i = 0; i < ETHER_ADDR_LEN; i++) 1082 sc_if->sk_enaddr[i] = 1083 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1084 1085 aprint_normal(": Ethernet address %s\n", 1086 ether_sprintf(sc_if->sk_enaddr)); 1087 1088 /* 1089 * Set up RAM buffer addresses. The Yukon2 has a small amount 1090 * of SRAM on it, somewhere between 4K and 48K. We need to 1091 * divide this up between the transmitter and receiver. We 1092 * give the receiver 2/3 of the memory (rounded down), and the 1093 * transmitter whatever remains. 1094 */ 1095 chunk = (2 * (sc->sk_ramsize / sizeof(u_int64_t)) / 3) & ~0xff; 1096 sc_if->sk_rx_ramstart = 0; 1097 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 1098 chunk = (sc->sk_ramsize / sizeof(u_int64_t)) - chunk; 1099 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 1100 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 1101 1102 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1103 " tx_ramstart=%#x tx_ramend=%#x\n", 1104 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1105 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1106 1107 /* Allocate the descriptor queues. */ 1108 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1109 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 1110 BUS_DMA_NOWAIT)) { 1111 aprint_error(": can't alloc rx buffers\n"); 1112 goto fail; 1113 } 1114 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 1115 sc_if->sk_ring_nseg, 1116 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1117 aprint_error(": can't map dma buffers (%zu bytes)\n", 1118 sizeof(struct msk_ring_data)); 1119 goto fail_1; 1120 } 1121 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1122 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1123 &sc_if->sk_ring_map)) { 1124 aprint_error(": can't create dma map\n"); 1125 goto fail_2; 1126 } 1127 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1128 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1129 aprint_error(": can't load dma map\n"); 1130 goto fail_3; 1131 } 1132 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1133 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1134 1135 if (sc->sk_type != SK_YUKON_FE && 1136 sc->sk_type != SK_YUKON_FE_P) 1137 sc_if->sk_pktlen = SK_JLEN; 1138 else 1139 sc_if->sk_pktlen = MCLBYTES; 1140 1141 /* Try to allocate memory for jumbo buffers. */ 1142 if (msk_alloc_jumbo_mem(sc_if)) { 1143 aprint_error(": jumbo buffer allocation failed\n"); 1144 goto fail_3; 1145 } 1146 1147 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1148 if (sc->sk_type != SK_YUKON_FE && 1149 sc->sk_type != SK_YUKON_FE_P) 1150 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1151 1152 ifp = &sc_if->sk_ethercom.ec_if; 1153 ifp->if_softc = sc_if; 1154 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1155 ifp->if_ioctl = msk_ioctl; 1156 ifp->if_start = msk_start; 1157 ifp->if_stop = msk_stop; 1158 ifp->if_init = msk_init; 1159 ifp->if_watchdog = msk_watchdog; 1160 ifp->if_baudrate = 1000000000; 1161 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1162 IFQ_SET_READY(&ifp->if_snd); 1163 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1164 1165 msk_reset(sc_if); 1166 1167 /* 1168 * Do miibus setup. 1169 */ 1170 msk_init_yukon(sc_if); 1171 1172 DPRINTFN(2, ("msk_attach: 1\n")); 1173 1174 sc_if->sk_mii.mii_ifp = ifp; 1175 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1176 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1177 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1178 1179 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1180 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1181 ether_mediachange, ether_mediastatus); 1182 mii_flags = MIIF_DOPAUSE; 1183 if (sc->sk_fibertype) 1184 mii_flags |= MIIF_HAVEFIBER; 1185 mii_attach(self, &sc_if->sk_mii, 0xffffffff, 0, 1186 MII_OFFSET_ANY, mii_flags); 1187 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1188 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1189 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1190 0, NULL); 1191 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1192 } else 1193 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1194 1195 callout_init(&sc_if->sk_tick_ch, 0); 1196 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1197 callout_schedule(&sc_if->sk_tick_ch, hz); 1198 1199 callout_init(&sc_if->sk_tick_rx, 0); 1200 callout_setfunc(&sc_if->sk_tick_rx, msk_fill_rx_tick, sc_if); 1201 1202 /* 1203 * Call MI attach routines. 1204 */ 1205 if_attach(ifp); 1206 if_deferred_start_init(ifp, NULL); 1207 ether_ifattach(ifp, sc_if->sk_enaddr); 1208 1209 if (pmf_device_register(self, NULL, msk_resume)) 1210 pmf_class_network_register(self, ifp); 1211 else 1212 aprint_error_dev(self, "couldn't establish power handler\n"); 1213 1214 if (sc->rnd_attached++ == 0) { 1215 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1216 RND_TYPE_NET, RND_FLAG_DEFAULT); 1217 } 1218 1219 DPRINTFN(2, ("msk_attach: end\n")); 1220 return; 1221 1222 fail_3: 1223 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1224 fail_2: 1225 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1226 fail_1: 1227 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1228 fail: 1229 sc->sk_if[sa->skc_port] = NULL; 1230 } 1231 1232 int 1233 msk_detach(device_t self, int flags) 1234 { 1235 struct sk_if_softc *sc_if = device_private(self); 1236 struct sk_softc *sc = sc_if->sk_softc; 1237 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1238 1239 if (sc->sk_if[sc_if->sk_port] == NULL) 1240 return (0); 1241 1242 msk_stop(ifp, 0); 1243 1244 if (--sc->rnd_attached == 0) 1245 rnd_detach_source(&sc->rnd_source); 1246 1247 callout_halt(&sc_if->sk_tick_ch, NULL); 1248 callout_destroy(&sc_if->sk_tick_ch); 1249 1250 callout_halt(&sc_if->sk_tick_rx, NULL); 1251 callout_destroy(&sc_if->sk_tick_rx); 1252 1253 /* Detach any PHYs we might have. */ 1254 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1255 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1256 1257 /* Delete any remaining media. */ 1258 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY); 1259 1260 pmf_device_deregister(self); 1261 1262 ether_ifdetach(ifp); 1263 if_detach(ifp); 1264 1265 msk_free_jumbo_mem(sc_if); 1266 1267 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_rdata, 1268 sizeof(struct msk_ring_data)); 1269 bus_dmamem_free(sc->sc_dmatag, 1270 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1271 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1272 sc->sk_if[sc_if->sk_port] = NULL; 1273 1274 return (0); 1275 } 1276 1277 int 1278 mskcprint(void *aux, const char *pnp) 1279 { 1280 struct skc_attach_args *sa = aux; 1281 1282 if (pnp) 1283 aprint_normal("msk port %c at %s", 1284 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1285 else 1286 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1287 return (UNCONF); 1288 } 1289 1290 /* 1291 * Attach the interface. Allocate softc structures, do ifmedia 1292 * setup and ethernet/BPF attach. 1293 */ 1294 void 1295 mskc_attach(device_t parent, device_t self, void *aux) 1296 { 1297 struct sk_softc *sc = device_private(self); 1298 struct pci_attach_args *pa = aux; 1299 struct skc_attach_args skca; 1300 pci_chipset_tag_t pc = pa->pa_pc; 1301 pcireg_t command, memtype; 1302 pci_intr_handle_t ih; 1303 const char *intrstr = NULL; 1304 bus_size_t size; 1305 int rc, sk_nodenum; 1306 u_int8_t hw, pmd; 1307 const char *revstr = NULL; 1308 const struct sysctlnode *node; 1309 void *kva; 1310 char intrbuf[PCI_INTRSTR_LEN]; 1311 1312 DPRINTFN(2, ("begin mskc_attach\n")); 1313 1314 sc->sk_dev = self; 1315 /* 1316 * Handle power management nonsense. 1317 */ 1318 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1319 1320 if (command == 0x01) { 1321 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1322 if (command & SK_PSTATE_MASK) { 1323 u_int32_t iobase, membase, irq; 1324 1325 /* Save important PCI config data. */ 1326 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1327 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1328 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1329 1330 /* Reset the power state. */ 1331 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1332 "mode -- setting to D0\n", 1333 command & SK_PSTATE_MASK); 1334 command &= 0xFFFFFFFC; 1335 pci_conf_write(pc, pa->pa_tag, 1336 SK_PCI_PWRMGMTCTRL, command); 1337 1338 /* Restore PCI config data. */ 1339 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1340 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1341 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1342 } 1343 } 1344 1345 /* 1346 * Map control/status registers. 1347 */ 1348 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1349 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1350 &sc->sk_bhandle, NULL, &size)) { 1351 aprint_error(": can't map mem space\n"); 1352 return; 1353 } 1354 1355 sc->sc_dmatag = pa->pa_dmat; 1356 1357 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1358 command |= PCI_COMMAND_MASTER_ENABLE; 1359 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1360 1361 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1362 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1363 1364 /* bail out here if chip is not recognized */ 1365 if (!(SK_IS_YUKON2(sc))) { 1366 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1367 goto fail_1; 1368 } 1369 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1370 1371 /* Allocate interrupt */ 1372 if (pci_intr_map(pa, &ih)) { 1373 aprint_error(": couldn't map interrupt\n"); 1374 goto fail_1; 1375 } 1376 1377 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1378 sc->sk_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, msk_intr, 1379 sc, device_xname(sc->sk_dev)); 1380 if (sc->sk_intrhand == NULL) { 1381 aprint_error(": couldn't establish interrupt"); 1382 if (intrstr != NULL) 1383 aprint_error(" at %s", intrstr); 1384 aprint_error("\n"); 1385 goto fail_1; 1386 } 1387 sc->sk_pc = pc; 1388 1389 if (bus_dmamem_alloc(sc->sc_dmatag, 1390 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1391 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1392 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, BUS_DMA_NOWAIT)) { 1393 aprint_error(": can't alloc status buffers\n"); 1394 goto fail_2; 1395 } 1396 1397 if (bus_dmamem_map(sc->sc_dmatag, 1398 &sc->sk_status_seg, sc->sk_status_nseg, 1399 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1400 &kva, BUS_DMA_NOWAIT)) { 1401 aprint_error(": can't map dma buffers (%zu bytes)\n", 1402 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1403 goto fail_3; 1404 } 1405 if (bus_dmamap_create(sc->sc_dmatag, 1406 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1407 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1408 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1409 aprint_error(": can't create dma map\n"); 1410 goto fail_4; 1411 } 1412 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1413 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1414 NULL, BUS_DMA_NOWAIT)) { 1415 aprint_error(": can't load dma map\n"); 1416 goto fail_5; 1417 } 1418 sc->sk_status_ring = (struct msk_status_desc *)kva; 1419 1420 sc->sk_int_mod = SK_IM_DEFAULT; 1421 sc->sk_int_mod_pending = 0; 1422 1423 /* Reset the adapter. */ 1424 mskc_reset(sc); 1425 1426 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1427 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1428 1429 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1430 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1431 sc->sk_fibertype = 1; 1432 1433 switch (sc->sk_type) { 1434 case SK_YUKON_XL: 1435 sc->sk_name = "Yukon-2 XL"; 1436 break; 1437 case SK_YUKON_EC_U: 1438 sc->sk_name = "Yukon-2 EC Ultra"; 1439 break; 1440 case SK_YUKON_EX: 1441 sc->sk_name = "Yukon-2 Extreme"; 1442 break; 1443 case SK_YUKON_EC: 1444 sc->sk_name = "Yukon-2 EC"; 1445 break; 1446 case SK_YUKON_FE: 1447 sc->sk_name = "Yukon-2 FE"; 1448 break; 1449 case SK_YUKON_FE_P: 1450 sc->sk_name = "Yukon-2 FE+"; 1451 break; 1452 case SK_YUKON_SUPR: 1453 sc->sk_name = "Yukon-2 Supreme"; 1454 break; 1455 case SK_YUKON_ULTRA2: 1456 sc->sk_name = "Yukon-2 Ultra 2"; 1457 break; 1458 case SK_YUKON_OPTIMA: 1459 sc->sk_name = "Yukon-2 Optima"; 1460 break; 1461 case SK_YUKON_PRM: 1462 sc->sk_name = "Yukon-2 Optima Prime"; 1463 break; 1464 case SK_YUKON_OPTIMA2: 1465 sc->sk_name = "Yukon-2 Optima 2"; 1466 break; 1467 default: 1468 sc->sk_name = "Yukon (Unknown)"; 1469 } 1470 1471 if (sc->sk_type == SK_YUKON_XL) { 1472 switch (sc->sk_rev) { 1473 case SK_YUKON_XL_REV_A0: 1474 sc->sk_workaround = 0; 1475 revstr = "A0"; 1476 break; 1477 case SK_YUKON_XL_REV_A1: 1478 sc->sk_workaround = SK_WA_4109; 1479 revstr = "A1"; 1480 break; 1481 case SK_YUKON_XL_REV_A2: 1482 sc->sk_workaround = SK_WA_4109; 1483 revstr = "A2"; 1484 break; 1485 case SK_YUKON_XL_REV_A3: 1486 sc->sk_workaround = SK_WA_4109; 1487 revstr = "A3"; 1488 break; 1489 default: 1490 sc->sk_workaround = 0; 1491 break; 1492 } 1493 } 1494 1495 if (sc->sk_type == SK_YUKON_EC) { 1496 switch (sc->sk_rev) { 1497 case SK_YUKON_EC_REV_A1: 1498 sc->sk_workaround = SK_WA_43_418 | SK_WA_4109; 1499 revstr = "A1"; 1500 break; 1501 case SK_YUKON_EC_REV_A2: 1502 sc->sk_workaround = SK_WA_4109; 1503 revstr = "A2"; 1504 break; 1505 case SK_YUKON_EC_REV_A3: 1506 sc->sk_workaround = SK_WA_4109; 1507 revstr = "A3"; 1508 break; 1509 default: 1510 sc->sk_workaround = 0; 1511 break; 1512 } 1513 } 1514 1515 if (sc->sk_type == SK_YUKON_FE) { 1516 sc->sk_workaround = SK_WA_4109; 1517 switch (sc->sk_rev) { 1518 case SK_YUKON_FE_REV_A1: 1519 revstr = "A1"; 1520 break; 1521 case SK_YUKON_FE_REV_A2: 1522 revstr = "A2"; 1523 break; 1524 default: 1525 sc->sk_workaround = 0; 1526 break; 1527 } 1528 } 1529 1530 if (sc->sk_type == SK_YUKON_EC_U) { 1531 sc->sk_workaround = SK_WA_4109; 1532 switch (sc->sk_rev) { 1533 case SK_YUKON_EC_U_REV_A0: 1534 revstr = "A0"; 1535 break; 1536 case SK_YUKON_EC_U_REV_A1: 1537 revstr = "A1"; 1538 break; 1539 case SK_YUKON_EC_U_REV_B0: 1540 revstr = "B0"; 1541 break; 1542 case SK_YUKON_EC_U_REV_B1: 1543 revstr = "B1"; 1544 break; 1545 default: 1546 sc->sk_workaround = 0; 1547 break; 1548 } 1549 } 1550 1551 if (sc->sk_type == SK_YUKON_FE) { 1552 switch (sc->sk_rev) { 1553 case SK_YUKON_FE_REV_A1: 1554 revstr = "A1"; 1555 break; 1556 case SK_YUKON_FE_REV_A2: 1557 revstr = "A2"; 1558 break; 1559 default: 1560 ; 1561 } 1562 } 1563 1564 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1565 revstr = "A0"; 1566 1567 if (sc->sk_type == SK_YUKON_EX) { 1568 switch (sc->sk_rev) { 1569 case SK_YUKON_EX_REV_A0: 1570 revstr = "A0"; 1571 break; 1572 case SK_YUKON_EX_REV_B0: 1573 revstr = "B0"; 1574 break; 1575 default: 1576 ; 1577 } 1578 } 1579 1580 if (sc->sk_type == SK_YUKON_SUPR) { 1581 switch (sc->sk_rev) { 1582 case SK_YUKON_SUPR_REV_A0: 1583 revstr = "A0"; 1584 break; 1585 case SK_YUKON_SUPR_REV_B0: 1586 revstr = "B0"; 1587 break; 1588 case SK_YUKON_SUPR_REV_B1: 1589 revstr = "B1"; 1590 break; 1591 default: 1592 ; 1593 } 1594 } 1595 1596 if (sc->sk_type == SK_YUKON_PRM) { 1597 switch (sc->sk_rev) { 1598 case SK_YUKON_PRM_REV_Z1: 1599 revstr = "Z1"; 1600 break; 1601 case SK_YUKON_PRM_REV_A0: 1602 revstr = "A0"; 1603 break; 1604 default: 1605 ; 1606 } 1607 } 1608 1609 /* Announce the product name. */ 1610 aprint_normal(", %s", sc->sk_name); 1611 if (revstr != NULL) 1612 aprint_normal(" rev. %s", revstr); 1613 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1614 1615 sc->sk_macs = 1; 1616 1617 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1618 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1619 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1620 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1621 sc->sk_macs++; 1622 } 1623 1624 skca.skc_port = SK_PORT_A; 1625 skca.skc_type = sc->sk_type; 1626 skca.skc_rev = sc->sk_rev; 1627 (void)config_found(sc->sk_dev, &skca, mskcprint); 1628 1629 if (sc->sk_macs > 1) { 1630 skca.skc_port = SK_PORT_B; 1631 skca.skc_type = sc->sk_type; 1632 skca.skc_rev = sc->sk_rev; 1633 (void)config_found(sc->sk_dev, &skca, mskcprint); 1634 } 1635 1636 /* Turn on the 'driver is loaded' LED. */ 1637 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1638 1639 /* skc sysctl setup */ 1640 1641 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1642 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1643 SYSCTL_DESCR("mskc per-controller controls"), 1644 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1645 CTL_EOL)) != 0) { 1646 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1647 goto fail_6; 1648 } 1649 1650 sk_nodenum = node->sysctl_num; 1651 1652 /* interrupt moderation time in usecs */ 1653 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1654 CTLFLAG_READWRITE, 1655 CTLTYPE_INT, "int_mod", 1656 SYSCTL_DESCR("msk interrupt moderation timer"), 1657 msk_sysctl_handler, 0, (void *)sc, 1658 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1659 CTL_EOL)) != 0) { 1660 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1661 goto fail_6; 1662 } 1663 1664 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1665 aprint_error_dev(self, "couldn't establish power handler\n"); 1666 1667 return; 1668 1669 fail_6: 1670 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1671 fail_4: 1672 bus_dmamem_unmap(sc->sc_dmatag, kva, 1673 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1674 fail_3: 1675 bus_dmamem_free(sc->sc_dmatag, 1676 &sc->sk_status_seg, sc->sk_status_nseg); 1677 sc->sk_status_nseg = 0; 1678 fail_5: 1679 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1680 fail_2: 1681 pci_intr_disestablish(pc, sc->sk_intrhand); 1682 sc->sk_intrhand = NULL; 1683 fail_1: 1684 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1685 sc->sk_bsize = 0; 1686 } 1687 1688 int 1689 mskc_detach(device_t self, int flags) 1690 { 1691 struct sk_softc *sc = device_private(self); 1692 int rv; 1693 1694 if (sc->sk_intrhand) 1695 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1696 1697 rv = config_detach_children(self, flags); 1698 if (rv != 0) 1699 return (rv); 1700 1701 if (sc->sk_status_nseg > 0) { 1702 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1703 bus_dmamem_unmap(sc->sc_dmatag, sc->sk_status_ring, 1704 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1705 bus_dmamem_free(sc->sc_dmatag, 1706 &sc->sk_status_seg, sc->sk_status_nseg); 1707 } 1708 1709 if (sc->sk_bsize > 0) 1710 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1711 1712 return(0); 1713 } 1714 1715 int 1716 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1717 { 1718 struct sk_softc *sc = sc_if->sk_softc; 1719 struct msk_tx_desc *f = NULL; 1720 u_int32_t frag, cur; 1721 int i; 1722 struct sk_txmap_entry *entry; 1723 bus_dmamap_t txmap; 1724 1725 DPRINTFN(2, ("msk_encap\n")); 1726 1727 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1728 if (entry == NULL) { 1729 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1730 return (ENOBUFS); 1731 } 1732 txmap = entry->dmamap; 1733 1734 cur = frag = *txidx; 1735 1736 #ifdef MSK_DEBUG 1737 if (mskdebug >= 2) 1738 msk_dump_mbuf(m_head); 1739 #endif 1740 1741 /* 1742 * Start packing the mbufs in this chain into 1743 * the fragment pointers. Stop when we run out 1744 * of fragments or hit the end of the mbuf chain. 1745 */ 1746 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1747 BUS_DMA_NOWAIT)) { 1748 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1749 return (ENOBUFS); 1750 } 1751 1752 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1753 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1754 bus_dmamap_unload(sc->sc_dmatag, txmap); 1755 return (ENOBUFS); 1756 } 1757 1758 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1759 1760 /* Sync the DMA map. */ 1761 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1762 BUS_DMASYNC_PREWRITE); 1763 1764 for (i = 0; i < txmap->dm_nsegs; i++) { 1765 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1766 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1767 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1768 f->sk_ctl = 0; 1769 if (i == 0) 1770 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1771 else 1772 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1773 cur = frag; 1774 SK_INC(frag, MSK_TX_RING_CNT); 1775 } 1776 1777 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1778 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1779 1780 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1781 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1782 1783 /* Sync descriptors before handing to chip */ 1784 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1785 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1786 1787 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1788 1789 /* Sync first descriptor to hand it off */ 1790 MSK_CDTXSYNC(sc_if, *txidx, 1, 1791 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1792 1793 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1794 1795 #ifdef MSK_DEBUG 1796 if (mskdebug >= 2) { 1797 struct msk_tx_desc *le; 1798 u_int32_t idx; 1799 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1800 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1801 msk_dump_txdesc(le, idx); 1802 } 1803 } 1804 #endif 1805 1806 *txidx = frag; 1807 1808 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1809 1810 return (0); 1811 } 1812 1813 void 1814 msk_start(struct ifnet *ifp) 1815 { 1816 struct sk_if_softc *sc_if = ifp->if_softc; 1817 struct mbuf *m_head = NULL; 1818 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1819 int pkts = 0; 1820 1821 DPRINTFN(2, ("msk_start\n")); 1822 1823 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1824 IFQ_POLL(&ifp->if_snd, m_head); 1825 if (m_head == NULL) 1826 break; 1827 1828 /* 1829 * Pack the data into the transmit ring. If we 1830 * don't have room, set the OACTIVE flag and wait 1831 * for the NIC to drain the ring. 1832 */ 1833 if (msk_encap(sc_if, m_head, &idx)) { 1834 ifp->if_flags |= IFF_OACTIVE; 1835 break; 1836 } 1837 1838 /* now we are committed to transmit the packet */ 1839 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1840 pkts++; 1841 1842 /* 1843 * If there's a BPF listener, bounce a copy of this frame 1844 * to him. 1845 */ 1846 bpf_mtap(ifp, m_head, BPF_D_OUT); 1847 } 1848 if (pkts == 0) 1849 return; 1850 1851 /* Transmit */ 1852 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1853 sc_if->sk_cdata.sk_tx_prod = idx; 1854 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1855 1856 /* Set a timeout in case the chip goes out to lunch. */ 1857 ifp->if_timer = 5; 1858 } 1859 } 1860 1861 void 1862 msk_watchdog(struct ifnet *ifp) 1863 { 1864 struct sk_if_softc *sc_if = ifp->if_softc; 1865 1866 /* 1867 * Reclaim first as there is a possibility of losing Tx completion 1868 * interrupts. 1869 */ 1870 msk_txeof(sc_if); 1871 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1872 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1873 1874 ifp->if_oerrors++; 1875 1876 /* XXX Resets both ports; we shouldn't do that. */ 1877 mskc_reset(sc_if->sk_softc); 1878 msk_reset(sc_if); 1879 msk_init(ifp); 1880 } 1881 } 1882 1883 static bool 1884 mskc_suspend(device_t dv, const pmf_qual_t *qual) 1885 { 1886 struct sk_softc *sc = device_private(dv); 1887 1888 DPRINTFN(2, ("mskc_suspend\n")); 1889 1890 /* Turn off the 'driver is loaded' LED. */ 1891 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1892 1893 return true; 1894 } 1895 1896 static bool 1897 mskc_resume(device_t dv, const pmf_qual_t *qual) 1898 { 1899 struct sk_softc *sc = device_private(dv); 1900 1901 DPRINTFN(2, ("mskc_resume\n")); 1902 1903 mskc_reset(sc); 1904 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1905 1906 return true; 1907 } 1908 1909 static __inline int 1910 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1911 { 1912 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1913 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1914 YU_RXSTAT_JABBER)) != 0 || 1915 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1916 YU_RXSTAT_BYTES(stat) != len) 1917 return (0); 1918 1919 return (1); 1920 } 1921 1922 void 1923 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1924 { 1925 struct sk_softc *sc = sc_if->sk_softc; 1926 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1927 struct mbuf *m; 1928 struct sk_chain *cur_rx; 1929 int cur, total_len = len; 1930 bus_dmamap_t dmamap; 1931 1932 DPRINTFN(2, ("msk_rxeof\n")); 1933 1934 cur = sc_if->sk_cdata.sk_rx_cons; 1935 1936 /* Sync the descriptor */ 1937 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1938 1939 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1940 if (cur_rx->sk_mbuf == NULL) 1941 return; 1942 1943 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1944 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1945 sc_if->sk_cdata.sk_rx_cnt--; 1946 1947 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1948 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1949 1950 m = cur_rx->sk_mbuf; 1951 cur_rx->sk_mbuf = NULL; 1952 1953 if (total_len < SK_MIN_FRAMELEN || 1954 total_len > ETHER_MAX_LEN_JUMBO || 1955 msk_rxvalid(sc, rxstat, total_len) == 0) { 1956 ifp->if_ierrors++; 1957 m_freem(m); 1958 return; 1959 } 1960 1961 m_set_rcvif(m, ifp); 1962 m->m_pkthdr.len = m->m_len = total_len; 1963 1964 /* pass it on. */ 1965 if_percpuq_enqueue(ifp->if_percpuq, m); 1966 } 1967 1968 void 1969 msk_txeof(struct sk_if_softc *sc_if) 1970 { 1971 struct sk_softc *sc = sc_if->sk_softc; 1972 struct msk_tx_desc *cur_tx; 1973 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1974 u_int32_t idx, reg, sk_ctl; 1975 struct sk_txmap_entry *entry; 1976 1977 DPRINTFN(2, ("msk_txeof\n")); 1978 1979 if (sc_if->sk_port == SK_PORT_A) 1980 reg = SK_STAT_BMU_TXA1_RIDX; 1981 else 1982 reg = SK_STAT_BMU_TXA2_RIDX; 1983 1984 /* 1985 * Go through our tx ring and free mbufs for those 1986 * frames that have been sent. 1987 */ 1988 idx = sc_if->sk_cdata.sk_tx_cons; 1989 while (idx != sk_win_read_2(sc, reg)) { 1990 MSK_CDTXSYNC(sc_if, idx, 1, 1991 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1992 1993 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1994 sk_ctl = cur_tx->sk_ctl; 1995 #ifdef MSK_DEBUG 1996 if (mskdebug >= 2) 1997 msk_dump_txdesc(cur_tx, idx); 1998 #endif 1999 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 2000 ifp->if_opackets++; 2001 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2002 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2003 2004 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2005 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2006 2007 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2008 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2009 2010 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2011 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2012 link); 2013 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2014 } 2015 sc_if->sk_cdata.sk_tx_cnt--; 2016 SK_INC(idx, MSK_TX_RING_CNT); 2017 } 2018 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2019 2020 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 2021 ifp->if_flags &= ~IFF_OACTIVE; 2022 2023 sc_if->sk_cdata.sk_tx_cons = idx; 2024 } 2025 2026 void 2027 msk_fill_rx_ring(struct sk_if_softc *sc_if) 2028 { 2029 /* Make sure to not completely wrap around */ 2030 while (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT - 1)) { 2031 if (msk_newbuf(sc_if, 2032 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 2033 goto schedretry; 2034 } 2035 } 2036 2037 return; 2038 2039 schedretry: 2040 /* Try later */ 2041 callout_schedule(&sc_if->sk_tick_rx, hz/2); 2042 } 2043 2044 static void 2045 msk_fill_rx_tick(void *xsc_if) 2046 { 2047 struct sk_if_softc *sc_if = xsc_if; 2048 int s, rx_prod; 2049 2050 KASSERT(KERNEL_LOCKED_P()); /* XXXSMP */ 2051 2052 s = splnet(); 2053 rx_prod = sc_if->sk_cdata.sk_rx_prod; 2054 msk_fill_rx_ring(sc_if); 2055 if (rx_prod != sc_if->sk_cdata.sk_rx_prod) { 2056 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2057 sc_if->sk_cdata.sk_rx_prod); 2058 } 2059 splx(s); 2060 } 2061 2062 void 2063 msk_tick(void *xsc_if) 2064 { 2065 struct sk_if_softc *sc_if = xsc_if; 2066 struct mii_data *mii = &sc_if->sk_mii; 2067 int s; 2068 2069 s = splnet(); 2070 mii_tick(mii); 2071 splx(s); 2072 2073 callout_schedule(&sc_if->sk_tick_ch, hz); 2074 } 2075 2076 void 2077 msk_intr_yukon(struct sk_if_softc *sc_if) 2078 { 2079 u_int8_t status; 2080 2081 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2082 /* RX overrun */ 2083 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2084 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2085 SK_RFCTL_RX_FIFO_OVER); 2086 } 2087 /* TX underrun */ 2088 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2089 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 2090 SK_TFCTL_TX_FIFO_UNDER); 2091 } 2092 2093 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 2094 } 2095 2096 int 2097 msk_intr(void *xsc) 2098 { 2099 struct sk_softc *sc = xsc; 2100 struct sk_if_softc *sc_if; 2101 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2102 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2103 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2104 int claimed = 0; 2105 u_int32_t status; 2106 struct msk_status_desc *cur_st; 2107 2108 status = CSR_READ_4(sc, SK_Y2_ISSR2); 2109 if (status == 0xffffffff) 2110 return (0); 2111 if (status == 0) { 2112 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2113 return (0); 2114 } 2115 2116 status = CSR_READ_4(sc, SK_ISR); 2117 2118 if (sc_if0 != NULL) 2119 ifp0 = &sc_if0->sk_ethercom.ec_if; 2120 if (sc_if1 != NULL) 2121 ifp1 = &sc_if1->sk_ethercom.ec_if; 2122 2123 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 2124 (ifp0->if_flags & IFF_RUNNING)) { 2125 msk_intr_yukon(sc_if0); 2126 } 2127 2128 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 2129 (ifp1->if_flags & IFF_RUNNING)) { 2130 msk_intr_yukon(sc_if1); 2131 } 2132 2133 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2134 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2135 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2136 2137 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 2138 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 2139 switch (cur_st->sk_opcode) { 2140 case SK_Y2_STOPC_RXSTAT: 2141 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 2142 msk_rxeof(sc_if, letoh16(cur_st->sk_len), 2143 letoh32(cur_st->sk_status)); 2144 if (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 2145 msk_fill_rx_tick(sc_if); 2146 break; 2147 case SK_Y2_STOPC_TXSTAT: 2148 if (sc_if0) 2149 msk_txeof(sc_if0); 2150 if (sc_if1) 2151 msk_txeof(sc_if1); 2152 break; 2153 default: 2154 aprint_error("opcode=0x%x\n", cur_st->sk_opcode); 2155 break; 2156 } 2157 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 2158 2159 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2160 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2161 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2162 } 2163 2164 if (status & SK_Y2_IMR_BMU) { 2165 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 2166 claimed = 1; 2167 } 2168 2169 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2170 2171 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2172 if_schedule_deferred_start(ifp0); 2173 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2174 if_schedule_deferred_start(ifp1); 2175 2176 KASSERT(sc->rnd_attached > 0); 2177 rnd_add_uint32(&sc->rnd_source, status); 2178 2179 if (sc->sk_int_mod_pending) 2180 msk_update_int_mod(sc, 1); 2181 2182 return claimed; 2183 } 2184 2185 void 2186 msk_init_yukon(struct sk_if_softc *sc_if) 2187 { 2188 u_int32_t v; 2189 u_int16_t reg; 2190 struct sk_softc *sc; 2191 int i; 2192 2193 sc = sc_if->sk_softc; 2194 2195 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 2196 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2197 2198 DPRINTFN(6, ("msk_init_yukon: 1\n")); 2199 2200 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 2201 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2202 2203 DPRINTFN(6, ("msk_init_yukon: 3\n")); 2204 2205 /* unused read of the interrupt source register */ 2206 DPRINTFN(6, ("msk_init_yukon: 4\n")); 2207 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2208 2209 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2210 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2211 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2212 2213 /* MIB Counter Clear Mode set */ 2214 reg |= YU_PAR_MIB_CLR; 2215 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2216 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2217 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2218 2219 /* MIB Counter Clear Mode clear */ 2220 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2221 reg &= ~YU_PAR_MIB_CLR; 2222 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2223 2224 /* receive control reg */ 2225 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2226 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2227 2228 /* transmit control register */ 2229 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2230 2231 /* transmit flow control register */ 2232 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2233 2234 /* transmit parameter register */ 2235 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2236 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2237 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2238 2239 /* serial mode register */ 2240 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2241 reg = YU_SMR_DATA_BLIND(0x1c) | 2242 YU_SMR_MFL_VLAN | 2243 YU_SMR_IPG_DATA(0x1e); 2244 2245 if (sc->sk_type != SK_YUKON_FE && 2246 sc->sk_type != SK_YUKON_FE_P) 2247 reg |= YU_SMR_MFL_JUMBO; 2248 2249 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2250 2251 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2252 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2253 /* msk_attach calls me before ether_ifattach so check null */ 2254 if (ifp != NULL && ifp->if_sadl != NULL) 2255 memcpy(sc_if->sk_enaddr, CLLADDR(ifp->if_sadl), 2256 sizeof(sc_if->sk_enaddr)); 2257 /* Setup Yukon's address */ 2258 for (i = 0; i < 3; i++) { 2259 /* Write Source Address 1 (unicast filter) */ 2260 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2261 sc_if->sk_enaddr[i * 2] | 2262 sc_if->sk_enaddr[i * 2 + 1] << 8); 2263 } 2264 2265 for (i = 0; i < 3; i++) { 2266 reg = sk_win_read_2(sc_if->sk_softc, 2267 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2268 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2269 } 2270 2271 /* Set promiscuous mode */ 2272 msk_setpromisc(sc_if); 2273 2274 /* Set multicast filter */ 2275 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2276 msk_setmulti(sc_if); 2277 2278 /* enable interrupt mask for counter overflows */ 2279 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2280 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2281 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2282 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2283 2284 /* Configure RX MAC FIFO Flush Mask */ 2285 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2286 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2287 YU_RXSTAT_JABBER; 2288 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2289 2290 /* Configure RX MAC FIFO */ 2291 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2292 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2293 SK_RFCTL_FIFO_FLUSH_ON); 2294 2295 /* Increase flush threshold to 64 bytes */ 2296 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2297 SK_RFCTL_FIFO_THRESHOLD + 1); 2298 2299 /* Configure TX MAC FIFO */ 2300 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2301 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2302 2303 #if 1 2304 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2305 #endif 2306 DPRINTFN(6, ("msk_init_yukon: end\n")); 2307 } 2308 2309 /* 2310 * Note that to properly initialize any part of the GEnesis chip, 2311 * you first have to take it out of reset mode. 2312 */ 2313 int 2314 msk_init(struct ifnet *ifp) 2315 { 2316 struct sk_if_softc *sc_if = ifp->if_softc; 2317 struct sk_softc *sc = sc_if->sk_softc; 2318 int rc = 0, s; 2319 uint32_t imr, imtimer_ticks; 2320 2321 2322 DPRINTFN(2, ("msk_init\n")); 2323 2324 s = splnet(); 2325 2326 /* Cancel pending I/O and free all RX/TX buffers. */ 2327 msk_stop(ifp, 1); 2328 2329 /* Configure I2C registers */ 2330 2331 /* Configure XMAC(s) */ 2332 msk_init_yukon(sc_if); 2333 if ((rc = ether_mediachange(ifp)) != 0) 2334 goto out; 2335 2336 /* Configure transmit arbiter(s) */ 2337 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2338 #if 0 2339 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2340 #endif 2341 2342 /* Configure RAMbuffers */ 2343 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2344 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2345 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2346 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2347 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2348 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2349 2350 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2351 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2352 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2353 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2354 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2355 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2356 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2357 2358 /* Configure BMUs */ 2359 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2360 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2361 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2362 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2363 2364 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2365 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2366 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2367 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2368 2369 /* Make sure the sync transmit queue is disabled. */ 2370 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2371 2372 /* Init descriptors */ 2373 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2374 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2375 "memory for rx buffers\n"); 2376 msk_stop(ifp, 1); 2377 splx(s); 2378 return ENOBUFS; 2379 } 2380 2381 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2382 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2383 "memory for tx buffers\n"); 2384 msk_stop(ifp, 1); 2385 splx(s); 2386 return ENOBUFS; 2387 } 2388 2389 /* Set interrupt moderation if changed via sysctl. */ 2390 switch (sc->sk_type) { 2391 case SK_YUKON_EC: 2392 case SK_YUKON_EC_U: 2393 case SK_YUKON_EX: 2394 case SK_YUKON_SUPR: 2395 case SK_YUKON_ULTRA2: 2396 case SK_YUKON_OPTIMA: 2397 case SK_YUKON_PRM: 2398 case SK_YUKON_OPTIMA2: 2399 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2400 break; 2401 case SK_YUKON_FE: 2402 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2403 break; 2404 case SK_YUKON_FE_P: 2405 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 2406 break; 2407 case SK_YUKON_XL: 2408 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2409 break; 2410 default: 2411 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2412 } 2413 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2414 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2415 sk_win_write_4(sc, SK_IMTIMERINIT, 2416 SK_IM_USECS(sc->sk_int_mod)); 2417 aprint_verbose_dev(sc->sk_dev, 2418 "interrupt moderation is %d us\n", sc->sk_int_mod); 2419 } 2420 2421 /* Initialize prefetch engine. */ 2422 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2423 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2424 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2425 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2426 MSK_RX_RING_ADDR(sc_if, 0)); 2427 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2428 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2429 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2430 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2431 2432 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2433 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2434 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2435 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2436 MSK_TX_RING_ADDR(sc_if, 0)); 2437 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2438 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2439 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2440 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2441 2442 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2443 sc_if->sk_cdata.sk_rx_prod); 2444 2445 /* Configure interrupt handling */ 2446 if (sc_if->sk_port == SK_PORT_A) 2447 sc->sk_intrmask |= SK_Y2_INTRS1; 2448 else 2449 sc->sk_intrmask |= SK_Y2_INTRS2; 2450 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2451 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2452 2453 ifp->if_flags |= IFF_RUNNING; 2454 ifp->if_flags &= ~IFF_OACTIVE; 2455 2456 callout_schedule(&sc_if->sk_tick_ch, hz); 2457 2458 out: 2459 splx(s); 2460 return rc; 2461 } 2462 2463 /* 2464 * Note: the logic of second parameter is inverted compared to OpenBSD 2465 * code, since this code uses the function as if_stop hook too. 2466 */ 2467 void 2468 msk_stop(struct ifnet *ifp, int disable) 2469 { 2470 struct sk_if_softc *sc_if = ifp->if_softc; 2471 struct sk_softc *sc = sc_if->sk_softc; 2472 struct sk_txmap_entry *dma; 2473 int i; 2474 2475 DPRINTFN(2, ("msk_stop\n")); 2476 2477 callout_stop(&sc_if->sk_tick_ch); 2478 callout_stop(&sc_if->sk_tick_rx); 2479 2480 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2481 2482 /* Stop transfer of Tx descriptors */ 2483 2484 /* Stop transfer of Rx descriptors */ 2485 2486 if (disable) { 2487 /* Turn off various components of this interface. */ 2488 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2489 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2490 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2491 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2492 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2493 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2494 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2495 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2496 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2497 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2498 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2499 2500 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2501 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2502 2503 /* Disable interrupts */ 2504 if (sc_if->sk_port == SK_PORT_A) 2505 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2506 else 2507 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2508 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2509 } 2510 2511 /* Free RX and TX mbufs still in the queues. */ 2512 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2513 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2514 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2515 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2516 } 2517 } 2518 2519 sc_if->sk_cdata.sk_rx_prod = 0; 2520 sc_if->sk_cdata.sk_rx_cons = 0; 2521 sc_if->sk_cdata.sk_rx_cnt = 0; 2522 2523 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2524 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2525 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2526 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2527 #if 1 2528 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2529 sc_if->sk_cdata.sk_tx_map[i], link); 2530 sc_if->sk_cdata.sk_tx_map[i] = 0; 2531 #endif 2532 } 2533 } 2534 2535 #if 1 2536 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2537 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2538 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2539 free(dma, M_DEVBUF); 2540 } 2541 #endif 2542 } 2543 2544 CFATTACH_DECL3_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2545 mskc_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2546 2547 CFATTACH_DECL3_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2548 msk_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2549 2550 #ifdef MSK_DEBUG 2551 void 2552 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2553 { 2554 #define DESC_PRINT(X) \ 2555 if (X) \ 2556 printf("txdesc[%d]." #X "=%#x\n", \ 2557 idx, X); 2558 2559 DESC_PRINT(letoh32(le->sk_addr)); 2560 DESC_PRINT(letoh16(le->sk_len)); 2561 DESC_PRINT(le->sk_ctl); 2562 DESC_PRINT(le->sk_opcode); 2563 #undef DESC_PRINT 2564 } 2565 2566 void 2567 msk_dump_bytes(const char *data, int len) 2568 { 2569 int c, i, j; 2570 2571 for (i = 0; i < len; i += 16) { 2572 printf("%08x ", i); 2573 c = len - i; 2574 if (c > 16) c = 16; 2575 2576 for (j = 0; j < c; j++) { 2577 printf("%02x ", data[i + j] & 0xff); 2578 if ((j & 0xf) == 7 && j > 0) 2579 printf(" "); 2580 } 2581 2582 for (; j < 16; j++) 2583 printf(" "); 2584 printf(" "); 2585 2586 for (j = 0; j < c; j++) { 2587 int ch = data[i + j] & 0xff; 2588 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2589 } 2590 2591 printf("\n"); 2592 2593 if (c < 16) 2594 break; 2595 } 2596 } 2597 2598 void 2599 msk_dump_mbuf(struct mbuf *m) 2600 { 2601 int count = m->m_pkthdr.len; 2602 2603 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2604 2605 while (count > 0 && m) { 2606 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2607 m, m->m_data, m->m_len); 2608 msk_dump_bytes(mtod(m, char *), m->m_len); 2609 2610 count -= m->m_len; 2611 m = m->m_next; 2612 } 2613 } 2614 #endif 2615 2616 static int 2617 msk_sysctl_handler(SYSCTLFN_ARGS) 2618 { 2619 int error, t; 2620 struct sysctlnode node; 2621 struct sk_softc *sc; 2622 2623 node = *rnode; 2624 sc = node.sysctl_data; 2625 t = sc->sk_int_mod; 2626 node.sysctl_data = &t; 2627 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2628 if (error || newp == NULL) 2629 return error; 2630 2631 if (t < SK_IM_MIN || t > SK_IM_MAX) 2632 return EINVAL; 2633 2634 /* update the softc with sysctl-changed value, and mark 2635 for hardware update */ 2636 sc->sk_int_mod = t; 2637 sc->sk_int_mod_pending = 1; 2638 return 0; 2639 } 2640 2641 /* 2642 * Set up sysctl(3) MIB, hw.msk.* - Individual controllers will be 2643 * set up in mskc_attach() 2644 */ 2645 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2646 { 2647 int rc; 2648 const struct sysctlnode *node; 2649 2650 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2651 0, CTLTYPE_NODE, "msk", 2652 SYSCTL_DESCR("msk interface controls"), 2653 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2654 goto err; 2655 } 2656 2657 msk_root_num = node->sysctl_num; 2658 return; 2659 2660 err: 2661 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2662 } 2663
Indexes created Mon Sep 22 05:09:51 GMT 2025