if_msk.c revision 1.75
1 /* $NetBSD: if_msk.c,v 1.75 2018/07/10 20:48:54 jdolecek Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.79 2009/10/15 17:54:56 deraadt Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.75 2018/07/10 20:48:54 jdolecek Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/mutex.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/device.h> 66 #include <sys/queue.h> 67 #include <sys/callout.h> 68 #include <sys/sysctl.h> 69 #include <sys/endian.h> 70 #ifdef __NetBSD__ 71 #define letoh16 htole16 72 #define letoh32 htole32 73 #endif 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #include <net/if_media.h> 80 81 #include <net/bpf.h> 82 #include <sys/rndsource.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 #include <dev/mii/brgphyreg.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 92 #include <dev/pci/if_skreg.h> 93 #include <dev/pci/if_mskvar.h> 94 95 int mskc_probe(device_t, cfdata_t, void *); 96 void mskc_attach(device_t, device_t, void *); 97 int mskc_detach(device_t, int); 98 void mskc_reset(struct sk_softc *); 99 static bool mskc_suspend(device_t, const pmf_qual_t *); 100 static bool mskc_resume(device_t, const pmf_qual_t *); 101 int msk_probe(device_t, cfdata_t, void *); 102 void msk_attach(device_t, device_t, void *); 103 int msk_detach(device_t, int); 104 void msk_reset(struct sk_if_softc *); 105 int mskcprint(void *, const char *); 106 int msk_intr(void *); 107 void msk_intr_yukon(struct sk_if_softc *); 108 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 109 void msk_txeof(struct sk_if_softc *); 110 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 111 void msk_start(struct ifnet *); 112 int msk_ioctl(struct ifnet *, u_long, void *); 113 int msk_init(struct ifnet *); 114 void msk_init_yukon(struct sk_if_softc *); 115 void msk_stop(struct ifnet *, int); 116 void msk_watchdog(struct ifnet *); 117 int msk_newbuf(struct sk_if_softc *, bus_dmamap_t); 118 int msk_alloc_jumbo_mem(struct sk_if_softc *); 119 void *msk_jalloc(struct sk_if_softc *); 120 void msk_jfree(struct mbuf *, void *, size_t, void *); 121 int msk_init_rx_ring(struct sk_if_softc *); 122 int msk_init_tx_ring(struct sk_if_softc *); 123 void msk_fill_rx_ring(struct sk_if_softc *); 124 125 void msk_update_int_mod(struct sk_softc *, int); 126 127 int msk_miibus_readreg(device_t, int, int); 128 void msk_miibus_writereg(device_t, int, int, int); 129 void msk_miibus_statchg(struct ifnet *); 130 131 void msk_setmulti(struct sk_if_softc *); 132 void msk_setpromisc(struct sk_if_softc *); 133 void msk_tick(void *); 134 static void msk_fill_rx_tick(void *); 135 136 /* #define MSK_DEBUG 1 */ 137 #ifdef MSK_DEBUG 138 #define DPRINTF(x) if (mskdebug) printf x 139 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 140 int mskdebug = MSK_DEBUG; 141 142 void msk_dump_txdesc(struct msk_tx_desc *, int); 143 void msk_dump_mbuf(struct mbuf *); 144 void msk_dump_bytes(const char *, int); 145 #else 146 #define DPRINTF(x) 147 #define DPRINTFN(n,x) 148 #endif 149 150 static int msk_sysctl_handler(SYSCTLFN_PROTO); 151 static int msk_root_num; 152 153 /* supported device vendors */ 154 static const struct msk_product { 155 pci_vendor_id_t msk_vendor; 156 pci_product_id_t msk_product; 157 } msk_products[] = { 158 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 159 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 160 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 162 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 163 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8079 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 197 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 198 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 } 199 }; 200 201 static inline u_int32_t 202 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 203 { 204 return CSR_READ_4(sc, reg); 205 } 206 207 static inline u_int16_t 208 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 209 { 210 return CSR_READ_2(sc, reg); 211 } 212 213 static inline u_int8_t 214 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 215 { 216 return CSR_READ_1(sc, reg); 217 } 218 219 static inline void 220 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 221 { 222 CSR_WRITE_4(sc, reg, x); 223 } 224 225 static inline void 226 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 227 { 228 CSR_WRITE_2(sc, reg, x); 229 } 230 231 static inline void 232 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 233 { 234 CSR_WRITE_1(sc, reg, x); 235 } 236 237 int 238 msk_miibus_readreg(device_t dev, int phy, int reg) 239 { 240 struct sk_if_softc *sc_if = device_private(dev); 241 u_int16_t val; 242 int i; 243 244 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 245 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 246 247 for (i = 0; i < SK_TIMEOUT; i++) { 248 DELAY(1); 249 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 250 if (val & YU_SMICR_READ_VALID) 251 break; 252 } 253 254 if (i == SK_TIMEOUT) { 255 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 256 return (0); 257 } 258 259 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 260 SK_TIMEOUT)); 261 262 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 263 264 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 265 phy, reg, val)); 266 267 return (val); 268 } 269 270 void 271 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 272 { 273 struct sk_if_softc *sc_if = device_private(dev); 274 int i; 275 276 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 277 phy, reg, val)); 278 279 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 280 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 281 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 282 283 for (i = 0; i < SK_TIMEOUT; i++) { 284 DELAY(1); 285 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 286 break; 287 } 288 289 if (i == SK_TIMEOUT) 290 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 291 } 292 293 void 294 msk_miibus_statchg(struct ifnet *ifp) 295 { 296 struct sk_if_softc *sc_if = ifp->if_softc; 297 struct mii_data *mii = &sc_if->sk_mii; 298 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 299 int gpcr; 300 301 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 302 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 303 304 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 305 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 306 /* Set speed. */ 307 gpcr |= YU_GPCR_SPEED_DIS; 308 switch (IFM_SUBTYPE(mii->mii_media_active)) { 309 case IFM_1000_SX: 310 case IFM_1000_LX: 311 case IFM_1000_CX: 312 case IFM_1000_T: 313 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 314 break; 315 case IFM_100_TX: 316 gpcr |= YU_GPCR_SPEED; 317 break; 318 } 319 320 /* Set duplex. */ 321 gpcr |= YU_GPCR_DPLX_DIS; 322 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 323 gpcr |= YU_GPCR_DUPLEX; 324 325 /* Disable flow control. */ 326 gpcr |= YU_GPCR_FCTL_DIS; 327 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 328 } 329 330 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 331 332 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 333 SK_YU_READ_2(sc_if, YUKON_GPCR))); 334 } 335 336 void 337 msk_setmulti(struct sk_if_softc *sc_if) 338 { 339 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 340 u_int32_t hashes[2] = { 0, 0 }; 341 int h; 342 struct ethercom *ec = &sc_if->sk_ethercom; 343 struct ether_multi *enm; 344 struct ether_multistep step; 345 u_int16_t reg; 346 347 /* First, zot all the existing filters. */ 348 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 349 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 350 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 351 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 352 353 354 /* Now program new ones. */ 355 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 356 reg |= YU_RCR_UFLEN; 357 allmulti: 358 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 359 if ((ifp->if_flags & IFF_PROMISC) != 0) 360 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 361 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 362 hashes[0] = 0xFFFFFFFF; 363 hashes[1] = 0xFFFFFFFF; 364 } 365 } else { 366 /* First find the tail of the list. */ 367 ETHER_FIRST_MULTI(step, ec, enm); 368 while (enm != NULL) { 369 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 370 ETHER_ADDR_LEN)) { 371 ifp->if_flags |= IFF_ALLMULTI; 372 goto allmulti; 373 } 374 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 375 ((1 << SK_HASH_BITS) - 1); 376 if (h < 32) 377 hashes[0] |= (1 << h); 378 else 379 hashes[1] |= (1 << (h - 32)); 380 381 ETHER_NEXT_MULTI(step, enm); 382 } 383 reg |= YU_RCR_MUFLEN; 384 } 385 386 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 387 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 388 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 389 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 390 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 391 } 392 393 void 394 msk_setpromisc(struct sk_if_softc *sc_if) 395 { 396 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 397 398 if (ifp->if_flags & IFF_PROMISC) 399 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 400 YU_RCR_UFLEN | YU_RCR_MUFLEN); 401 else 402 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 403 YU_RCR_UFLEN | YU_RCR_MUFLEN); 404 } 405 406 int 407 msk_init_rx_ring(struct sk_if_softc *sc_if) 408 { 409 struct msk_chain_data *cd = &sc_if->sk_cdata; 410 struct msk_ring_data *rd = sc_if->sk_rdata; 411 int i, nexti; 412 413 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 414 415 for (i = 0; i < MSK_RX_RING_CNT; i++) { 416 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 417 if (i == (MSK_RX_RING_CNT - 1)) 418 nexti = 0; 419 else 420 nexti = i + 1; 421 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 422 } 423 424 sc_if->sk_cdata.sk_rx_prod = 0; 425 sc_if->sk_cdata.sk_rx_cons = 0; 426 sc_if->sk_cdata.sk_rx_cnt = 0; 427 428 msk_fill_rx_ring(sc_if); 429 return (0); 430 } 431 432 int 433 msk_init_tx_ring(struct sk_if_softc *sc_if) 434 { 435 struct sk_softc *sc = sc_if->sk_softc; 436 struct msk_chain_data *cd = &sc_if->sk_cdata; 437 struct msk_ring_data *rd = sc_if->sk_rdata; 438 bus_dmamap_t dmamap; 439 struct sk_txmap_entry *entry; 440 int i, nexti; 441 442 memset(rd->sk_tx_ring, 0, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 443 444 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 445 for (i = 0; i < MSK_TX_RING_CNT; i++) { 446 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 447 if (i == (MSK_TX_RING_CNT - 1)) 448 nexti = 0; 449 else 450 nexti = i + 1; 451 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 452 453 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 454 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 455 return (ENOBUFS); 456 457 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 458 if (!entry) { 459 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 460 return (ENOBUFS); 461 } 462 entry->dmamap = dmamap; 463 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 464 } 465 466 sc_if->sk_cdata.sk_tx_prod = 0; 467 sc_if->sk_cdata.sk_tx_cons = 0; 468 sc_if->sk_cdata.sk_tx_cnt = 0; 469 470 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 471 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 472 473 return (0); 474 } 475 476 int 477 msk_newbuf(struct sk_if_softc *sc_if, bus_dmamap_t dmamap) 478 { 479 struct mbuf *m_new = NULL; 480 struct sk_chain *c; 481 struct msk_rx_desc *r; 482 void *buf = NULL; 483 484 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 485 if (m_new == NULL) 486 return (ENOBUFS); 487 488 /* Allocate the jumbo buffer */ 489 buf = msk_jalloc(sc_if); 490 if (buf == NULL) { 491 m_freem(m_new); 492 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 493 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 494 return (ENOBUFS); 495 } 496 497 /* Attach the buffer to the mbuf */ 498 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 499 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 500 501 m_adj(m_new, ETHER_ALIGN); 502 503 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 504 r = c->sk_le; 505 c->sk_mbuf = m_new; 506 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + 507 (((vaddr_t)m_new->m_data 508 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 509 r->sk_len = htole16(SK_JLEN); 510 r->sk_ctl = 0; 511 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 512 513 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 514 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 515 516 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 517 sc_if->sk_cdata.sk_rx_cnt++; 518 519 return (0); 520 } 521 522 /* 523 * Memory management for jumbo frames. 524 */ 525 526 int 527 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 528 { 529 struct sk_softc *sc = sc_if->sk_softc; 530 char *ptr, *kva; 531 int i, state, error; 532 struct sk_jpool_entry *entry; 533 534 state = error = 0; 535 536 /* Grab a big chunk o' storage. */ 537 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 538 &sc_if->sk_cdata.sk_jumbo_seg, 1, &sc_if->sk_cdata.sk_jumbo_nseg, 539 BUS_DMA_NOWAIT)) { 540 aprint_error(": can't alloc rx buffers"); 541 return (ENOBUFS); 542 } 543 544 state = 1; 545 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 546 sc_if->sk_cdata.sk_jumbo_nseg, MSK_JMEM, (void **)&kva, 547 BUS_DMA_NOWAIT)) { 548 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 549 error = ENOBUFS; 550 goto out; 551 } 552 553 state = 2; 554 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 555 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 556 aprint_error(": can't create dma map"); 557 error = ENOBUFS; 558 goto out; 559 } 560 561 state = 3; 562 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 563 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 564 aprint_error(": can't load dma map"); 565 error = ENOBUFS; 566 goto out; 567 } 568 569 state = 4; 570 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 571 DPRINTFN(1,("msk_jumbo_buf = %p\n", (void *)sc_if->sk_cdata.sk_jumbo_buf)); 572 573 LIST_INIT(&sc_if->sk_jfree_listhead); 574 LIST_INIT(&sc_if->sk_jinuse_listhead); 575 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 576 577 /* 578 * Now divide it up into 9K pieces and save the addresses 579 * in an array. 580 */ 581 ptr = sc_if->sk_cdata.sk_jumbo_buf; 582 for (i = 0; i < MSK_JSLOTS; i++) { 583 sc_if->sk_cdata.sk_jslots[i] = ptr; 584 ptr += SK_JLEN; 585 entry = malloc(sizeof(struct sk_jpool_entry), 586 M_DEVBUF, M_NOWAIT); 587 if (entry == NULL) { 588 sc_if->sk_cdata.sk_jumbo_buf = NULL; 589 aprint_error(": no memory for jumbo buffer queue!"); 590 error = ENOBUFS; 591 goto out; 592 } 593 entry->slot = i; 594 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 595 entry, jpool_entries); 596 } 597 out: 598 if (error != 0) { 599 switch (state) { 600 case 4: 601 bus_dmamap_unload(sc->sc_dmatag, 602 sc_if->sk_cdata.sk_rx_jumbo_map); 603 case 3: 604 bus_dmamap_destroy(sc->sc_dmatag, 605 sc_if->sk_cdata.sk_rx_jumbo_map); 606 case 2: 607 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 608 case 1: 609 bus_dmamem_free(sc->sc_dmatag, 610 &sc_if->sk_cdata.sk_jumbo_seg, 611 sc_if->sk_cdata.sk_jumbo_nseg); 612 break; 613 default: 614 break; 615 } 616 } 617 618 return error; 619 } 620 621 static void 622 msk_free_jumbo_mem(struct sk_if_softc *sc_if) 623 { 624 struct sk_softc *sc = sc_if->sk_softc; 625 626 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 627 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 628 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_cdata.sk_jumbo_buf, MSK_JMEM); 629 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 630 sc_if->sk_cdata.sk_jumbo_nseg); 631 } 632 633 /* 634 * Allocate a jumbo buffer. 635 */ 636 void * 637 msk_jalloc(struct sk_if_softc *sc_if) 638 { 639 struct sk_jpool_entry *entry; 640 641 mutex_enter(&sc_if->sk_jpool_mtx); 642 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 643 644 if (entry == NULL) { 645 mutex_exit(&sc_if->sk_jpool_mtx); 646 return NULL; 647 } 648 649 LIST_REMOVE(entry, jpool_entries); 650 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 651 mutex_exit(&sc_if->sk_jpool_mtx); 652 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 653 } 654 655 /* 656 * Release a jumbo buffer. 657 */ 658 void 659 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 660 { 661 struct sk_jpool_entry *entry; 662 struct sk_if_softc *sc; 663 int i; 664 665 /* Extract the softc struct pointer. */ 666 sc = (struct sk_if_softc *)arg; 667 668 if (sc == NULL) 669 panic("msk_jfree: can't find softc pointer!"); 670 671 /* calculate the slot this buffer belongs to */ 672 i = ((vaddr_t)buf 673 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 674 675 if ((i < 0) || (i >= MSK_JSLOTS)) 676 panic("msk_jfree: asked to free buffer that we don't manage!"); 677 678 mutex_enter(&sc->sk_jpool_mtx); 679 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 680 if (entry == NULL) 681 panic("msk_jfree: buffer not in use!"); 682 entry->slot = i; 683 LIST_REMOVE(entry, jpool_entries); 684 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 685 mutex_exit(&sc->sk_jpool_mtx); 686 687 if (__predict_true(m != NULL)) 688 pool_cache_put(mb_cache, m); 689 690 /* Now that we know we have a free RX buffer, refill if running out */ 691 if ((sc->sk_ethercom.ec_if.if_flags & IFF_RUNNING) != 0 692 && sc->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 693 callout_schedule(&sc->sk_tick_rx, 0); 694 } 695 696 int 697 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 698 { 699 struct sk_if_softc *sc = ifp->if_softc; 700 int s, error; 701 702 s = splnet(); 703 704 DPRINTFN(2, ("msk_ioctl ETHER\n")); 705 switch (cmd) { 706 case SIOCSIFFLAGS: 707 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 708 break; 709 710 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 711 case IFF_RUNNING: 712 msk_stop(ifp, 1); 713 break; 714 case IFF_UP: 715 msk_init(ifp); 716 break; 717 case IFF_UP | IFF_RUNNING: 718 if ((ifp->if_flags ^ sc->sk_if_flags) == IFF_PROMISC) { 719 msk_setpromisc(sc); 720 msk_setmulti(sc); 721 } else 722 msk_init(ifp); 723 break; 724 } 725 sc->sk_if_flags = ifp->if_flags; 726 break; 727 default: 728 error = ether_ioctl(ifp, cmd, data); 729 if (error == ENETRESET) { 730 error = 0; 731 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 732 ; 733 else if (ifp->if_flags & IFF_RUNNING) { 734 /* 735 * Multicast list has changed; set the hardware 736 * filter accordingly. 737 */ 738 msk_setmulti(sc); 739 } 740 } 741 break; 742 } 743 744 splx(s); 745 return error; 746 } 747 748 void 749 msk_update_int_mod(struct sk_softc *sc, int verbose) 750 { 751 u_int32_t imtimer_ticks; 752 753 /* 754 * Configure interrupt moderation. The moderation timer 755 * defers interrupts specified in the interrupt moderation 756 * timer mask based on the timeout specified in the interrupt 757 * moderation timer init register. Each bit in the timer 758 * register represents one tick, so to specify a timeout in 759 * microseconds, we have to multiply by the correct number of 760 * ticks-per-microsecond. 761 */ 762 switch (sc->sk_type) { 763 case SK_YUKON_EC: 764 case SK_YUKON_EC_U: 765 case SK_YUKON_EX: 766 case SK_YUKON_SUPR: 767 case SK_YUKON_ULTRA2: 768 case SK_YUKON_OPTIMA: 769 case SK_YUKON_PRM: 770 case SK_YUKON_OPTIMA2: 771 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 772 break; 773 case SK_YUKON_FE: 774 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 775 break; 776 case SK_YUKON_FE_P: 777 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 778 break; 779 case SK_YUKON_XL: 780 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 781 break; 782 default: 783 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 784 } 785 if (verbose) 786 aprint_verbose_dev(sc->sk_dev, 787 "interrupt moderation is %d us\n", sc->sk_int_mod); 788 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 789 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 790 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 791 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 792 sc->sk_int_mod_pending = 0; 793 } 794 795 static int 796 msk_lookup(const struct pci_attach_args *pa) 797 { 798 const struct msk_product *pmsk; 799 800 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 801 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 802 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 803 return 1; 804 } 805 return 0; 806 } 807 808 /* 809 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 810 * IDs against our list and return a device name if we find a match. 811 */ 812 int 813 mskc_probe(device_t parent, cfdata_t match, void *aux) 814 { 815 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 816 817 return msk_lookup(pa); 818 } 819 820 /* 821 * Force the GEnesis into reset, then bring it out of reset. 822 */ 823 void 824 mskc_reset(struct sk_softc *sc) 825 { 826 u_int32_t imtimer_ticks, reg1; 827 int reg; 828 829 DPRINTFN(2, ("mskc_reset\n")); 830 831 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 832 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 833 834 DELAY(1000); 835 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 836 DELAY(2); 837 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 838 sk_win_write_1(sc, SK_TESTCTL1, 2); 839 840 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 841 sc->sk_type >= SK_YUKON_FE_P) { 842 uint32_t our; 843 844 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 845 846 /* enable all clocks. */ 847 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 848 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 849 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST| 850 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN| 851 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY| 852 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 853 /* Set all bits to 0 except bits 15..12 */ 854 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 855 /* Set to default value */ 856 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 857 858 /* 859 * Disable status race, workaround for Yukon EC Ultra & 860 * Yukon EX. 861 */ 862 reg1 = sk_win_read_4(sc, SK_GPIO); 863 reg1 |= SK_Y2_GPIO_STAT_RACE_DIS; 864 sk_win_write_4(sc, SK_GPIO, reg1); 865 sk_win_read_4(sc, SK_GPIO); 866 } 867 868 /* release PHY from PowerDown/Coma mode. */ 869 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 870 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 871 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 872 else 873 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 874 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 875 876 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 877 sk_win_write_1(sc, SK_Y2_CLKGATE, 878 SK_Y2_CLKGATE_LINK1_GATE_DIS | 879 SK_Y2_CLKGATE_LINK2_GATE_DIS | 880 SK_Y2_CLKGATE_LINK1_CORE_DIS | 881 SK_Y2_CLKGATE_LINK2_CORE_DIS | 882 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 883 else 884 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 885 886 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 887 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 888 DELAY(1000); 889 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 890 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 891 892 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 893 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 894 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 895 } 896 897 sk_win_write_1(sc, SK_TESTCTL1, 1); 898 899 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 900 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 901 CSR_READ_2(sc, SK_LINK_CTRL))); 902 903 /* Disable ASF */ 904 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 905 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 906 907 /* Clear I2C IRQ noise */ 908 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 909 910 /* Disable hardware timer */ 911 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 912 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 913 914 /* Disable descriptor polling */ 915 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 916 917 /* Disable time stamps */ 918 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 919 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 920 921 /* Enable RAM interface */ 922 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 923 for (reg = SK_TO0;reg <= SK_TO11; reg++) 924 sk_win_write_1(sc, reg, 36); 925 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 926 for (reg = SK_TO0;reg <= SK_TO11; reg++) 927 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 928 929 /* 930 * Configure interrupt moderation. The moderation timer 931 * defers interrupts specified in the interrupt moderation 932 * timer mask based on the timeout specified in the interrupt 933 * moderation timer init register. Each bit in the timer 934 * register represents one tick, so to specify a timeout in 935 * microseconds, we have to multiply by the correct number of 936 * ticks-per-microsecond. 937 */ 938 switch (sc->sk_type) { 939 case SK_YUKON_EC: 940 case SK_YUKON_EC_U: 941 case SK_YUKON_EX: 942 case SK_YUKON_SUPR: 943 case SK_YUKON_ULTRA2: 944 case SK_YUKON_OPTIMA: 945 case SK_YUKON_PRM: 946 case SK_YUKON_OPTIMA2: 947 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 948 break; 949 case SK_YUKON_FE: 950 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 951 break; 952 case SK_YUKON_FE_P: 953 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 954 break; 955 case SK_YUKON_XL: 956 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 957 break; 958 default: 959 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 960 break; 961 } 962 963 /* Reset status ring. */ 964 memset(sc->sk_status_ring, 0, 965 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 966 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 967 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 968 sc->sk_status_idx = 0; 969 970 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 971 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 972 973 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 974 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 975 sc->sk_status_map->dm_segs[0].ds_addr); 976 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 977 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 978 if (sc->sk_type == SK_YUKON_EC && 979 sc->sk_rev == SK_YUKON_EC_REV_A1) { 980 /* WA for dev. #4.3 */ 981 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK); 982 /* WA for dev. #4.18 */ 983 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 984 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 985 } else { 986 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 987 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 988 if (sc->sk_type == SK_YUKON_XL) 989 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x04); 990 else 991 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x10); 992 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 993 } 994 995 #if 0 996 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 997 #endif 998 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 999 1000 /* Enable status unit. */ 1001 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 1002 1003 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 1004 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 1005 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 1006 1007 msk_update_int_mod(sc, 0); 1008 } 1009 1010 int 1011 msk_probe(device_t parent, cfdata_t match, void *aux) 1012 { 1013 struct skc_attach_args *sa = aux; 1014 1015 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1016 return (0); 1017 1018 switch (sa->skc_type) { 1019 case SK_YUKON_XL: 1020 case SK_YUKON_EC_U: 1021 case SK_YUKON_EX: 1022 case SK_YUKON_EC: 1023 case SK_YUKON_FE: 1024 case SK_YUKON_FE_P: 1025 case SK_YUKON_SUPR: 1026 case SK_YUKON_ULTRA2: 1027 case SK_YUKON_OPTIMA: 1028 case SK_YUKON_PRM: 1029 case SK_YUKON_OPTIMA2: 1030 return (1); 1031 } 1032 1033 return (0); 1034 } 1035 1036 void 1037 msk_reset(struct sk_if_softc *sc_if) 1038 { 1039 /* GMAC and GPHY Reset */ 1040 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1041 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1042 DELAY(1000); 1043 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1044 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1045 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1046 } 1047 1048 static bool 1049 msk_resume(device_t dv, const pmf_qual_t *qual) 1050 { 1051 struct sk_if_softc *sc_if = device_private(dv); 1052 1053 msk_init_yukon(sc_if); 1054 return true; 1055 } 1056 1057 /* 1058 * Each XMAC chip is attached as a separate logical IP interface. 1059 * Single port cards will have only one logical interface of course. 1060 */ 1061 void 1062 msk_attach(device_t parent, device_t self, void *aux) 1063 { 1064 struct sk_if_softc *sc_if = device_private(self); 1065 struct sk_softc *sc = device_private(parent); 1066 struct skc_attach_args *sa = aux; 1067 struct ifnet *ifp; 1068 void *kva; 1069 int i; 1070 u_int32_t chunk; 1071 int mii_flags; 1072 1073 sc_if->sk_dev = self; 1074 sc_if->sk_port = sa->skc_port; 1075 sc_if->sk_softc = sc; 1076 sc->sk_if[sa->skc_port] = sc_if; 1077 1078 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1079 1080 /* 1081 * Get station address for this interface. Note that 1082 * dual port cards actually come with three station 1083 * addresses: one for each port, plus an extra. The 1084 * extra one is used by the SysKonnect driver software 1085 * as a 'virtual' station address for when both ports 1086 * are operating in failover mode. Currently we don't 1087 * use this extra address. 1088 */ 1089 for (i = 0; i < ETHER_ADDR_LEN; i++) 1090 sc_if->sk_enaddr[i] = 1091 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1092 1093 aprint_normal(": Ethernet address %s\n", 1094 ether_sprintf(sc_if->sk_enaddr)); 1095 1096 /* 1097 * Set up RAM buffer addresses. The Yukon2 has a small amount 1098 * of SRAM on it, somewhere between 4K and 48K. We need to 1099 * divide this up between the transmitter and receiver. We 1100 * give the receiver 2/3 of the memory (rounded down), and the 1101 * transmitter whatever remains. 1102 */ 1103 chunk = (2 * (sc->sk_ramsize / sizeof(u_int64_t)) / 3) & ~0xff; 1104 sc_if->sk_rx_ramstart = 0; 1105 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 1106 chunk = (sc->sk_ramsize / sizeof(u_int64_t)) - chunk; 1107 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 1108 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 1109 1110 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1111 " tx_ramstart=%#x tx_ramend=%#x\n", 1112 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1113 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1114 1115 /* Allocate the descriptor queues. */ 1116 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1117 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 1118 BUS_DMA_NOWAIT)) { 1119 aprint_error(": can't alloc rx buffers\n"); 1120 goto fail; 1121 } 1122 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 1123 sc_if->sk_ring_nseg, 1124 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1125 aprint_error(": can't map dma buffers (%zu bytes)\n", 1126 sizeof(struct msk_ring_data)); 1127 goto fail_1; 1128 } 1129 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1130 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1131 &sc_if->sk_ring_map)) { 1132 aprint_error(": can't create dma map\n"); 1133 goto fail_2; 1134 } 1135 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1136 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1137 aprint_error(": can't load dma map\n"); 1138 goto fail_3; 1139 } 1140 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1141 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1142 1143 if (sc->sk_type != SK_YUKON_FE && 1144 sc->sk_type != SK_YUKON_FE_P) 1145 sc_if->sk_pktlen = SK_JLEN; 1146 else 1147 sc_if->sk_pktlen = MCLBYTES; 1148 1149 /* Try to allocate memory for jumbo buffers. */ 1150 if (msk_alloc_jumbo_mem(sc_if)) { 1151 aprint_error(": jumbo buffer allocation failed\n"); 1152 goto fail_3; 1153 } 1154 1155 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1156 if (sc->sk_type != SK_YUKON_FE && 1157 sc->sk_type != SK_YUKON_FE_P) 1158 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1159 1160 ifp = &sc_if->sk_ethercom.ec_if; 1161 ifp->if_softc = sc_if; 1162 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1163 ifp->if_ioctl = msk_ioctl; 1164 ifp->if_start = msk_start; 1165 ifp->if_stop = msk_stop; 1166 ifp->if_init = msk_init; 1167 ifp->if_watchdog = msk_watchdog; 1168 ifp->if_baudrate = 1000000000; 1169 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1170 IFQ_SET_READY(&ifp->if_snd); 1171 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1172 1173 msk_reset(sc_if); 1174 1175 /* 1176 * Do miibus setup. 1177 */ 1178 msk_init_yukon(sc_if); 1179 1180 DPRINTFN(2, ("msk_attach: 1\n")); 1181 1182 sc_if->sk_mii.mii_ifp = ifp; 1183 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1184 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1185 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1186 1187 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1188 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1189 ether_mediachange, ether_mediastatus); 1190 mii_flags = MIIF_DOPAUSE; 1191 if (sc->sk_fibertype) 1192 mii_flags |= MIIF_HAVEFIBER; 1193 mii_attach(self, &sc_if->sk_mii, 0xffffffff, 0, 1194 MII_OFFSET_ANY, mii_flags); 1195 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1196 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1197 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1198 0, NULL); 1199 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1200 } else 1201 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1202 1203 callout_init(&sc_if->sk_tick_ch, 0); 1204 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1205 callout_schedule(&sc_if->sk_tick_ch, hz); 1206 1207 callout_init(&sc_if->sk_tick_rx, 0); 1208 callout_setfunc(&sc_if->sk_tick_rx, msk_fill_rx_tick, sc_if); 1209 1210 /* 1211 * Call MI attach routines. 1212 */ 1213 if_attach(ifp); 1214 if_deferred_start_init(ifp, NULL); 1215 ether_ifattach(ifp, sc_if->sk_enaddr); 1216 1217 if (pmf_device_register(self, NULL, msk_resume)) 1218 pmf_class_network_register(self, ifp); 1219 else 1220 aprint_error_dev(self, "couldn't establish power handler\n"); 1221 1222 if (sc->rnd_attached++ == 0) { 1223 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1224 RND_TYPE_NET, RND_FLAG_DEFAULT); 1225 } 1226 1227 DPRINTFN(2, ("msk_attach: end\n")); 1228 return; 1229 1230 fail_3: 1231 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1232 fail_2: 1233 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1234 fail_1: 1235 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1236 fail: 1237 sc->sk_if[sa->skc_port] = NULL; 1238 } 1239 1240 int 1241 msk_detach(device_t self, int flags) 1242 { 1243 struct sk_if_softc *sc_if = device_private(self); 1244 struct sk_softc *sc = sc_if->sk_softc; 1245 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1246 1247 if (sc->sk_if[sc_if->sk_port] == NULL) 1248 return (0); 1249 1250 msk_stop(ifp, 0); 1251 1252 if (--sc->rnd_attached == 0) 1253 rnd_detach_source(&sc->rnd_source); 1254 1255 callout_halt(&sc_if->sk_tick_ch, NULL); 1256 callout_destroy(&sc_if->sk_tick_ch); 1257 1258 callout_halt(&sc_if->sk_tick_rx, NULL); 1259 callout_destroy(&sc_if->sk_tick_rx); 1260 1261 /* Detach any PHYs we might have. */ 1262 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1263 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1264 1265 /* Delete any remaining media. */ 1266 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY); 1267 1268 pmf_device_deregister(self); 1269 1270 ether_ifdetach(ifp); 1271 if_detach(ifp); 1272 1273 msk_free_jumbo_mem(sc_if); 1274 1275 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_rdata, 1276 sizeof(struct msk_ring_data)); 1277 bus_dmamem_free(sc->sc_dmatag, 1278 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1279 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1280 sc->sk_if[sc_if->sk_port] = NULL; 1281 1282 return (0); 1283 } 1284 1285 int 1286 mskcprint(void *aux, const char *pnp) 1287 { 1288 struct skc_attach_args *sa = aux; 1289 1290 if (pnp) 1291 aprint_normal("msk port %c at %s", 1292 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1293 else 1294 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1295 return (UNCONF); 1296 } 1297 1298 /* 1299 * Attach the interface. Allocate softc structures, do ifmedia 1300 * setup and ethernet/BPF attach. 1301 */ 1302 void 1303 mskc_attach(device_t parent, device_t self, void *aux) 1304 { 1305 struct sk_softc *sc = device_private(self); 1306 struct pci_attach_args *pa = aux; 1307 struct skc_attach_args skca; 1308 pci_chipset_tag_t pc = pa->pa_pc; 1309 pcireg_t command, memtype; 1310 pci_intr_handle_t ih; 1311 const char *intrstr = NULL; 1312 bus_size_t size; 1313 int rc, sk_nodenum; 1314 u_int8_t hw, pmd; 1315 const char *revstr = NULL; 1316 const struct sysctlnode *node; 1317 void *kva; 1318 char intrbuf[PCI_INTRSTR_LEN]; 1319 1320 DPRINTFN(2, ("begin mskc_attach\n")); 1321 1322 sc->sk_dev = self; 1323 /* 1324 * Handle power management nonsense. 1325 */ 1326 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1327 1328 if (command == 0x01) { 1329 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1330 if (command & SK_PSTATE_MASK) { 1331 u_int32_t iobase, membase, irq; 1332 1333 /* Save important PCI config data. */ 1334 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1335 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1336 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1337 1338 /* Reset the power state. */ 1339 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1340 "mode -- setting to D0\n", 1341 command & SK_PSTATE_MASK); 1342 command &= 0xFFFFFFFC; 1343 pci_conf_write(pc, pa->pa_tag, 1344 SK_PCI_PWRMGMTCTRL, command); 1345 1346 /* Restore PCI config data. */ 1347 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1348 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1349 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1350 } 1351 } 1352 1353 /* 1354 * Map control/status registers. 1355 */ 1356 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1357 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1358 &sc->sk_bhandle, NULL, &size)) { 1359 aprint_error(": can't map mem space\n"); 1360 return; 1361 } 1362 1363 sc->sc_dmatag = pa->pa_dmat; 1364 1365 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1366 command |= PCI_COMMAND_MASTER_ENABLE; 1367 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1368 1369 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1370 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1371 1372 /* bail out here if chip is not recognized */ 1373 if (!(SK_IS_YUKON2(sc))) { 1374 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1375 goto fail_1; 1376 } 1377 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1378 1379 /* Allocate interrupt */ 1380 if (pci_intr_map(pa, &ih)) { 1381 aprint_error(": couldn't map interrupt\n"); 1382 goto fail_1; 1383 } 1384 1385 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1386 sc->sk_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, msk_intr, 1387 sc, device_xname(sc->sk_dev)); 1388 if (sc->sk_intrhand == NULL) { 1389 aprint_error(": couldn't establish interrupt"); 1390 if (intrstr != NULL) 1391 aprint_error(" at %s", intrstr); 1392 aprint_error("\n"); 1393 goto fail_1; 1394 } 1395 sc->sk_pc = pc; 1396 1397 if (bus_dmamem_alloc(sc->sc_dmatag, 1398 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1399 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1400 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, BUS_DMA_NOWAIT)) { 1401 aprint_error(": can't alloc status buffers\n"); 1402 goto fail_2; 1403 } 1404 1405 if (bus_dmamem_map(sc->sc_dmatag, 1406 &sc->sk_status_seg, sc->sk_status_nseg, 1407 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1408 &kva, BUS_DMA_NOWAIT)) { 1409 aprint_error(": can't map dma buffers (%zu bytes)\n", 1410 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1411 goto fail_3; 1412 } 1413 if (bus_dmamap_create(sc->sc_dmatag, 1414 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1415 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1416 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1417 aprint_error(": can't create dma map\n"); 1418 goto fail_4; 1419 } 1420 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1421 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1422 NULL, BUS_DMA_NOWAIT)) { 1423 aprint_error(": can't load dma map\n"); 1424 goto fail_5; 1425 } 1426 sc->sk_status_ring = (struct msk_status_desc *)kva; 1427 1428 sc->sk_int_mod = SK_IM_DEFAULT; 1429 sc->sk_int_mod_pending = 0; 1430 1431 /* Reset the adapter. */ 1432 mskc_reset(sc); 1433 1434 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1435 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1436 1437 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1438 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1439 sc->sk_fibertype = 1; 1440 1441 switch (sc->sk_type) { 1442 case SK_YUKON_XL: 1443 sc->sk_name = "Yukon-2 XL"; 1444 break; 1445 case SK_YUKON_EC_U: 1446 sc->sk_name = "Yukon-2 EC Ultra"; 1447 break; 1448 case SK_YUKON_EX: 1449 sc->sk_name = "Yukon-2 Extreme"; 1450 break; 1451 case SK_YUKON_EC: 1452 sc->sk_name = "Yukon-2 EC"; 1453 break; 1454 case SK_YUKON_FE: 1455 sc->sk_name = "Yukon-2 FE"; 1456 break; 1457 case SK_YUKON_FE_P: 1458 sc->sk_name = "Yukon-2 FE+"; 1459 break; 1460 case SK_YUKON_SUPR: 1461 sc->sk_name = "Yukon-2 Supreme"; 1462 break; 1463 case SK_YUKON_ULTRA2: 1464 sc->sk_name = "Yukon-2 Ultra 2"; 1465 break; 1466 case SK_YUKON_OPTIMA: 1467 sc->sk_name = "Yukon-2 Optima"; 1468 break; 1469 case SK_YUKON_PRM: 1470 sc->sk_name = "Yukon-2 Optima Prime"; 1471 break; 1472 case SK_YUKON_OPTIMA2: 1473 sc->sk_name = "Yukon-2 Optima 2"; 1474 break; 1475 default: 1476 sc->sk_name = "Yukon (Unknown)"; 1477 } 1478 1479 if (sc->sk_type == SK_YUKON_XL) { 1480 switch (sc->sk_rev) { 1481 case SK_YUKON_XL_REV_A0: 1482 revstr = "A0"; 1483 break; 1484 case SK_YUKON_XL_REV_A1: 1485 revstr = "A1"; 1486 break; 1487 case SK_YUKON_XL_REV_A2: 1488 revstr = "A2"; 1489 break; 1490 case SK_YUKON_XL_REV_A3: 1491 revstr = "A3"; 1492 break; 1493 default: 1494 break; 1495 } 1496 } 1497 1498 if (sc->sk_type == SK_YUKON_EC) { 1499 switch (sc->sk_rev) { 1500 case SK_YUKON_EC_REV_A1: 1501 revstr = "A1"; 1502 break; 1503 case SK_YUKON_EC_REV_A2: 1504 revstr = "A2"; 1505 break; 1506 case SK_YUKON_EC_REV_A3: 1507 revstr = "A3"; 1508 break; 1509 default: 1510 break; 1511 } 1512 } 1513 1514 if (sc->sk_type == SK_YUKON_FE) { 1515 switch (sc->sk_rev) { 1516 case SK_YUKON_FE_REV_A1: 1517 revstr = "A1"; 1518 break; 1519 case SK_YUKON_FE_REV_A2: 1520 revstr = "A2"; 1521 break; 1522 default: 1523 break; 1524 } 1525 } 1526 1527 if (sc->sk_type == SK_YUKON_EC_U) { 1528 switch (sc->sk_rev) { 1529 case SK_YUKON_EC_U_REV_A0: 1530 revstr = "A0"; 1531 break; 1532 case SK_YUKON_EC_U_REV_A1: 1533 revstr = "A1"; 1534 break; 1535 case SK_YUKON_EC_U_REV_B0: 1536 revstr = "B0"; 1537 break; 1538 case SK_YUKON_EC_U_REV_B1: 1539 revstr = "B1"; 1540 break; 1541 default: 1542 break; 1543 } 1544 } 1545 1546 if (sc->sk_type == SK_YUKON_FE) { 1547 switch (sc->sk_rev) { 1548 case SK_YUKON_FE_REV_A1: 1549 revstr = "A1"; 1550 break; 1551 case SK_YUKON_FE_REV_A2: 1552 revstr = "A2"; 1553 break; 1554 default: 1555 ; 1556 } 1557 } 1558 1559 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1560 revstr = "A0"; 1561 1562 if (sc->sk_type == SK_YUKON_EX) { 1563 switch (sc->sk_rev) { 1564 case SK_YUKON_EX_REV_A0: 1565 revstr = "A0"; 1566 break; 1567 case SK_YUKON_EX_REV_B0: 1568 revstr = "B0"; 1569 break; 1570 default: 1571 ; 1572 } 1573 } 1574 1575 if (sc->sk_type == SK_YUKON_SUPR) { 1576 switch (sc->sk_rev) { 1577 case SK_YUKON_SUPR_REV_A0: 1578 revstr = "A0"; 1579 break; 1580 case SK_YUKON_SUPR_REV_B0: 1581 revstr = "B0"; 1582 break; 1583 case SK_YUKON_SUPR_REV_B1: 1584 revstr = "B1"; 1585 break; 1586 default: 1587 ; 1588 } 1589 } 1590 1591 if (sc->sk_type == SK_YUKON_PRM) { 1592 switch (sc->sk_rev) { 1593 case SK_YUKON_PRM_REV_Z1: 1594 revstr = "Z1"; 1595 break; 1596 case SK_YUKON_PRM_REV_A0: 1597 revstr = "A0"; 1598 break; 1599 default: 1600 ; 1601 } 1602 } 1603 1604 /* Announce the product name. */ 1605 aprint_normal(", %s", sc->sk_name); 1606 if (revstr != NULL) 1607 aprint_normal(" rev. %s", revstr); 1608 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1609 1610 sc->sk_macs = 1; 1611 1612 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1613 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1614 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1615 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1616 sc->sk_macs++; 1617 } 1618 1619 skca.skc_port = SK_PORT_A; 1620 skca.skc_type = sc->sk_type; 1621 skca.skc_rev = sc->sk_rev; 1622 (void)config_found(sc->sk_dev, &skca, mskcprint); 1623 1624 if (sc->sk_macs > 1) { 1625 skca.skc_port = SK_PORT_B; 1626 skca.skc_type = sc->sk_type; 1627 skca.skc_rev = sc->sk_rev; 1628 (void)config_found(sc->sk_dev, &skca, mskcprint); 1629 } 1630 1631 /* Turn on the 'driver is loaded' LED. */ 1632 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1633 1634 /* skc sysctl setup */ 1635 1636 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1637 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1638 SYSCTL_DESCR("mskc per-controller controls"), 1639 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1640 CTL_EOL)) != 0) { 1641 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1642 goto fail_6; 1643 } 1644 1645 sk_nodenum = node->sysctl_num; 1646 1647 /* interrupt moderation time in usecs */ 1648 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1649 CTLFLAG_READWRITE, 1650 CTLTYPE_INT, "int_mod", 1651 SYSCTL_DESCR("msk interrupt moderation timer"), 1652 msk_sysctl_handler, 0, (void *)sc, 1653 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1654 CTL_EOL)) != 0) { 1655 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1656 goto fail_6; 1657 } 1658 1659 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1660 aprint_error_dev(self, "couldn't establish power handler\n"); 1661 1662 return; 1663 1664 fail_6: 1665 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1666 fail_4: 1667 bus_dmamem_unmap(sc->sc_dmatag, kva, 1668 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1669 fail_3: 1670 bus_dmamem_free(sc->sc_dmatag, 1671 &sc->sk_status_seg, sc->sk_status_nseg); 1672 sc->sk_status_nseg = 0; 1673 fail_5: 1674 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1675 fail_2: 1676 pci_intr_disestablish(pc, sc->sk_intrhand); 1677 sc->sk_intrhand = NULL; 1678 fail_1: 1679 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1680 sc->sk_bsize = 0; 1681 } 1682 1683 int 1684 mskc_detach(device_t self, int flags) 1685 { 1686 struct sk_softc *sc = device_private(self); 1687 int rv; 1688 1689 if (sc->sk_intrhand) 1690 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1691 1692 rv = config_detach_children(self, flags); 1693 if (rv != 0) 1694 return (rv); 1695 1696 if (sc->sk_status_nseg > 0) { 1697 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1698 bus_dmamem_unmap(sc->sc_dmatag, sc->sk_status_ring, 1699 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1700 bus_dmamem_free(sc->sc_dmatag, 1701 &sc->sk_status_seg, sc->sk_status_nseg); 1702 } 1703 1704 if (sc->sk_bsize > 0) 1705 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1706 1707 return(0); 1708 } 1709 1710 int 1711 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1712 { 1713 struct sk_softc *sc = sc_if->sk_softc; 1714 struct msk_tx_desc *f = NULL; 1715 u_int32_t frag, cur; 1716 int i; 1717 struct sk_txmap_entry *entry; 1718 bus_dmamap_t txmap; 1719 1720 DPRINTFN(2, ("msk_encap\n")); 1721 1722 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1723 if (entry == NULL) { 1724 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1725 return (ENOBUFS); 1726 } 1727 txmap = entry->dmamap; 1728 1729 cur = frag = *txidx; 1730 1731 #ifdef MSK_DEBUG 1732 if (mskdebug >= 2) 1733 msk_dump_mbuf(m_head); 1734 #endif 1735 1736 /* 1737 * Start packing the mbufs in this chain into 1738 * the fragment pointers. Stop when we run out 1739 * of fragments or hit the end of the mbuf chain. 1740 */ 1741 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1742 BUS_DMA_NOWAIT)) { 1743 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1744 return (ENOBUFS); 1745 } 1746 1747 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1748 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1749 bus_dmamap_unload(sc->sc_dmatag, txmap); 1750 return (ENOBUFS); 1751 } 1752 1753 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1754 1755 /* Sync the DMA map. */ 1756 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1757 BUS_DMASYNC_PREWRITE); 1758 1759 for (i = 0; i < txmap->dm_nsegs; i++) { 1760 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1761 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1762 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1763 f->sk_ctl = 0; 1764 if (i == 0) 1765 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1766 else 1767 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1768 cur = frag; 1769 SK_INC(frag, MSK_TX_RING_CNT); 1770 } 1771 1772 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1773 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1774 1775 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1776 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1777 1778 /* Sync descriptors before handing to chip */ 1779 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1780 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1781 1782 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1783 1784 /* Sync first descriptor to hand it off */ 1785 MSK_CDTXSYNC(sc_if, *txidx, 1, 1786 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1787 1788 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1789 1790 #ifdef MSK_DEBUG 1791 if (mskdebug >= 2) { 1792 struct msk_tx_desc *le; 1793 u_int32_t idx; 1794 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1795 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1796 msk_dump_txdesc(le, idx); 1797 } 1798 } 1799 #endif 1800 1801 *txidx = frag; 1802 1803 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1804 1805 return (0); 1806 } 1807 1808 void 1809 msk_start(struct ifnet *ifp) 1810 { 1811 struct sk_if_softc *sc_if = ifp->if_softc; 1812 struct mbuf *m_head = NULL; 1813 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1814 int pkts = 0; 1815 1816 DPRINTFN(2, ("msk_start\n")); 1817 1818 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1819 IFQ_POLL(&ifp->if_snd, m_head); 1820 if (m_head == NULL) 1821 break; 1822 1823 /* 1824 * Pack the data into the transmit ring. If we 1825 * don't have room, set the OACTIVE flag and wait 1826 * for the NIC to drain the ring. 1827 */ 1828 if (msk_encap(sc_if, m_head, &idx)) { 1829 ifp->if_flags |= IFF_OACTIVE; 1830 break; 1831 } 1832 1833 /* now we are committed to transmit the packet */ 1834 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1835 pkts++; 1836 1837 /* 1838 * If there's a BPF listener, bounce a copy of this frame 1839 * to him. 1840 */ 1841 bpf_mtap(ifp, m_head, BPF_D_OUT); 1842 } 1843 if (pkts == 0) 1844 return; 1845 1846 /* Transmit */ 1847 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1848 sc_if->sk_cdata.sk_tx_prod = idx; 1849 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1850 1851 /* Set a timeout in case the chip goes out to lunch. */ 1852 ifp->if_timer = 5; 1853 } 1854 } 1855 1856 void 1857 msk_watchdog(struct ifnet *ifp) 1858 { 1859 struct sk_if_softc *sc_if = ifp->if_softc; 1860 1861 /* 1862 * Reclaim first as there is a possibility of losing Tx completion 1863 * interrupts. 1864 */ 1865 msk_txeof(sc_if); 1866 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1867 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1868 1869 ifp->if_oerrors++; 1870 1871 /* XXX Resets both ports; we shouldn't do that. */ 1872 mskc_reset(sc_if->sk_softc); 1873 msk_reset(sc_if); 1874 msk_init(ifp); 1875 } 1876 } 1877 1878 static bool 1879 mskc_suspend(device_t dv, const pmf_qual_t *qual) 1880 { 1881 struct sk_softc *sc = device_private(dv); 1882 1883 DPRINTFN(2, ("mskc_suspend\n")); 1884 1885 /* Turn off the 'driver is loaded' LED. */ 1886 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1887 1888 return true; 1889 } 1890 1891 static bool 1892 mskc_resume(device_t dv, const pmf_qual_t *qual) 1893 { 1894 struct sk_softc *sc = device_private(dv); 1895 1896 DPRINTFN(2, ("mskc_resume\n")); 1897 1898 mskc_reset(sc); 1899 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1900 1901 return true; 1902 } 1903 1904 static __inline int 1905 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1906 { 1907 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1908 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1909 YU_RXSTAT_JABBER)) != 0 || 1910 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1911 YU_RXSTAT_BYTES(stat) != len) 1912 return (0); 1913 1914 return (1); 1915 } 1916 1917 void 1918 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1919 { 1920 struct sk_softc *sc = sc_if->sk_softc; 1921 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1922 struct mbuf *m; 1923 struct sk_chain *cur_rx; 1924 int cur, total_len = len; 1925 bus_dmamap_t dmamap; 1926 1927 DPRINTFN(2, ("msk_rxeof\n")); 1928 1929 cur = sc_if->sk_cdata.sk_rx_cons; 1930 1931 /* Sync the descriptor */ 1932 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1933 1934 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1935 if (cur_rx->sk_mbuf == NULL) 1936 return; 1937 1938 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1939 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1940 sc_if->sk_cdata.sk_rx_cnt--; 1941 1942 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1943 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1944 1945 m = cur_rx->sk_mbuf; 1946 cur_rx->sk_mbuf = NULL; 1947 1948 if (total_len < SK_MIN_FRAMELEN || 1949 total_len > ETHER_MAX_LEN_JUMBO || 1950 msk_rxvalid(sc, rxstat, total_len) == 0) { 1951 ifp->if_ierrors++; 1952 m_freem(m); 1953 return; 1954 } 1955 1956 m_set_rcvif(m, ifp); 1957 m->m_pkthdr.len = m->m_len = total_len; 1958 1959 /* pass it on. */ 1960 if_percpuq_enqueue(ifp->if_percpuq, m); 1961 } 1962 1963 void 1964 msk_txeof(struct sk_if_softc *sc_if) 1965 { 1966 struct sk_softc *sc = sc_if->sk_softc; 1967 struct msk_tx_desc *cur_tx; 1968 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1969 u_int32_t idx, reg, sk_ctl; 1970 struct sk_txmap_entry *entry; 1971 1972 DPRINTFN(2, ("msk_txeof\n")); 1973 1974 if (sc_if->sk_port == SK_PORT_A) 1975 reg = SK_STAT_BMU_TXA1_RIDX; 1976 else 1977 reg = SK_STAT_BMU_TXA2_RIDX; 1978 1979 /* 1980 * Go through our tx ring and free mbufs for those 1981 * frames that have been sent. 1982 */ 1983 idx = sc_if->sk_cdata.sk_tx_cons; 1984 while (idx != sk_win_read_2(sc, reg)) { 1985 MSK_CDTXSYNC(sc_if, idx, 1, 1986 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1987 1988 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1989 sk_ctl = cur_tx->sk_ctl; 1990 #ifdef MSK_DEBUG 1991 if (mskdebug >= 2) 1992 msk_dump_txdesc(cur_tx, idx); 1993 #endif 1994 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1995 ifp->if_opackets++; 1996 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1997 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1998 1999 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2000 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2001 2002 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2003 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2004 2005 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2006 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2007 link); 2008 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2009 } 2010 sc_if->sk_cdata.sk_tx_cnt--; 2011 SK_INC(idx, MSK_TX_RING_CNT); 2012 } 2013 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2014 2015 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 2016 ifp->if_flags &= ~IFF_OACTIVE; 2017 2018 sc_if->sk_cdata.sk_tx_cons = idx; 2019 } 2020 2021 void 2022 msk_fill_rx_ring(struct sk_if_softc *sc_if) 2023 { 2024 /* Make sure to not completely wrap around */ 2025 while (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT - 1)) { 2026 if (msk_newbuf(sc_if, 2027 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 2028 goto schedretry; 2029 } 2030 } 2031 2032 return; 2033 2034 schedretry: 2035 /* Try later */ 2036 callout_schedule(&sc_if->sk_tick_rx, hz/2); 2037 } 2038 2039 static void 2040 msk_fill_rx_tick(void *xsc_if) 2041 { 2042 struct sk_if_softc *sc_if = xsc_if; 2043 int s, rx_prod; 2044 2045 KASSERT(KERNEL_LOCKED_P()); /* XXXSMP */ 2046 2047 s = splnet(); 2048 rx_prod = sc_if->sk_cdata.sk_rx_prod; 2049 msk_fill_rx_ring(sc_if); 2050 if (rx_prod != sc_if->sk_cdata.sk_rx_prod) { 2051 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2052 sc_if->sk_cdata.sk_rx_prod); 2053 } 2054 splx(s); 2055 } 2056 2057 void 2058 msk_tick(void *xsc_if) 2059 { 2060 struct sk_if_softc *sc_if = xsc_if; 2061 struct mii_data *mii = &sc_if->sk_mii; 2062 int s; 2063 2064 s = splnet(); 2065 mii_tick(mii); 2066 splx(s); 2067 2068 callout_schedule(&sc_if->sk_tick_ch, hz); 2069 } 2070 2071 void 2072 msk_intr_yukon(struct sk_if_softc *sc_if) 2073 { 2074 u_int8_t status; 2075 2076 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2077 /* RX overrun */ 2078 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2079 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2080 SK_RFCTL_RX_FIFO_OVER); 2081 } 2082 /* TX underrun */ 2083 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2084 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 2085 SK_TFCTL_TX_FIFO_UNDER); 2086 } 2087 2088 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 2089 } 2090 2091 int 2092 msk_intr(void *xsc) 2093 { 2094 struct sk_softc *sc = xsc; 2095 struct sk_if_softc *sc_if; 2096 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2097 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2098 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2099 int claimed = 0; 2100 u_int32_t status; 2101 struct msk_status_desc *cur_st; 2102 2103 status = CSR_READ_4(sc, SK_Y2_ISSR2); 2104 if (status == 0xffffffff) 2105 return (0); 2106 if (status == 0) { 2107 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2108 return (0); 2109 } 2110 2111 status = CSR_READ_4(sc, SK_ISR); 2112 2113 if (sc_if0 != NULL) 2114 ifp0 = &sc_if0->sk_ethercom.ec_if; 2115 if (sc_if1 != NULL) 2116 ifp1 = &sc_if1->sk_ethercom.ec_if; 2117 2118 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 2119 (ifp0->if_flags & IFF_RUNNING)) { 2120 msk_intr_yukon(sc_if0); 2121 } 2122 2123 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 2124 (ifp1->if_flags & IFF_RUNNING)) { 2125 msk_intr_yukon(sc_if1); 2126 } 2127 2128 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2129 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2130 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2131 2132 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 2133 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 2134 switch (cur_st->sk_opcode) { 2135 case SK_Y2_STOPC_RXSTAT: 2136 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 2137 msk_rxeof(sc_if, letoh16(cur_st->sk_len), 2138 letoh32(cur_st->sk_status)); 2139 if (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 2140 msk_fill_rx_tick(sc_if); 2141 break; 2142 case SK_Y2_STOPC_TXSTAT: 2143 if (sc_if0) 2144 msk_txeof(sc_if0); 2145 if (sc_if1) 2146 msk_txeof(sc_if1); 2147 break; 2148 default: 2149 aprint_error("opcode=0x%x\n", cur_st->sk_opcode); 2150 break; 2151 } 2152 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 2153 2154 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2155 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2156 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2157 } 2158 2159 if (status & SK_Y2_IMR_BMU) { 2160 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 2161 claimed = 1; 2162 } 2163 2164 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2165 2166 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2167 if_schedule_deferred_start(ifp0); 2168 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2169 if_schedule_deferred_start(ifp1); 2170 2171 KASSERT(sc->rnd_attached > 0); 2172 rnd_add_uint32(&sc->rnd_source, status); 2173 2174 if (sc->sk_int_mod_pending) 2175 msk_update_int_mod(sc, 1); 2176 2177 return claimed; 2178 } 2179 2180 void 2181 msk_init_yukon(struct sk_if_softc *sc_if) 2182 { 2183 u_int32_t v; 2184 u_int16_t reg; 2185 struct sk_softc *sc; 2186 int i; 2187 2188 sc = sc_if->sk_softc; 2189 2190 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 2191 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2192 2193 DPRINTFN(6, ("msk_init_yukon: 1\n")); 2194 2195 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 2196 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2197 2198 DPRINTFN(6, ("msk_init_yukon: 3\n")); 2199 2200 /* unused read of the interrupt source register */ 2201 DPRINTFN(6, ("msk_init_yukon: 4\n")); 2202 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2203 2204 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2205 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2206 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2207 2208 /* MIB Counter Clear Mode set */ 2209 reg |= YU_PAR_MIB_CLR; 2210 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2211 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2212 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2213 2214 /* MIB Counter Clear Mode clear */ 2215 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2216 reg &= ~YU_PAR_MIB_CLR; 2217 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2218 2219 /* receive control reg */ 2220 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2221 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2222 2223 /* transmit control register */ 2224 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2225 2226 /* transmit flow control register */ 2227 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2228 2229 /* transmit parameter register */ 2230 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2231 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2232 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2233 2234 /* serial mode register */ 2235 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2236 reg = YU_SMR_DATA_BLIND(0x1c) | 2237 YU_SMR_MFL_VLAN | 2238 YU_SMR_IPG_DATA(0x1e); 2239 2240 if (sc->sk_type != SK_YUKON_FE && 2241 sc->sk_type != SK_YUKON_FE_P) 2242 reg |= YU_SMR_MFL_JUMBO; 2243 2244 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2245 2246 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2247 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2248 /* msk_attach calls me before ether_ifattach so check null */ 2249 if (ifp != NULL && ifp->if_sadl != NULL) 2250 memcpy(sc_if->sk_enaddr, CLLADDR(ifp->if_sadl), 2251 sizeof(sc_if->sk_enaddr)); 2252 /* Setup Yukon's address */ 2253 for (i = 0; i < 3; i++) { 2254 /* Write Source Address 1 (unicast filter) */ 2255 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2256 sc_if->sk_enaddr[i * 2] | 2257 sc_if->sk_enaddr[i * 2 + 1] << 8); 2258 } 2259 2260 for (i = 0; i < 3; i++) { 2261 reg = sk_win_read_2(sc_if->sk_softc, 2262 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2263 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2264 } 2265 2266 /* Set promiscuous mode */ 2267 msk_setpromisc(sc_if); 2268 2269 /* Set multicast filter */ 2270 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2271 msk_setmulti(sc_if); 2272 2273 /* enable interrupt mask for counter overflows */ 2274 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2275 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2276 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2277 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2278 2279 /* Configure RX MAC FIFO Flush Mask */ 2280 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2281 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2282 YU_RXSTAT_JABBER; 2283 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2284 2285 /* Configure RX MAC FIFO */ 2286 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2287 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2288 SK_RFCTL_FIFO_FLUSH_ON); 2289 2290 /* Increase flush threshold to 64 bytes */ 2291 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2292 SK_RFCTL_FIFO_THRESHOLD + 1); 2293 2294 /* Configure TX MAC FIFO */ 2295 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2296 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2297 2298 #if 1 2299 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2300 #endif 2301 DPRINTFN(6, ("msk_init_yukon: end\n")); 2302 } 2303 2304 /* 2305 * Note that to properly initialize any part of the GEnesis chip, 2306 * you first have to take it out of reset mode. 2307 */ 2308 int 2309 msk_init(struct ifnet *ifp) 2310 { 2311 struct sk_if_softc *sc_if = ifp->if_softc; 2312 struct sk_softc *sc = sc_if->sk_softc; 2313 int rc = 0, s; 2314 uint32_t imr, imtimer_ticks; 2315 2316 2317 DPRINTFN(2, ("msk_init\n")); 2318 2319 s = splnet(); 2320 2321 /* Cancel pending I/O and free all RX/TX buffers. */ 2322 msk_stop(ifp, 1); 2323 2324 /* Configure I2C registers */ 2325 2326 /* Configure XMAC(s) */ 2327 msk_init_yukon(sc_if); 2328 if ((rc = ether_mediachange(ifp)) != 0) 2329 goto out; 2330 2331 /* Configure transmit arbiter(s) */ 2332 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2333 #if 0 2334 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2335 #endif 2336 2337 /* Configure RAMbuffers */ 2338 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2339 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2340 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2341 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2342 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2343 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2344 2345 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2346 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2347 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2348 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2349 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2350 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2351 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2352 2353 /* Configure BMUs */ 2354 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2355 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2356 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2357 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2358 2359 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2360 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2361 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2362 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2363 2364 /* Make sure the sync transmit queue is disabled. */ 2365 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2366 2367 /* Init descriptors */ 2368 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2369 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2370 "memory for rx buffers\n"); 2371 msk_stop(ifp, 1); 2372 splx(s); 2373 return ENOBUFS; 2374 } 2375 2376 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2377 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2378 "memory for tx buffers\n"); 2379 msk_stop(ifp, 1); 2380 splx(s); 2381 return ENOBUFS; 2382 } 2383 2384 /* Set interrupt moderation if changed via sysctl. */ 2385 switch (sc->sk_type) { 2386 case SK_YUKON_EC: 2387 case SK_YUKON_EC_U: 2388 case SK_YUKON_EX: 2389 case SK_YUKON_SUPR: 2390 case SK_YUKON_ULTRA2: 2391 case SK_YUKON_OPTIMA: 2392 case SK_YUKON_PRM: 2393 case SK_YUKON_OPTIMA2: 2394 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2395 break; 2396 case SK_YUKON_FE: 2397 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2398 break; 2399 case SK_YUKON_FE_P: 2400 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 2401 break; 2402 case SK_YUKON_XL: 2403 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2404 break; 2405 default: 2406 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2407 } 2408 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2409 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2410 sk_win_write_4(sc, SK_IMTIMERINIT, 2411 SK_IM_USECS(sc->sk_int_mod)); 2412 aprint_verbose_dev(sc->sk_dev, 2413 "interrupt moderation is %d us\n", sc->sk_int_mod); 2414 } 2415 2416 /* Initialize prefetch engine. */ 2417 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2418 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2419 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2420 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2421 MSK_RX_RING_ADDR(sc_if, 0)); 2422 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2423 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2424 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2425 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2426 2427 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2428 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2429 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2430 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2431 MSK_TX_RING_ADDR(sc_if, 0)); 2432 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2433 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2434 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2435 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2436 2437 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2438 sc_if->sk_cdata.sk_rx_prod); 2439 2440 /* Configure interrupt handling */ 2441 if (sc_if->sk_port == SK_PORT_A) 2442 sc->sk_intrmask |= SK_Y2_INTRS1; 2443 else 2444 sc->sk_intrmask |= SK_Y2_INTRS2; 2445 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2446 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2447 2448 ifp->if_flags |= IFF_RUNNING; 2449 ifp->if_flags &= ~IFF_OACTIVE; 2450 2451 callout_schedule(&sc_if->sk_tick_ch, hz); 2452 2453 out: 2454 splx(s); 2455 return rc; 2456 } 2457 2458 /* 2459 * Note: the logic of second parameter is inverted compared to OpenBSD 2460 * code, since this code uses the function as if_stop hook too. 2461 */ 2462 void 2463 msk_stop(struct ifnet *ifp, int disable) 2464 { 2465 struct sk_if_softc *sc_if = ifp->if_softc; 2466 struct sk_softc *sc = sc_if->sk_softc; 2467 struct sk_txmap_entry *dma; 2468 int i; 2469 2470 DPRINTFN(2, ("msk_stop\n")); 2471 2472 callout_stop(&sc_if->sk_tick_ch); 2473 callout_stop(&sc_if->sk_tick_rx); 2474 2475 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2476 2477 /* Stop transfer of Tx descriptors */ 2478 2479 /* Stop transfer of Rx descriptors */ 2480 2481 if (disable) { 2482 /* Turn off various components of this interface. */ 2483 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2484 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2485 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2486 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2487 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2488 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2489 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2490 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2491 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2492 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2493 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2494 2495 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2496 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2497 2498 /* Disable interrupts */ 2499 if (sc_if->sk_port == SK_PORT_A) 2500 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2501 else 2502 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2503 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2504 } 2505 2506 /* Free RX and TX mbufs still in the queues. */ 2507 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2508 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2509 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2510 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2511 } 2512 } 2513 2514 sc_if->sk_cdata.sk_rx_prod = 0; 2515 sc_if->sk_cdata.sk_rx_cons = 0; 2516 sc_if->sk_cdata.sk_rx_cnt = 0; 2517 2518 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2519 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2520 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2521 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2522 #if 1 2523 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2524 sc_if->sk_cdata.sk_tx_map[i], link); 2525 sc_if->sk_cdata.sk_tx_map[i] = 0; 2526 #endif 2527 } 2528 } 2529 2530 #if 1 2531 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2532 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2533 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2534 free(dma, M_DEVBUF); 2535 } 2536 #endif 2537 } 2538 2539 CFATTACH_DECL3_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2540 mskc_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2541 2542 CFATTACH_DECL3_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2543 msk_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2544 2545 #ifdef MSK_DEBUG 2546 void 2547 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2548 { 2549 #define DESC_PRINT(X) \ 2550 if (X) \ 2551 printf("txdesc[%d]." #X "=%#x\n", \ 2552 idx, X); 2553 2554 DESC_PRINT(letoh32(le->sk_addr)); 2555 DESC_PRINT(letoh16(le->sk_len)); 2556 DESC_PRINT(le->sk_ctl); 2557 DESC_PRINT(le->sk_opcode); 2558 #undef DESC_PRINT 2559 } 2560 2561 void 2562 msk_dump_bytes(const char *data, int len) 2563 { 2564 int c, i, j; 2565 2566 for (i = 0; i < len; i += 16) { 2567 printf("%08x ", i); 2568 c = len - i; 2569 if (c > 16) c = 16; 2570 2571 for (j = 0; j < c; j++) { 2572 printf("%02x ", data[i + j] & 0xff); 2573 if ((j & 0xf) == 7 && j > 0) 2574 printf(" "); 2575 } 2576 2577 for (; j < 16; j++) 2578 printf(" "); 2579 printf(" "); 2580 2581 for (j = 0; j < c; j++) { 2582 int ch = data[i + j] & 0xff; 2583 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2584 } 2585 2586 printf("\n"); 2587 2588 if (c < 16) 2589 break; 2590 } 2591 } 2592 2593 void 2594 msk_dump_mbuf(struct mbuf *m) 2595 { 2596 int count = m->m_pkthdr.len; 2597 2598 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2599 2600 while (count > 0 && m) { 2601 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2602 m, m->m_data, m->m_len); 2603 msk_dump_bytes(mtod(m, char *), m->m_len); 2604 2605 count -= m->m_len; 2606 m = m->m_next; 2607 } 2608 } 2609 #endif 2610 2611 static int 2612 msk_sysctl_handler(SYSCTLFN_ARGS) 2613 { 2614 int error, t; 2615 struct sysctlnode node; 2616 struct sk_softc *sc; 2617 2618 node = *rnode; 2619 sc = node.sysctl_data; 2620 t = sc->sk_int_mod; 2621 node.sysctl_data = &t; 2622 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2623 if (error || newp == NULL) 2624 return error; 2625 2626 if (t < SK_IM_MIN || t > SK_IM_MAX) 2627 return EINVAL; 2628 2629 /* update the softc with sysctl-changed value, and mark 2630 for hardware update */ 2631 sc->sk_int_mod = t; 2632 sc->sk_int_mod_pending = 1; 2633 return 0; 2634 } 2635 2636 /* 2637 * Set up sysctl(3) MIB, hw.msk.* - Individual controllers will be 2638 * set up in mskc_attach() 2639 */ 2640 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2641 { 2642 int rc; 2643 const struct sysctlnode *node; 2644 2645 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2646 0, CTLTYPE_NODE, "msk", 2647 SYSCTL_DESCR("msk interface controls"), 2648 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2649 goto err; 2650 } 2651 2652 msk_root_num = node->sysctl_num; 2653 return; 2654 2655 err: 2656 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2657 } 2658
Indexes created Mon Sep 22 05:09:51 GMT 2025