if_msk.c revision 1.77
1 /* $NetBSD: if_msk.c,v 1.77 2018/09/12 13:52:36 jakllsch Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.79 2009/10/15 17:54:56 deraadt Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.77 2018/09/12 13:52:36 jakllsch Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/mutex.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/device.h> 66 #include <sys/queue.h> 67 #include <sys/callout.h> 68 #include <sys/sysctl.h> 69 #include <sys/endian.h> 70 #ifdef __NetBSD__ 71 #define letoh16 htole16 72 #define letoh32 htole32 73 #endif 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #include <net/if_media.h> 80 81 #include <net/bpf.h> 82 #include <sys/rndsource.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 #include <dev/mii/brgphyreg.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 92 #include <dev/pci/if_skreg.h> 93 #include <dev/pci/if_mskvar.h> 94 95 int mskc_probe(device_t, cfdata_t, void *); 96 void mskc_attach(device_t, device_t, void *); 97 int mskc_detach(device_t, int); 98 void mskc_reset(struct sk_softc *); 99 static bool mskc_suspend(device_t, const pmf_qual_t *); 100 static bool mskc_resume(device_t, const pmf_qual_t *); 101 int msk_probe(device_t, cfdata_t, void *); 102 void msk_attach(device_t, device_t, void *); 103 int msk_detach(device_t, int); 104 void msk_reset(struct sk_if_softc *); 105 int mskcprint(void *, const char *); 106 int msk_intr(void *); 107 void msk_intr_yukon(struct sk_if_softc *); 108 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 109 void msk_txeof(struct sk_if_softc *); 110 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 111 void msk_start(struct ifnet *); 112 int msk_ioctl(struct ifnet *, u_long, void *); 113 int msk_init(struct ifnet *); 114 void msk_init_yukon(struct sk_if_softc *); 115 void msk_stop(struct ifnet *, int); 116 void msk_watchdog(struct ifnet *); 117 int msk_newbuf(struct sk_if_softc *, bus_dmamap_t); 118 int msk_alloc_jumbo_mem(struct sk_if_softc *); 119 void *msk_jalloc(struct sk_if_softc *); 120 void msk_jfree(struct mbuf *, void *, size_t, void *); 121 int msk_init_rx_ring(struct sk_if_softc *); 122 int msk_init_tx_ring(struct sk_if_softc *); 123 void msk_fill_rx_ring(struct sk_if_softc *); 124 125 void msk_update_int_mod(struct sk_softc *, int); 126 127 int msk_miibus_readreg(device_t, int, int); 128 void msk_miibus_writereg(device_t, int, int, int); 129 void msk_miibus_statchg(struct ifnet *); 130 131 void msk_setmulti(struct sk_if_softc *); 132 void msk_setpromisc(struct sk_if_softc *); 133 void msk_tick(void *); 134 static void msk_fill_rx_tick(void *); 135 136 /* #define MSK_DEBUG 1 */ 137 #ifdef MSK_DEBUG 138 #define DPRINTF(x) if (mskdebug) printf x 139 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 140 int mskdebug = MSK_DEBUG; 141 142 void msk_dump_txdesc(struct msk_tx_desc *, int); 143 void msk_dump_mbuf(struct mbuf *); 144 void msk_dump_bytes(const char *, int); 145 #else 146 #define DPRINTF(x) 147 #define DPRINTFN(n,x) 148 #endif 149 150 static int msk_sysctl_handler(SYSCTLFN_PROTO); 151 static int msk_root_num; 152 153 /* supported device vendors */ 154 static const struct msk_product { 155 pci_vendor_id_t msk_vendor; 156 pci_product_id_t msk_product; 157 } msk_products[] = { 158 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 159 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 160 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 162 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 163 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8079 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 197 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 198 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 }, 199 { 0, 0 } 200 }; 201 202 static inline u_int32_t 203 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 204 { 205 return CSR_READ_4(sc, reg); 206 } 207 208 static inline u_int16_t 209 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 210 { 211 return CSR_READ_2(sc, reg); 212 } 213 214 static inline u_int8_t 215 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 216 { 217 return CSR_READ_1(sc, reg); 218 } 219 220 static inline void 221 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 222 { 223 CSR_WRITE_4(sc, reg, x); 224 } 225 226 static inline void 227 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 228 { 229 CSR_WRITE_2(sc, reg, x); 230 } 231 232 static inline void 233 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 234 { 235 CSR_WRITE_1(sc, reg, x); 236 } 237 238 int 239 msk_miibus_readreg(device_t dev, int phy, int reg) 240 { 241 struct sk_if_softc *sc_if = device_private(dev); 242 u_int16_t val; 243 int i; 244 245 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 246 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 247 248 for (i = 0; i < SK_TIMEOUT; i++) { 249 DELAY(1); 250 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 251 if (val & YU_SMICR_READ_VALID) 252 break; 253 } 254 255 if (i == SK_TIMEOUT) { 256 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 257 return (0); 258 } 259 260 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 261 SK_TIMEOUT)); 262 263 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 264 265 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 266 phy, reg, val)); 267 268 return (val); 269 } 270 271 void 272 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 273 { 274 struct sk_if_softc *sc_if = device_private(dev); 275 int i; 276 277 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 278 phy, reg, val)); 279 280 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 281 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 282 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 283 284 for (i = 0; i < SK_TIMEOUT; i++) { 285 DELAY(1); 286 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 287 break; 288 } 289 290 if (i == SK_TIMEOUT) 291 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 292 } 293 294 void 295 msk_miibus_statchg(struct ifnet *ifp) 296 { 297 struct sk_if_softc *sc_if = ifp->if_softc; 298 struct mii_data *mii = &sc_if->sk_mii; 299 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 300 int gpcr; 301 302 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 303 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 304 305 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 306 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 307 /* Set speed. */ 308 gpcr |= YU_GPCR_SPEED_DIS; 309 switch (IFM_SUBTYPE(mii->mii_media_active)) { 310 case IFM_1000_SX: 311 case IFM_1000_LX: 312 case IFM_1000_CX: 313 case IFM_1000_T: 314 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 315 break; 316 case IFM_100_TX: 317 gpcr |= YU_GPCR_SPEED; 318 break; 319 } 320 321 /* Set duplex. */ 322 gpcr |= YU_GPCR_DPLX_DIS; 323 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 324 gpcr |= YU_GPCR_DUPLEX; 325 326 /* Disable flow control. */ 327 gpcr |= YU_GPCR_FCTL_DIS; 328 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 329 } 330 331 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 332 333 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 334 SK_YU_READ_2(sc_if, YUKON_GPCR))); 335 } 336 337 void 338 msk_setmulti(struct sk_if_softc *sc_if) 339 { 340 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 341 u_int32_t hashes[2] = { 0, 0 }; 342 int h; 343 struct ethercom *ec = &sc_if->sk_ethercom; 344 struct ether_multi *enm; 345 struct ether_multistep step; 346 u_int16_t reg; 347 348 /* First, zot all the existing filters. */ 349 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 350 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 351 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 352 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 353 354 355 /* Now program new ones. */ 356 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 357 reg |= YU_RCR_UFLEN; 358 allmulti: 359 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 360 if ((ifp->if_flags & IFF_PROMISC) != 0) 361 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 362 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 363 hashes[0] = 0xFFFFFFFF; 364 hashes[1] = 0xFFFFFFFF; 365 } 366 } else { 367 /* First find the tail of the list. */ 368 ETHER_FIRST_MULTI(step, ec, enm); 369 while (enm != NULL) { 370 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 371 ETHER_ADDR_LEN)) { 372 ifp->if_flags |= IFF_ALLMULTI; 373 goto allmulti; 374 } 375 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 376 ((1 << SK_HASH_BITS) - 1); 377 if (h < 32) 378 hashes[0] |= (1 << h); 379 else 380 hashes[1] |= (1 << (h - 32)); 381 382 ETHER_NEXT_MULTI(step, enm); 383 } 384 reg |= YU_RCR_MUFLEN; 385 } 386 387 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 388 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 389 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 390 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 391 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 392 } 393 394 void 395 msk_setpromisc(struct sk_if_softc *sc_if) 396 { 397 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 398 399 if (ifp->if_flags & IFF_PROMISC) 400 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 401 YU_RCR_UFLEN | YU_RCR_MUFLEN); 402 else 403 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 404 YU_RCR_UFLEN | YU_RCR_MUFLEN); 405 } 406 407 int 408 msk_init_rx_ring(struct sk_if_softc *sc_if) 409 { 410 struct msk_chain_data *cd = &sc_if->sk_cdata; 411 struct msk_ring_data *rd = sc_if->sk_rdata; 412 int i, nexti; 413 414 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 415 416 for (i = 0; i < MSK_RX_RING_CNT; i++) { 417 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 418 if (i == (MSK_RX_RING_CNT - 1)) 419 nexti = 0; 420 else 421 nexti = i + 1; 422 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 423 } 424 425 sc_if->sk_cdata.sk_rx_prod = 0; 426 sc_if->sk_cdata.sk_rx_cons = 0; 427 sc_if->sk_cdata.sk_rx_cnt = 0; 428 429 msk_fill_rx_ring(sc_if); 430 return (0); 431 } 432 433 int 434 msk_init_tx_ring(struct sk_if_softc *sc_if) 435 { 436 struct sk_softc *sc = sc_if->sk_softc; 437 struct msk_chain_data *cd = &sc_if->sk_cdata; 438 struct msk_ring_data *rd = sc_if->sk_rdata; 439 bus_dmamap_t dmamap; 440 struct sk_txmap_entry *entry; 441 int i, nexti; 442 443 memset(rd->sk_tx_ring, 0, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 444 445 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 446 for (i = 0; i < MSK_TX_RING_CNT; i++) { 447 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 448 if (i == (MSK_TX_RING_CNT - 1)) 449 nexti = 0; 450 else 451 nexti = i + 1; 452 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 453 454 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 455 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 456 return (ENOBUFS); 457 458 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 459 if (!entry) { 460 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 461 return (ENOBUFS); 462 } 463 entry->dmamap = dmamap; 464 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 465 } 466 467 sc_if->sk_cdata.sk_tx_prod = 0; 468 sc_if->sk_cdata.sk_tx_cons = 0; 469 sc_if->sk_cdata.sk_tx_cnt = 0; 470 471 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 472 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 473 474 return (0); 475 } 476 477 int 478 msk_newbuf(struct sk_if_softc *sc_if, bus_dmamap_t dmamap) 479 { 480 struct mbuf *m_new = NULL; 481 struct sk_chain *c; 482 struct msk_rx_desc *r; 483 void *buf = NULL; 484 485 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 486 if (m_new == NULL) 487 return (ENOBUFS); 488 489 /* Allocate the jumbo buffer */ 490 buf = msk_jalloc(sc_if); 491 if (buf == NULL) { 492 m_freem(m_new); 493 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 494 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 495 return (ENOBUFS); 496 } 497 498 /* Attach the buffer to the mbuf */ 499 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 500 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 501 502 m_adj(m_new, ETHER_ALIGN); 503 504 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 505 r = c->sk_le; 506 c->sk_mbuf = m_new; 507 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + 508 (((vaddr_t)m_new->m_data 509 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 510 r->sk_len = htole16(SK_JLEN); 511 r->sk_ctl = 0; 512 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 513 514 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 515 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 516 517 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 518 sc_if->sk_cdata.sk_rx_cnt++; 519 520 return (0); 521 } 522 523 /* 524 * Memory management for jumbo frames. 525 */ 526 527 int 528 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 529 { 530 struct sk_softc *sc = sc_if->sk_softc; 531 char *ptr, *kva; 532 int i, state, error; 533 struct sk_jpool_entry *entry; 534 535 state = error = 0; 536 537 /* Grab a big chunk o' storage. */ 538 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 539 &sc_if->sk_cdata.sk_jumbo_seg, 1, &sc_if->sk_cdata.sk_jumbo_nseg, 540 BUS_DMA_NOWAIT)) { 541 aprint_error(": can't alloc rx buffers"); 542 return (ENOBUFS); 543 } 544 545 state = 1; 546 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 547 sc_if->sk_cdata.sk_jumbo_nseg, MSK_JMEM, (void **)&kva, 548 BUS_DMA_NOWAIT)) { 549 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 550 error = ENOBUFS; 551 goto out; 552 } 553 554 state = 2; 555 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 556 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 557 aprint_error(": can't create dma map"); 558 error = ENOBUFS; 559 goto out; 560 } 561 562 state = 3; 563 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 564 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 565 aprint_error(": can't load dma map"); 566 error = ENOBUFS; 567 goto out; 568 } 569 570 state = 4; 571 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 572 DPRINTFN(1,("msk_jumbo_buf = %p\n", (void *)sc_if->sk_cdata.sk_jumbo_buf)); 573 574 LIST_INIT(&sc_if->sk_jfree_listhead); 575 LIST_INIT(&sc_if->sk_jinuse_listhead); 576 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 577 578 /* 579 * Now divide it up into 9K pieces and save the addresses 580 * in an array. 581 */ 582 ptr = sc_if->sk_cdata.sk_jumbo_buf; 583 for (i = 0; i < MSK_JSLOTS; i++) { 584 sc_if->sk_cdata.sk_jslots[i] = ptr; 585 ptr += SK_JLEN; 586 entry = malloc(sizeof(struct sk_jpool_entry), 587 M_DEVBUF, M_NOWAIT); 588 if (entry == NULL) { 589 sc_if->sk_cdata.sk_jumbo_buf = NULL; 590 aprint_error(": no memory for jumbo buffer queue!"); 591 error = ENOBUFS; 592 goto out; 593 } 594 entry->slot = i; 595 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 596 entry, jpool_entries); 597 } 598 out: 599 if (error != 0) { 600 switch (state) { 601 case 4: 602 bus_dmamap_unload(sc->sc_dmatag, 603 sc_if->sk_cdata.sk_rx_jumbo_map); 604 case 3: 605 bus_dmamap_destroy(sc->sc_dmatag, 606 sc_if->sk_cdata.sk_rx_jumbo_map); 607 case 2: 608 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 609 case 1: 610 bus_dmamem_free(sc->sc_dmatag, 611 &sc_if->sk_cdata.sk_jumbo_seg, 612 sc_if->sk_cdata.sk_jumbo_nseg); 613 break; 614 default: 615 break; 616 } 617 } 618 619 return error; 620 } 621 622 static void 623 msk_free_jumbo_mem(struct sk_if_softc *sc_if) 624 { 625 struct sk_softc *sc = sc_if->sk_softc; 626 627 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 628 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 629 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_cdata.sk_jumbo_buf, MSK_JMEM); 630 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 631 sc_if->sk_cdata.sk_jumbo_nseg); 632 } 633 634 /* 635 * Allocate a jumbo buffer. 636 */ 637 void * 638 msk_jalloc(struct sk_if_softc *sc_if) 639 { 640 struct sk_jpool_entry *entry; 641 642 mutex_enter(&sc_if->sk_jpool_mtx); 643 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 644 645 if (entry == NULL) { 646 mutex_exit(&sc_if->sk_jpool_mtx); 647 return NULL; 648 } 649 650 LIST_REMOVE(entry, jpool_entries); 651 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 652 mutex_exit(&sc_if->sk_jpool_mtx); 653 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 654 } 655 656 /* 657 * Release a jumbo buffer. 658 */ 659 void 660 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 661 { 662 struct sk_jpool_entry *entry; 663 struct sk_if_softc *sc; 664 int i; 665 666 /* Extract the softc struct pointer. */ 667 sc = (struct sk_if_softc *)arg; 668 669 if (sc == NULL) 670 panic("msk_jfree: can't find softc pointer!"); 671 672 /* calculate the slot this buffer belongs to */ 673 i = ((vaddr_t)buf 674 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 675 676 if ((i < 0) || (i >= MSK_JSLOTS)) 677 panic("msk_jfree: asked to free buffer that we don't manage!"); 678 679 mutex_enter(&sc->sk_jpool_mtx); 680 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 681 if (entry == NULL) 682 panic("msk_jfree: buffer not in use!"); 683 entry->slot = i; 684 LIST_REMOVE(entry, jpool_entries); 685 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 686 mutex_exit(&sc->sk_jpool_mtx); 687 688 if (__predict_true(m != NULL)) 689 pool_cache_put(mb_cache, m); 690 691 /* Now that we know we have a free RX buffer, refill if running out */ 692 if ((sc->sk_ethercom.ec_if.if_flags & IFF_RUNNING) != 0 693 && sc->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 694 callout_schedule(&sc->sk_tick_rx, 0); 695 } 696 697 int 698 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 699 { 700 struct sk_if_softc *sc = ifp->if_softc; 701 int s, error; 702 703 s = splnet(); 704 705 DPRINTFN(2, ("msk_ioctl ETHER\n")); 706 switch (cmd) { 707 case SIOCSIFFLAGS: 708 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 709 break; 710 711 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 712 case IFF_RUNNING: 713 msk_stop(ifp, 1); 714 break; 715 case IFF_UP: 716 msk_init(ifp); 717 break; 718 case IFF_UP | IFF_RUNNING: 719 if ((ifp->if_flags ^ sc->sk_if_flags) == IFF_PROMISC) { 720 msk_setpromisc(sc); 721 msk_setmulti(sc); 722 } else 723 msk_init(ifp); 724 break; 725 } 726 sc->sk_if_flags = ifp->if_flags; 727 break; 728 default: 729 error = ether_ioctl(ifp, cmd, data); 730 if (error == ENETRESET) { 731 error = 0; 732 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 733 ; 734 else if (ifp->if_flags & IFF_RUNNING) { 735 /* 736 * Multicast list has changed; set the hardware 737 * filter accordingly. 738 */ 739 msk_setmulti(sc); 740 } 741 } 742 break; 743 } 744 745 splx(s); 746 return error; 747 } 748 749 void 750 msk_update_int_mod(struct sk_softc *sc, int verbose) 751 { 752 u_int32_t imtimer_ticks; 753 754 /* 755 * Configure interrupt moderation. The moderation timer 756 * defers interrupts specified in the interrupt moderation 757 * timer mask based on the timeout specified in the interrupt 758 * moderation timer init register. Each bit in the timer 759 * register represents one tick, so to specify a timeout in 760 * microseconds, we have to multiply by the correct number of 761 * ticks-per-microsecond. 762 */ 763 switch (sc->sk_type) { 764 case SK_YUKON_EC: 765 case SK_YUKON_EC_U: 766 case SK_YUKON_EX: 767 case SK_YUKON_SUPR: 768 case SK_YUKON_ULTRA2: 769 case SK_YUKON_OPTIMA: 770 case SK_YUKON_PRM: 771 case SK_YUKON_OPTIMA2: 772 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 773 break; 774 case SK_YUKON_FE: 775 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 776 break; 777 case SK_YUKON_FE_P: 778 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 779 break; 780 case SK_YUKON_XL: 781 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 782 break; 783 default: 784 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 785 } 786 if (verbose) 787 aprint_verbose_dev(sc->sk_dev, 788 "interrupt moderation is %d us\n", sc->sk_int_mod); 789 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 790 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 791 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 792 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 793 sc->sk_int_mod_pending = 0; 794 } 795 796 static int 797 msk_lookup(const struct pci_attach_args *pa) 798 { 799 const struct msk_product *pmsk; 800 801 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 802 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 803 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 804 return 1; 805 } 806 return 0; 807 } 808 809 /* 810 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 811 * IDs against our list and return a device name if we find a match. 812 */ 813 int 814 mskc_probe(device_t parent, cfdata_t match, void *aux) 815 { 816 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 817 818 return msk_lookup(pa); 819 } 820 821 /* 822 * Force the GEnesis into reset, then bring it out of reset. 823 */ 824 void 825 mskc_reset(struct sk_softc *sc) 826 { 827 u_int32_t imtimer_ticks, reg1; 828 int reg; 829 830 DPRINTFN(2, ("mskc_reset\n")); 831 832 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 833 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 834 835 DELAY(1000); 836 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 837 DELAY(2); 838 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 839 sk_win_write_1(sc, SK_TESTCTL1, 2); 840 841 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 842 sc->sk_type >= SK_YUKON_FE_P) { 843 uint32_t our; 844 845 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 846 847 /* enable all clocks. */ 848 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 849 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 850 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST| 851 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN| 852 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY| 853 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 854 /* Set all bits to 0 except bits 15..12 */ 855 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 856 /* Set to default value */ 857 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 858 859 /* 860 * Disable status race, workaround for Yukon EC Ultra & 861 * Yukon EX. 862 */ 863 reg1 = sk_win_read_4(sc, SK_GPIO); 864 reg1 |= SK_Y2_GPIO_STAT_RACE_DIS; 865 sk_win_write_4(sc, SK_GPIO, reg1); 866 sk_win_read_4(sc, SK_GPIO); 867 } 868 869 /* release PHY from PowerDown/Coma mode. */ 870 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 871 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 872 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 873 else 874 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 875 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 876 877 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 878 sk_win_write_1(sc, SK_Y2_CLKGATE, 879 SK_Y2_CLKGATE_LINK1_GATE_DIS | 880 SK_Y2_CLKGATE_LINK2_GATE_DIS | 881 SK_Y2_CLKGATE_LINK1_CORE_DIS | 882 SK_Y2_CLKGATE_LINK2_CORE_DIS | 883 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 884 else 885 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 886 887 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 888 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 889 DELAY(1000); 890 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 891 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 892 893 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 894 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 895 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 896 } 897 898 sk_win_write_1(sc, SK_TESTCTL1, 1); 899 900 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 901 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 902 CSR_READ_2(sc, SK_LINK_CTRL))); 903 904 /* Disable ASF */ 905 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 906 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 907 908 /* Clear I2C IRQ noise */ 909 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 910 911 /* Disable hardware timer */ 912 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 913 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 914 915 /* Disable descriptor polling */ 916 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 917 918 /* Disable time stamps */ 919 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 920 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 921 922 /* Enable RAM interface */ 923 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 924 for (reg = SK_TO0;reg <= SK_TO11; reg++) 925 sk_win_write_1(sc, reg, 36); 926 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 927 for (reg = SK_TO0;reg <= SK_TO11; reg++) 928 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 929 930 /* 931 * Configure interrupt moderation. The moderation timer 932 * defers interrupts specified in the interrupt moderation 933 * timer mask based on the timeout specified in the interrupt 934 * moderation timer init register. Each bit in the timer 935 * register represents one tick, so to specify a timeout in 936 * microseconds, we have to multiply by the correct number of 937 * ticks-per-microsecond. 938 */ 939 switch (sc->sk_type) { 940 case SK_YUKON_EC: 941 case SK_YUKON_EC_U: 942 case SK_YUKON_EX: 943 case SK_YUKON_SUPR: 944 case SK_YUKON_ULTRA2: 945 case SK_YUKON_OPTIMA: 946 case SK_YUKON_PRM: 947 case SK_YUKON_OPTIMA2: 948 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 949 break; 950 case SK_YUKON_FE: 951 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 952 break; 953 case SK_YUKON_FE_P: 954 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 955 break; 956 case SK_YUKON_XL: 957 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 958 break; 959 default: 960 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 961 break; 962 } 963 964 /* Reset status ring. */ 965 memset(sc->sk_status_ring, 0, 966 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 967 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 968 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 969 sc->sk_status_idx = 0; 970 971 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 972 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 973 974 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 975 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 976 sc->sk_status_map->dm_segs[0].ds_addr); 977 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 978 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 979 if (sc->sk_type == SK_YUKON_EC && 980 sc->sk_rev == SK_YUKON_EC_REV_A1) { 981 /* WA for dev. #4.3 */ 982 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK); 983 /* WA for dev. #4.18 */ 984 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 985 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 986 } else { 987 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 988 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 989 if (sc->sk_type == SK_YUKON_XL) 990 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x04); 991 else 992 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x10); 993 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 994 } 995 996 #if 0 997 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 998 #endif 999 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 1000 1001 /* Enable status unit. */ 1002 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 1003 1004 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 1005 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 1006 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 1007 1008 msk_update_int_mod(sc, 0); 1009 } 1010 1011 int 1012 msk_probe(device_t parent, cfdata_t match, void *aux) 1013 { 1014 struct skc_attach_args *sa = aux; 1015 1016 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1017 return (0); 1018 1019 switch (sa->skc_type) { 1020 case SK_YUKON_XL: 1021 case SK_YUKON_EC_U: 1022 case SK_YUKON_EX: 1023 case SK_YUKON_EC: 1024 case SK_YUKON_FE: 1025 case SK_YUKON_FE_P: 1026 case SK_YUKON_SUPR: 1027 case SK_YUKON_ULTRA2: 1028 case SK_YUKON_OPTIMA: 1029 case SK_YUKON_PRM: 1030 case SK_YUKON_OPTIMA2: 1031 return (1); 1032 } 1033 1034 return (0); 1035 } 1036 1037 void 1038 msk_reset(struct sk_if_softc *sc_if) 1039 { 1040 /* GMAC and GPHY Reset */ 1041 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1042 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1043 DELAY(1000); 1044 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1045 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1046 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1047 } 1048 1049 static bool 1050 msk_resume(device_t dv, const pmf_qual_t *qual) 1051 { 1052 struct sk_if_softc *sc_if = device_private(dv); 1053 1054 msk_init_yukon(sc_if); 1055 return true; 1056 } 1057 1058 /* 1059 * Each XMAC chip is attached as a separate logical IP interface. 1060 * Single port cards will have only one logical interface of course. 1061 */ 1062 void 1063 msk_attach(device_t parent, device_t self, void *aux) 1064 { 1065 struct sk_if_softc *sc_if = device_private(self); 1066 struct sk_softc *sc = device_private(parent); 1067 struct skc_attach_args *sa = aux; 1068 struct ifnet *ifp; 1069 void *kva; 1070 int i; 1071 u_int32_t chunk; 1072 int mii_flags; 1073 1074 sc_if->sk_dev = self; 1075 sc_if->sk_port = sa->skc_port; 1076 sc_if->sk_softc = sc; 1077 sc->sk_if[sa->skc_port] = sc_if; 1078 1079 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1080 1081 /* 1082 * Get station address for this interface. Note that 1083 * dual port cards actually come with three station 1084 * addresses: one for each port, plus an extra. The 1085 * extra one is used by the SysKonnect driver software 1086 * as a 'virtual' station address for when both ports 1087 * are operating in failover mode. Currently we don't 1088 * use this extra address. 1089 */ 1090 for (i = 0; i < ETHER_ADDR_LEN; i++) 1091 sc_if->sk_enaddr[i] = 1092 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1093 1094 aprint_normal(": Ethernet address %s\n", 1095 ether_sprintf(sc_if->sk_enaddr)); 1096 1097 /* 1098 * Set up RAM buffer addresses. The Yukon2 has a small amount 1099 * of SRAM on it, somewhere between 4K and 48K. We need to 1100 * divide this up between the transmitter and receiver. We 1101 * give the receiver 2/3 of the memory (rounded down), and the 1102 * transmitter whatever remains. 1103 */ 1104 chunk = (2 * (sc->sk_ramsize / sizeof(u_int64_t)) / 3) & ~0xff; 1105 sc_if->sk_rx_ramstart = 0; 1106 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 1107 chunk = (sc->sk_ramsize / sizeof(u_int64_t)) - chunk; 1108 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 1109 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 1110 1111 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1112 " tx_ramstart=%#x tx_ramend=%#x\n", 1113 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1114 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1115 1116 /* Allocate the descriptor queues. */ 1117 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1118 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 1119 BUS_DMA_NOWAIT)) { 1120 aprint_error(": can't alloc rx buffers\n"); 1121 goto fail; 1122 } 1123 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 1124 sc_if->sk_ring_nseg, 1125 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1126 aprint_error(": can't map dma buffers (%zu bytes)\n", 1127 sizeof(struct msk_ring_data)); 1128 goto fail_1; 1129 } 1130 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1131 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1132 &sc_if->sk_ring_map)) { 1133 aprint_error(": can't create dma map\n"); 1134 goto fail_2; 1135 } 1136 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1137 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1138 aprint_error(": can't load dma map\n"); 1139 goto fail_3; 1140 } 1141 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1142 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1143 1144 if (sc->sk_type != SK_YUKON_FE && 1145 sc->sk_type != SK_YUKON_FE_P) 1146 sc_if->sk_pktlen = SK_JLEN; 1147 else 1148 sc_if->sk_pktlen = MCLBYTES; 1149 1150 /* Try to allocate memory for jumbo buffers. */ 1151 if (msk_alloc_jumbo_mem(sc_if)) { 1152 aprint_error(": jumbo buffer allocation failed\n"); 1153 goto fail_3; 1154 } 1155 1156 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1157 if (sc->sk_type != SK_YUKON_FE && 1158 sc->sk_type != SK_YUKON_FE_P) 1159 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1160 1161 ifp = &sc_if->sk_ethercom.ec_if; 1162 ifp->if_softc = sc_if; 1163 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1164 ifp->if_ioctl = msk_ioctl; 1165 ifp->if_start = msk_start; 1166 ifp->if_stop = msk_stop; 1167 ifp->if_init = msk_init; 1168 ifp->if_watchdog = msk_watchdog; 1169 ifp->if_baudrate = 1000000000; 1170 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1171 IFQ_SET_READY(&ifp->if_snd); 1172 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1173 1174 msk_reset(sc_if); 1175 1176 /* 1177 * Do miibus setup. 1178 */ 1179 msk_init_yukon(sc_if); 1180 1181 DPRINTFN(2, ("msk_attach: 1\n")); 1182 1183 sc_if->sk_mii.mii_ifp = ifp; 1184 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1185 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1186 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1187 1188 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1189 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1190 ether_mediachange, ether_mediastatus); 1191 mii_flags = MIIF_DOPAUSE; 1192 if (sc->sk_fibertype) 1193 mii_flags |= MIIF_HAVEFIBER; 1194 mii_attach(self, &sc_if->sk_mii, 0xffffffff, 0, 1195 MII_OFFSET_ANY, mii_flags); 1196 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1197 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1198 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1199 0, NULL); 1200 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1201 } else 1202 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1203 1204 callout_init(&sc_if->sk_tick_ch, 0); 1205 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1206 callout_schedule(&sc_if->sk_tick_ch, hz); 1207 1208 callout_init(&sc_if->sk_tick_rx, 0); 1209 callout_setfunc(&sc_if->sk_tick_rx, msk_fill_rx_tick, sc_if); 1210 1211 /* 1212 * Call MI attach routines. 1213 */ 1214 if_attach(ifp); 1215 if_deferred_start_init(ifp, NULL); 1216 ether_ifattach(ifp, sc_if->sk_enaddr); 1217 1218 if (pmf_device_register(self, NULL, msk_resume)) 1219 pmf_class_network_register(self, ifp); 1220 else 1221 aprint_error_dev(self, "couldn't establish power handler\n"); 1222 1223 if (sc->rnd_attached++ == 0) { 1224 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1225 RND_TYPE_NET, RND_FLAG_DEFAULT); 1226 } 1227 1228 DPRINTFN(2, ("msk_attach: end\n")); 1229 return; 1230 1231 fail_3: 1232 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1233 fail_2: 1234 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1235 fail_1: 1236 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1237 fail: 1238 sc->sk_if[sa->skc_port] = NULL; 1239 } 1240 1241 int 1242 msk_detach(device_t self, int flags) 1243 { 1244 struct sk_if_softc *sc_if = device_private(self); 1245 struct sk_softc *sc = sc_if->sk_softc; 1246 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1247 1248 if (sc->sk_if[sc_if->sk_port] == NULL) 1249 return (0); 1250 1251 msk_stop(ifp, 0); 1252 1253 if (--sc->rnd_attached == 0) 1254 rnd_detach_source(&sc->rnd_source); 1255 1256 callout_halt(&sc_if->sk_tick_ch, NULL); 1257 callout_destroy(&sc_if->sk_tick_ch); 1258 1259 callout_halt(&sc_if->sk_tick_rx, NULL); 1260 callout_destroy(&sc_if->sk_tick_rx); 1261 1262 /* Detach any PHYs we might have. */ 1263 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1264 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1265 1266 /* Delete any remaining media. */ 1267 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY); 1268 1269 pmf_device_deregister(self); 1270 1271 ether_ifdetach(ifp); 1272 if_detach(ifp); 1273 1274 msk_free_jumbo_mem(sc_if); 1275 1276 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_rdata, 1277 sizeof(struct msk_ring_data)); 1278 bus_dmamem_free(sc->sc_dmatag, 1279 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1280 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1281 sc->sk_if[sc_if->sk_port] = NULL; 1282 1283 return (0); 1284 } 1285 1286 int 1287 mskcprint(void *aux, const char *pnp) 1288 { 1289 struct skc_attach_args *sa = aux; 1290 1291 if (pnp) 1292 aprint_normal("msk port %c at %s", 1293 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1294 else 1295 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1296 return (UNCONF); 1297 } 1298 1299 /* 1300 * Attach the interface. Allocate softc structures, do ifmedia 1301 * setup and ethernet/BPF attach. 1302 */ 1303 void 1304 mskc_attach(device_t parent, device_t self, void *aux) 1305 { 1306 struct sk_softc *sc = device_private(self); 1307 struct pci_attach_args *pa = aux; 1308 struct skc_attach_args skca; 1309 pci_chipset_tag_t pc = pa->pa_pc; 1310 pcireg_t command, memtype; 1311 pci_intr_handle_t ih; 1312 const char *intrstr = NULL; 1313 int rc, sk_nodenum; 1314 u_int8_t hw, pmd; 1315 const char *revstr = NULL; 1316 const struct sysctlnode *node; 1317 void *kva; 1318 char intrbuf[PCI_INTRSTR_LEN]; 1319 1320 DPRINTFN(2, ("begin mskc_attach\n")); 1321 1322 sc->sk_dev = self; 1323 /* 1324 * Handle power management nonsense. 1325 */ 1326 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1327 1328 if (command == 0x01) { 1329 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1330 if (command & SK_PSTATE_MASK) { 1331 u_int32_t iobase, membase, irq; 1332 1333 /* Save important PCI config data. */ 1334 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1335 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1336 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1337 1338 /* Reset the power state. */ 1339 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1340 "mode -- setting to D0\n", 1341 command & SK_PSTATE_MASK); 1342 command &= 0xFFFFFFFC; 1343 pci_conf_write(pc, pa->pa_tag, 1344 SK_PCI_PWRMGMTCTRL, command); 1345 1346 /* Restore PCI config data. */ 1347 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1348 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1349 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1350 } 1351 } 1352 1353 /* 1354 * Map control/status registers. 1355 */ 1356 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1357 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1358 &sc->sk_bhandle, NULL, &sc->sk_bsize)) { 1359 aprint_error(": can't map mem space\n"); 1360 return; 1361 } 1362 1363 sc->sc_dmatag = pa->pa_dmat; 1364 1365 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1366 command |= PCI_COMMAND_MASTER_ENABLE; 1367 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1368 1369 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1370 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1371 1372 /* bail out here if chip is not recognized */ 1373 if (!(SK_IS_YUKON2(sc))) { 1374 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1375 goto fail_1; 1376 } 1377 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1378 1379 /* Allocate interrupt */ 1380 if (pci_intr_map(pa, &ih)) { 1381 aprint_error(": couldn't map interrupt\n"); 1382 goto fail_1; 1383 } 1384 1385 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1386 sc->sk_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, msk_intr, 1387 sc, device_xname(sc->sk_dev)); 1388 if (sc->sk_intrhand == NULL) { 1389 aprint_error(": couldn't establish interrupt"); 1390 if (intrstr != NULL) 1391 aprint_error(" at %s", intrstr); 1392 aprint_error("\n"); 1393 goto fail_1; 1394 } 1395 sc->sk_pc = pc; 1396 1397 if (bus_dmamem_alloc(sc->sc_dmatag, 1398 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1399 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1400 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, BUS_DMA_NOWAIT)) { 1401 aprint_error(": can't alloc status buffers\n"); 1402 goto fail_2; 1403 } 1404 1405 if (bus_dmamem_map(sc->sc_dmatag, 1406 &sc->sk_status_seg, sc->sk_status_nseg, 1407 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1408 &kva, BUS_DMA_NOWAIT)) { 1409 aprint_error(": can't map dma buffers (%zu bytes)\n", 1410 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1411 goto fail_3; 1412 } 1413 if (bus_dmamap_create(sc->sc_dmatag, 1414 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1415 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1416 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1417 aprint_error(": can't create dma map\n"); 1418 goto fail_4; 1419 } 1420 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1421 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1422 NULL, BUS_DMA_NOWAIT)) { 1423 aprint_error(": can't load dma map\n"); 1424 goto fail_5; 1425 } 1426 sc->sk_status_ring = (struct msk_status_desc *)kva; 1427 1428 sc->sk_int_mod = SK_IM_DEFAULT; 1429 sc->sk_int_mod_pending = 0; 1430 1431 /* Reset the adapter. */ 1432 mskc_reset(sc); 1433 1434 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1435 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1436 1437 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1438 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1439 sc->sk_fibertype = 1; 1440 1441 switch (sc->sk_type) { 1442 case SK_YUKON_XL: 1443 sc->sk_name = "Yukon-2 XL"; 1444 break; 1445 case SK_YUKON_EC_U: 1446 sc->sk_name = "Yukon-2 EC Ultra"; 1447 break; 1448 case SK_YUKON_EX: 1449 sc->sk_name = "Yukon-2 Extreme"; 1450 break; 1451 case SK_YUKON_EC: 1452 sc->sk_name = "Yukon-2 EC"; 1453 break; 1454 case SK_YUKON_FE: 1455 sc->sk_name = "Yukon-2 FE"; 1456 break; 1457 case SK_YUKON_FE_P: 1458 sc->sk_name = "Yukon-2 FE+"; 1459 break; 1460 case SK_YUKON_SUPR: 1461 sc->sk_name = "Yukon-2 Supreme"; 1462 break; 1463 case SK_YUKON_ULTRA2: 1464 sc->sk_name = "Yukon-2 Ultra 2"; 1465 break; 1466 case SK_YUKON_OPTIMA: 1467 sc->sk_name = "Yukon-2 Optima"; 1468 break; 1469 case SK_YUKON_PRM: 1470 sc->sk_name = "Yukon-2 Optima Prime"; 1471 break; 1472 case SK_YUKON_OPTIMA2: 1473 sc->sk_name = "Yukon-2 Optima 2"; 1474 break; 1475 default: 1476 sc->sk_name = "Yukon (Unknown)"; 1477 } 1478 1479 if (sc->sk_type == SK_YUKON_XL) { 1480 switch (sc->sk_rev) { 1481 case SK_YUKON_XL_REV_A0: 1482 revstr = "A0"; 1483 break; 1484 case SK_YUKON_XL_REV_A1: 1485 revstr = "A1"; 1486 break; 1487 case SK_YUKON_XL_REV_A2: 1488 revstr = "A2"; 1489 break; 1490 case SK_YUKON_XL_REV_A3: 1491 revstr = "A3"; 1492 break; 1493 default: 1494 break; 1495 } 1496 } 1497 1498 if (sc->sk_type == SK_YUKON_EC) { 1499 switch (sc->sk_rev) { 1500 case SK_YUKON_EC_REV_A1: 1501 revstr = "A1"; 1502 break; 1503 case SK_YUKON_EC_REV_A2: 1504 revstr = "A2"; 1505 break; 1506 case SK_YUKON_EC_REV_A3: 1507 revstr = "A3"; 1508 break; 1509 default: 1510 break; 1511 } 1512 } 1513 1514 if (sc->sk_type == SK_YUKON_FE) { 1515 switch (sc->sk_rev) { 1516 case SK_YUKON_FE_REV_A1: 1517 revstr = "A1"; 1518 break; 1519 case SK_YUKON_FE_REV_A2: 1520 revstr = "A2"; 1521 break; 1522 default: 1523 break; 1524 } 1525 } 1526 1527 if (sc->sk_type == SK_YUKON_EC_U) { 1528 switch (sc->sk_rev) { 1529 case SK_YUKON_EC_U_REV_A0: 1530 revstr = "A0"; 1531 break; 1532 case SK_YUKON_EC_U_REV_A1: 1533 revstr = "A1"; 1534 break; 1535 case SK_YUKON_EC_U_REV_B0: 1536 revstr = "B0"; 1537 break; 1538 case SK_YUKON_EC_U_REV_B1: 1539 revstr = "B1"; 1540 break; 1541 default: 1542 break; 1543 } 1544 } 1545 1546 if (sc->sk_type == SK_YUKON_FE) { 1547 switch (sc->sk_rev) { 1548 case SK_YUKON_FE_REV_A1: 1549 revstr = "A1"; 1550 break; 1551 case SK_YUKON_FE_REV_A2: 1552 revstr = "A2"; 1553 break; 1554 default: 1555 ; 1556 } 1557 } 1558 1559 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1560 revstr = "A0"; 1561 1562 if (sc->sk_type == SK_YUKON_EX) { 1563 switch (sc->sk_rev) { 1564 case SK_YUKON_EX_REV_A0: 1565 revstr = "A0"; 1566 break; 1567 case SK_YUKON_EX_REV_B0: 1568 revstr = "B0"; 1569 break; 1570 default: 1571 ; 1572 } 1573 } 1574 1575 if (sc->sk_type == SK_YUKON_SUPR) { 1576 switch (sc->sk_rev) { 1577 case SK_YUKON_SUPR_REV_A0: 1578 revstr = "A0"; 1579 break; 1580 case SK_YUKON_SUPR_REV_B0: 1581 revstr = "B0"; 1582 break; 1583 case SK_YUKON_SUPR_REV_B1: 1584 revstr = "B1"; 1585 break; 1586 default: 1587 ; 1588 } 1589 } 1590 1591 if (sc->sk_type == SK_YUKON_PRM) { 1592 switch (sc->sk_rev) { 1593 case SK_YUKON_PRM_REV_Z1: 1594 revstr = "Z1"; 1595 break; 1596 case SK_YUKON_PRM_REV_A0: 1597 revstr = "A0"; 1598 break; 1599 default: 1600 ; 1601 } 1602 } 1603 1604 /* Announce the product name. */ 1605 aprint_normal(", %s", sc->sk_name); 1606 if (revstr != NULL) 1607 aprint_normal(" rev. %s", revstr); 1608 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1609 1610 sc->sk_macs = 1; 1611 1612 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1613 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1614 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1615 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1616 sc->sk_macs++; 1617 } 1618 1619 skca.skc_port = SK_PORT_A; 1620 skca.skc_type = sc->sk_type; 1621 skca.skc_rev = sc->sk_rev; 1622 (void)config_found(sc->sk_dev, &skca, mskcprint); 1623 1624 if (sc->sk_macs > 1) { 1625 skca.skc_port = SK_PORT_B; 1626 skca.skc_type = sc->sk_type; 1627 skca.skc_rev = sc->sk_rev; 1628 (void)config_found(sc->sk_dev, &skca, mskcprint); 1629 } 1630 1631 /* Turn on the 'driver is loaded' LED. */ 1632 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1633 1634 /* skc sysctl setup */ 1635 1636 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1637 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1638 SYSCTL_DESCR("mskc per-controller controls"), 1639 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1640 CTL_EOL)) != 0) { 1641 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1642 goto fail_6; 1643 } 1644 1645 sk_nodenum = node->sysctl_num; 1646 1647 /* interrupt moderation time in usecs */ 1648 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1649 CTLFLAG_READWRITE, 1650 CTLTYPE_INT, "int_mod", 1651 SYSCTL_DESCR("msk interrupt moderation timer"), 1652 msk_sysctl_handler, 0, (void *)sc, 1653 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1654 CTL_EOL)) != 0) { 1655 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1656 goto fail_6; 1657 } 1658 1659 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1660 aprint_error_dev(self, "couldn't establish power handler\n"); 1661 1662 return; 1663 1664 fail_6: 1665 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1666 fail_4: 1667 bus_dmamem_unmap(sc->sc_dmatag, kva, 1668 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1669 fail_3: 1670 bus_dmamem_free(sc->sc_dmatag, 1671 &sc->sk_status_seg, sc->sk_status_nseg); 1672 sc->sk_status_nseg = 0; 1673 fail_5: 1674 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1675 fail_2: 1676 pci_intr_disestablish(pc, sc->sk_intrhand); 1677 sc->sk_intrhand = NULL; 1678 fail_1: 1679 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1680 sc->sk_bsize = 0; 1681 } 1682 1683 int 1684 mskc_detach(device_t self, int flags) 1685 { 1686 struct sk_softc *sc = device_private(self); 1687 int rv; 1688 1689 if (sc->sk_intrhand) { 1690 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1691 sc->sk_intrhand = NULL; 1692 } 1693 1694 rv = config_detach_children(self, flags); 1695 if (rv != 0) 1696 return (rv); 1697 1698 if (sc->sk_status_nseg > 0) { 1699 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1700 bus_dmamem_unmap(sc->sc_dmatag, sc->sk_status_ring, 1701 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1702 bus_dmamem_free(sc->sc_dmatag, 1703 &sc->sk_status_seg, sc->sk_status_nseg); 1704 } 1705 1706 if (sc->sk_bsize > 0) 1707 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1708 1709 return(0); 1710 } 1711 1712 int 1713 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1714 { 1715 struct sk_softc *sc = sc_if->sk_softc; 1716 struct msk_tx_desc *f = NULL; 1717 u_int32_t frag, cur; 1718 int i; 1719 struct sk_txmap_entry *entry; 1720 bus_dmamap_t txmap; 1721 1722 DPRINTFN(2, ("msk_encap\n")); 1723 1724 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1725 if (entry == NULL) { 1726 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1727 return (ENOBUFS); 1728 } 1729 txmap = entry->dmamap; 1730 1731 cur = frag = *txidx; 1732 1733 #ifdef MSK_DEBUG 1734 if (mskdebug >= 2) 1735 msk_dump_mbuf(m_head); 1736 #endif 1737 1738 /* 1739 * Start packing the mbufs in this chain into 1740 * the fragment pointers. Stop when we run out 1741 * of fragments or hit the end of the mbuf chain. 1742 */ 1743 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1744 BUS_DMA_NOWAIT)) { 1745 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1746 return (ENOBUFS); 1747 } 1748 1749 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1750 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1751 bus_dmamap_unload(sc->sc_dmatag, txmap); 1752 return (ENOBUFS); 1753 } 1754 1755 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1756 1757 /* Sync the DMA map. */ 1758 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1759 BUS_DMASYNC_PREWRITE); 1760 1761 for (i = 0; i < txmap->dm_nsegs; i++) { 1762 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1763 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1764 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1765 f->sk_ctl = 0; 1766 if (i == 0) 1767 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1768 else 1769 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1770 cur = frag; 1771 SK_INC(frag, MSK_TX_RING_CNT); 1772 } 1773 1774 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1775 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1776 1777 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1778 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1779 1780 /* Sync descriptors before handing to chip */ 1781 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1782 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1783 1784 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1785 1786 /* Sync first descriptor to hand it off */ 1787 MSK_CDTXSYNC(sc_if, *txidx, 1, 1788 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1789 1790 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1791 1792 #ifdef MSK_DEBUG 1793 if (mskdebug >= 2) { 1794 struct msk_tx_desc *le; 1795 u_int32_t idx; 1796 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1797 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1798 msk_dump_txdesc(le, idx); 1799 } 1800 } 1801 #endif 1802 1803 *txidx = frag; 1804 1805 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1806 1807 return (0); 1808 } 1809 1810 void 1811 msk_start(struct ifnet *ifp) 1812 { 1813 struct sk_if_softc *sc_if = ifp->if_softc; 1814 struct mbuf *m_head = NULL; 1815 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1816 int pkts = 0; 1817 1818 DPRINTFN(2, ("msk_start\n")); 1819 1820 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1821 IFQ_POLL(&ifp->if_snd, m_head); 1822 if (m_head == NULL) 1823 break; 1824 1825 /* 1826 * Pack the data into the transmit ring. If we 1827 * don't have room, set the OACTIVE flag and wait 1828 * for the NIC to drain the ring. 1829 */ 1830 if (msk_encap(sc_if, m_head, &idx)) { 1831 ifp->if_flags |= IFF_OACTIVE; 1832 break; 1833 } 1834 1835 /* now we are committed to transmit the packet */ 1836 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1837 pkts++; 1838 1839 /* 1840 * If there's a BPF listener, bounce a copy of this frame 1841 * to him. 1842 */ 1843 bpf_mtap(ifp, m_head, BPF_D_OUT); 1844 } 1845 if (pkts == 0) 1846 return; 1847 1848 /* Transmit */ 1849 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1850 sc_if->sk_cdata.sk_tx_prod = idx; 1851 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1852 1853 /* Set a timeout in case the chip goes out to lunch. */ 1854 ifp->if_timer = 5; 1855 } 1856 } 1857 1858 void 1859 msk_watchdog(struct ifnet *ifp) 1860 { 1861 struct sk_if_softc *sc_if = ifp->if_softc; 1862 1863 /* 1864 * Reclaim first as there is a possibility of losing Tx completion 1865 * interrupts. 1866 */ 1867 msk_txeof(sc_if); 1868 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1869 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1870 1871 ifp->if_oerrors++; 1872 1873 /* XXX Resets both ports; we shouldn't do that. */ 1874 mskc_reset(sc_if->sk_softc); 1875 msk_reset(sc_if); 1876 msk_init(ifp); 1877 } 1878 } 1879 1880 static bool 1881 mskc_suspend(device_t dv, const pmf_qual_t *qual) 1882 { 1883 struct sk_softc *sc = device_private(dv); 1884 1885 DPRINTFN(2, ("mskc_suspend\n")); 1886 1887 /* Turn off the 'driver is loaded' LED. */ 1888 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1889 1890 return true; 1891 } 1892 1893 static bool 1894 mskc_resume(device_t dv, const pmf_qual_t *qual) 1895 { 1896 struct sk_softc *sc = device_private(dv); 1897 1898 DPRINTFN(2, ("mskc_resume\n")); 1899 1900 mskc_reset(sc); 1901 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1902 1903 return true; 1904 } 1905 1906 static __inline int 1907 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1908 { 1909 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1910 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1911 YU_RXSTAT_JABBER)) != 0 || 1912 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1913 YU_RXSTAT_BYTES(stat) != len) 1914 return (0); 1915 1916 return (1); 1917 } 1918 1919 void 1920 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1921 { 1922 struct sk_softc *sc = sc_if->sk_softc; 1923 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1924 struct mbuf *m; 1925 struct sk_chain *cur_rx; 1926 int cur, total_len = len; 1927 bus_dmamap_t dmamap; 1928 1929 DPRINTFN(2, ("msk_rxeof\n")); 1930 1931 cur = sc_if->sk_cdata.sk_rx_cons; 1932 1933 /* Sync the descriptor */ 1934 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1935 1936 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1937 if (cur_rx->sk_mbuf == NULL) 1938 return; 1939 1940 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1941 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1942 sc_if->sk_cdata.sk_rx_cnt--; 1943 1944 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1945 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1946 1947 m = cur_rx->sk_mbuf; 1948 cur_rx->sk_mbuf = NULL; 1949 1950 if (total_len < SK_MIN_FRAMELEN || 1951 total_len > ETHER_MAX_LEN_JUMBO || 1952 msk_rxvalid(sc, rxstat, total_len) == 0) { 1953 ifp->if_ierrors++; 1954 m_freem(m); 1955 return; 1956 } 1957 1958 m_set_rcvif(m, ifp); 1959 m->m_pkthdr.len = m->m_len = total_len; 1960 1961 /* pass it on. */ 1962 if_percpuq_enqueue(ifp->if_percpuq, m); 1963 } 1964 1965 void 1966 msk_txeof(struct sk_if_softc *sc_if) 1967 { 1968 struct sk_softc *sc = sc_if->sk_softc; 1969 struct msk_tx_desc *cur_tx; 1970 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1971 u_int32_t idx, reg, sk_ctl; 1972 struct sk_txmap_entry *entry; 1973 1974 DPRINTFN(2, ("msk_txeof\n")); 1975 1976 if (sc_if->sk_port == SK_PORT_A) 1977 reg = SK_STAT_BMU_TXA1_RIDX; 1978 else 1979 reg = SK_STAT_BMU_TXA2_RIDX; 1980 1981 /* 1982 * Go through our tx ring and free mbufs for those 1983 * frames that have been sent. 1984 */ 1985 idx = sc_if->sk_cdata.sk_tx_cons; 1986 while (idx != sk_win_read_2(sc, reg)) { 1987 MSK_CDTXSYNC(sc_if, idx, 1, 1988 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1989 1990 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1991 sk_ctl = cur_tx->sk_ctl; 1992 #ifdef MSK_DEBUG 1993 if (mskdebug >= 2) 1994 msk_dump_txdesc(cur_tx, idx); 1995 #endif 1996 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1997 ifp->if_opackets++; 1998 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1999 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2000 2001 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2002 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2003 2004 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2005 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2006 2007 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2008 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2009 link); 2010 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2011 } 2012 sc_if->sk_cdata.sk_tx_cnt--; 2013 SK_INC(idx, MSK_TX_RING_CNT); 2014 } 2015 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2016 2017 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 2018 ifp->if_flags &= ~IFF_OACTIVE; 2019 2020 sc_if->sk_cdata.sk_tx_cons = idx; 2021 } 2022 2023 void 2024 msk_fill_rx_ring(struct sk_if_softc *sc_if) 2025 { 2026 /* Make sure to not completely wrap around */ 2027 while (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT - 1)) { 2028 if (msk_newbuf(sc_if, 2029 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 2030 goto schedretry; 2031 } 2032 } 2033 2034 return; 2035 2036 schedretry: 2037 /* Try later */ 2038 callout_schedule(&sc_if->sk_tick_rx, hz/2); 2039 } 2040 2041 static void 2042 msk_fill_rx_tick(void *xsc_if) 2043 { 2044 struct sk_if_softc *sc_if = xsc_if; 2045 int s, rx_prod; 2046 2047 KASSERT(KERNEL_LOCKED_P()); /* XXXSMP */ 2048 2049 s = splnet(); 2050 rx_prod = sc_if->sk_cdata.sk_rx_prod; 2051 msk_fill_rx_ring(sc_if); 2052 if (rx_prod != sc_if->sk_cdata.sk_rx_prod) { 2053 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2054 sc_if->sk_cdata.sk_rx_prod); 2055 } 2056 splx(s); 2057 } 2058 2059 void 2060 msk_tick(void *xsc_if) 2061 { 2062 struct sk_if_softc *sc_if = xsc_if; 2063 struct mii_data *mii = &sc_if->sk_mii; 2064 int s; 2065 2066 s = splnet(); 2067 mii_tick(mii); 2068 splx(s); 2069 2070 callout_schedule(&sc_if->sk_tick_ch, hz); 2071 } 2072 2073 void 2074 msk_intr_yukon(struct sk_if_softc *sc_if) 2075 { 2076 u_int8_t status; 2077 2078 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2079 /* RX overrun */ 2080 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2081 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2082 SK_RFCTL_RX_FIFO_OVER); 2083 } 2084 /* TX underrun */ 2085 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2086 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 2087 SK_TFCTL_TX_FIFO_UNDER); 2088 } 2089 2090 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 2091 } 2092 2093 int 2094 msk_intr(void *xsc) 2095 { 2096 struct sk_softc *sc = xsc; 2097 struct sk_if_softc *sc_if; 2098 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2099 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2100 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2101 int claimed = 0; 2102 u_int32_t status; 2103 struct msk_status_desc *cur_st; 2104 2105 status = CSR_READ_4(sc, SK_Y2_ISSR2); 2106 if (status == 0xffffffff) 2107 return (0); 2108 if (status == 0) { 2109 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2110 return (0); 2111 } 2112 2113 status = CSR_READ_4(sc, SK_ISR); 2114 2115 if (sc_if0 != NULL) 2116 ifp0 = &sc_if0->sk_ethercom.ec_if; 2117 if (sc_if1 != NULL) 2118 ifp1 = &sc_if1->sk_ethercom.ec_if; 2119 2120 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 2121 (ifp0->if_flags & IFF_RUNNING)) { 2122 msk_intr_yukon(sc_if0); 2123 } 2124 2125 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 2126 (ifp1->if_flags & IFF_RUNNING)) { 2127 msk_intr_yukon(sc_if1); 2128 } 2129 2130 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2131 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2132 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2133 2134 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 2135 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 2136 switch (cur_st->sk_opcode) { 2137 case SK_Y2_STOPC_RXSTAT: 2138 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 2139 msk_rxeof(sc_if, letoh16(cur_st->sk_len), 2140 letoh32(cur_st->sk_status)); 2141 if (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 2142 msk_fill_rx_tick(sc_if); 2143 break; 2144 case SK_Y2_STOPC_TXSTAT: 2145 if (sc_if0) 2146 msk_txeof(sc_if0); 2147 if (sc_if1) 2148 msk_txeof(sc_if1); 2149 break; 2150 default: 2151 aprint_error("opcode=0x%x\n", cur_st->sk_opcode); 2152 break; 2153 } 2154 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 2155 2156 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2157 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2158 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2159 } 2160 2161 if (status & SK_Y2_IMR_BMU) { 2162 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 2163 claimed = 1; 2164 } 2165 2166 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2167 2168 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2169 if_schedule_deferred_start(ifp0); 2170 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2171 if_schedule_deferred_start(ifp1); 2172 2173 KASSERT(sc->rnd_attached > 0); 2174 rnd_add_uint32(&sc->rnd_source, status); 2175 2176 if (sc->sk_int_mod_pending) 2177 msk_update_int_mod(sc, 1); 2178 2179 return claimed; 2180 } 2181 2182 void 2183 msk_init_yukon(struct sk_if_softc *sc_if) 2184 { 2185 u_int32_t v; 2186 u_int16_t reg; 2187 struct sk_softc *sc; 2188 int i; 2189 2190 sc = sc_if->sk_softc; 2191 2192 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 2193 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2194 2195 DPRINTFN(6, ("msk_init_yukon: 1\n")); 2196 2197 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 2198 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2199 2200 DPRINTFN(6, ("msk_init_yukon: 3\n")); 2201 2202 /* unused read of the interrupt source register */ 2203 DPRINTFN(6, ("msk_init_yukon: 4\n")); 2204 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2205 2206 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2207 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2208 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2209 2210 /* MIB Counter Clear Mode set */ 2211 reg |= YU_PAR_MIB_CLR; 2212 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2213 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2214 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2215 2216 /* MIB Counter Clear Mode clear */ 2217 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2218 reg &= ~YU_PAR_MIB_CLR; 2219 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2220 2221 /* receive control reg */ 2222 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2223 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2224 2225 /* transmit control register */ 2226 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2227 2228 /* transmit flow control register */ 2229 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2230 2231 /* transmit parameter register */ 2232 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2233 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2234 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2235 2236 /* serial mode register */ 2237 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2238 reg = YU_SMR_DATA_BLIND(0x1c) | 2239 YU_SMR_MFL_VLAN | 2240 YU_SMR_IPG_DATA(0x1e); 2241 2242 if (sc->sk_type != SK_YUKON_FE && 2243 sc->sk_type != SK_YUKON_FE_P) 2244 reg |= YU_SMR_MFL_JUMBO; 2245 2246 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2247 2248 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2249 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2250 /* msk_attach calls me before ether_ifattach so check null */ 2251 if (ifp != NULL && ifp->if_sadl != NULL) 2252 memcpy(sc_if->sk_enaddr, CLLADDR(ifp->if_sadl), 2253 sizeof(sc_if->sk_enaddr)); 2254 /* Setup Yukon's address */ 2255 for (i = 0; i < 3; i++) { 2256 /* Write Source Address 1 (unicast filter) */ 2257 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2258 sc_if->sk_enaddr[i * 2] | 2259 sc_if->sk_enaddr[i * 2 + 1] << 8); 2260 } 2261 2262 for (i = 0; i < 3; i++) { 2263 reg = sk_win_read_2(sc_if->sk_softc, 2264 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2265 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2266 } 2267 2268 /* Set promiscuous mode */ 2269 msk_setpromisc(sc_if); 2270 2271 /* Set multicast filter */ 2272 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2273 msk_setmulti(sc_if); 2274 2275 /* enable interrupt mask for counter overflows */ 2276 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2277 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2278 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2279 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2280 2281 /* Configure RX MAC FIFO Flush Mask */ 2282 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2283 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2284 YU_RXSTAT_JABBER; 2285 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2286 2287 /* Configure RX MAC FIFO */ 2288 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2289 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2290 SK_RFCTL_FIFO_FLUSH_ON); 2291 2292 /* Increase flush threshold to 64 bytes */ 2293 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2294 SK_RFCTL_FIFO_THRESHOLD + 1); 2295 2296 /* Configure TX MAC FIFO */ 2297 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2298 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2299 2300 #if 1 2301 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2302 #endif 2303 DPRINTFN(6, ("msk_init_yukon: end\n")); 2304 } 2305 2306 /* 2307 * Note that to properly initialize any part of the GEnesis chip, 2308 * you first have to take it out of reset mode. 2309 */ 2310 int 2311 msk_init(struct ifnet *ifp) 2312 { 2313 struct sk_if_softc *sc_if = ifp->if_softc; 2314 struct sk_softc *sc = sc_if->sk_softc; 2315 int rc = 0, s; 2316 uint32_t imr, imtimer_ticks; 2317 2318 2319 DPRINTFN(2, ("msk_init\n")); 2320 2321 s = splnet(); 2322 2323 /* Cancel pending I/O and free all RX/TX buffers. */ 2324 msk_stop(ifp, 1); 2325 2326 /* Configure I2C registers */ 2327 2328 /* Configure XMAC(s) */ 2329 msk_init_yukon(sc_if); 2330 if ((rc = ether_mediachange(ifp)) != 0) 2331 goto out; 2332 2333 /* Configure transmit arbiter(s) */ 2334 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2335 #if 0 2336 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2337 #endif 2338 2339 /* Configure RAMbuffers */ 2340 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2341 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2342 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2343 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2344 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2345 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2346 2347 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2348 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2349 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2350 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2351 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2352 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2353 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2354 2355 /* Configure BMUs */ 2356 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2357 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2358 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2359 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2360 2361 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2362 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2363 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2364 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2365 2366 /* Make sure the sync transmit queue is disabled. */ 2367 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2368 2369 /* Init descriptors */ 2370 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2371 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2372 "memory for rx buffers\n"); 2373 msk_stop(ifp, 1); 2374 splx(s); 2375 return ENOBUFS; 2376 } 2377 2378 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2379 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2380 "memory for tx buffers\n"); 2381 msk_stop(ifp, 1); 2382 splx(s); 2383 return ENOBUFS; 2384 } 2385 2386 /* Set interrupt moderation if changed via sysctl. */ 2387 switch (sc->sk_type) { 2388 case SK_YUKON_EC: 2389 case SK_YUKON_EC_U: 2390 case SK_YUKON_EX: 2391 case SK_YUKON_SUPR: 2392 case SK_YUKON_ULTRA2: 2393 case SK_YUKON_OPTIMA: 2394 case SK_YUKON_PRM: 2395 case SK_YUKON_OPTIMA2: 2396 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2397 break; 2398 case SK_YUKON_FE: 2399 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2400 break; 2401 case SK_YUKON_FE_P: 2402 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 2403 break; 2404 case SK_YUKON_XL: 2405 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2406 break; 2407 default: 2408 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2409 } 2410 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2411 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2412 sk_win_write_4(sc, SK_IMTIMERINIT, 2413 SK_IM_USECS(sc->sk_int_mod)); 2414 aprint_verbose_dev(sc->sk_dev, 2415 "interrupt moderation is %d us\n", sc->sk_int_mod); 2416 } 2417 2418 /* Initialize prefetch engine. */ 2419 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2420 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2421 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2422 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2423 MSK_RX_RING_ADDR(sc_if, 0)); 2424 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2425 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2426 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2427 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2428 2429 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2430 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2431 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2432 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2433 MSK_TX_RING_ADDR(sc_if, 0)); 2434 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2435 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2436 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2437 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2438 2439 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2440 sc_if->sk_cdata.sk_rx_prod); 2441 2442 /* Configure interrupt handling */ 2443 if (sc_if->sk_port == SK_PORT_A) 2444 sc->sk_intrmask |= SK_Y2_INTRS1; 2445 else 2446 sc->sk_intrmask |= SK_Y2_INTRS2; 2447 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2448 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2449 2450 ifp->if_flags |= IFF_RUNNING; 2451 ifp->if_flags &= ~IFF_OACTIVE; 2452 2453 callout_schedule(&sc_if->sk_tick_ch, hz); 2454 2455 out: 2456 splx(s); 2457 return rc; 2458 } 2459 2460 /* 2461 * Note: the logic of second parameter is inverted compared to OpenBSD 2462 * code, since this code uses the function as if_stop hook too. 2463 */ 2464 void 2465 msk_stop(struct ifnet *ifp, int disable) 2466 { 2467 struct sk_if_softc *sc_if = ifp->if_softc; 2468 struct sk_softc *sc = sc_if->sk_softc; 2469 struct sk_txmap_entry *dma; 2470 int i; 2471 2472 DPRINTFN(2, ("msk_stop\n")); 2473 2474 callout_stop(&sc_if->sk_tick_ch); 2475 callout_stop(&sc_if->sk_tick_rx); 2476 2477 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2478 2479 /* Stop transfer of Tx descriptors */ 2480 2481 /* Stop transfer of Rx descriptors */ 2482 2483 if (disable) { 2484 /* Turn off various components of this interface. */ 2485 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2486 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2487 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2488 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2489 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2490 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2491 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2492 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2493 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2494 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2495 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2496 2497 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2498 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2499 2500 /* Disable interrupts */ 2501 if (sc_if->sk_port == SK_PORT_A) 2502 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2503 else 2504 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2505 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2506 } 2507 2508 /* Free RX and TX mbufs still in the queues. */ 2509 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2510 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2511 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2512 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2513 } 2514 } 2515 2516 sc_if->sk_cdata.sk_rx_prod = 0; 2517 sc_if->sk_cdata.sk_rx_cons = 0; 2518 sc_if->sk_cdata.sk_rx_cnt = 0; 2519 2520 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2521 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2522 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2523 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2524 #if 1 2525 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2526 sc_if->sk_cdata.sk_tx_map[i], link); 2527 sc_if->sk_cdata.sk_tx_map[i] = 0; 2528 #endif 2529 } 2530 } 2531 2532 #if 1 2533 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2534 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2535 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2536 free(dma, M_DEVBUF); 2537 } 2538 #endif 2539 } 2540 2541 CFATTACH_DECL3_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2542 mskc_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2543 2544 CFATTACH_DECL3_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2545 msk_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2546 2547 #ifdef MSK_DEBUG 2548 void 2549 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2550 { 2551 #define DESC_PRINT(X) \ 2552 if (X) \ 2553 printf("txdesc[%d]." #X "=%#x\n", \ 2554 idx, X); 2555 2556 DESC_PRINT(letoh32(le->sk_addr)); 2557 DESC_PRINT(letoh16(le->sk_len)); 2558 DESC_PRINT(le->sk_ctl); 2559 DESC_PRINT(le->sk_opcode); 2560 #undef DESC_PRINT 2561 } 2562 2563 void 2564 msk_dump_bytes(const char *data, int len) 2565 { 2566 int c, i, j; 2567 2568 for (i = 0; i < len; i += 16) { 2569 printf("%08x ", i); 2570 c = len - i; 2571 if (c > 16) c = 16; 2572 2573 for (j = 0; j < c; j++) { 2574 printf("%02x ", data[i + j] & 0xff); 2575 if ((j & 0xf) == 7 && j > 0) 2576 printf(" "); 2577 } 2578 2579 for (; j < 16; j++) 2580 printf(" "); 2581 printf(" "); 2582 2583 for (j = 0; j < c; j++) { 2584 int ch = data[i + j] & 0xff; 2585 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2586 } 2587 2588 printf("\n"); 2589 2590 if (c < 16) 2591 break; 2592 } 2593 } 2594 2595 void 2596 msk_dump_mbuf(struct mbuf *m) 2597 { 2598 int count = m->m_pkthdr.len; 2599 2600 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2601 2602 while (count > 0 && m) { 2603 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2604 m, m->m_data, m->m_len); 2605 msk_dump_bytes(mtod(m, char *), m->m_len); 2606 2607 count -= m->m_len; 2608 m = m->m_next; 2609 } 2610 } 2611 #endif 2612 2613 static int 2614 msk_sysctl_handler(SYSCTLFN_ARGS) 2615 { 2616 int error, t; 2617 struct sysctlnode node; 2618 struct sk_softc *sc; 2619 2620 node = *rnode; 2621 sc = node.sysctl_data; 2622 t = sc->sk_int_mod; 2623 node.sysctl_data = &t; 2624 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2625 if (error || newp == NULL) 2626 return error; 2627 2628 if (t < SK_IM_MIN || t > SK_IM_MAX) 2629 return EINVAL; 2630 2631 /* update the softc with sysctl-changed value, and mark 2632 for hardware update */ 2633 sc->sk_int_mod = t; 2634 sc->sk_int_mod_pending = 1; 2635 return 0; 2636 } 2637 2638 /* 2639 * Set up sysctl(3) MIB, hw.msk.* - Individual controllers will be 2640 * set up in mskc_attach() 2641 */ 2642 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2643 { 2644 int rc; 2645 const struct sysctlnode *node; 2646 2647 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2648 0, CTLTYPE_NODE, "msk", 2649 SYSCTL_DESCR("msk interface controls"), 2650 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2651 goto err; 2652 } 2653 2654 msk_root_num = node->sysctl_num; 2655 return; 2656 2657 err: 2658 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2659 } 2660
Indexes created Wed Sep 24 02:09:48 GMT 2025