if_msk.c revision 1.82
1 /* $NetBSD: if_msk.c,v 1.82 2018/12/27 08:13:50 mrg Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.79 2009/10/15 17:54:56 deraadt Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.82 2018/12/27 08:13:50 mrg Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/mutex.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/device.h> 66 #include <sys/queue.h> 67 #include <sys/callout.h> 68 #include <sys/sysctl.h> 69 #include <sys/endian.h> 70 #ifdef __NetBSD__ 71 #define letoh16 htole16 72 #define letoh32 htole32 73 #endif 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #include <net/if_media.h> 80 81 #include <net/bpf.h> 82 #include <sys/rndsource.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 #include <dev/mii/brgphyreg.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 92 #include <dev/pci/if_skreg.h> 93 #include <dev/pci/if_mskvar.h> 94 95 int mskc_probe(device_t, cfdata_t, void *); 96 void mskc_attach(device_t, device_t, void *); 97 int mskc_detach(device_t, int); 98 void mskc_reset(struct sk_softc *); 99 static bool mskc_suspend(device_t, const pmf_qual_t *); 100 static bool mskc_resume(device_t, const pmf_qual_t *); 101 int msk_probe(device_t, cfdata_t, void *); 102 void msk_attach(device_t, device_t, void *); 103 int msk_detach(device_t, int); 104 void msk_reset(struct sk_if_softc *); 105 int mskcprint(void *, const char *); 106 int msk_intr(void *); 107 void msk_intr_yukon(struct sk_if_softc *); 108 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 109 void msk_txeof(struct sk_if_softc *); 110 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 111 void msk_start(struct ifnet *); 112 int msk_ioctl(struct ifnet *, u_long, void *); 113 int msk_init(struct ifnet *); 114 void msk_init_yukon(struct sk_if_softc *); 115 void msk_stop(struct ifnet *, int); 116 void msk_watchdog(struct ifnet *); 117 int msk_newbuf(struct sk_if_softc *, bus_dmamap_t); 118 int msk_alloc_jumbo_mem(struct sk_if_softc *); 119 void *msk_jalloc(struct sk_if_softc *); 120 void msk_jfree(struct mbuf *, void *, size_t, void *); 121 int msk_init_rx_ring(struct sk_if_softc *); 122 int msk_init_tx_ring(struct sk_if_softc *); 123 void msk_fill_rx_ring(struct sk_if_softc *); 124 125 void msk_update_int_mod(struct sk_softc *, int); 126 127 int msk_miibus_readreg(device_t, int, int); 128 void msk_miibus_writereg(device_t, int, int, int); 129 void msk_miibus_statchg(struct ifnet *); 130 131 void msk_setmulti(struct sk_if_softc *); 132 void msk_setpromisc(struct sk_if_softc *); 133 void msk_tick(void *); 134 static void msk_fill_rx_tick(void *); 135 136 /* #define MSK_DEBUG 1 */ 137 #ifdef MSK_DEBUG 138 #define DPRINTF(x) if (mskdebug) printf x 139 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 140 int mskdebug = MSK_DEBUG; 141 142 void msk_dump_txdesc(struct msk_tx_desc *, int); 143 void msk_dump_mbuf(struct mbuf *); 144 void msk_dump_bytes(const char *, int); 145 #else 146 #define DPRINTF(x) 147 #define DPRINTFN(n,x) 148 #endif 149 150 static int msk_sysctl_handler(SYSCTLFN_PROTO); 151 static int msk_root_num; 152 153 #define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL) 154 #define MSK_ADDR_HI(x) ((uint64_t) (x) >> 32) 155 156 /* supported device vendors */ 157 static const struct msk_product { 158 pci_vendor_id_t msk_vendor; 159 pci_product_id_t msk_product; 160 } msk_products[] = { 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 163 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 164 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8079 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 197 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 198 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 199 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 200 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 201 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 }, 202 { 0, 0 } 203 }; 204 205 static inline u_int32_t 206 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 207 { 208 return CSR_READ_4(sc, reg); 209 } 210 211 static inline u_int16_t 212 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 213 { 214 return CSR_READ_2(sc, reg); 215 } 216 217 static inline u_int8_t 218 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 219 { 220 return CSR_READ_1(sc, reg); 221 } 222 223 static inline void 224 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 225 { 226 CSR_WRITE_4(sc, reg, x); 227 } 228 229 static inline void 230 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 231 { 232 CSR_WRITE_2(sc, reg, x); 233 } 234 235 static inline void 236 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 237 { 238 CSR_WRITE_1(sc, reg, x); 239 } 240 241 int 242 msk_miibus_readreg(device_t dev, int phy, int reg) 243 { 244 struct sk_if_softc *sc_if = device_private(dev); 245 u_int16_t val; 246 int i; 247 248 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 249 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 250 251 for (i = 0; i < SK_TIMEOUT; i++) { 252 DELAY(1); 253 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 254 if (val & YU_SMICR_READ_VALID) 255 break; 256 } 257 258 if (i == SK_TIMEOUT) { 259 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 260 return (0); 261 } 262 263 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 264 SK_TIMEOUT)); 265 266 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 267 268 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 269 phy, reg, val)); 270 271 return (val); 272 } 273 274 void 275 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 276 { 277 struct sk_if_softc *sc_if = device_private(dev); 278 int i; 279 280 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 281 phy, reg, val)); 282 283 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 284 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 285 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 286 287 for (i = 0; i < SK_TIMEOUT; i++) { 288 DELAY(1); 289 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 290 break; 291 } 292 293 if (i == SK_TIMEOUT) 294 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 295 } 296 297 void 298 msk_miibus_statchg(struct ifnet *ifp) 299 { 300 struct sk_if_softc *sc_if = ifp->if_softc; 301 struct mii_data *mii = &sc_if->sk_mii; 302 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 303 int gpcr; 304 305 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 306 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 307 308 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 309 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 310 /* Set speed. */ 311 gpcr |= YU_GPCR_SPEED_DIS; 312 switch (IFM_SUBTYPE(mii->mii_media_active)) { 313 case IFM_1000_SX: 314 case IFM_1000_LX: 315 case IFM_1000_CX: 316 case IFM_1000_T: 317 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 318 break; 319 case IFM_100_TX: 320 gpcr |= YU_GPCR_SPEED; 321 break; 322 } 323 324 /* Set duplex. */ 325 gpcr |= YU_GPCR_DPLX_DIS; 326 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 327 gpcr |= YU_GPCR_DUPLEX; 328 329 /* Disable flow control. */ 330 gpcr |= YU_GPCR_FCTL_DIS; 331 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 332 } 333 334 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 335 336 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 337 SK_YU_READ_2(sc_if, YUKON_GPCR))); 338 } 339 340 void 341 msk_setmulti(struct sk_if_softc *sc_if) 342 { 343 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 344 u_int32_t hashes[2] = { 0, 0 }; 345 int h; 346 struct ethercom *ec = &sc_if->sk_ethercom; 347 struct ether_multi *enm; 348 struct ether_multistep step; 349 u_int16_t reg; 350 351 /* First, zot all the existing filters. */ 352 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 353 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 354 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 355 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 356 357 358 /* Now program new ones. */ 359 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 360 reg |= YU_RCR_UFLEN; 361 allmulti: 362 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 363 if ((ifp->if_flags & IFF_PROMISC) != 0) 364 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 365 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 366 hashes[0] = 0xFFFFFFFF; 367 hashes[1] = 0xFFFFFFFF; 368 } 369 } else { 370 /* First find the tail of the list. */ 371 ETHER_FIRST_MULTI(step, ec, enm); 372 while (enm != NULL) { 373 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 374 ETHER_ADDR_LEN)) { 375 ifp->if_flags |= IFF_ALLMULTI; 376 goto allmulti; 377 } 378 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 379 ((1 << SK_HASH_BITS) - 1); 380 if (h < 32) 381 hashes[0] |= (1 << h); 382 else 383 hashes[1] |= (1 << (h - 32)); 384 385 ETHER_NEXT_MULTI(step, enm); 386 } 387 reg |= YU_RCR_MUFLEN; 388 } 389 390 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 391 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 392 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 393 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 394 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 395 } 396 397 void 398 msk_setpromisc(struct sk_if_softc *sc_if) 399 { 400 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 401 402 if (ifp->if_flags & IFF_PROMISC) 403 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 404 YU_RCR_UFLEN | YU_RCR_MUFLEN); 405 else 406 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 407 YU_RCR_UFLEN | YU_RCR_MUFLEN); 408 } 409 410 int 411 msk_init_rx_ring(struct sk_if_softc *sc_if) 412 { 413 struct msk_chain_data *cd = &sc_if->sk_cdata; 414 struct msk_ring_data *rd = sc_if->sk_rdata; 415 struct msk_rx_desc *r; 416 int i, nexti; 417 418 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 419 420 for (i = 0; i < MSK_RX_RING_CNT; i++) { 421 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 422 if (i == (MSK_RX_RING_CNT - 1)) 423 nexti = 0; 424 else 425 nexti = i + 1; 426 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 427 } 428 429 sc_if->sk_cdata.sk_rx_prod = 0; 430 sc_if->sk_cdata.sk_rx_cons = 0; 431 sc_if->sk_cdata.sk_rx_cnt = 0; 432 sc_if->sk_cdata.sk_rx_hiaddr = 0; 433 434 /* Mark the first ring element to initialize the high address. */ 435 sc_if->sk_cdata.sk_rx_hiaddr = 0; 436 r = &rd->sk_rx_ring[cd->sk_rx_prod]; 437 r->sk_addr = htole32(cd->sk_rx_hiaddr); 438 r->sk_len = 0; 439 r->sk_ctl = 0; 440 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN; 441 MSK_CDRXSYNC(sc_if, cd->sk_rx_prod, 442 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 443 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 444 sc_if->sk_cdata.sk_rx_cnt++; 445 446 msk_fill_rx_ring(sc_if); 447 return (0); 448 } 449 450 int 451 msk_init_tx_ring(struct sk_if_softc *sc_if) 452 { 453 struct sk_softc *sc = sc_if->sk_softc; 454 struct msk_chain_data *cd = &sc_if->sk_cdata; 455 struct msk_ring_data *rd = sc_if->sk_rdata; 456 struct msk_tx_desc *t; 457 bus_dmamap_t dmamap; 458 struct sk_txmap_entry *entry; 459 int i, nexti; 460 461 memset(rd->sk_tx_ring, 0, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 462 463 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 464 for (i = 0; i < MSK_TX_RING_CNT; i++) { 465 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 466 if (i == (MSK_TX_RING_CNT - 1)) 467 nexti = 0; 468 else 469 nexti = i + 1; 470 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 471 472 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 473 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 474 return (ENOBUFS); 475 476 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 477 if (!entry) { 478 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 479 return (ENOBUFS); 480 } 481 entry->dmamap = dmamap; 482 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 483 } 484 485 sc_if->sk_cdata.sk_tx_prod = 0; 486 sc_if->sk_cdata.sk_tx_cons = 0; 487 sc_if->sk_cdata.sk_tx_cnt = 0; 488 sc_if->sk_cdata.sk_tx_hiaddr = 0; 489 490 /* Mark the first ring element to initialize the high address. */ 491 sc_if->sk_cdata.sk_tx_hiaddr = 0; 492 t = &rd->sk_tx_ring[cd->sk_tx_prod]; 493 t->sk_addr = htole32(cd->sk_tx_hiaddr); 494 t->sk_len = 0; 495 t->sk_ctl = 0; 496 t->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 497 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 498 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 499 SK_INC(sc_if->sk_cdata.sk_tx_prod, MSK_TX_RING_CNT); 500 sc_if->sk_cdata.sk_tx_cnt++; 501 502 return (0); 503 } 504 505 int 506 msk_newbuf(struct sk_if_softc *sc_if, bus_dmamap_t dmamap) 507 { 508 struct mbuf *m_new = NULL; 509 struct sk_chain *c; 510 struct msk_rx_desc *r; 511 void *buf = NULL; 512 bus_addr_t addr; 513 514 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 515 if (m_new == NULL) 516 return (ENOBUFS); 517 518 /* Allocate the jumbo buffer */ 519 buf = msk_jalloc(sc_if); 520 if (buf == NULL) { 521 m_freem(m_new); 522 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 523 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 524 return (ENOBUFS); 525 } 526 527 /* Attach the buffer to the mbuf */ 528 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 529 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 530 531 m_adj(m_new, ETHER_ALIGN); 532 533 addr = dmamap->dm_segs[0].ds_addr + 534 ((vaddr_t)m_new->m_data - 535 (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf); 536 537 if (sc_if->sk_cdata.sk_rx_hiaddr != MSK_ADDR_HI(addr)) { 538 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 539 r = c->sk_le; 540 c->sk_mbuf = NULL; 541 r->sk_addr = htole32(MSK_ADDR_HI(addr)); 542 r->sk_len = 0; 543 r->sk_ctl = 0; 544 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN; 545 sc_if->sk_cdata.sk_rx_hiaddr = MSK_ADDR_HI(addr); 546 547 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 548 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 549 550 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 551 sc_if->sk_cdata.sk_rx_cnt++; 552 553 DPRINTFN(10, ("%s: rx ADDR64: %#x\n", 554 sc_if->sk_ethercom.ec_if.if_xname, (unsigned)MSK_ADDR_HI(addr))); 555 } 556 557 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 558 r = c->sk_le; 559 c->sk_mbuf = m_new; 560 r->sk_addr = htole32(MSK_ADDR_LO(addr)); 561 r->sk_len = htole16(SK_JLEN); 562 r->sk_ctl = 0; 563 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 564 565 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 566 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 567 568 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 569 sc_if->sk_cdata.sk_rx_cnt++; 570 571 return (0); 572 } 573 574 /* 575 * Memory management for jumbo frames. 576 */ 577 578 int 579 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 580 { 581 struct sk_softc *sc = sc_if->sk_softc; 582 char *ptr, *kva; 583 int i, state, error; 584 struct sk_jpool_entry *entry; 585 586 state = error = 0; 587 588 /* Grab a big chunk o' storage. */ 589 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 590 &sc_if->sk_cdata.sk_jumbo_seg, 1, &sc_if->sk_cdata.sk_jumbo_nseg, 591 BUS_DMA_NOWAIT)) { 592 aprint_error(": can't alloc rx buffers"); 593 return (ENOBUFS); 594 } 595 596 state = 1; 597 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 598 sc_if->sk_cdata.sk_jumbo_nseg, MSK_JMEM, (void **)&kva, 599 BUS_DMA_NOWAIT)) { 600 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 601 error = ENOBUFS; 602 goto out; 603 } 604 605 state = 2; 606 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 607 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 608 aprint_error(": can't create dma map"); 609 error = ENOBUFS; 610 goto out; 611 } 612 613 state = 3; 614 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 615 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 616 aprint_error(": can't load dma map"); 617 error = ENOBUFS; 618 goto out; 619 } 620 621 state = 4; 622 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 623 DPRINTFN(1,("msk_jumbo_buf = %p\n", (void *)sc_if->sk_cdata.sk_jumbo_buf)); 624 625 LIST_INIT(&sc_if->sk_jfree_listhead); 626 LIST_INIT(&sc_if->sk_jinuse_listhead); 627 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 628 629 /* 630 * Now divide it up into 9K pieces and save the addresses 631 * in an array. 632 */ 633 ptr = sc_if->sk_cdata.sk_jumbo_buf; 634 for (i = 0; i < MSK_JSLOTS; i++) { 635 sc_if->sk_cdata.sk_jslots[i] = ptr; 636 ptr += SK_JLEN; 637 entry = malloc(sizeof(struct sk_jpool_entry), 638 M_DEVBUF, M_NOWAIT); 639 if (entry == NULL) { 640 sc_if->sk_cdata.sk_jumbo_buf = NULL; 641 aprint_error(": no memory for jumbo buffer queue!"); 642 error = ENOBUFS; 643 goto out; 644 } 645 entry->slot = i; 646 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 647 entry, jpool_entries); 648 } 649 out: 650 if (error != 0) { 651 switch (state) { 652 case 4: 653 bus_dmamap_unload(sc->sc_dmatag, 654 sc_if->sk_cdata.sk_rx_jumbo_map); 655 case 3: 656 bus_dmamap_destroy(sc->sc_dmatag, 657 sc_if->sk_cdata.sk_rx_jumbo_map); 658 case 2: 659 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 660 case 1: 661 bus_dmamem_free(sc->sc_dmatag, 662 &sc_if->sk_cdata.sk_jumbo_seg, 663 sc_if->sk_cdata.sk_jumbo_nseg); 664 break; 665 default: 666 break; 667 } 668 } 669 670 return error; 671 } 672 673 static void 674 msk_free_jumbo_mem(struct sk_if_softc *sc_if) 675 { 676 struct sk_softc *sc = sc_if->sk_softc; 677 678 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 679 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 680 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_cdata.sk_jumbo_buf, MSK_JMEM); 681 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 682 sc_if->sk_cdata.sk_jumbo_nseg); 683 } 684 685 /* 686 * Allocate a jumbo buffer. 687 */ 688 void * 689 msk_jalloc(struct sk_if_softc *sc_if) 690 { 691 struct sk_jpool_entry *entry; 692 693 mutex_enter(&sc_if->sk_jpool_mtx); 694 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 695 696 if (entry == NULL) { 697 mutex_exit(&sc_if->sk_jpool_mtx); 698 return NULL; 699 } 700 701 LIST_REMOVE(entry, jpool_entries); 702 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 703 mutex_exit(&sc_if->sk_jpool_mtx); 704 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 705 } 706 707 /* 708 * Release a jumbo buffer. 709 */ 710 void 711 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 712 { 713 struct sk_jpool_entry *entry; 714 struct sk_if_softc *sc; 715 int i; 716 717 /* Extract the softc struct pointer. */ 718 sc = (struct sk_if_softc *)arg; 719 720 if (sc == NULL) 721 panic("msk_jfree: can't find softc pointer!"); 722 723 /* calculate the slot this buffer belongs to */ 724 i = ((vaddr_t)buf 725 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 726 727 if ((i < 0) || (i >= MSK_JSLOTS)) 728 panic("msk_jfree: asked to free buffer that we don't manage!"); 729 730 mutex_enter(&sc->sk_jpool_mtx); 731 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 732 if (entry == NULL) 733 panic("msk_jfree: buffer not in use!"); 734 entry->slot = i; 735 LIST_REMOVE(entry, jpool_entries); 736 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 737 mutex_exit(&sc->sk_jpool_mtx); 738 739 if (__predict_true(m != NULL)) 740 pool_cache_put(mb_cache, m); 741 742 /* Now that we know we have a free RX buffer, refill if running out */ 743 if ((sc->sk_ethercom.ec_if.if_flags & IFF_RUNNING) != 0 744 && sc->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 745 callout_schedule(&sc->sk_tick_rx, 0); 746 } 747 748 int 749 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 750 { 751 struct sk_if_softc *sc = ifp->if_softc; 752 int s, error; 753 754 s = splnet(); 755 756 DPRINTFN(2, ("msk_ioctl ETHER cmd %lx\n", cmd)); 757 switch (cmd) { 758 case SIOCSIFFLAGS: 759 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 760 break; 761 762 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 763 case IFF_RUNNING: 764 msk_stop(ifp, 1); 765 break; 766 case IFF_UP: 767 msk_init(ifp); 768 break; 769 case IFF_UP | IFF_RUNNING: 770 if ((ifp->if_flags ^ sc->sk_if_flags) == IFF_PROMISC) { 771 msk_setpromisc(sc); 772 msk_setmulti(sc); 773 } else 774 msk_init(ifp); 775 break; 776 } 777 sc->sk_if_flags = ifp->if_flags; 778 break; 779 default: 780 error = ether_ioctl(ifp, cmd, data); 781 if (error == ENETRESET) { 782 error = 0; 783 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 784 ; 785 else if (ifp->if_flags & IFF_RUNNING) { 786 /* 787 * Multicast list has changed; set the hardware 788 * filter accordingly. 789 */ 790 msk_setmulti(sc); 791 } 792 } 793 break; 794 } 795 796 splx(s); 797 return error; 798 } 799 800 void 801 msk_update_int_mod(struct sk_softc *sc, int verbose) 802 { 803 u_int32_t imtimer_ticks; 804 805 /* 806 * Configure interrupt moderation. The moderation timer 807 * defers interrupts specified in the interrupt moderation 808 * timer mask based on the timeout specified in the interrupt 809 * moderation timer init register. Each bit in the timer 810 * register represents one tick, so to specify a timeout in 811 * microseconds, we have to multiply by the correct number of 812 * ticks-per-microsecond. 813 */ 814 switch (sc->sk_type) { 815 case SK_YUKON_EC: 816 case SK_YUKON_EC_U: 817 case SK_YUKON_EX: 818 case SK_YUKON_SUPR: 819 case SK_YUKON_ULTRA2: 820 case SK_YUKON_OPTIMA: 821 case SK_YUKON_PRM: 822 case SK_YUKON_OPTIMA2: 823 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 824 break; 825 case SK_YUKON_FE: 826 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 827 break; 828 case SK_YUKON_FE_P: 829 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 830 break; 831 case SK_YUKON_XL: 832 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 833 break; 834 default: 835 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 836 } 837 if (verbose) 838 aprint_verbose_dev(sc->sk_dev, 839 "interrupt moderation is %d us\n", sc->sk_int_mod); 840 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 841 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 842 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 843 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 844 sc->sk_int_mod_pending = 0; 845 } 846 847 static int 848 msk_lookup(const struct pci_attach_args *pa) 849 { 850 const struct msk_product *pmsk; 851 852 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 853 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 854 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 855 return 1; 856 } 857 return 0; 858 } 859 860 /* 861 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 862 * IDs against our list and return a device name if we find a match. 863 */ 864 int 865 mskc_probe(device_t parent, cfdata_t match, void *aux) 866 { 867 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 868 869 return msk_lookup(pa); 870 } 871 872 /* 873 * Force the GEnesis into reset, then bring it out of reset. 874 */ 875 void 876 mskc_reset(struct sk_softc *sc) 877 { 878 u_int32_t imtimer_ticks, reg1; 879 int reg; 880 881 DPRINTFN(2, ("mskc_reset\n")); 882 883 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 884 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 885 886 DELAY(1000); 887 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 888 DELAY(2); 889 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 890 sk_win_write_1(sc, SK_TESTCTL1, 2); 891 892 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 893 sc->sk_type >= SK_YUKON_FE_P) { 894 uint32_t our; 895 896 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 897 898 /* enable all clocks. */ 899 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 900 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 901 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST| 902 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN| 903 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY| 904 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 905 /* Set all bits to 0 except bits 15..12 */ 906 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 907 /* Set to default value */ 908 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 909 910 /* 911 * Disable status race, workaround for Yukon EC Ultra & 912 * Yukon EX. 913 */ 914 reg1 = sk_win_read_4(sc, SK_GPIO); 915 reg1 |= SK_Y2_GPIO_STAT_RACE_DIS; 916 sk_win_write_4(sc, SK_GPIO, reg1); 917 sk_win_read_4(sc, SK_GPIO); 918 } 919 920 /* release PHY from PowerDown/Coma mode. */ 921 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 922 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 923 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 924 else 925 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 926 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 927 928 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 929 sk_win_write_1(sc, SK_Y2_CLKGATE, 930 SK_Y2_CLKGATE_LINK1_GATE_DIS | 931 SK_Y2_CLKGATE_LINK2_GATE_DIS | 932 SK_Y2_CLKGATE_LINK1_CORE_DIS | 933 SK_Y2_CLKGATE_LINK2_CORE_DIS | 934 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 935 else 936 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 937 938 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 939 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 940 DELAY(1000); 941 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 942 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 943 944 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 945 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 946 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 947 } 948 949 sk_win_write_1(sc, SK_TESTCTL1, 1); 950 951 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 952 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 953 CSR_READ_2(sc, SK_LINK_CTRL))); 954 955 /* Disable ASF */ 956 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 957 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 958 959 /* Clear I2C IRQ noise */ 960 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 961 962 /* Disable hardware timer */ 963 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 964 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 965 966 /* Disable descriptor polling */ 967 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 968 969 /* Disable time stamps */ 970 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 971 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 972 973 /* Enable RAM interface */ 974 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 975 for (reg = SK_TO0;reg <= SK_TO11; reg++) 976 sk_win_write_1(sc, reg, 36); 977 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 978 for (reg = SK_TO0;reg <= SK_TO11; reg++) 979 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 980 981 /* 982 * Configure interrupt moderation. The moderation timer 983 * defers interrupts specified in the interrupt moderation 984 * timer mask based on the timeout specified in the interrupt 985 * moderation timer init register. Each bit in the timer 986 * register represents one tick, so to specify a timeout in 987 * microseconds, we have to multiply by the correct number of 988 * ticks-per-microsecond. 989 */ 990 switch (sc->sk_type) { 991 case SK_YUKON_EC: 992 case SK_YUKON_EC_U: 993 case SK_YUKON_EX: 994 case SK_YUKON_SUPR: 995 case SK_YUKON_ULTRA2: 996 case SK_YUKON_OPTIMA: 997 case SK_YUKON_PRM: 998 case SK_YUKON_OPTIMA2: 999 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1000 break; 1001 case SK_YUKON_FE: 1002 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 1003 break; 1004 case SK_YUKON_FE_P: 1005 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 1006 break; 1007 case SK_YUKON_XL: 1008 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 1009 break; 1010 default: 1011 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1012 break; 1013 } 1014 1015 /* Reset status ring. */ 1016 memset(sc->sk_status_ring, 0, 1017 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1018 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 1019 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1020 sc->sk_status_idx = 0; 1021 1022 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 1023 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 1024 1025 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 1026 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 1027 MSK_ADDR_LO(sc->sk_status_map->dm_segs[0].ds_addr)); 1028 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 1029 MSK_ADDR_HI(sc->sk_status_map->dm_segs[0].ds_addr)); 1030 if (sc->sk_type == SK_YUKON_EC && 1031 sc->sk_rev == SK_YUKON_EC_REV_A1) { 1032 /* WA for dev. #4.3 */ 1033 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK); 1034 /* WA for dev. #4.18 */ 1035 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 1036 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 1037 } else { 1038 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 1039 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 1040 if (sc->sk_type == SK_YUKON_XL) 1041 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x04); 1042 else 1043 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x10); 1044 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 1045 } 1046 1047 #if 0 1048 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 1049 #endif 1050 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 1051 1052 /* Enable status unit. */ 1053 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 1054 1055 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 1056 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 1057 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 1058 1059 msk_update_int_mod(sc, 0); 1060 } 1061 1062 int 1063 msk_probe(device_t parent, cfdata_t match, void *aux) 1064 { 1065 struct skc_attach_args *sa = aux; 1066 1067 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1068 return (0); 1069 1070 switch (sa->skc_type) { 1071 case SK_YUKON_XL: 1072 case SK_YUKON_EC_U: 1073 case SK_YUKON_EX: 1074 case SK_YUKON_EC: 1075 case SK_YUKON_FE: 1076 case SK_YUKON_FE_P: 1077 case SK_YUKON_SUPR: 1078 case SK_YUKON_ULTRA2: 1079 case SK_YUKON_OPTIMA: 1080 case SK_YUKON_PRM: 1081 case SK_YUKON_OPTIMA2: 1082 return (1); 1083 } 1084 1085 return (0); 1086 } 1087 1088 void 1089 msk_reset(struct sk_if_softc *sc_if) 1090 { 1091 /* GMAC and GPHY Reset */ 1092 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1093 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1094 DELAY(1000); 1095 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1096 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1097 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1098 } 1099 1100 static bool 1101 msk_resume(device_t dv, const pmf_qual_t *qual) 1102 { 1103 struct sk_if_softc *sc_if = device_private(dv); 1104 1105 msk_init_yukon(sc_if); 1106 return true; 1107 } 1108 1109 /* 1110 * Each XMAC chip is attached as a separate logical IP interface. 1111 * Single port cards will have only one logical interface of course. 1112 */ 1113 void 1114 msk_attach(device_t parent, device_t self, void *aux) 1115 { 1116 struct sk_if_softc *sc_if = device_private(self); 1117 struct sk_softc *sc = device_private(parent); 1118 struct skc_attach_args *sa = aux; 1119 struct ifnet *ifp; 1120 void *kva; 1121 int i; 1122 u_int32_t chunk; 1123 int mii_flags; 1124 1125 sc_if->sk_dev = self; 1126 sc_if->sk_port = sa->skc_port; 1127 sc_if->sk_softc = sc; 1128 sc->sk_if[sa->skc_port] = sc_if; 1129 1130 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1131 1132 /* 1133 * Get station address for this interface. Note that 1134 * dual port cards actually come with three station 1135 * addresses: one for each port, plus an extra. The 1136 * extra one is used by the SysKonnect driver software 1137 * as a 'virtual' station address for when both ports 1138 * are operating in failover mode. Currently we don't 1139 * use this extra address. 1140 */ 1141 for (i = 0; i < ETHER_ADDR_LEN; i++) 1142 sc_if->sk_enaddr[i] = 1143 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1144 1145 aprint_normal(": Ethernet address %s\n", 1146 ether_sprintf(sc_if->sk_enaddr)); 1147 1148 /* 1149 * Set up RAM buffer addresses. The Yukon2 has a small amount 1150 * of SRAM on it, somewhere between 4K and 48K. We need to 1151 * divide this up between the transmitter and receiver. We 1152 * give the receiver 2/3 of the memory (rounded down), and the 1153 * transmitter whatever remains. 1154 */ 1155 if (sc->sk_ramsize) { 1156 chunk = (2 * (sc->sk_ramsize / sizeof(u_int64_t)) / 3) & ~0xff; 1157 sc_if->sk_rx_ramstart = 0; 1158 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 1159 chunk = (sc->sk_ramsize / sizeof(u_int64_t)) - chunk; 1160 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 1161 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 1162 1163 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1164 " tx_ramstart=%#x tx_ramend=%#x\n", 1165 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1166 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1167 } 1168 1169 /* Allocate the descriptor queues. */ 1170 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1171 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 1172 BUS_DMA_NOWAIT)) { 1173 aprint_error(": can't alloc rx buffers\n"); 1174 goto fail; 1175 } 1176 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 1177 sc_if->sk_ring_nseg, 1178 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1179 aprint_error(": can't map dma buffers (%zu bytes)\n", 1180 sizeof(struct msk_ring_data)); 1181 goto fail_1; 1182 } 1183 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1184 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1185 &sc_if->sk_ring_map)) { 1186 aprint_error(": can't create dma map\n"); 1187 goto fail_2; 1188 } 1189 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1190 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1191 aprint_error(": can't load dma map\n"); 1192 goto fail_3; 1193 } 1194 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1195 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1196 1197 if (sc->sk_type != SK_YUKON_FE && 1198 sc->sk_type != SK_YUKON_FE_P) 1199 sc_if->sk_pktlen = SK_JLEN; 1200 else 1201 sc_if->sk_pktlen = MCLBYTES; 1202 1203 /* Try to allocate memory for jumbo buffers. */ 1204 if (msk_alloc_jumbo_mem(sc_if)) { 1205 aprint_error(": jumbo buffer allocation failed\n"); 1206 goto fail_3; 1207 } 1208 1209 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1210 if (sc->sk_type != SK_YUKON_FE && 1211 sc->sk_type != SK_YUKON_FE_P) 1212 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1213 1214 ifp = &sc_if->sk_ethercom.ec_if; 1215 ifp->if_softc = sc_if; 1216 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1217 ifp->if_ioctl = msk_ioctl; 1218 ifp->if_start = msk_start; 1219 ifp->if_stop = msk_stop; 1220 ifp->if_init = msk_init; 1221 ifp->if_watchdog = msk_watchdog; 1222 ifp->if_baudrate = 1000000000; 1223 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1224 IFQ_SET_READY(&ifp->if_snd); 1225 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1226 1227 msk_reset(sc_if); 1228 1229 /* 1230 * Do miibus setup. 1231 */ 1232 msk_init_yukon(sc_if); 1233 1234 DPRINTFN(2, ("msk_attach: 1\n")); 1235 1236 sc_if->sk_mii.mii_ifp = ifp; 1237 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1238 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1239 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1240 1241 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1242 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1243 ether_mediachange, ether_mediastatus); 1244 mii_flags = MIIF_DOPAUSE; 1245 if (sc->sk_fibertype) 1246 mii_flags |= MIIF_HAVEFIBER; 1247 mii_attach(self, &sc_if->sk_mii, 0xffffffff, 0, 1248 MII_OFFSET_ANY, mii_flags); 1249 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1250 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1251 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1252 0, NULL); 1253 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1254 } else 1255 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1256 1257 callout_init(&sc_if->sk_tick_ch, 0); 1258 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1259 callout_schedule(&sc_if->sk_tick_ch, hz); 1260 1261 callout_init(&sc_if->sk_tick_rx, 0); 1262 callout_setfunc(&sc_if->sk_tick_rx, msk_fill_rx_tick, sc_if); 1263 1264 /* 1265 * Call MI attach routines. 1266 */ 1267 if_attach(ifp); 1268 if_deferred_start_init(ifp, NULL); 1269 ether_ifattach(ifp, sc_if->sk_enaddr); 1270 1271 if (pmf_device_register(self, NULL, msk_resume)) 1272 pmf_class_network_register(self, ifp); 1273 else 1274 aprint_error_dev(self, "couldn't establish power handler\n"); 1275 1276 if (sc->rnd_attached++ == 0) { 1277 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1278 RND_TYPE_NET, RND_FLAG_DEFAULT); 1279 } 1280 1281 DPRINTFN(2, ("msk_attach: end\n")); 1282 return; 1283 1284 fail_3: 1285 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1286 fail_2: 1287 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1288 fail_1: 1289 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1290 fail: 1291 sc->sk_if[sa->skc_port] = NULL; 1292 } 1293 1294 int 1295 msk_detach(device_t self, int flags) 1296 { 1297 struct sk_if_softc *sc_if = device_private(self); 1298 struct sk_softc *sc = sc_if->sk_softc; 1299 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1300 1301 if (sc->sk_if[sc_if->sk_port] == NULL) 1302 return (0); 1303 1304 msk_stop(ifp, 1); 1305 1306 if (--sc->rnd_attached == 0) 1307 rnd_detach_source(&sc->rnd_source); 1308 1309 callout_halt(&sc_if->sk_tick_ch, NULL); 1310 callout_destroy(&sc_if->sk_tick_ch); 1311 1312 callout_halt(&sc_if->sk_tick_rx, NULL); 1313 callout_destroy(&sc_if->sk_tick_rx); 1314 1315 /* Detach any PHYs we might have. */ 1316 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1317 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1318 1319 /* Delete any remaining media. */ 1320 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY); 1321 1322 pmf_device_deregister(self); 1323 1324 ether_ifdetach(ifp); 1325 if_detach(ifp); 1326 1327 msk_free_jumbo_mem(sc_if); 1328 1329 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_rdata, 1330 sizeof(struct msk_ring_data)); 1331 bus_dmamem_free(sc->sc_dmatag, 1332 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1333 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1334 sc->sk_if[sc_if->sk_port] = NULL; 1335 1336 return (0); 1337 } 1338 1339 int 1340 mskcprint(void *aux, const char *pnp) 1341 { 1342 struct skc_attach_args *sa = aux; 1343 1344 if (pnp) 1345 aprint_normal("msk port %c at %s", 1346 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1347 else 1348 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1349 return (UNCONF); 1350 } 1351 1352 /* 1353 * Attach the interface. Allocate softc structures, do ifmedia 1354 * setup and ethernet/BPF attach. 1355 */ 1356 void 1357 mskc_attach(device_t parent, device_t self, void *aux) 1358 { 1359 struct sk_softc *sc = device_private(self); 1360 struct pci_attach_args *pa = aux; 1361 struct skc_attach_args skca; 1362 pci_chipset_tag_t pc = pa->pa_pc; 1363 pcireg_t command, memtype; 1364 const char *intrstr = NULL; 1365 int rc, sk_nodenum; 1366 u_int8_t hw, pmd; 1367 const char *revstr = NULL; 1368 const struct sysctlnode *node; 1369 void *kva; 1370 char intrbuf[PCI_INTRSTR_LEN]; 1371 1372 DPRINTFN(2, ("begin mskc_attach\n")); 1373 1374 sc->sk_dev = self; 1375 /* 1376 * Handle power management nonsense. 1377 */ 1378 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1379 1380 if (command == 0x01) { 1381 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1382 if (command & SK_PSTATE_MASK) { 1383 u_int32_t iobase, membase, irq; 1384 1385 /* Save important PCI config data. */ 1386 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1387 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1388 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1389 1390 /* Reset the power state. */ 1391 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1392 "mode -- setting to D0\n", 1393 command & SK_PSTATE_MASK); 1394 command &= 0xFFFFFFFC; 1395 pci_conf_write(pc, pa->pa_tag, 1396 SK_PCI_PWRMGMTCTRL, command); 1397 1398 /* Restore PCI config data. */ 1399 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1400 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1401 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1402 } 1403 } 1404 1405 /* 1406 * Map control/status registers. 1407 */ 1408 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1409 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1410 &sc->sk_bhandle, NULL, &sc->sk_bsize)) { 1411 aprint_error(": can't map mem space\n"); 1412 return; 1413 } 1414 1415 if (pci_dma64_available(pa)) 1416 sc->sc_dmatag = pa->pa_dmat64; 1417 else 1418 sc->sc_dmatag = pa->pa_dmat; 1419 1420 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1421 command |= PCI_COMMAND_MASTER_ENABLE; 1422 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1423 1424 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1425 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1426 1427 /* bail out here if chip is not recognized */ 1428 if (!(SK_IS_YUKON2(sc))) { 1429 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1430 goto fail_1; 1431 } 1432 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1433 1434 /* Allocate interrupt */ 1435 if (pci_intr_alloc(pa, &sc->sk_pihp, NULL, 0)) { 1436 aprint_error(": couldn't map interrupt\n"); 1437 goto fail_1; 1438 } 1439 1440 intrstr = pci_intr_string(pc, sc->sk_pihp[0], intrbuf, sizeof(intrbuf)); 1441 sc->sk_intrhand = pci_intr_establish_xname(pc, sc->sk_pihp[0], IPL_NET, 1442 msk_intr, sc, device_xname(sc->sk_dev)); 1443 if (sc->sk_intrhand == NULL) { 1444 aprint_error(": couldn't establish interrupt"); 1445 if (intrstr != NULL) 1446 aprint_error(" at %s", intrstr); 1447 aprint_error("\n"); 1448 goto fail_1; 1449 } 1450 sc->sk_pc = pc; 1451 1452 if (bus_dmamem_alloc(sc->sc_dmatag, 1453 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1454 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1455 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, BUS_DMA_NOWAIT)) { 1456 aprint_error(": can't alloc status buffers\n"); 1457 goto fail_2; 1458 } 1459 1460 if (bus_dmamem_map(sc->sc_dmatag, 1461 &sc->sk_status_seg, sc->sk_status_nseg, 1462 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1463 &kva, BUS_DMA_NOWAIT)) { 1464 aprint_error(": can't map dma buffers (%zu bytes)\n", 1465 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1466 goto fail_3; 1467 } 1468 if (bus_dmamap_create(sc->sc_dmatag, 1469 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1470 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1471 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1472 aprint_error(": can't create dma map\n"); 1473 goto fail_4; 1474 } 1475 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1476 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1477 NULL, BUS_DMA_NOWAIT)) { 1478 aprint_error(": can't load dma map\n"); 1479 goto fail_5; 1480 } 1481 sc->sk_status_ring = (struct msk_status_desc *)kva; 1482 1483 sc->sk_int_mod = SK_IM_DEFAULT; 1484 sc->sk_int_mod_pending = 0; 1485 1486 /* Reset the adapter. */ 1487 mskc_reset(sc); 1488 1489 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1490 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1491 1492 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1493 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1494 sc->sk_fibertype = 1; 1495 1496 switch (sc->sk_type) { 1497 case SK_YUKON_XL: 1498 sc->sk_name = "Yukon-2 XL"; 1499 break; 1500 case SK_YUKON_EC_U: 1501 sc->sk_name = "Yukon-2 EC Ultra"; 1502 break; 1503 case SK_YUKON_EX: 1504 sc->sk_name = "Yukon-2 Extreme"; 1505 break; 1506 case SK_YUKON_EC: 1507 sc->sk_name = "Yukon-2 EC"; 1508 break; 1509 case SK_YUKON_FE: 1510 sc->sk_name = "Yukon-2 FE"; 1511 break; 1512 case SK_YUKON_FE_P: 1513 sc->sk_name = "Yukon-2 FE+"; 1514 break; 1515 case SK_YUKON_SUPR: 1516 sc->sk_name = "Yukon-2 Supreme"; 1517 break; 1518 case SK_YUKON_ULTRA2: 1519 sc->sk_name = "Yukon-2 Ultra 2"; 1520 break; 1521 case SK_YUKON_OPTIMA: 1522 sc->sk_name = "Yukon-2 Optima"; 1523 break; 1524 case SK_YUKON_PRM: 1525 sc->sk_name = "Yukon-2 Optima Prime"; 1526 break; 1527 case SK_YUKON_OPTIMA2: 1528 sc->sk_name = "Yukon-2 Optima 2"; 1529 break; 1530 default: 1531 sc->sk_name = "Yukon (Unknown)"; 1532 } 1533 1534 if (sc->sk_type == SK_YUKON_XL) { 1535 switch (sc->sk_rev) { 1536 case SK_YUKON_XL_REV_A0: 1537 revstr = "A0"; 1538 break; 1539 case SK_YUKON_XL_REV_A1: 1540 revstr = "A1"; 1541 break; 1542 case SK_YUKON_XL_REV_A2: 1543 revstr = "A2"; 1544 break; 1545 case SK_YUKON_XL_REV_A3: 1546 revstr = "A3"; 1547 break; 1548 default: 1549 break; 1550 } 1551 } 1552 1553 if (sc->sk_type == SK_YUKON_EC) { 1554 switch (sc->sk_rev) { 1555 case SK_YUKON_EC_REV_A1: 1556 revstr = "A1"; 1557 break; 1558 case SK_YUKON_EC_REV_A2: 1559 revstr = "A2"; 1560 break; 1561 case SK_YUKON_EC_REV_A3: 1562 revstr = "A3"; 1563 break; 1564 default: 1565 break; 1566 } 1567 } 1568 1569 if (sc->sk_type == SK_YUKON_FE) { 1570 switch (sc->sk_rev) { 1571 case SK_YUKON_FE_REV_A1: 1572 revstr = "A1"; 1573 break; 1574 case SK_YUKON_FE_REV_A2: 1575 revstr = "A2"; 1576 break; 1577 default: 1578 break; 1579 } 1580 } 1581 1582 if (sc->sk_type == SK_YUKON_EC_U) { 1583 switch (sc->sk_rev) { 1584 case SK_YUKON_EC_U_REV_A0: 1585 revstr = "A0"; 1586 break; 1587 case SK_YUKON_EC_U_REV_A1: 1588 revstr = "A1"; 1589 break; 1590 case SK_YUKON_EC_U_REV_B0: 1591 revstr = "B0"; 1592 break; 1593 case SK_YUKON_EC_U_REV_B1: 1594 revstr = "B1"; 1595 break; 1596 default: 1597 break; 1598 } 1599 } 1600 1601 if (sc->sk_type == SK_YUKON_FE) { 1602 switch (sc->sk_rev) { 1603 case SK_YUKON_FE_REV_A1: 1604 revstr = "A1"; 1605 break; 1606 case SK_YUKON_FE_REV_A2: 1607 revstr = "A2"; 1608 break; 1609 default: 1610 ; 1611 } 1612 } 1613 1614 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1615 revstr = "A0"; 1616 1617 if (sc->sk_type == SK_YUKON_EX) { 1618 switch (sc->sk_rev) { 1619 case SK_YUKON_EX_REV_A0: 1620 revstr = "A0"; 1621 break; 1622 case SK_YUKON_EX_REV_B0: 1623 revstr = "B0"; 1624 break; 1625 default: 1626 ; 1627 } 1628 } 1629 1630 if (sc->sk_type == SK_YUKON_SUPR) { 1631 switch (sc->sk_rev) { 1632 case SK_YUKON_SUPR_REV_A0: 1633 revstr = "A0"; 1634 break; 1635 case SK_YUKON_SUPR_REV_B0: 1636 revstr = "B0"; 1637 break; 1638 case SK_YUKON_SUPR_REV_B1: 1639 revstr = "B1"; 1640 break; 1641 default: 1642 ; 1643 } 1644 } 1645 1646 if (sc->sk_type == SK_YUKON_PRM) { 1647 switch (sc->sk_rev) { 1648 case SK_YUKON_PRM_REV_Z1: 1649 revstr = "Z1"; 1650 break; 1651 case SK_YUKON_PRM_REV_A0: 1652 revstr = "A0"; 1653 break; 1654 default: 1655 ; 1656 } 1657 } 1658 1659 /* Announce the product name. */ 1660 aprint_normal(", %s", sc->sk_name); 1661 if (revstr != NULL) 1662 aprint_normal(" rev. %s", revstr); 1663 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1664 1665 sc->sk_macs = 1; 1666 1667 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1668 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1669 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1670 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1671 sc->sk_macs++; 1672 } 1673 1674 skca.skc_port = SK_PORT_A; 1675 skca.skc_type = sc->sk_type; 1676 skca.skc_rev = sc->sk_rev; 1677 (void)config_found(sc->sk_dev, &skca, mskcprint); 1678 1679 if (sc->sk_macs > 1) { 1680 skca.skc_port = SK_PORT_B; 1681 skca.skc_type = sc->sk_type; 1682 skca.skc_rev = sc->sk_rev; 1683 (void)config_found(sc->sk_dev, &skca, mskcprint); 1684 } 1685 1686 /* Turn on the 'driver is loaded' LED. */ 1687 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1688 1689 /* skc sysctl setup */ 1690 1691 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1692 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1693 SYSCTL_DESCR("mskc per-controller controls"), 1694 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1695 CTL_EOL)) != 0) { 1696 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1697 goto fail_6; 1698 } 1699 1700 sk_nodenum = node->sysctl_num; 1701 1702 /* interrupt moderation time in usecs */ 1703 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1704 CTLFLAG_READWRITE, 1705 CTLTYPE_INT, "int_mod", 1706 SYSCTL_DESCR("msk interrupt moderation timer"), 1707 msk_sysctl_handler, 0, (void *)sc, 1708 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1709 CTL_EOL)) != 0) { 1710 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1711 goto fail_6; 1712 } 1713 1714 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1715 aprint_error_dev(self, "couldn't establish power handler\n"); 1716 1717 return; 1718 1719 fail_6: 1720 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1721 fail_4: 1722 bus_dmamem_unmap(sc->sc_dmatag, kva, 1723 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1724 fail_3: 1725 bus_dmamem_free(sc->sc_dmatag, 1726 &sc->sk_status_seg, sc->sk_status_nseg); 1727 sc->sk_status_nseg = 0; 1728 fail_5: 1729 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1730 fail_2: 1731 pci_intr_disestablish(pc, sc->sk_intrhand); 1732 sc->sk_intrhand = NULL; 1733 fail_1: 1734 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1735 sc->sk_bsize = 0; 1736 } 1737 1738 int 1739 mskc_detach(device_t self, int flags) 1740 { 1741 struct sk_softc *sc = device_private(self); 1742 int rv; 1743 1744 if (sc->sk_intrhand) { 1745 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1746 sc->sk_intrhand = NULL; 1747 } 1748 1749 if (sc->sk_pihp != NULL) { 1750 pci_intr_release(sc->sk_pc, sc->sk_pihp, 1); 1751 sc->sk_pihp = NULL; 1752 } 1753 1754 rv = config_detach_children(self, flags); 1755 if (rv != 0) 1756 return (rv); 1757 1758 if (sc->sk_status_nseg > 0) { 1759 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1760 bus_dmamem_unmap(sc->sc_dmatag, sc->sk_status_ring, 1761 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1762 bus_dmamem_free(sc->sc_dmatag, 1763 &sc->sk_status_seg, sc->sk_status_nseg); 1764 } 1765 1766 if (sc->sk_bsize > 0) 1767 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1768 1769 return(0); 1770 } 1771 1772 int 1773 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1774 { 1775 struct sk_softc *sc = sc_if->sk_softc; 1776 struct msk_tx_desc *f = NULL; 1777 u_int32_t frag, cur, hiaddr, old_hiaddr, total; 1778 u_int32_t entries = 0; 1779 size_t i; 1780 struct sk_txmap_entry *entry; 1781 bus_dmamap_t txmap; 1782 bus_addr_t addr; 1783 1784 DPRINTFN(2, ("msk_encap\n")); 1785 1786 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1787 if (entry == NULL) { 1788 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1789 return (ENOBUFS); 1790 } 1791 txmap = entry->dmamap; 1792 1793 cur = frag = *txidx; 1794 1795 #ifdef MSK_DEBUG 1796 if (mskdebug >= 2) 1797 msk_dump_mbuf(m_head); 1798 #endif 1799 1800 /* 1801 * Start packing the mbufs in this chain into 1802 * the fragment pointers. Stop when we run out 1803 * of fragments or hit the end of the mbuf chain. 1804 */ 1805 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1806 BUS_DMA_NOWAIT)) { 1807 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1808 return (ENOBUFS); 1809 } 1810 1811 /* Count how many tx descriptors needed. */ 1812 hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1813 for (total = i = 0; i < txmap->dm_nsegs; i++) { 1814 if (hiaddr != MSK_ADDR_HI(txmap->dm_segs[i].ds_addr)) { 1815 hiaddr = MSK_ADDR_HI(txmap->dm_segs[i].ds_addr); 1816 total++; 1817 } 1818 total++; 1819 } 1820 1821 if (total > MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2) { 1822 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1823 bus_dmamap_unload(sc->sc_dmatag, txmap); 1824 return (ENOBUFS); 1825 } 1826 1827 DPRINTFN(2, ("msk_encap: dm_nsegs=%d total desc=%u\n", 1828 txmap->dm_nsegs, total)); 1829 1830 /* Sync the DMA map. */ 1831 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1832 BUS_DMASYNC_PREWRITE); 1833 1834 old_hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1835 for (i = 0; i < txmap->dm_nsegs; i++) { 1836 addr = txmap->dm_segs[i].ds_addr; 1837 DPRINTFN(2, ("msk_encap: addr %llx\n", 1838 (unsigned long long)addr)); 1839 hiaddr = MSK_ADDR_HI(addr); 1840 1841 if (sc_if->sk_cdata.sk_tx_hiaddr != hiaddr) { 1842 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1843 f->sk_addr = htole32(hiaddr); 1844 f->sk_len = 0; 1845 f->sk_ctl = 0; 1846 if (i == 0) 1847 f->sk_opcode = SK_Y2_BMUOPC_ADDR64; 1848 else 1849 f->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 1850 sc_if->sk_cdata.sk_tx_hiaddr = hiaddr; 1851 SK_INC(frag, MSK_TX_RING_CNT); 1852 entries++; 1853 DPRINTFN(10, ("%s: tx ADDR64: %#x\n", 1854 sc_if->sk_ethercom.ec_if.if_xname, hiaddr)); 1855 } 1856 1857 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1858 f->sk_addr = htole32(MSK_ADDR_LO(addr)); 1859 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1860 f->sk_ctl = 0; 1861 if (i == 0) { 1862 if (hiaddr != old_hiaddr) 1863 f->sk_opcode = SK_Y2_TXOPC_PACKET | SK_Y2_TXOPC_OWN; 1864 else 1865 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1866 } else 1867 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1868 cur = frag; 1869 SK_INC(frag, MSK_TX_RING_CNT); 1870 entries++; 1871 } 1872 KASSERTMSG(entries == total, "entries %u total %u", entries, total); 1873 1874 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1875 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1876 1877 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1878 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1879 1880 /* Sync descriptors before handing to chip */ 1881 MSK_CDTXSYNC(sc_if, *txidx, entries, 1882 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1883 1884 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1885 1886 /* Sync first descriptor to hand it off */ 1887 MSK_CDTXSYNC(sc_if, *txidx, 1, 1888 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1889 1890 sc_if->sk_cdata.sk_tx_cnt += entries; 1891 1892 #ifdef MSK_DEBUG 1893 if (mskdebug >= 2) { 1894 struct msk_tx_desc *le; 1895 u_int32_t idx; 1896 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1897 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1898 msk_dump_txdesc(le, idx); 1899 } 1900 } 1901 #endif 1902 1903 *txidx = frag; 1904 1905 DPRINTFN(2, ("msk_encap: successful: %u entries\n", entries)); 1906 1907 return (0); 1908 } 1909 1910 void 1911 msk_start(struct ifnet *ifp) 1912 { 1913 struct sk_if_softc *sc_if = ifp->if_softc; 1914 struct mbuf *m_head = NULL; 1915 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1916 int pkts = 0; 1917 1918 DPRINTFN(2, ("msk_start\n")); 1919 1920 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1921 IFQ_POLL(&ifp->if_snd, m_head); 1922 if (m_head == NULL) 1923 break; 1924 1925 /* 1926 * Pack the data into the transmit ring. If we 1927 * don't have room, set the OACTIVE flag and wait 1928 * for the NIC to drain the ring. 1929 */ 1930 if (msk_encap(sc_if, m_head, &idx)) { 1931 ifp->if_flags |= IFF_OACTIVE; 1932 break; 1933 } 1934 1935 /* now we are committed to transmit the packet */ 1936 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1937 pkts++; 1938 1939 /* 1940 * If there's a BPF listener, bounce a copy of this frame 1941 * to him. 1942 */ 1943 bpf_mtap(ifp, m_head, BPF_D_OUT); 1944 } 1945 if (pkts == 0) 1946 return; 1947 1948 /* Transmit */ 1949 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1950 sc_if->sk_cdata.sk_tx_prod = idx; 1951 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1952 1953 /* Set a timeout in case the chip goes out to lunch. */ 1954 ifp->if_timer = 5; 1955 } 1956 } 1957 1958 void 1959 msk_watchdog(struct ifnet *ifp) 1960 { 1961 struct sk_if_softc *sc_if = ifp->if_softc; 1962 1963 /* 1964 * Reclaim first as there is a possibility of losing Tx completion 1965 * interrupts. 1966 */ 1967 msk_txeof(sc_if); 1968 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1969 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1970 1971 ifp->if_oerrors++; 1972 1973 /* XXX Resets both ports; we shouldn't do that. */ 1974 mskc_reset(sc_if->sk_softc); 1975 msk_reset(sc_if); 1976 msk_init(ifp); 1977 } 1978 } 1979 1980 static bool 1981 mskc_suspend(device_t dv, const pmf_qual_t *qual) 1982 { 1983 struct sk_softc *sc = device_private(dv); 1984 1985 DPRINTFN(2, ("mskc_suspend\n")); 1986 1987 /* Turn off the 'driver is loaded' LED. */ 1988 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1989 1990 return true; 1991 } 1992 1993 static bool 1994 mskc_resume(device_t dv, const pmf_qual_t *qual) 1995 { 1996 struct sk_softc *sc = device_private(dv); 1997 1998 DPRINTFN(2, ("mskc_resume\n")); 1999 2000 mskc_reset(sc); 2001 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 2002 2003 return true; 2004 } 2005 2006 static __inline int 2007 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 2008 { 2009 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 2010 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 2011 YU_RXSTAT_JABBER)) != 0 || 2012 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 2013 YU_RXSTAT_BYTES(stat) != len) 2014 return (0); 2015 2016 return (1); 2017 } 2018 2019 void 2020 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 2021 { 2022 struct sk_softc *sc = sc_if->sk_softc; 2023 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2024 struct mbuf *m; 2025 unsigned cur, prod, tail, total_len = len; 2026 bus_dmamap_t dmamap; 2027 2028 cur = sc_if->sk_cdata.sk_rx_cons; 2029 prod = sc_if->sk_cdata.sk_rx_prod; 2030 2031 /* Sync the descriptor */ 2032 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2033 2034 DPRINTFN(2, ("msk_rxeof: cur %u prod %u rx_cnt %u\n", cur, prod, sc_if->sk_cdata.sk_rx_cnt)); 2035 2036 while (prod != cur) { 2037 tail = cur; 2038 SK_INC(cur, MSK_RX_RING_CNT); 2039 2040 sc_if->sk_cdata.sk_rx_cnt--; 2041 m = sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf; 2042 sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf = NULL; 2043 if (m != NULL) 2044 break; /* found it */ 2045 } 2046 sc_if->sk_cdata.sk_rx_cons = cur; 2047 DPRINTFN(2, ("msk_rxeof: cur %u rx_cnt %u m %p\n", cur, sc_if->sk_cdata.sk_rx_cnt, m)); 2048 2049 if (m == NULL) 2050 return; 2051 2052 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2053 2054 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2055 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2056 2057 if (total_len < SK_MIN_FRAMELEN || 2058 total_len > ETHER_MAX_LEN_JUMBO || 2059 msk_rxvalid(sc, rxstat, total_len) == 0) { 2060 ifp->if_ierrors++; 2061 m_freem(m); 2062 return; 2063 } 2064 2065 m_set_rcvif(m, ifp); 2066 m->m_pkthdr.len = m->m_len = total_len; 2067 2068 /* pass it on. */ 2069 if_percpuq_enqueue(ifp->if_percpuq, m); 2070 } 2071 2072 void 2073 msk_txeof(struct sk_if_softc *sc_if) 2074 { 2075 struct sk_softc *sc = sc_if->sk_softc; 2076 struct msk_tx_desc *cur_tx; 2077 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2078 u_int32_t idx, reg, sk_ctl; 2079 struct sk_txmap_entry *entry; 2080 2081 DPRINTFN(2, ("msk_txeof\n")); 2082 2083 if (sc_if->sk_port == SK_PORT_A) 2084 reg = SK_STAT_BMU_TXA1_RIDX; 2085 else 2086 reg = SK_STAT_BMU_TXA2_RIDX; 2087 2088 /* 2089 * Go through our tx ring and free mbufs for those 2090 * frames that have been sent. 2091 */ 2092 idx = sc_if->sk_cdata.sk_tx_cons; 2093 while (idx != sk_win_read_2(sc, reg)) { 2094 MSK_CDTXSYNC(sc_if, idx, 1, 2095 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2096 2097 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2098 sk_ctl = cur_tx->sk_ctl; 2099 #ifdef MSK_DEBUG 2100 if (mskdebug >= 2) 2101 msk_dump_txdesc(cur_tx, idx); 2102 #endif 2103 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 2104 ifp->if_opackets++; 2105 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2106 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2107 2108 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2109 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2110 2111 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2112 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2113 2114 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2115 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2116 link); 2117 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2118 } 2119 sc_if->sk_cdata.sk_tx_cnt--; 2120 SK_INC(idx, MSK_TX_RING_CNT); 2121 } 2122 if (idx == sc_if->sk_cdata.sk_tx_cons) 2123 return; 2124 2125 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2126 2127 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 2128 ifp->if_flags &= ~IFF_OACTIVE; 2129 2130 sc_if->sk_cdata.sk_tx_cons = idx; 2131 } 2132 2133 void 2134 msk_fill_rx_ring(struct sk_if_softc *sc_if) 2135 { 2136 /* Make sure to not completely wrap around */ 2137 while (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT - 1)) { 2138 if (msk_newbuf(sc_if, 2139 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 2140 goto schedretry; 2141 } 2142 } 2143 2144 return; 2145 2146 schedretry: 2147 /* Try later */ 2148 callout_schedule(&sc_if->sk_tick_rx, hz/2); 2149 } 2150 2151 static void 2152 msk_fill_rx_tick(void *xsc_if) 2153 { 2154 struct sk_if_softc *sc_if = xsc_if; 2155 int s, rx_prod; 2156 2157 KASSERT(KERNEL_LOCKED_P()); /* XXXSMP */ 2158 2159 s = splnet(); 2160 rx_prod = sc_if->sk_cdata.sk_rx_prod; 2161 msk_fill_rx_ring(sc_if); 2162 if (rx_prod != sc_if->sk_cdata.sk_rx_prod) { 2163 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2164 sc_if->sk_cdata.sk_rx_prod); 2165 } 2166 splx(s); 2167 } 2168 2169 void 2170 msk_tick(void *xsc_if) 2171 { 2172 struct sk_if_softc *sc_if = xsc_if; 2173 struct mii_data *mii = &sc_if->sk_mii; 2174 int s; 2175 2176 s = splnet(); 2177 mii_tick(mii); 2178 splx(s); 2179 2180 callout_schedule(&sc_if->sk_tick_ch, hz); 2181 } 2182 2183 void 2184 msk_intr_yukon(struct sk_if_softc *sc_if) 2185 { 2186 u_int8_t status; 2187 2188 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2189 /* RX overrun */ 2190 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2191 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2192 SK_RFCTL_RX_FIFO_OVER); 2193 } 2194 /* TX underrun */ 2195 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2196 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 2197 SK_TFCTL_TX_FIFO_UNDER); 2198 } 2199 2200 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 2201 } 2202 2203 int 2204 msk_intr(void *xsc) 2205 { 2206 struct sk_softc *sc = xsc; 2207 struct sk_if_softc *sc_if; 2208 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2209 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2210 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2211 int claimed = 0; 2212 u_int32_t status; 2213 struct msk_status_desc *cur_st; 2214 2215 status = CSR_READ_4(sc, SK_Y2_ISSR2); 2216 if (status == 0xffffffff) 2217 return (0); 2218 if (status == 0) { 2219 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2220 return (0); 2221 } 2222 2223 status = CSR_READ_4(sc, SK_ISR); 2224 2225 if (sc_if0 != NULL) 2226 ifp0 = &sc_if0->sk_ethercom.ec_if; 2227 if (sc_if1 != NULL) 2228 ifp1 = &sc_if1->sk_ethercom.ec_if; 2229 2230 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 2231 (ifp0->if_flags & IFF_RUNNING)) { 2232 msk_intr_yukon(sc_if0); 2233 } 2234 2235 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 2236 (ifp1->if_flags & IFF_RUNNING)) { 2237 msk_intr_yukon(sc_if1); 2238 } 2239 2240 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2241 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2242 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2243 2244 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 2245 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 2246 switch (cur_st->sk_opcode) { 2247 case SK_Y2_STOPC_RXSTAT: 2248 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 2249 if (sc_if) { 2250 msk_rxeof(sc_if, letoh16(cur_st->sk_len), 2251 letoh32(cur_st->sk_status)); 2252 if (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 2253 msk_fill_rx_tick(sc_if); 2254 } 2255 break; 2256 case SK_Y2_STOPC_TXSTAT: 2257 if (sc_if0) 2258 msk_txeof(sc_if0); 2259 if (sc_if1) 2260 msk_txeof(sc_if1); 2261 break; 2262 default: 2263 aprint_error("opcode=0x%x\n", cur_st->sk_opcode); 2264 break; 2265 } 2266 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 2267 2268 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2269 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2270 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2271 } 2272 2273 if (status & SK_Y2_IMR_BMU) { 2274 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 2275 claimed = 1; 2276 } 2277 2278 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2279 2280 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2281 if_schedule_deferred_start(ifp0); 2282 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2283 if_schedule_deferred_start(ifp1); 2284 2285 KASSERT(sc->rnd_attached > 0); 2286 rnd_add_uint32(&sc->rnd_source, status); 2287 2288 if (sc->sk_int_mod_pending) 2289 msk_update_int_mod(sc, 1); 2290 2291 return claimed; 2292 } 2293 2294 void 2295 msk_init_yukon(struct sk_if_softc *sc_if) 2296 { 2297 u_int32_t v; 2298 u_int16_t reg; 2299 struct sk_softc *sc; 2300 int i; 2301 2302 sc = sc_if->sk_softc; 2303 2304 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 2305 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2306 2307 DPRINTFN(6, ("msk_init_yukon: 1\n")); 2308 2309 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 2310 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2311 2312 DPRINTFN(6, ("msk_init_yukon: 3\n")); 2313 2314 /* unused read of the interrupt source register */ 2315 DPRINTFN(6, ("msk_init_yukon: 4\n")); 2316 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2317 2318 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2319 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2320 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2321 2322 /* MIB Counter Clear Mode set */ 2323 reg |= YU_PAR_MIB_CLR; 2324 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2325 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2326 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2327 2328 /* MIB Counter Clear Mode clear */ 2329 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2330 reg &= ~YU_PAR_MIB_CLR; 2331 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2332 2333 /* receive control reg */ 2334 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2335 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2336 2337 /* transmit control register */ 2338 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2339 2340 /* transmit flow control register */ 2341 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2342 2343 /* transmit parameter register */ 2344 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2345 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2346 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2347 2348 /* serial mode register */ 2349 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2350 reg = YU_SMR_DATA_BLIND(0x1c) | 2351 YU_SMR_MFL_VLAN | 2352 YU_SMR_IPG_DATA(0x1e); 2353 2354 if (sc->sk_type != SK_YUKON_FE && 2355 sc->sk_type != SK_YUKON_FE_P) 2356 reg |= YU_SMR_MFL_JUMBO; 2357 2358 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2359 2360 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2361 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2362 /* msk_attach calls me before ether_ifattach so check null */ 2363 if (ifp != NULL && ifp->if_sadl != NULL) 2364 memcpy(sc_if->sk_enaddr, CLLADDR(ifp->if_sadl), 2365 sizeof(sc_if->sk_enaddr)); 2366 /* Setup Yukon's address */ 2367 for (i = 0; i < 3; i++) { 2368 /* Write Source Address 1 (unicast filter) */ 2369 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2370 sc_if->sk_enaddr[i * 2] | 2371 sc_if->sk_enaddr[i * 2 + 1] << 8); 2372 } 2373 2374 for (i = 0; i < 3; i++) { 2375 reg = sk_win_read_2(sc_if->sk_softc, 2376 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2377 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2378 } 2379 2380 /* Set promiscuous mode */ 2381 msk_setpromisc(sc_if); 2382 2383 /* Set multicast filter */ 2384 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2385 msk_setmulti(sc_if); 2386 2387 /* enable interrupt mask for counter overflows */ 2388 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2389 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2390 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2391 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2392 2393 /* Configure RX MAC FIFO Flush Mask */ 2394 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2395 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2396 YU_RXSTAT_JABBER; 2397 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2398 2399 /* Configure RX MAC FIFO */ 2400 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2401 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2402 SK_RFCTL_FIFO_FLUSH_ON); 2403 2404 /* Increase flush threshold to 64 bytes */ 2405 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2406 SK_RFCTL_FIFO_THRESHOLD + 1); 2407 2408 /* Configure TX MAC FIFO */ 2409 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2410 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2411 2412 #if 1 2413 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2414 #endif 2415 DPRINTFN(6, ("msk_init_yukon: end\n")); 2416 } 2417 2418 /* 2419 * Note that to properly initialize any part of the GEnesis chip, 2420 * you first have to take it out of reset mode. 2421 */ 2422 int 2423 msk_init(struct ifnet *ifp) 2424 { 2425 struct sk_if_softc *sc_if = ifp->if_softc; 2426 struct sk_softc *sc = sc_if->sk_softc; 2427 int rc = 0, s; 2428 uint32_t imr, imtimer_ticks; 2429 2430 2431 DPRINTFN(2, ("msk_init\n")); 2432 2433 s = splnet(); 2434 2435 /* Cancel pending I/O and free all RX/TX buffers. */ 2436 msk_stop(ifp, 1); 2437 2438 /* Configure I2C registers */ 2439 2440 /* Configure XMAC(s) */ 2441 msk_init_yukon(sc_if); 2442 if ((rc = ether_mediachange(ifp)) != 0) 2443 goto out; 2444 2445 /* Configure transmit arbiter(s) */ 2446 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2447 #if 0 2448 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2449 #endif 2450 2451 if (sc->sk_ramsize) { 2452 /* Configure RAMbuffers */ 2453 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2454 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2455 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2456 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2457 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2458 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2459 2460 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2461 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2462 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2463 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2464 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2465 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2466 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2467 } 2468 2469 /* Configure BMUs */ 2470 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2471 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2472 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2473 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2474 2475 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2476 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2477 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2478 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2479 2480 /* Make sure the sync transmit queue is disabled. */ 2481 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2482 2483 /* Init descriptors */ 2484 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2485 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2486 "memory for rx buffers\n"); 2487 msk_stop(ifp, 1); 2488 splx(s); 2489 return ENOBUFS; 2490 } 2491 2492 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2493 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2494 "memory for tx buffers\n"); 2495 msk_stop(ifp, 1); 2496 splx(s); 2497 return ENOBUFS; 2498 } 2499 2500 /* Set interrupt moderation if changed via sysctl. */ 2501 switch (sc->sk_type) { 2502 case SK_YUKON_EC: 2503 case SK_YUKON_EC_U: 2504 case SK_YUKON_EX: 2505 case SK_YUKON_SUPR: 2506 case SK_YUKON_ULTRA2: 2507 case SK_YUKON_OPTIMA: 2508 case SK_YUKON_PRM: 2509 case SK_YUKON_OPTIMA2: 2510 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2511 break; 2512 case SK_YUKON_FE: 2513 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2514 break; 2515 case SK_YUKON_FE_P: 2516 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 2517 break; 2518 case SK_YUKON_XL: 2519 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2520 break; 2521 default: 2522 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2523 } 2524 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2525 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2526 sk_win_write_4(sc, SK_IMTIMERINIT, 2527 SK_IM_USECS(sc->sk_int_mod)); 2528 aprint_verbose_dev(sc->sk_dev, 2529 "interrupt moderation is %d us\n", sc->sk_int_mod); 2530 } 2531 2532 /* Initialize prefetch engine. */ 2533 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2534 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2535 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2536 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2537 MSK_RX_RING_ADDR(sc_if, 0)); 2538 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2539 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2540 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2541 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2542 2543 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2544 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2545 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2546 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2547 MSK_TX_RING_ADDR(sc_if, 0)); 2548 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2549 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2550 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2551 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2552 2553 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2554 sc_if->sk_cdata.sk_rx_prod); 2555 2556 /* Configure interrupt handling */ 2557 if (sc_if->sk_port == SK_PORT_A) 2558 sc->sk_intrmask |= SK_Y2_INTRS1; 2559 else 2560 sc->sk_intrmask |= SK_Y2_INTRS2; 2561 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2562 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2563 2564 ifp->if_flags |= IFF_RUNNING; 2565 ifp->if_flags &= ~IFF_OACTIVE; 2566 2567 callout_schedule(&sc_if->sk_tick_ch, hz); 2568 2569 out: 2570 splx(s); 2571 return rc; 2572 } 2573 2574 /* 2575 * Note: the logic of second parameter is inverted compared to OpenBSD 2576 * code, since this code uses the function as if_stop hook too. 2577 */ 2578 void 2579 msk_stop(struct ifnet *ifp, int disable) 2580 { 2581 struct sk_if_softc *sc_if = ifp->if_softc; 2582 struct sk_softc *sc = sc_if->sk_softc; 2583 struct sk_txmap_entry *dma; 2584 int i; 2585 2586 DPRINTFN(2, ("msk_stop\n")); 2587 2588 callout_stop(&sc_if->sk_tick_ch); 2589 callout_stop(&sc_if->sk_tick_rx); 2590 2591 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2592 2593 /* Stop transfer of Tx descriptors */ 2594 2595 /* Stop transfer of Rx descriptors */ 2596 2597 if (disable) { 2598 /* Turn off various components of this interface. */ 2599 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2600 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2601 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2602 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2603 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2604 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2605 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2606 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2607 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2608 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2609 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2610 2611 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2612 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2613 2614 /* Disable interrupts */ 2615 if (sc_if->sk_port == SK_PORT_A) 2616 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2617 else 2618 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2619 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2620 } 2621 2622 /* Free RX and TX mbufs still in the queues. */ 2623 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2624 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2625 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2626 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2627 } 2628 } 2629 2630 sc_if->sk_cdata.sk_rx_prod = 0; 2631 sc_if->sk_cdata.sk_rx_cons = 0; 2632 sc_if->sk_cdata.sk_rx_cnt = 0; 2633 2634 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2635 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2636 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2637 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2638 #if 1 2639 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2640 sc_if->sk_cdata.sk_tx_map[i], link); 2641 sc_if->sk_cdata.sk_tx_map[i] = 0; 2642 #endif 2643 } 2644 } 2645 2646 #if 1 2647 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2648 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2649 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2650 free(dma, M_DEVBUF); 2651 } 2652 #endif 2653 } 2654 2655 CFATTACH_DECL3_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2656 mskc_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2657 2658 CFATTACH_DECL3_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2659 msk_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2660 2661 #ifdef MSK_DEBUG 2662 void 2663 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2664 { 2665 #define DESC_PRINT(X) \ 2666 if (X) \ 2667 printf("txdesc[%d]." #X "=%#x\n", \ 2668 idx, X); 2669 2670 DESC_PRINT(letoh32(le->sk_addr)); 2671 DESC_PRINT(letoh16(le->sk_len)); 2672 DESC_PRINT(le->sk_ctl); 2673 DESC_PRINT(le->sk_opcode); 2674 #undef DESC_PRINT 2675 } 2676 2677 void 2678 msk_dump_bytes(const char *data, int len) 2679 { 2680 int c, i, j; 2681 2682 for (i = 0; i < len; i += 16) { 2683 printf("%08x ", i); 2684 c = len - i; 2685 if (c > 16) c = 16; 2686 2687 for (j = 0; j < c; j++) { 2688 printf("%02x ", data[i + j] & 0xff); 2689 if ((j & 0xf) == 7 && j > 0) 2690 printf(" "); 2691 } 2692 2693 for (; j < 16; j++) 2694 printf(" "); 2695 printf(" "); 2696 2697 for (j = 0; j < c; j++) { 2698 int ch = data[i + j] & 0xff; 2699 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2700 } 2701 2702 printf("\n"); 2703 2704 if (c < 16) 2705 break; 2706 } 2707 } 2708 2709 void 2710 msk_dump_mbuf(struct mbuf *m) 2711 { 2712 int count = m->m_pkthdr.len; 2713 2714 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2715 2716 while (count > 0 && m) { 2717 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2718 m, m->m_data, m->m_len); 2719 if (mskdebug >= 4) 2720 msk_dump_bytes(mtod(m, char *), m->m_len); 2721 2722 count -= m->m_len; 2723 m = m->m_next; 2724 } 2725 } 2726 #endif 2727 2728 static int 2729 msk_sysctl_handler(SYSCTLFN_ARGS) 2730 { 2731 int error, t; 2732 struct sysctlnode node; 2733 struct sk_softc *sc; 2734 2735 node = *rnode; 2736 sc = node.sysctl_data; 2737 t = sc->sk_int_mod; 2738 node.sysctl_data = &t; 2739 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2740 if (error || newp == NULL) 2741 return error; 2742 2743 if (t < SK_IM_MIN || t > SK_IM_MAX) 2744 return EINVAL; 2745 2746 /* update the softc with sysctl-changed value, and mark 2747 for hardware update */ 2748 sc->sk_int_mod = t; 2749 sc->sk_int_mod_pending = 1; 2750 return 0; 2751 } 2752 2753 /* 2754 * Set up sysctl(3) MIB, hw.msk.* - Individual controllers will be 2755 * set up in mskc_attach() 2756 */ 2757 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2758 { 2759 int rc; 2760 const struct sysctlnode *node; 2761 2762 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2763 0, CTLTYPE_NODE, "msk", 2764 SYSCTL_DESCR("msk interface controls"), 2765 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2766 goto err; 2767 } 2768 2769 msk_root_num = node->sysctl_num; 2770 return; 2771 2772 err: 2773 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2774 } 2775
Indexes created Mon Sep 22 13:09:51 GMT 2025