if_msk.c revision 1.89
1 /* $NetBSD: if_msk.c,v 1.89 2019/05/23 13:10:52 msaitoh Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.79 2009/10/15 17:54:56 deraadt Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.89 2019/05/23 13:10:52 msaitoh Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/mutex.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/device.h> 66 #include <sys/queue.h> 67 #include <sys/callout.h> 68 #include <sys/sysctl.h> 69 #include <sys/endian.h> 70 #ifdef __NetBSD__ 71 #define letoh16 htole16 72 #define letoh32 htole32 73 #endif 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #include <net/if_media.h> 80 81 #include <net/bpf.h> 82 #include <sys/rndsource.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 #include <dev/mii/brgphyreg.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 92 #include <dev/pci/if_skreg.h> 93 #include <dev/pci/if_mskvar.h> 94 95 int mskc_probe(device_t, cfdata_t, void *); 96 void mskc_attach(device_t, device_t, void *); 97 int mskc_detach(device_t, int); 98 void mskc_reset(struct sk_softc *); 99 static bool mskc_suspend(device_t, const pmf_qual_t *); 100 static bool mskc_resume(device_t, const pmf_qual_t *); 101 int msk_probe(device_t, cfdata_t, void *); 102 void msk_attach(device_t, device_t, void *); 103 int msk_detach(device_t, int); 104 void msk_reset(struct sk_if_softc *); 105 int mskcprint(void *, const char *); 106 int msk_intr(void *); 107 void msk_intr_yukon(struct sk_if_softc *); 108 void msk_rxeof(struct sk_if_softc *, uint16_t, uint32_t); 109 void msk_txeof(struct sk_if_softc *); 110 int msk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 111 void msk_start(struct ifnet *); 112 int msk_ioctl(struct ifnet *, u_long, void *); 113 int msk_init(struct ifnet *); 114 void msk_init_yukon(struct sk_if_softc *); 115 void msk_stop(struct ifnet *, int); 116 void msk_watchdog(struct ifnet *); 117 int msk_newbuf(struct sk_if_softc *, bus_dmamap_t); 118 int msk_alloc_jumbo_mem(struct sk_if_softc *); 119 void *msk_jalloc(struct sk_if_softc *); 120 void msk_jfree(struct mbuf *, void *, size_t, void *); 121 int msk_init_rx_ring(struct sk_if_softc *); 122 int msk_init_tx_ring(struct sk_if_softc *); 123 void msk_fill_rx_ring(struct sk_if_softc *); 124 125 void msk_update_int_mod(struct sk_softc *, int); 126 127 int msk_miibus_readreg(device_t, int, int, uint16_t *); 128 int msk_miibus_writereg(device_t, int, int, uint16_t); 129 void msk_miibus_statchg(struct ifnet *); 130 131 void msk_setmulti(struct sk_if_softc *); 132 void msk_setpromisc(struct sk_if_softc *); 133 void msk_tick(void *); 134 static void msk_fill_rx_tick(void *); 135 136 /* #define MSK_DEBUG 1 */ 137 #ifdef MSK_DEBUG 138 #define DPRINTF(x) if (mskdebug) printf x 139 #define DPRINTFN(n, x) if (mskdebug >= (n)) printf x 140 int mskdebug = MSK_DEBUG; 141 142 void msk_dump_txdesc(struct msk_tx_desc *, int); 143 void msk_dump_mbuf(struct mbuf *); 144 void msk_dump_bytes(const char *, int); 145 #else 146 #define DPRINTF(x) 147 #define DPRINTFN(n, x) 148 #endif 149 150 static int msk_sysctl_handler(SYSCTLFN_PROTO); 151 static int msk_root_num; 152 153 #define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL) 154 #define MSK_ADDR_HI(x) ((uint64_t) (x) >> 32) 155 156 /* supported device vendors */ 157 static const struct msk_product { 158 pci_vendor_id_t msk_vendor; 159 pci_product_id_t msk_product; 160 } msk_products[] = { 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 163 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 164 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8079 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 197 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 198 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 199 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 200 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 201 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 }, 202 { 0, 0 } 203 }; 204 205 static inline uint32_t 206 sk_win_read_4(struct sk_softc *sc, uint32_t reg) 207 { 208 return CSR_READ_4(sc, reg); 209 } 210 211 static inline uint16_t 212 sk_win_read_2(struct sk_softc *sc, uint32_t reg) 213 { 214 return CSR_READ_2(sc, reg); 215 } 216 217 static inline uint8_t 218 sk_win_read_1(struct sk_softc *sc, uint32_t reg) 219 { 220 return CSR_READ_1(sc, reg); 221 } 222 223 static inline void 224 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x) 225 { 226 CSR_WRITE_4(sc, reg, x); 227 } 228 229 static inline void 230 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x) 231 { 232 CSR_WRITE_2(sc, reg, x); 233 } 234 235 static inline void 236 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x) 237 { 238 CSR_WRITE_1(sc, reg, x); 239 } 240 241 int 242 msk_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 243 { 244 struct sk_if_softc *sc_if = device_private(dev); 245 uint16_t data; 246 int i; 247 248 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 249 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 250 251 for (i = 0; i < SK_TIMEOUT; i++) { 252 DELAY(1); 253 data = SK_YU_READ_2(sc_if, YUKON_SMICR); 254 if (data & YU_SMICR_READ_VALID) 255 break; 256 } 257 258 if (i == SK_TIMEOUT) { 259 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 260 return ETIMEDOUT; 261 } 262 263 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, SK_TIMEOUT)); 264 265 *val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 266 267 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#hx\n", 268 phy, reg, *val)); 269 270 return 0; 271 } 272 273 int 274 msk_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 275 { 276 struct sk_if_softc *sc_if = device_private(dev); 277 int i; 278 279 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#hx\n", 280 phy, reg, val)); 281 282 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 283 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 284 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 285 286 for (i = 0; i < SK_TIMEOUT; i++) { 287 DELAY(1); 288 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 289 break; 290 } 291 292 if (i == SK_TIMEOUT) { 293 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 294 return ETIMEDOUT; 295 } 296 297 return 0; 298 } 299 300 void 301 msk_miibus_statchg(struct ifnet *ifp) 302 { 303 struct sk_if_softc *sc_if = ifp->if_softc; 304 struct mii_data *mii = &sc_if->sk_mii; 305 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 306 int gpcr; 307 308 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 309 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 310 311 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 312 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 313 /* Set speed. */ 314 gpcr |= YU_GPCR_SPEED_DIS; 315 switch (IFM_SUBTYPE(mii->mii_media_active)) { 316 case IFM_1000_SX: 317 case IFM_1000_LX: 318 case IFM_1000_CX: 319 case IFM_1000_T: 320 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 321 break; 322 case IFM_100_TX: 323 gpcr |= YU_GPCR_SPEED; 324 break; 325 } 326 327 /* Set duplex. */ 328 gpcr |= YU_GPCR_DPLX_DIS; 329 if ((mii->mii_media_active & IFM_FDX) != 0) 330 gpcr |= YU_GPCR_DUPLEX; 331 332 /* Disable flow control. */ 333 gpcr |= YU_GPCR_FCTL_DIS; 334 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 335 } 336 337 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 338 339 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 340 SK_YU_READ_2(sc_if, YUKON_GPCR))); 341 } 342 343 void 344 msk_setmulti(struct sk_if_softc *sc_if) 345 { 346 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 347 uint32_t hashes[2] = { 0, 0 }; 348 int h; 349 struct ethercom *ec = &sc_if->sk_ethercom; 350 struct ether_multi *enm; 351 struct ether_multistep step; 352 uint16_t reg; 353 354 /* First, zot all the existing filters. */ 355 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 356 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 357 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 358 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 359 360 361 /* Now program new ones. */ 362 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 363 reg |= YU_RCR_UFLEN; 364 allmulti: 365 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 366 if ((ifp->if_flags & IFF_PROMISC) != 0) 367 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 368 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 369 hashes[0] = 0xFFFFFFFF; 370 hashes[1] = 0xFFFFFFFF; 371 } 372 } else { 373 /* First find the tail of the list. */ 374 ETHER_FIRST_MULTI(step, ec, enm); 375 while (enm != NULL) { 376 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 377 ETHER_ADDR_LEN)) { 378 ifp->if_flags |= IFF_ALLMULTI; 379 goto allmulti; 380 } 381 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 382 ((1 << SK_HASH_BITS) - 1); 383 if (h < 32) 384 hashes[0] |= (1 << h); 385 else 386 hashes[1] |= (1 << (h - 32)); 387 388 ETHER_NEXT_MULTI(step, enm); 389 } 390 reg |= YU_RCR_MUFLEN; 391 } 392 393 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 394 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 395 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 396 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 397 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 398 } 399 400 void 401 msk_setpromisc(struct sk_if_softc *sc_if) 402 { 403 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 404 405 if (ifp->if_flags & IFF_PROMISC) 406 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 407 YU_RCR_UFLEN | YU_RCR_MUFLEN); 408 else 409 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 410 YU_RCR_UFLEN | YU_RCR_MUFLEN); 411 } 412 413 int 414 msk_init_rx_ring(struct sk_if_softc *sc_if) 415 { 416 struct msk_chain_data *cd = &sc_if->sk_cdata; 417 struct msk_ring_data *rd = sc_if->sk_rdata; 418 struct msk_rx_desc *r; 419 int i, nexti; 420 421 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 422 423 for (i = 0; i < MSK_RX_RING_CNT; i++) { 424 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 425 if (i == (MSK_RX_RING_CNT - 1)) 426 nexti = 0; 427 else 428 nexti = i + 1; 429 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 430 } 431 432 sc_if->sk_cdata.sk_rx_prod = 0; 433 sc_if->sk_cdata.sk_rx_cons = 0; 434 sc_if->sk_cdata.sk_rx_cnt = 0; 435 sc_if->sk_cdata.sk_rx_hiaddr = 0; 436 437 /* Mark the first ring element to initialize the high address. */ 438 sc_if->sk_cdata.sk_rx_hiaddr = 0; 439 r = &rd->sk_rx_ring[cd->sk_rx_prod]; 440 r->sk_addr = htole32(cd->sk_rx_hiaddr); 441 r->sk_len = 0; 442 r->sk_ctl = 0; 443 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN; 444 MSK_CDRXSYNC(sc_if, cd->sk_rx_prod, 445 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 446 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 447 sc_if->sk_cdata.sk_rx_cnt++; 448 449 msk_fill_rx_ring(sc_if); 450 return 0; 451 } 452 453 int 454 msk_init_tx_ring(struct sk_if_softc *sc_if) 455 { 456 struct sk_softc *sc = sc_if->sk_softc; 457 struct msk_chain_data *cd = &sc_if->sk_cdata; 458 struct msk_ring_data *rd = sc_if->sk_rdata; 459 struct msk_tx_desc *t; 460 bus_dmamap_t dmamap; 461 struct sk_txmap_entry *entry; 462 int i, nexti; 463 464 memset(rd->sk_tx_ring, 0, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 465 466 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 467 for (i = 0; i < MSK_TX_RING_CNT; i++) { 468 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 469 if (i == (MSK_TX_RING_CNT - 1)) 470 nexti = 0; 471 else 472 nexti = i + 1; 473 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 474 475 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 476 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 477 return ENOBUFS; 478 479 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 480 if (!entry) { 481 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 482 return ENOBUFS; 483 } 484 entry->dmamap = dmamap; 485 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 486 } 487 488 sc_if->sk_cdata.sk_tx_prod = 0; 489 sc_if->sk_cdata.sk_tx_cons = 0; 490 sc_if->sk_cdata.sk_tx_cnt = 0; 491 sc_if->sk_cdata.sk_tx_hiaddr = 0; 492 493 /* Mark the first ring element to initialize the high address. */ 494 sc_if->sk_cdata.sk_tx_hiaddr = 0; 495 t = &rd->sk_tx_ring[cd->sk_tx_prod]; 496 t->sk_addr = htole32(cd->sk_tx_hiaddr); 497 t->sk_len = 0; 498 t->sk_ctl = 0; 499 t->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 500 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 501 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 502 SK_INC(sc_if->sk_cdata.sk_tx_prod, MSK_TX_RING_CNT); 503 sc_if->sk_cdata.sk_tx_cnt++; 504 505 return 0; 506 } 507 508 int 509 msk_newbuf(struct sk_if_softc *sc_if, bus_dmamap_t dmamap) 510 { 511 struct mbuf *m_new = NULL; 512 struct sk_chain *c; 513 struct msk_rx_desc *r; 514 void *buf = NULL; 515 bus_addr_t addr; 516 517 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 518 if (m_new == NULL) 519 return ENOBUFS; 520 521 /* Allocate the jumbo buffer */ 522 buf = msk_jalloc(sc_if); 523 if (buf == NULL) { 524 m_freem(m_new); 525 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 526 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 527 return ENOBUFS; 528 } 529 530 /* Attach the buffer to the mbuf */ 531 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 532 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 533 534 m_adj(m_new, ETHER_ALIGN); 535 536 addr = dmamap->dm_segs[0].ds_addr + 537 ((vaddr_t)m_new->m_data - 538 (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf); 539 540 if (sc_if->sk_cdata.sk_rx_hiaddr != MSK_ADDR_HI(addr)) { 541 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 542 r = c->sk_le; 543 c->sk_mbuf = NULL; 544 r->sk_addr = htole32(MSK_ADDR_HI(addr)); 545 r->sk_len = 0; 546 r->sk_ctl = 0; 547 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN; 548 sc_if->sk_cdata.sk_rx_hiaddr = MSK_ADDR_HI(addr); 549 550 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 551 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 552 553 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 554 sc_if->sk_cdata.sk_rx_cnt++; 555 556 DPRINTFN(10, ("%s: rx ADDR64: %#x\n", 557 sc_if->sk_ethercom.ec_if.if_xname, 558 (unsigned)MSK_ADDR_HI(addr))); 559 } 560 561 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 562 r = c->sk_le; 563 c->sk_mbuf = m_new; 564 r->sk_addr = htole32(MSK_ADDR_LO(addr)); 565 r->sk_len = htole16(SK_JLEN); 566 r->sk_ctl = 0; 567 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 568 569 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 570 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 571 572 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 573 sc_if->sk_cdata.sk_rx_cnt++; 574 575 return 0; 576 } 577 578 /* 579 * Memory management for jumbo frames. 580 */ 581 582 int 583 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 584 { 585 struct sk_softc *sc = sc_if->sk_softc; 586 char *ptr, *kva; 587 int i, state, error; 588 struct sk_jpool_entry *entry; 589 590 state = error = 0; 591 592 /* Grab a big chunk o' storage. */ 593 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 594 &sc_if->sk_cdata.sk_jumbo_seg, 1, &sc_if->sk_cdata.sk_jumbo_nseg, 595 BUS_DMA_NOWAIT)) { 596 aprint_error(": can't alloc rx buffers"); 597 return ENOBUFS; 598 } 599 600 state = 1; 601 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 602 sc_if->sk_cdata.sk_jumbo_nseg, MSK_JMEM, (void **)&kva, 603 BUS_DMA_NOWAIT)) { 604 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 605 error = ENOBUFS; 606 goto out; 607 } 608 609 state = 2; 610 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 611 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 612 aprint_error(": can't create dma map"); 613 error = ENOBUFS; 614 goto out; 615 } 616 617 state = 3; 618 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 619 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 620 aprint_error(": can't load dma map"); 621 error = ENOBUFS; 622 goto out; 623 } 624 625 state = 4; 626 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 627 DPRINTFN(1,("msk_jumbo_buf = %p\n", 628 (void *)sc_if->sk_cdata.sk_jumbo_buf)); 629 630 LIST_INIT(&sc_if->sk_jfree_listhead); 631 LIST_INIT(&sc_if->sk_jinuse_listhead); 632 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 633 634 /* 635 * Now divide it up into 9K pieces and save the addresses 636 * in an array. 637 */ 638 ptr = sc_if->sk_cdata.sk_jumbo_buf; 639 for (i = 0; i < MSK_JSLOTS; i++) { 640 sc_if->sk_cdata.sk_jslots[i] = ptr; 641 ptr += SK_JLEN; 642 entry = malloc(sizeof(struct sk_jpool_entry), 643 M_DEVBUF, M_NOWAIT); 644 if (entry == NULL) { 645 sc_if->sk_cdata.sk_jumbo_buf = NULL; 646 aprint_error(": no memory for jumbo buffer queue!"); 647 error = ENOBUFS; 648 goto out; 649 } 650 entry->slot = i; 651 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 652 entry, jpool_entries); 653 } 654 out: 655 if (error != 0) { 656 switch (state) { 657 case 4: 658 bus_dmamap_unload(sc->sc_dmatag, 659 sc_if->sk_cdata.sk_rx_jumbo_map); 660 /* FALLTHROUGH */ 661 case 3: 662 bus_dmamap_destroy(sc->sc_dmatag, 663 sc_if->sk_cdata.sk_rx_jumbo_map); 664 /* FALLTHROUGH */ 665 case 2: 666 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 667 /* FALLTHROUGH */ 668 case 1: 669 bus_dmamem_free(sc->sc_dmatag, 670 &sc_if->sk_cdata.sk_jumbo_seg, 671 sc_if->sk_cdata.sk_jumbo_nseg); 672 break; 673 default: 674 break; 675 } 676 } 677 678 return error; 679 } 680 681 static void 682 msk_free_jumbo_mem(struct sk_if_softc *sc_if) 683 { 684 struct sk_softc *sc = sc_if->sk_softc; 685 686 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 687 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 688 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_cdata.sk_jumbo_buf, MSK_JMEM); 689 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 690 sc_if->sk_cdata.sk_jumbo_nseg); 691 } 692 693 /* 694 * Allocate a jumbo buffer. 695 */ 696 void * 697 msk_jalloc(struct sk_if_softc *sc_if) 698 { 699 struct sk_jpool_entry *entry; 700 701 mutex_enter(&sc_if->sk_jpool_mtx); 702 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 703 704 if (entry == NULL) { 705 mutex_exit(&sc_if->sk_jpool_mtx); 706 return NULL; 707 } 708 709 LIST_REMOVE(entry, jpool_entries); 710 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 711 mutex_exit(&sc_if->sk_jpool_mtx); 712 return sc_if->sk_cdata.sk_jslots[entry->slot]; 713 } 714 715 /* 716 * Release a jumbo buffer. 717 */ 718 void 719 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 720 { 721 struct sk_jpool_entry *entry; 722 struct sk_if_softc *sc; 723 int i; 724 725 /* Extract the softc struct pointer. */ 726 sc = (struct sk_if_softc *)arg; 727 728 if (sc == NULL) 729 panic("msk_jfree: can't find softc pointer!"); 730 731 /* calculate the slot this buffer belongs to */ 732 i = ((vaddr_t)buf 733 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 734 735 if ((i < 0) || (i >= MSK_JSLOTS)) 736 panic("msk_jfree: asked to free buffer that we don't manage!"); 737 738 mutex_enter(&sc->sk_jpool_mtx); 739 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 740 if (entry == NULL) 741 panic("msk_jfree: buffer not in use!"); 742 entry->slot = i; 743 LIST_REMOVE(entry, jpool_entries); 744 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 745 mutex_exit(&sc->sk_jpool_mtx); 746 747 if (__predict_true(m != NULL)) 748 pool_cache_put(mb_cache, m); 749 750 /* Now that we know we have a free RX buffer, refill if running out */ 751 if ((sc->sk_ethercom.ec_if.if_flags & IFF_RUNNING) != 0 752 && sc->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 753 callout_schedule(&sc->sk_tick_rx, 0); 754 } 755 756 int 757 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 758 { 759 struct sk_if_softc *sc = ifp->if_softc; 760 int s, error; 761 762 s = splnet(); 763 764 DPRINTFN(2, ("msk_ioctl ETHER cmd %lx\n", cmd)); 765 switch (cmd) { 766 case SIOCSIFFLAGS: 767 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 768 break; 769 770 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 771 case IFF_RUNNING: 772 msk_stop(ifp, 1); 773 break; 774 case IFF_UP: 775 msk_init(ifp); 776 break; 777 case IFF_UP | IFF_RUNNING: 778 if ((ifp->if_flags ^ sc->sk_if_flags) == IFF_PROMISC) { 779 msk_setpromisc(sc); 780 msk_setmulti(sc); 781 } else 782 msk_init(ifp); 783 break; 784 } 785 sc->sk_if_flags = ifp->if_flags; 786 break; 787 default: 788 error = ether_ioctl(ifp, cmd, data); 789 if (error == ENETRESET) { 790 error = 0; 791 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 792 ; 793 else if (ifp->if_flags & IFF_RUNNING) { 794 /* 795 * Multicast list has changed; set the hardware 796 * filter accordingly. 797 */ 798 msk_setmulti(sc); 799 } 800 } 801 break; 802 } 803 804 splx(s); 805 return error; 806 } 807 808 void 809 msk_update_int_mod(struct sk_softc *sc, int verbose) 810 { 811 uint32_t imtimer_ticks; 812 813 /* 814 * Configure interrupt moderation. The moderation timer 815 * defers interrupts specified in the interrupt moderation 816 * timer mask based on the timeout specified in the interrupt 817 * moderation timer init register. Each bit in the timer 818 * register represents one tick, so to specify a timeout in 819 * microseconds, we have to multiply by the correct number of 820 * ticks-per-microsecond. 821 */ 822 switch (sc->sk_type) { 823 case SK_YUKON_EC: 824 case SK_YUKON_EC_U: 825 case SK_YUKON_EX: 826 case SK_YUKON_SUPR: 827 case SK_YUKON_ULTRA2: 828 case SK_YUKON_OPTIMA: 829 case SK_YUKON_PRM: 830 case SK_YUKON_OPTIMA2: 831 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 832 break; 833 case SK_YUKON_FE: 834 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 835 break; 836 case SK_YUKON_FE_P: 837 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 838 break; 839 case SK_YUKON_XL: 840 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 841 break; 842 default: 843 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 844 } 845 if (verbose) 846 aprint_verbose_dev(sc->sk_dev, 847 "interrupt moderation is %d us\n", sc->sk_int_mod); 848 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 849 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF | SK_ISR_TX2_S_EOF | 850 SK_ISR_RX1_EOF | SK_ISR_RX2_EOF); 851 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 852 sc->sk_int_mod_pending = 0; 853 } 854 855 static int 856 msk_lookup(const struct pci_attach_args *pa) 857 { 858 const struct msk_product *pmsk; 859 860 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 861 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 862 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 863 return 1; 864 } 865 return 0; 866 } 867 868 /* 869 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 870 * IDs against our list and return a device name if we find a match. 871 */ 872 int 873 mskc_probe(device_t parent, cfdata_t match, void *aux) 874 { 875 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 876 877 return msk_lookup(pa); 878 } 879 880 /* 881 * Force the GEnesis into reset, then bring it out of reset. 882 */ 883 void 884 mskc_reset(struct sk_softc *sc) 885 { 886 uint32_t imtimer_ticks, reg1; 887 int reg; 888 889 DPRINTFN(2, ("mskc_reset\n")); 890 891 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 892 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 893 894 DELAY(1000); 895 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 896 DELAY(2); 897 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 898 sk_win_write_1(sc, SK_TESTCTL1, 2); 899 900 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 901 sc->sk_type >= SK_YUKON_FE_P) { 902 uint32_t our; 903 904 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 905 906 /* enable all clocks. */ 907 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 908 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 909 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST | 910 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN | 911 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY | 912 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 913 /* Set all bits to 0 except bits 15..12 */ 914 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 915 /* Set to default value */ 916 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 917 918 /* 919 * Disable status race, workaround for Yukon EC Ultra & 920 * Yukon EX. 921 */ 922 reg1 = sk_win_read_4(sc, SK_GPIO); 923 reg1 |= SK_Y2_GPIO_STAT_RACE_DIS; 924 sk_win_write_4(sc, SK_GPIO, reg1); 925 sk_win_read_4(sc, SK_GPIO); 926 } 927 928 /* release PHY from PowerDown/Coma mode. */ 929 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 930 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 931 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 932 else 933 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 934 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 935 936 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 937 sk_win_write_1(sc, SK_Y2_CLKGATE, 938 SK_Y2_CLKGATE_LINK1_GATE_DIS | 939 SK_Y2_CLKGATE_LINK2_GATE_DIS | 940 SK_Y2_CLKGATE_LINK1_CORE_DIS | 941 SK_Y2_CLKGATE_LINK2_CORE_DIS | 942 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 943 else 944 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 945 946 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 947 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 948 DELAY(1000); 949 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 950 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 951 952 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 953 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 954 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 955 } 956 957 sk_win_write_1(sc, SK_TESTCTL1, 1); 958 959 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 960 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 961 CSR_READ_2(sc, SK_LINK_CTRL))); 962 963 /* Disable ASF */ 964 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 965 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 966 967 /* Clear I2C IRQ noise */ 968 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 969 970 /* Disable hardware timer */ 971 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 972 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 973 974 /* Disable descriptor polling */ 975 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 976 977 /* Disable time stamps */ 978 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 979 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 980 981 /* Enable RAM interface */ 982 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 983 for (reg = SK_TO0;reg <= SK_TO11; reg++) 984 sk_win_write_1(sc, reg, 36); 985 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 986 for (reg = SK_TO0;reg <= SK_TO11; reg++) 987 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 988 989 /* 990 * Configure interrupt moderation. The moderation timer 991 * defers interrupts specified in the interrupt moderation 992 * timer mask based on the timeout specified in the interrupt 993 * moderation timer init register. Each bit in the timer 994 * register represents one tick, so to specify a timeout in 995 * microseconds, we have to multiply by the correct number of 996 * ticks-per-microsecond. 997 */ 998 switch (sc->sk_type) { 999 case SK_YUKON_EC: 1000 case SK_YUKON_EC_U: 1001 case SK_YUKON_EX: 1002 case SK_YUKON_SUPR: 1003 case SK_YUKON_ULTRA2: 1004 case SK_YUKON_OPTIMA: 1005 case SK_YUKON_PRM: 1006 case SK_YUKON_OPTIMA2: 1007 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1008 break; 1009 case SK_YUKON_FE: 1010 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 1011 break; 1012 case SK_YUKON_FE_P: 1013 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 1014 break; 1015 case SK_YUKON_XL: 1016 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 1017 break; 1018 default: 1019 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1020 break; 1021 } 1022 1023 /* Reset status ring. */ 1024 memset(sc->sk_status_ring, 0, 1025 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1026 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 1027 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1028 sc->sk_status_idx = 0; 1029 1030 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 1031 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 1032 1033 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 1034 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 1035 MSK_ADDR_LO(sc->sk_status_map->dm_segs[0].ds_addr)); 1036 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 1037 MSK_ADDR_HI(sc->sk_status_map->dm_segs[0].ds_addr)); 1038 if (sc->sk_type == SK_YUKON_EC && 1039 sc->sk_rev == SK_YUKON_EC_REV_A1) { 1040 /* WA for dev. #4.3 */ 1041 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 1042 SK_STAT_BMU_TXTHIDX_MSK); 1043 /* WA for dev. #4.18 */ 1044 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 1045 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 1046 } else { 1047 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 1048 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 1049 if (sc->sk_type == SK_YUKON_XL) 1050 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x04); 1051 else 1052 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x10); 1053 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 1054 } 1055 1056 #if 0 1057 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 1058 #endif 1059 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 1060 1061 /* Enable status unit. */ 1062 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 1063 1064 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 1065 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 1066 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 1067 1068 msk_update_int_mod(sc, 0); 1069 } 1070 1071 int 1072 msk_probe(device_t parent, cfdata_t match, void *aux) 1073 { 1074 struct skc_attach_args *sa = aux; 1075 1076 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1077 return 0; 1078 1079 switch (sa->skc_type) { 1080 case SK_YUKON_XL: 1081 case SK_YUKON_EC_U: 1082 case SK_YUKON_EX: 1083 case SK_YUKON_EC: 1084 case SK_YUKON_FE: 1085 case SK_YUKON_FE_P: 1086 case SK_YUKON_SUPR: 1087 case SK_YUKON_ULTRA2: 1088 case SK_YUKON_OPTIMA: 1089 case SK_YUKON_PRM: 1090 case SK_YUKON_OPTIMA2: 1091 return 1; 1092 } 1093 1094 return 0; 1095 } 1096 1097 void 1098 msk_reset(struct sk_if_softc *sc_if) 1099 { 1100 /* GMAC and GPHY Reset */ 1101 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1102 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1103 DELAY(1000); 1104 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1105 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1106 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1107 } 1108 1109 static bool 1110 msk_resume(device_t dv, const pmf_qual_t *qual) 1111 { 1112 struct sk_if_softc *sc_if = device_private(dv); 1113 1114 msk_init_yukon(sc_if); 1115 return true; 1116 } 1117 1118 /* 1119 * Each XMAC chip is attached as a separate logical IP interface. 1120 * Single port cards will have only one logical interface of course. 1121 */ 1122 void 1123 msk_attach(device_t parent, device_t self, void *aux) 1124 { 1125 struct sk_if_softc *sc_if = device_private(self); 1126 struct sk_softc *sc = device_private(parent); 1127 struct skc_attach_args *sa = aux; 1128 struct ifnet *ifp; 1129 struct mii_data * const mii = &sc_if->sk_mii; 1130 void *kva; 1131 int i; 1132 uint32_t chunk; 1133 int mii_flags; 1134 1135 sc_if->sk_dev = self; 1136 sc_if->sk_port = sa->skc_port; 1137 sc_if->sk_softc = sc; 1138 sc->sk_if[sa->skc_port] = sc_if; 1139 1140 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1141 1142 /* 1143 * Get station address for this interface. Note that 1144 * dual port cards actually come with three station 1145 * addresses: one for each port, plus an extra. The 1146 * extra one is used by the SysKonnect driver software 1147 * as a 'virtual' station address for when both ports 1148 * are operating in failover mode. Currently we don't 1149 * use this extra address. 1150 */ 1151 for (i = 0; i < ETHER_ADDR_LEN; i++) 1152 sc_if->sk_enaddr[i] = 1153 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1154 1155 aprint_normal(": Ethernet address %s\n", 1156 ether_sprintf(sc_if->sk_enaddr)); 1157 1158 /* 1159 * Set up RAM buffer addresses. The Yukon2 has a small amount 1160 * of SRAM on it, somewhere between 4K and 48K. We need to 1161 * divide this up between the transmitter and receiver. We 1162 * give the receiver 2/3 of the memory (rounded down), and the 1163 * transmitter whatever remains. 1164 */ 1165 if (sc->sk_ramsize) { 1166 chunk = (2 * (sc->sk_ramsize / sizeof(uint64_t)) / 3) & ~0xff; 1167 sc_if->sk_rx_ramstart = 0; 1168 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 1169 chunk = (sc->sk_ramsize / sizeof(uint64_t)) - chunk; 1170 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 1171 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 1172 1173 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1174 " tx_ramstart=%#x tx_ramend=%#x\n", 1175 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1176 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1177 } 1178 1179 /* Allocate the descriptor queues. */ 1180 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1181 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 1182 BUS_DMA_NOWAIT)) { 1183 aprint_error(": can't alloc rx buffers\n"); 1184 goto fail; 1185 } 1186 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 1187 sc_if->sk_ring_nseg, 1188 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1189 aprint_error(": can't map dma buffers (%zu bytes)\n", 1190 sizeof(struct msk_ring_data)); 1191 goto fail_1; 1192 } 1193 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1194 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1195 &sc_if->sk_ring_map)) { 1196 aprint_error(": can't create dma map\n"); 1197 goto fail_2; 1198 } 1199 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1200 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1201 aprint_error(": can't load dma map\n"); 1202 goto fail_3; 1203 } 1204 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1205 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1206 1207 if (sc->sk_type != SK_YUKON_FE && 1208 sc->sk_type != SK_YUKON_FE_P) 1209 sc_if->sk_pktlen = SK_JLEN; 1210 else 1211 sc_if->sk_pktlen = MCLBYTES; 1212 1213 /* Try to allocate memory for jumbo buffers. */ 1214 if (msk_alloc_jumbo_mem(sc_if)) { 1215 aprint_error(": jumbo buffer allocation failed\n"); 1216 goto fail_3; 1217 } 1218 1219 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1220 if (sc->sk_type != SK_YUKON_FE && 1221 sc->sk_type != SK_YUKON_FE_P) 1222 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1223 1224 ifp = &sc_if->sk_ethercom.ec_if; 1225 ifp->if_softc = sc_if; 1226 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1227 ifp->if_ioctl = msk_ioctl; 1228 ifp->if_start = msk_start; 1229 ifp->if_stop = msk_stop; 1230 ifp->if_init = msk_init; 1231 ifp->if_watchdog = msk_watchdog; 1232 ifp->if_baudrate = 1000000000; 1233 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1234 IFQ_SET_READY(&ifp->if_snd); 1235 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1236 1237 msk_reset(sc_if); 1238 1239 /* 1240 * Do miibus setup. 1241 */ 1242 msk_init_yukon(sc_if); 1243 1244 DPRINTFN(2, ("msk_attach: 1\n")); 1245 1246 mii->mii_ifp = ifp; 1247 mii->mii_readreg = msk_miibus_readreg; 1248 mii->mii_writereg = msk_miibus_writereg; 1249 mii->mii_statchg = msk_miibus_statchg; 1250 1251 sc_if->sk_ethercom.ec_mii = mii; 1252 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1253 mii_flags = MIIF_DOPAUSE; 1254 if (sc->sk_fibertype) 1255 mii_flags |= MIIF_HAVEFIBER; 1256 mii_attach(self, mii, 0xffffffff, 0, MII_OFFSET_ANY, mii_flags); 1257 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1258 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1259 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 1260 0, NULL); 1261 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 1262 } else 1263 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1264 1265 callout_init(&sc_if->sk_tick_ch, 0); 1266 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1267 callout_schedule(&sc_if->sk_tick_ch, hz); 1268 1269 callout_init(&sc_if->sk_tick_rx, 0); 1270 callout_setfunc(&sc_if->sk_tick_rx, msk_fill_rx_tick, sc_if); 1271 1272 /* 1273 * Call MI attach routines. 1274 */ 1275 if_attach(ifp); 1276 if_deferred_start_init(ifp, NULL); 1277 ether_ifattach(ifp, sc_if->sk_enaddr); 1278 1279 if (pmf_device_register(self, NULL, msk_resume)) 1280 pmf_class_network_register(self, ifp); 1281 else 1282 aprint_error_dev(self, "couldn't establish power handler\n"); 1283 1284 if (sc->rnd_attached++ == 0) { 1285 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1286 RND_TYPE_NET, RND_FLAG_DEFAULT); 1287 } 1288 1289 DPRINTFN(2, ("msk_attach: end\n")); 1290 return; 1291 1292 fail_3: 1293 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1294 fail_2: 1295 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1296 fail_1: 1297 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1298 fail: 1299 sc->sk_if[sa->skc_port] = NULL; 1300 } 1301 1302 int 1303 msk_detach(device_t self, int flags) 1304 { 1305 struct sk_if_softc *sc_if = device_private(self); 1306 struct sk_softc *sc = sc_if->sk_softc; 1307 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1308 1309 if (sc->sk_if[sc_if->sk_port] == NULL) 1310 return 0; 1311 1312 msk_stop(ifp, 1); 1313 1314 if (--sc->rnd_attached == 0) 1315 rnd_detach_source(&sc->rnd_source); 1316 1317 callout_halt(&sc_if->sk_tick_ch, NULL); 1318 callout_destroy(&sc_if->sk_tick_ch); 1319 1320 callout_halt(&sc_if->sk_tick_rx, NULL); 1321 callout_destroy(&sc_if->sk_tick_rx); 1322 1323 /* Detach any PHYs we might have. */ 1324 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1325 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1326 1327 /* Delete any remaining media. */ 1328 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY); 1329 1330 pmf_device_deregister(self); 1331 1332 ether_ifdetach(ifp); 1333 if_detach(ifp); 1334 1335 msk_free_jumbo_mem(sc_if); 1336 1337 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_rdata, 1338 sizeof(struct msk_ring_data)); 1339 bus_dmamem_free(sc->sc_dmatag, 1340 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1341 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1342 sc->sk_if[sc_if->sk_port] = NULL; 1343 1344 return 0; 1345 } 1346 1347 int 1348 mskcprint(void *aux, const char *pnp) 1349 { 1350 struct skc_attach_args *sa = aux; 1351 1352 if (pnp) 1353 aprint_normal("msk port %c at %s", 1354 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1355 else 1356 aprint_normal(" port %c", 1357 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1358 return UNCONF; 1359 } 1360 1361 /* 1362 * Attach the interface. Allocate softc structures, do ifmedia 1363 * setup and ethernet/BPF attach. 1364 */ 1365 void 1366 mskc_attach(device_t parent, device_t self, void *aux) 1367 { 1368 struct sk_softc *sc = device_private(self); 1369 struct pci_attach_args *pa = aux; 1370 struct skc_attach_args skca; 1371 pci_chipset_tag_t pc = pa->pa_pc; 1372 pcireg_t command, memtype; 1373 const char *intrstr = NULL; 1374 int rc, sk_nodenum; 1375 uint8_t hw, pmd; 1376 const char *revstr = NULL; 1377 const struct sysctlnode *node; 1378 void *kva; 1379 char intrbuf[PCI_INTRSTR_LEN]; 1380 1381 DPRINTFN(2, ("begin mskc_attach\n")); 1382 1383 sc->sk_dev = self; 1384 /* 1385 * Handle power management nonsense. 1386 */ 1387 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1388 1389 if (command == 0x01) { 1390 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1391 if (command & SK_PSTATE_MASK) { 1392 uint32_t iobase, membase, irq; 1393 1394 /* Save important PCI config data. */ 1395 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1396 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1397 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1398 1399 /* Reset the power state. */ 1400 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1401 "mode -- setting to D0\n", 1402 command & SK_PSTATE_MASK); 1403 command &= 0xFFFFFFFC; 1404 pci_conf_write(pc, pa->pa_tag, 1405 SK_PCI_PWRMGMTCTRL, command); 1406 1407 /* Restore PCI config data. */ 1408 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1409 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1410 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1411 } 1412 } 1413 1414 /* 1415 * Map control/status registers. 1416 */ 1417 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1418 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1419 &sc->sk_bhandle, NULL, &sc->sk_bsize)) { 1420 aprint_error(": can't map mem space\n"); 1421 return; 1422 } 1423 1424 if (pci_dma64_available(pa)) 1425 sc->sc_dmatag = pa->pa_dmat64; 1426 else 1427 sc->sc_dmatag = pa->pa_dmat; 1428 1429 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1430 command |= PCI_COMMAND_MASTER_ENABLE; 1431 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1432 1433 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1434 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1435 1436 /* bail out here if chip is not recognized */ 1437 if (!(SK_IS_YUKON2(sc))) { 1438 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1439 goto fail_1; 1440 } 1441 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1442 1443 /* Allocate interrupt */ 1444 if (pci_intr_alloc(pa, &sc->sk_pihp, NULL, 0)) { 1445 aprint_error(": couldn't map interrupt\n"); 1446 goto fail_1; 1447 } 1448 1449 intrstr = pci_intr_string(pc, sc->sk_pihp[0], intrbuf, sizeof(intrbuf)); 1450 sc->sk_intrhand = pci_intr_establish_xname(pc, sc->sk_pihp[0], IPL_NET, 1451 msk_intr, sc, device_xname(sc->sk_dev)); 1452 if (sc->sk_intrhand == NULL) { 1453 aprint_error(": couldn't establish interrupt"); 1454 if (intrstr != NULL) 1455 aprint_error(" at %s", intrstr); 1456 aprint_error("\n"); 1457 goto fail_1; 1458 } 1459 sc->sk_pc = pc; 1460 1461 if (bus_dmamem_alloc(sc->sc_dmatag, 1462 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1463 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1464 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, BUS_DMA_NOWAIT)) { 1465 aprint_error(": can't alloc status buffers\n"); 1466 goto fail_2; 1467 } 1468 1469 if (bus_dmamem_map(sc->sc_dmatag, 1470 &sc->sk_status_seg, sc->sk_status_nseg, 1471 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1472 &kva, BUS_DMA_NOWAIT)) { 1473 aprint_error(": can't map dma buffers (%zu bytes)\n", 1474 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1475 goto fail_3; 1476 } 1477 if (bus_dmamap_create(sc->sc_dmatag, 1478 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1479 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1480 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1481 aprint_error(": can't create dma map\n"); 1482 goto fail_4; 1483 } 1484 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1485 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1486 NULL, BUS_DMA_NOWAIT)) { 1487 aprint_error(": can't load dma map\n"); 1488 goto fail_5; 1489 } 1490 sc->sk_status_ring = (struct msk_status_desc *)kva; 1491 1492 sc->sk_int_mod = SK_IM_DEFAULT; 1493 sc->sk_int_mod_pending = 0; 1494 1495 /* Reset the adapter. */ 1496 mskc_reset(sc); 1497 1498 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1499 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1500 1501 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1502 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1503 sc->sk_fibertype = 1; 1504 1505 switch (sc->sk_type) { 1506 case SK_YUKON_XL: 1507 sc->sk_name = "Yukon-2 XL"; 1508 break; 1509 case SK_YUKON_EC_U: 1510 sc->sk_name = "Yukon-2 EC Ultra"; 1511 break; 1512 case SK_YUKON_EX: 1513 sc->sk_name = "Yukon-2 Extreme"; 1514 break; 1515 case SK_YUKON_EC: 1516 sc->sk_name = "Yukon-2 EC"; 1517 break; 1518 case SK_YUKON_FE: 1519 sc->sk_name = "Yukon-2 FE"; 1520 break; 1521 case SK_YUKON_FE_P: 1522 sc->sk_name = "Yukon-2 FE+"; 1523 break; 1524 case SK_YUKON_SUPR: 1525 sc->sk_name = "Yukon-2 Supreme"; 1526 break; 1527 case SK_YUKON_ULTRA2: 1528 sc->sk_name = "Yukon-2 Ultra 2"; 1529 break; 1530 case SK_YUKON_OPTIMA: 1531 sc->sk_name = "Yukon-2 Optima"; 1532 break; 1533 case SK_YUKON_PRM: 1534 sc->sk_name = "Yukon-2 Optima Prime"; 1535 break; 1536 case SK_YUKON_OPTIMA2: 1537 sc->sk_name = "Yukon-2 Optima 2"; 1538 break; 1539 default: 1540 sc->sk_name = "Yukon (Unknown)"; 1541 } 1542 1543 if (sc->sk_type == SK_YUKON_XL) { 1544 switch (sc->sk_rev) { 1545 case SK_YUKON_XL_REV_A0: 1546 revstr = "A0"; 1547 break; 1548 case SK_YUKON_XL_REV_A1: 1549 revstr = "A1"; 1550 break; 1551 case SK_YUKON_XL_REV_A2: 1552 revstr = "A2"; 1553 break; 1554 case SK_YUKON_XL_REV_A3: 1555 revstr = "A3"; 1556 break; 1557 default: 1558 break; 1559 } 1560 } 1561 1562 if (sc->sk_type == SK_YUKON_EC) { 1563 switch (sc->sk_rev) { 1564 case SK_YUKON_EC_REV_A1: 1565 revstr = "A1"; 1566 break; 1567 case SK_YUKON_EC_REV_A2: 1568 revstr = "A2"; 1569 break; 1570 case SK_YUKON_EC_REV_A3: 1571 revstr = "A3"; 1572 break; 1573 default: 1574 break; 1575 } 1576 } 1577 1578 if (sc->sk_type == SK_YUKON_FE) { 1579 switch (sc->sk_rev) { 1580 case SK_YUKON_FE_REV_A1: 1581 revstr = "A1"; 1582 break; 1583 case SK_YUKON_FE_REV_A2: 1584 revstr = "A2"; 1585 break; 1586 default: 1587 break; 1588 } 1589 } 1590 1591 if (sc->sk_type == SK_YUKON_EC_U) { 1592 switch (sc->sk_rev) { 1593 case SK_YUKON_EC_U_REV_A0: 1594 revstr = "A0"; 1595 break; 1596 case SK_YUKON_EC_U_REV_A1: 1597 revstr = "A1"; 1598 break; 1599 case SK_YUKON_EC_U_REV_B0: 1600 revstr = "B0"; 1601 break; 1602 case SK_YUKON_EC_U_REV_B1: 1603 revstr = "B1"; 1604 break; 1605 default: 1606 break; 1607 } 1608 } 1609 1610 if (sc->sk_type == SK_YUKON_FE) { 1611 switch (sc->sk_rev) { 1612 case SK_YUKON_FE_REV_A1: 1613 revstr = "A1"; 1614 break; 1615 case SK_YUKON_FE_REV_A2: 1616 revstr = "A2"; 1617 break; 1618 default: 1619 ; 1620 } 1621 } 1622 1623 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1624 revstr = "A0"; 1625 1626 if (sc->sk_type == SK_YUKON_EX) { 1627 switch (sc->sk_rev) { 1628 case SK_YUKON_EX_REV_A0: 1629 revstr = "A0"; 1630 break; 1631 case SK_YUKON_EX_REV_B0: 1632 revstr = "B0"; 1633 break; 1634 default: 1635 ; 1636 } 1637 } 1638 1639 if (sc->sk_type == SK_YUKON_SUPR) { 1640 switch (sc->sk_rev) { 1641 case SK_YUKON_SUPR_REV_A0: 1642 revstr = "A0"; 1643 break; 1644 case SK_YUKON_SUPR_REV_B0: 1645 revstr = "B0"; 1646 break; 1647 case SK_YUKON_SUPR_REV_B1: 1648 revstr = "B1"; 1649 break; 1650 default: 1651 ; 1652 } 1653 } 1654 1655 if (sc->sk_type == SK_YUKON_PRM) { 1656 switch (sc->sk_rev) { 1657 case SK_YUKON_PRM_REV_Z1: 1658 revstr = "Z1"; 1659 break; 1660 case SK_YUKON_PRM_REV_A0: 1661 revstr = "A0"; 1662 break; 1663 default: 1664 ; 1665 } 1666 } 1667 1668 /* Announce the product name. */ 1669 aprint_normal(", %s", sc->sk_name); 1670 if (revstr != NULL) 1671 aprint_normal(" rev. %s", revstr); 1672 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1673 1674 sc->sk_macs = 1; 1675 1676 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1677 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1678 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1679 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1680 sc->sk_macs++; 1681 } 1682 1683 skca.skc_port = SK_PORT_A; 1684 skca.skc_type = sc->sk_type; 1685 skca.skc_rev = sc->sk_rev; 1686 (void)config_found(sc->sk_dev, &skca, mskcprint); 1687 1688 if (sc->sk_macs > 1) { 1689 skca.skc_port = SK_PORT_B; 1690 skca.skc_type = sc->sk_type; 1691 skca.skc_rev = sc->sk_rev; 1692 (void)config_found(sc->sk_dev, &skca, mskcprint); 1693 } 1694 1695 /* Turn on the 'driver is loaded' LED. */ 1696 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1697 1698 /* skc sysctl setup */ 1699 1700 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1701 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1702 SYSCTL_DESCR("mskc per-controller controls"), 1703 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1704 CTL_EOL)) != 0) { 1705 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1706 goto fail_6; 1707 } 1708 1709 sk_nodenum = node->sysctl_num; 1710 1711 /* interrupt moderation time in usecs */ 1712 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1713 CTLFLAG_READWRITE, 1714 CTLTYPE_INT, "int_mod", 1715 SYSCTL_DESCR("msk interrupt moderation timer"), 1716 msk_sysctl_handler, 0, (void *)sc, 1717 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1718 CTL_EOL)) != 0) { 1719 aprint_normal_dev(sc->sk_dev, 1720 "couldn't create int_mod sysctl node\n"); 1721 goto fail_6; 1722 } 1723 1724 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1725 aprint_error_dev(self, "couldn't establish power handler\n"); 1726 1727 return; 1728 1729 fail_6: 1730 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1731 fail_4: 1732 bus_dmamem_unmap(sc->sc_dmatag, kva, 1733 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1734 fail_3: 1735 bus_dmamem_free(sc->sc_dmatag, 1736 &sc->sk_status_seg, sc->sk_status_nseg); 1737 sc->sk_status_nseg = 0; 1738 fail_5: 1739 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1740 fail_2: 1741 pci_intr_disestablish(pc, sc->sk_intrhand); 1742 sc->sk_intrhand = NULL; 1743 fail_1: 1744 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1745 sc->sk_bsize = 0; 1746 } 1747 1748 int 1749 mskc_detach(device_t self, int flags) 1750 { 1751 struct sk_softc *sc = device_private(self); 1752 int rv; 1753 1754 if (sc->sk_intrhand) { 1755 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1756 sc->sk_intrhand = NULL; 1757 } 1758 1759 if (sc->sk_pihp != NULL) { 1760 pci_intr_release(sc->sk_pc, sc->sk_pihp, 1); 1761 sc->sk_pihp = NULL; 1762 } 1763 1764 rv = config_detach_children(self, flags); 1765 if (rv != 0) 1766 return rv; 1767 1768 if (sc->sk_status_nseg > 0) { 1769 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1770 bus_dmamem_unmap(sc->sc_dmatag, sc->sk_status_ring, 1771 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1772 bus_dmamem_free(sc->sc_dmatag, 1773 &sc->sk_status_seg, sc->sk_status_nseg); 1774 } 1775 1776 if (sc->sk_bsize > 0) 1777 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1778 1779 return 0; 1780 } 1781 1782 int 1783 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1784 { 1785 struct sk_softc *sc = sc_if->sk_softc; 1786 struct msk_tx_desc *f = NULL; 1787 uint32_t frag, cur, hiaddr, old_hiaddr, total; 1788 uint32_t entries = 0; 1789 size_t i; 1790 struct sk_txmap_entry *entry; 1791 bus_dmamap_t txmap; 1792 bus_addr_t addr; 1793 1794 DPRINTFN(2, ("msk_encap\n")); 1795 1796 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1797 if (entry == NULL) { 1798 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1799 return ENOBUFS; 1800 } 1801 txmap = entry->dmamap; 1802 1803 cur = frag = *txidx; 1804 1805 #ifdef MSK_DEBUG 1806 if (mskdebug >= 2) 1807 msk_dump_mbuf(m_head); 1808 #endif 1809 1810 /* 1811 * Start packing the mbufs in this chain into 1812 * the fragment pointers. Stop when we run out 1813 * of fragments or hit the end of the mbuf chain. 1814 */ 1815 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1816 BUS_DMA_NOWAIT)) { 1817 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1818 return ENOBUFS; 1819 } 1820 1821 /* Count how many tx descriptors needed. */ 1822 hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1823 for (total = i = 0; i < txmap->dm_nsegs; i++) { 1824 if (hiaddr != MSK_ADDR_HI(txmap->dm_segs[i].ds_addr)) { 1825 hiaddr = MSK_ADDR_HI(txmap->dm_segs[i].ds_addr); 1826 total++; 1827 } 1828 total++; 1829 } 1830 1831 if (total > MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2) { 1832 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1833 bus_dmamap_unload(sc->sc_dmatag, txmap); 1834 return ENOBUFS; 1835 } 1836 1837 DPRINTFN(2, ("msk_encap: dm_nsegs=%d total desc=%u\n", 1838 txmap->dm_nsegs, total)); 1839 1840 /* Sync the DMA map. */ 1841 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1842 BUS_DMASYNC_PREWRITE); 1843 1844 old_hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1845 for (i = 0; i < txmap->dm_nsegs; i++) { 1846 addr = txmap->dm_segs[i].ds_addr; 1847 DPRINTFN(2, ("msk_encap: addr %llx\n", 1848 (unsigned long long)addr)); 1849 hiaddr = MSK_ADDR_HI(addr); 1850 1851 if (sc_if->sk_cdata.sk_tx_hiaddr != hiaddr) { 1852 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1853 f->sk_addr = htole32(hiaddr); 1854 f->sk_len = 0; 1855 f->sk_ctl = 0; 1856 if (i == 0) 1857 f->sk_opcode = SK_Y2_BMUOPC_ADDR64; 1858 else 1859 f->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 1860 sc_if->sk_cdata.sk_tx_hiaddr = hiaddr; 1861 SK_INC(frag, MSK_TX_RING_CNT); 1862 entries++; 1863 DPRINTFN(10, ("%s: tx ADDR64: %#x\n", 1864 sc_if->sk_ethercom.ec_if.if_xname, hiaddr)); 1865 } 1866 1867 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1868 f->sk_addr = htole32(MSK_ADDR_LO(addr)); 1869 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1870 f->sk_ctl = 0; 1871 if (i == 0) { 1872 if (hiaddr != old_hiaddr) 1873 f->sk_opcode = SK_Y2_TXOPC_PACKET | SK_Y2_TXOPC_OWN; 1874 else 1875 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1876 } else 1877 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1878 cur = frag; 1879 SK_INC(frag, MSK_TX_RING_CNT); 1880 entries++; 1881 } 1882 KASSERTMSG(entries == total, "entries %u total %u", entries, total); 1883 1884 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1885 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1886 1887 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1888 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1889 1890 /* Sync descriptors before handing to chip */ 1891 MSK_CDTXSYNC(sc_if, *txidx, entries, 1892 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1893 1894 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1895 1896 /* Sync first descriptor to hand it off */ 1897 MSK_CDTXSYNC(sc_if, *txidx, 1, 1898 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1899 1900 sc_if->sk_cdata.sk_tx_cnt += entries; 1901 1902 #ifdef MSK_DEBUG 1903 if (mskdebug >= 2) { 1904 struct msk_tx_desc *le; 1905 uint32_t idx; 1906 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1907 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1908 msk_dump_txdesc(le, idx); 1909 } 1910 } 1911 #endif 1912 1913 *txidx = frag; 1914 1915 DPRINTFN(2, ("msk_encap: successful: %u entries\n", entries)); 1916 1917 return 0; 1918 } 1919 1920 void 1921 msk_start(struct ifnet *ifp) 1922 { 1923 struct sk_if_softc *sc_if = ifp->if_softc; 1924 struct mbuf *m_head = NULL; 1925 uint32_t idx = sc_if->sk_cdata.sk_tx_prod; 1926 int pkts = 0; 1927 1928 DPRINTFN(2, ("msk_start\n")); 1929 1930 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1931 IFQ_POLL(&ifp->if_snd, m_head); 1932 if (m_head == NULL) 1933 break; 1934 1935 /* 1936 * Pack the data into the transmit ring. If we 1937 * don't have room, set the OACTIVE flag and wait 1938 * for the NIC to drain the ring. 1939 */ 1940 if (msk_encap(sc_if, m_head, &idx)) { 1941 ifp->if_flags |= IFF_OACTIVE; 1942 break; 1943 } 1944 1945 /* now we are committed to transmit the packet */ 1946 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1947 pkts++; 1948 1949 /* 1950 * If there's a BPF listener, bounce a copy of this frame 1951 * to him. 1952 */ 1953 bpf_mtap(ifp, m_head, BPF_D_OUT); 1954 } 1955 if (pkts == 0) 1956 return; 1957 1958 /* Transmit */ 1959 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1960 sc_if->sk_cdata.sk_tx_prod = idx; 1961 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1962 1963 /* Set a timeout in case the chip goes out to lunch. */ 1964 ifp->if_timer = 5; 1965 } 1966 } 1967 1968 void 1969 msk_watchdog(struct ifnet *ifp) 1970 { 1971 struct sk_if_softc *sc_if = ifp->if_softc; 1972 1973 /* 1974 * Reclaim first as there is a possibility of losing Tx completion 1975 * interrupts. 1976 */ 1977 msk_txeof(sc_if); 1978 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1979 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1980 1981 ifp->if_oerrors++; 1982 1983 /* XXX Resets both ports; we shouldn't do that. */ 1984 mskc_reset(sc_if->sk_softc); 1985 msk_reset(sc_if); 1986 msk_init(ifp); 1987 } 1988 } 1989 1990 static bool 1991 mskc_suspend(device_t dv, const pmf_qual_t *qual) 1992 { 1993 struct sk_softc *sc = device_private(dv); 1994 1995 DPRINTFN(2, ("mskc_suspend\n")); 1996 1997 /* Turn off the 'driver is loaded' LED. */ 1998 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1999 2000 return true; 2001 } 2002 2003 static bool 2004 mskc_resume(device_t dv, const pmf_qual_t *qual) 2005 { 2006 struct sk_softc *sc = device_private(dv); 2007 2008 DPRINTFN(2, ("mskc_resume\n")); 2009 2010 mskc_reset(sc); 2011 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 2012 2013 return true; 2014 } 2015 2016 static __inline int 2017 msk_rxvalid(struct sk_softc *sc, uint32_t stat, uint32_t len) 2018 { 2019 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 2020 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 2021 YU_RXSTAT_JABBER)) != 0 || 2022 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 2023 YU_RXSTAT_BYTES(stat) != len) 2024 return 0; 2025 2026 return 1; 2027 } 2028 2029 void 2030 msk_rxeof(struct sk_if_softc *sc_if, uint16_t len, uint32_t rxstat) 2031 { 2032 struct sk_softc *sc = sc_if->sk_softc; 2033 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2034 struct mbuf *m; 2035 unsigned cur, prod, tail, total_len = len; 2036 bus_dmamap_t dmamap; 2037 2038 cur = sc_if->sk_cdata.sk_rx_cons; 2039 prod = sc_if->sk_cdata.sk_rx_prod; 2040 2041 /* Sync the descriptor */ 2042 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2043 2044 DPRINTFN(2, ("msk_rxeof: cur %u prod %u rx_cnt %u\n", cur, prod, 2045 sc_if->sk_cdata.sk_rx_cnt)); 2046 2047 while (prod != cur) { 2048 tail = cur; 2049 SK_INC(cur, MSK_RX_RING_CNT); 2050 2051 sc_if->sk_cdata.sk_rx_cnt--; 2052 m = sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf; 2053 sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf = NULL; 2054 if (m != NULL) 2055 break; /* found it */ 2056 } 2057 sc_if->sk_cdata.sk_rx_cons = cur; 2058 DPRINTFN(2, ("msk_rxeof: cur %u rx_cnt %u m %p\n", cur, 2059 sc_if->sk_cdata.sk_rx_cnt, m)); 2060 2061 if (m == NULL) 2062 return; 2063 2064 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2065 2066 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2067 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2068 2069 if (total_len < SK_MIN_FRAMELEN || 2070 total_len > ETHER_MAX_LEN_JUMBO || 2071 msk_rxvalid(sc, rxstat, total_len) == 0) { 2072 ifp->if_ierrors++; 2073 m_freem(m); 2074 return; 2075 } 2076 2077 m_set_rcvif(m, ifp); 2078 m->m_pkthdr.len = m->m_len = total_len; 2079 2080 /* pass it on. */ 2081 if_percpuq_enqueue(ifp->if_percpuq, m); 2082 } 2083 2084 void 2085 msk_txeof(struct sk_if_softc *sc_if) 2086 { 2087 struct sk_softc *sc = sc_if->sk_softc; 2088 struct msk_tx_desc *cur_tx; 2089 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2090 uint32_t idx, reg, sk_ctl; 2091 struct sk_txmap_entry *entry; 2092 2093 DPRINTFN(2, ("msk_txeof\n")); 2094 2095 if (sc_if->sk_port == SK_PORT_A) 2096 reg = SK_STAT_BMU_TXA1_RIDX; 2097 else 2098 reg = SK_STAT_BMU_TXA2_RIDX; 2099 2100 /* 2101 * Go through our tx ring and free mbufs for those 2102 * frames that have been sent. 2103 */ 2104 idx = sc_if->sk_cdata.sk_tx_cons; 2105 while (idx != sk_win_read_2(sc, reg)) { 2106 MSK_CDTXSYNC(sc_if, idx, 1, 2107 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2108 2109 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2110 sk_ctl = cur_tx->sk_ctl; 2111 #ifdef MSK_DEBUG 2112 if (mskdebug >= 2) 2113 msk_dump_txdesc(cur_tx, idx); 2114 #endif 2115 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 2116 ifp->if_opackets++; 2117 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2118 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2119 2120 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2121 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2122 2123 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2124 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2125 2126 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2127 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2128 link); 2129 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2130 } 2131 sc_if->sk_cdata.sk_tx_cnt--; 2132 SK_INC(idx, MSK_TX_RING_CNT); 2133 } 2134 if (idx == sc_if->sk_cdata.sk_tx_cons) 2135 return; 2136 2137 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2138 2139 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 2140 ifp->if_flags &= ~IFF_OACTIVE; 2141 2142 sc_if->sk_cdata.sk_tx_cons = idx; 2143 } 2144 2145 void 2146 msk_fill_rx_ring(struct sk_if_softc *sc_if) 2147 { 2148 /* Make sure to not completely wrap around */ 2149 while (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT - 1)) { 2150 if (msk_newbuf(sc_if, 2151 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 2152 goto schedretry; 2153 } 2154 } 2155 2156 return; 2157 2158 schedretry: 2159 /* Try later */ 2160 callout_schedule(&sc_if->sk_tick_rx, hz/2); 2161 } 2162 2163 static void 2164 msk_fill_rx_tick(void *xsc_if) 2165 { 2166 struct sk_if_softc *sc_if = xsc_if; 2167 int s, rx_prod; 2168 2169 KASSERT(KERNEL_LOCKED_P()); /* XXXSMP */ 2170 2171 s = splnet(); 2172 rx_prod = sc_if->sk_cdata.sk_rx_prod; 2173 msk_fill_rx_ring(sc_if); 2174 if (rx_prod != sc_if->sk_cdata.sk_rx_prod) { 2175 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2176 sc_if->sk_cdata.sk_rx_prod); 2177 } 2178 splx(s); 2179 } 2180 2181 void 2182 msk_tick(void *xsc_if) 2183 { 2184 struct sk_if_softc *sc_if = xsc_if; 2185 struct mii_data *mii = &sc_if->sk_mii; 2186 int s; 2187 2188 s = splnet(); 2189 mii_tick(mii); 2190 splx(s); 2191 2192 callout_schedule(&sc_if->sk_tick_ch, hz); 2193 } 2194 2195 void 2196 msk_intr_yukon(struct sk_if_softc *sc_if) 2197 { 2198 uint8_t status; 2199 2200 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2201 /* RX overrun */ 2202 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2203 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2204 SK_RFCTL_RX_FIFO_OVER); 2205 } 2206 /* TX underrun */ 2207 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2208 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 2209 SK_TFCTL_TX_FIFO_UNDER); 2210 } 2211 2212 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 2213 } 2214 2215 int 2216 msk_intr(void *xsc) 2217 { 2218 struct sk_softc *sc = xsc; 2219 struct sk_if_softc *sc_if; 2220 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2221 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2222 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2223 int claimed = 0; 2224 uint32_t status; 2225 struct msk_status_desc *cur_st; 2226 2227 status = CSR_READ_4(sc, SK_Y2_ISSR2); 2228 if (status == 0xffffffff) 2229 return 0; 2230 if (status == 0) { 2231 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2232 return 0; 2233 } 2234 2235 status = CSR_READ_4(sc, SK_ISR); 2236 2237 if (sc_if0 != NULL) 2238 ifp0 = &sc_if0->sk_ethercom.ec_if; 2239 if (sc_if1 != NULL) 2240 ifp1 = &sc_if1->sk_ethercom.ec_if; 2241 2242 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 2243 (ifp0->if_flags & IFF_RUNNING)) { 2244 msk_intr_yukon(sc_if0); 2245 } 2246 2247 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 2248 (ifp1->if_flags & IFF_RUNNING)) { 2249 msk_intr_yukon(sc_if1); 2250 } 2251 2252 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2253 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2254 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2255 2256 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 2257 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 2258 switch (cur_st->sk_opcode) { 2259 case SK_Y2_STOPC_RXSTAT: 2260 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 2261 if (sc_if) { 2262 msk_rxeof(sc_if, letoh16(cur_st->sk_len), 2263 letoh32(cur_st->sk_status)); 2264 if (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 2265 msk_fill_rx_tick(sc_if); 2266 } 2267 break; 2268 case SK_Y2_STOPC_TXSTAT: 2269 if (sc_if0) 2270 msk_txeof(sc_if0); 2271 if (sc_if1) 2272 msk_txeof(sc_if1); 2273 break; 2274 default: 2275 aprint_error("opcode=0x%x\n", cur_st->sk_opcode); 2276 break; 2277 } 2278 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 2279 2280 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2281 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2282 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2283 } 2284 2285 if (status & SK_Y2_IMR_BMU) { 2286 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 2287 claimed = 1; 2288 } 2289 2290 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2291 2292 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2293 if_schedule_deferred_start(ifp0); 2294 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2295 if_schedule_deferred_start(ifp1); 2296 2297 KASSERT(sc->rnd_attached > 0); 2298 rnd_add_uint32(&sc->rnd_source, status); 2299 2300 if (sc->sk_int_mod_pending) 2301 msk_update_int_mod(sc, 1); 2302 2303 return claimed; 2304 } 2305 2306 void 2307 msk_init_yukon(struct sk_if_softc *sc_if) 2308 { 2309 uint32_t v; 2310 uint16_t reg; 2311 struct sk_softc *sc; 2312 int i; 2313 2314 sc = sc_if->sk_softc; 2315 2316 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 2317 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2318 2319 DPRINTFN(6, ("msk_init_yukon: 1\n")); 2320 2321 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 2322 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2323 2324 DPRINTFN(6, ("msk_init_yukon: 3\n")); 2325 2326 /* unused read of the interrupt source register */ 2327 DPRINTFN(6, ("msk_init_yukon: 4\n")); 2328 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2329 2330 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2331 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2332 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2333 2334 /* MIB Counter Clear Mode set */ 2335 reg |= YU_PAR_MIB_CLR; 2336 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2337 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2338 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2339 2340 /* MIB Counter Clear Mode clear */ 2341 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2342 reg &= ~YU_PAR_MIB_CLR; 2343 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2344 2345 /* receive control reg */ 2346 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2347 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2348 2349 /* transmit control register */ 2350 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2351 2352 /* transmit flow control register */ 2353 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2354 2355 /* transmit parameter register */ 2356 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2357 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2358 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2359 2360 /* serial mode register */ 2361 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2362 reg = YU_SMR_DATA_BLIND(0x1c) | 2363 YU_SMR_MFL_VLAN | 2364 YU_SMR_IPG_DATA(0x1e); 2365 2366 if (sc->sk_type != SK_YUKON_FE && 2367 sc->sk_type != SK_YUKON_FE_P) 2368 reg |= YU_SMR_MFL_JUMBO; 2369 2370 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2371 2372 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2373 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2374 /* msk_attach calls me before ether_ifattach so check null */ 2375 if (ifp != NULL && ifp->if_sadl != NULL) 2376 memcpy(sc_if->sk_enaddr, CLLADDR(ifp->if_sadl), 2377 sizeof(sc_if->sk_enaddr)); 2378 /* Setup Yukon's address */ 2379 for (i = 0; i < 3; i++) { 2380 /* Write Source Address 1 (unicast filter) */ 2381 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2382 sc_if->sk_enaddr[i * 2] | 2383 sc_if->sk_enaddr[i * 2 + 1] << 8); 2384 } 2385 2386 for (i = 0; i < 3; i++) { 2387 reg = sk_win_read_2(sc_if->sk_softc, 2388 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2389 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2390 } 2391 2392 /* Set promiscuous mode */ 2393 msk_setpromisc(sc_if); 2394 2395 /* Set multicast filter */ 2396 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2397 msk_setmulti(sc_if); 2398 2399 /* enable interrupt mask for counter overflows */ 2400 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2401 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2402 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2403 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2404 2405 /* Configure RX MAC FIFO Flush Mask */ 2406 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2407 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2408 YU_RXSTAT_JABBER; 2409 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2410 2411 /* Configure RX MAC FIFO */ 2412 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2413 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2414 SK_RFCTL_FIFO_FLUSH_ON); 2415 2416 /* Increase flush threshold to 64 bytes */ 2417 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2418 SK_RFCTL_FIFO_THRESHOLD + 1); 2419 2420 /* Configure TX MAC FIFO */ 2421 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2422 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2423 2424 #if 1 2425 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2426 #endif 2427 DPRINTFN(6, ("msk_init_yukon: end\n")); 2428 } 2429 2430 /* 2431 * Note that to properly initialize any part of the GEnesis chip, 2432 * you first have to take it out of reset mode. 2433 */ 2434 int 2435 msk_init(struct ifnet *ifp) 2436 { 2437 struct sk_if_softc *sc_if = ifp->if_softc; 2438 struct sk_softc *sc = sc_if->sk_softc; 2439 int rc = 0, s; 2440 uint32_t imr, imtimer_ticks; 2441 2442 2443 DPRINTFN(2, ("msk_init\n")); 2444 2445 s = splnet(); 2446 2447 /* Cancel pending I/O and free all RX/TX buffers. */ 2448 msk_stop(ifp, 1); 2449 2450 /* Configure I2C registers */ 2451 2452 /* Configure XMAC(s) */ 2453 msk_init_yukon(sc_if); 2454 if ((rc = ether_mediachange(ifp)) != 0) 2455 goto out; 2456 2457 /* Configure transmit arbiter(s) */ 2458 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2459 #if 0 2460 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); 2461 #endif 2462 2463 if (sc->sk_ramsize) { 2464 /* Configure RAMbuffers */ 2465 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2466 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2467 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2468 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2469 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2470 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2471 2472 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2473 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2474 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2475 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2476 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2477 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2478 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2479 } 2480 2481 /* Configure BMUs */ 2482 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2483 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2484 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2485 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2486 2487 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2488 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2489 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2490 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2491 2492 /* Make sure the sync transmit queue is disabled. */ 2493 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2494 2495 /* Init descriptors */ 2496 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2497 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2498 "memory for rx buffers\n"); 2499 msk_stop(ifp, 1); 2500 splx(s); 2501 return ENOBUFS; 2502 } 2503 2504 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2505 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2506 "memory for tx buffers\n"); 2507 msk_stop(ifp, 1); 2508 splx(s); 2509 return ENOBUFS; 2510 } 2511 2512 /* Set interrupt moderation if changed via sysctl. */ 2513 switch (sc->sk_type) { 2514 case SK_YUKON_EC: 2515 case SK_YUKON_EC_U: 2516 case SK_YUKON_EX: 2517 case SK_YUKON_SUPR: 2518 case SK_YUKON_ULTRA2: 2519 case SK_YUKON_OPTIMA: 2520 case SK_YUKON_PRM: 2521 case SK_YUKON_OPTIMA2: 2522 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2523 break; 2524 case SK_YUKON_FE: 2525 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2526 break; 2527 case SK_YUKON_FE_P: 2528 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 2529 break; 2530 case SK_YUKON_XL: 2531 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2532 break; 2533 default: 2534 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2535 } 2536 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2537 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2538 sk_win_write_4(sc, SK_IMTIMERINIT, 2539 SK_IM_USECS(sc->sk_int_mod)); 2540 aprint_verbose_dev(sc->sk_dev, 2541 "interrupt moderation is %d us\n", sc->sk_int_mod); 2542 } 2543 2544 /* Initialize prefetch engine. */ 2545 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2546 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2547 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2548 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2549 MSK_RX_RING_ADDR(sc_if, 0)); 2550 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2551 (uint64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2552 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2553 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2554 2555 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2556 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2557 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2558 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2559 MSK_TX_RING_ADDR(sc_if, 0)); 2560 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2561 (uint64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2562 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2563 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2564 2565 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2566 sc_if->sk_cdata.sk_rx_prod); 2567 2568 /* Configure interrupt handling */ 2569 if (sc_if->sk_port == SK_PORT_A) 2570 sc->sk_intrmask |= SK_Y2_INTRS1; 2571 else 2572 sc->sk_intrmask |= SK_Y2_INTRS2; 2573 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2574 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2575 2576 ifp->if_flags |= IFF_RUNNING; 2577 ifp->if_flags &= ~IFF_OACTIVE; 2578 2579 callout_schedule(&sc_if->sk_tick_ch, hz); 2580 2581 out: 2582 splx(s); 2583 return rc; 2584 } 2585 2586 /* 2587 * Note: the logic of second parameter is inverted compared to OpenBSD 2588 * code, since this code uses the function as if_stop hook too. 2589 */ 2590 void 2591 msk_stop(struct ifnet *ifp, int disable) 2592 { 2593 struct sk_if_softc *sc_if = ifp->if_softc; 2594 struct sk_softc *sc = sc_if->sk_softc; 2595 struct sk_txmap_entry *dma; 2596 int i; 2597 2598 DPRINTFN(2, ("msk_stop\n")); 2599 2600 callout_stop(&sc_if->sk_tick_ch); 2601 callout_stop(&sc_if->sk_tick_rx); 2602 2603 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2604 2605 /* Stop transfer of Tx descriptors */ 2606 2607 /* Stop transfer of Rx descriptors */ 2608 2609 if (disable) { 2610 /* Turn off various components of this interface. */ 2611 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2612 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2613 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2614 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2615 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2616 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2617 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2618 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2619 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2620 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2621 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2622 2623 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2624 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2625 2626 /* Disable interrupts */ 2627 if (sc_if->sk_port == SK_PORT_A) 2628 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2629 else 2630 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2631 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2632 } 2633 2634 /* Free RX and TX mbufs still in the queues. */ 2635 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2636 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2637 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2638 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2639 } 2640 } 2641 2642 sc_if->sk_cdata.sk_rx_prod = 0; 2643 sc_if->sk_cdata.sk_rx_cons = 0; 2644 sc_if->sk_cdata.sk_rx_cnt = 0; 2645 2646 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2647 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2648 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2649 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2650 #if 1 2651 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2652 sc_if->sk_cdata.sk_tx_map[i], link); 2653 sc_if->sk_cdata.sk_tx_map[i] = 0; 2654 #endif 2655 } 2656 } 2657 2658 #if 1 2659 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2660 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2661 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2662 free(dma, M_DEVBUF); 2663 } 2664 #endif 2665 } 2666 2667 CFATTACH_DECL3_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2668 mskc_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2669 2670 CFATTACH_DECL3_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2671 msk_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2672 2673 #ifdef MSK_DEBUG 2674 void 2675 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2676 { 2677 #define DESC_PRINT(X) \ 2678 if (X) \ 2679 printf("txdesc[%d]." #X "=%#x\n", \ 2680 idx, X); 2681 2682 DESC_PRINT(letoh32(le->sk_addr)); 2683 DESC_PRINT(letoh16(le->sk_len)); 2684 DESC_PRINT(le->sk_ctl); 2685 DESC_PRINT(le->sk_opcode); 2686 #undef DESC_PRINT 2687 } 2688 2689 void 2690 msk_dump_bytes(const char *data, int len) 2691 { 2692 int c, i, j; 2693 2694 for (i = 0; i < len; i += 16) { 2695 printf("%08x ", i); 2696 c = len - i; 2697 if (c > 16) c = 16; 2698 2699 for (j = 0; j < c; j++) { 2700 printf("%02x ", data[i + j] & 0xff); 2701 if ((j & 0xf) == 7 && j > 0) 2702 printf(" "); 2703 } 2704 2705 for (; j < 16; j++) 2706 printf(" "); 2707 printf(" "); 2708 2709 for (j = 0; j < c; j++) { 2710 int ch = data[i + j] & 0xff; 2711 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2712 } 2713 2714 printf("\n"); 2715 2716 if (c < 16) 2717 break; 2718 } 2719 } 2720 2721 void 2722 msk_dump_mbuf(struct mbuf *m) 2723 { 2724 int count = m->m_pkthdr.len; 2725 2726 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2727 2728 while (count > 0 && m) { 2729 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2730 m, m->m_data, m->m_len); 2731 if (mskdebug >= 4) 2732 msk_dump_bytes(mtod(m, char *), m->m_len); 2733 2734 count -= m->m_len; 2735 m = m->m_next; 2736 } 2737 } 2738 #endif 2739 2740 static int 2741 msk_sysctl_handler(SYSCTLFN_ARGS) 2742 { 2743 int error, t; 2744 struct sysctlnode node; 2745 struct sk_softc *sc; 2746 2747 node = *rnode; 2748 sc = node.sysctl_data; 2749 t = sc->sk_int_mod; 2750 node.sysctl_data = &t; 2751 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2752 if (error || newp == NULL) 2753 return error; 2754 2755 if (t < SK_IM_MIN || t > SK_IM_MAX) 2756 return EINVAL; 2757 2758 /* update the softc with sysctl-changed value, and mark 2759 for hardware update */ 2760 sc->sk_int_mod = t; 2761 sc->sk_int_mod_pending = 1; 2762 return 0; 2763 } 2764 2765 /* 2766 * Set up sysctl(3) MIB, hw.msk.* - Individual controllers will be 2767 * set up in mskc_attach() 2768 */ 2769 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2770 { 2771 int rc; 2772 const struct sysctlnode *node; 2773 2774 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2775 0, CTLTYPE_NODE, "msk", 2776 SYSCTL_DESCR("msk interface controls"), 2777 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2778 goto err; 2779 } 2780 2781 msk_root_num = node->sysctl_num; 2782 return; 2783 2784 err: 2785 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2786 } 2787
Indexes created Tue Sep 23 14:10:03 GMT 2025