if_msk.c revision 1.9.2.1
1 /* $NetBSD: if_msk.c,v 1.9.2.1 2007/08/15 13:48:32 skrll Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.42 2007/01/17 02:43:02 krw Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 56 #include "bpfilter.h" 57 #include "rnd.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/sockio.h> 62 #include <sys/mbuf.h> 63 #include <sys/malloc.h> 64 #include <sys/kernel.h> 65 #include <sys/socket.h> 66 #include <sys/device.h> 67 #include <sys/queue.h> 68 #include <sys/callout.h> 69 #include <sys/sysctl.h> 70 #include <sys/endian.h> 71 #ifdef __NetBSD__ 72 #define letoh16 htole16 73 #define letoh32 htole32 74 #endif 75 76 #include <net/if.h> 77 #include <net/if_dl.h> 78 #include <net/if_types.h> 79 80 #include <net/if_media.h> 81 82 #if NBPFILTER > 0 83 #include <net/bpf.h> 84 #endif 85 #if NRND > 0 86 #include <sys/rnd.h> 87 #endif 88 89 #include <dev/mii/mii.h> 90 #include <dev/mii/miivar.h> 91 #include <dev/mii/brgphyreg.h> 92 93 #include <dev/pci/pcireg.h> 94 #include <dev/pci/pcivar.h> 95 #include <dev/pci/pcidevs.h> 96 97 #include <dev/pci/if_skreg.h> 98 #include <dev/pci/if_mskvar.h> 99 100 int mskc_probe(struct device *, struct cfdata *, void *); 101 void mskc_attach(struct device *, struct device *self, void *aux); 102 void mskc_shutdown(void *); 103 int msk_probe(struct device *, struct cfdata *, void *); 104 void msk_attach(struct device *, struct device *self, void *aux); 105 int mskcprint(void *, const char *); 106 int msk_intr(void *); 107 void msk_intr_yukon(struct sk_if_softc *); 108 __inline int msk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 109 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 110 void msk_txeof(struct sk_if_softc *, int); 111 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 112 void msk_start(struct ifnet *); 113 int msk_ioctl(struct ifnet *, u_long, void *); 114 int msk_init(struct ifnet *); 115 void msk_init_yukon(struct sk_if_softc *); 116 void msk_stop(struct ifnet *, int); 117 void msk_watchdog(struct ifnet *); 118 int msk_ifmedia_upd(struct ifnet *); 119 void msk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 120 void msk_reset(struct sk_softc *); 121 int msk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 122 int msk_alloc_jumbo_mem(struct sk_if_softc *); 123 void *msk_jalloc(struct sk_if_softc *); 124 void msk_jfree(struct mbuf *, void *, size_t, void *); 125 int msk_init_rx_ring(struct sk_if_softc *); 126 int msk_init_tx_ring(struct sk_if_softc *); 127 128 void msk_update_int_mod(struct sk_softc *); 129 130 int msk_miibus_readreg(struct device *, int, int); 131 void msk_miibus_writereg(struct device *, int, int, int); 132 void msk_miibus_statchg(struct device *); 133 134 void msk_setfilt(struct sk_if_softc *, void *, int); 135 void msk_setmulti(struct sk_if_softc *); 136 void msk_setpromisc(struct sk_if_softc *); 137 void msk_tick(void *); 138 139 /* #define MSK_DEBUG 1 */ 140 #ifdef MSK_DEBUG 141 #define DPRINTF(x) if (mskdebug) printf x 142 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 143 int mskdebug = MSK_DEBUG; 144 145 void msk_dump_txdesc(struct msk_tx_desc *, int); 146 void msk_dump_mbuf(struct mbuf *); 147 void msk_dump_bytes(const char *, int); 148 #else 149 #define DPRINTF(x) 150 #define DPRINTFN(n,x) 151 #endif 152 153 static int msk_sysctl_handler(SYSCTLFN_PROTO); 154 static int msk_root_num; 155 156 /* supported device vendors */ 157 static const struct msk_product { 158 pci_vendor_id_t msk_vendor; 159 pci_product_id_t msk_product; 160 } msk_products[] = { 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 163 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_1 }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 187 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 188 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 } 189 }; 190 191 static inline u_int32_t 192 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 193 { 194 return CSR_READ_4(sc, reg); 195 } 196 197 static inline u_int16_t 198 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 199 { 200 return CSR_READ_2(sc, reg); 201 } 202 203 static inline u_int8_t 204 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 205 { 206 return CSR_READ_1(sc, reg); 207 } 208 209 static inline void 210 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 211 { 212 CSR_WRITE_4(sc, reg, x); 213 } 214 215 static inline void 216 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 217 { 218 CSR_WRITE_2(sc, reg, x); 219 } 220 221 static inline void 222 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 223 { 224 CSR_WRITE_1(sc, reg, x); 225 } 226 227 int 228 msk_miibus_readreg(struct device *dev, int phy, int reg) 229 { 230 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 231 u_int16_t val; 232 int i; 233 234 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 235 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 236 237 for (i = 0; i < SK_TIMEOUT; i++) { 238 DELAY(1); 239 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 240 if (val & YU_SMICR_READ_VALID) 241 break; 242 } 243 244 if (i == SK_TIMEOUT) { 245 aprint_error("%s: phy failed to come ready\n", 246 sc_if->sk_dev.dv_xname); 247 return (0); 248 } 249 250 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 251 SK_TIMEOUT)); 252 253 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 254 255 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 256 phy, reg, val)); 257 258 return (val); 259 } 260 261 void 262 msk_miibus_writereg(struct device *dev, int phy, int reg, int val) 263 { 264 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 265 int i; 266 267 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 268 phy, reg, val)); 269 270 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 271 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 272 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 273 274 for (i = 0; i < SK_TIMEOUT; i++) { 275 DELAY(1); 276 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 277 break; 278 } 279 280 if (i == SK_TIMEOUT) 281 aprint_error("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 282 } 283 284 void 285 msk_miibus_statchg(struct device *dev) 286 { 287 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 288 struct mii_data *mii = &sc_if->sk_mii; 289 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 290 int gpcr; 291 292 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 293 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 294 295 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 296 /* Set speed. */ 297 gpcr |= YU_GPCR_SPEED_DIS; 298 switch (IFM_SUBTYPE(mii->mii_media_active)) { 299 case IFM_1000_SX: 300 case IFM_1000_LX: 301 case IFM_1000_CX: 302 case IFM_1000_T: 303 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 304 break; 305 case IFM_100_TX: 306 gpcr |= YU_GPCR_SPEED; 307 break; 308 } 309 310 /* Set duplex. */ 311 gpcr |= YU_GPCR_DPLX_DIS; 312 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 313 gpcr |= YU_GPCR_DUPLEX; 314 315 /* Disable flow control. */ 316 gpcr |= YU_GPCR_FCTL_DIS; 317 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 318 } 319 320 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 321 322 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 323 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 324 } 325 326 #define HASH_BITS 6 327 328 void 329 msk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 330 { 331 char *addr = addrv; 332 int base = XM_RXFILT_ENTRY(slot); 333 334 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 335 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 336 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 337 } 338 339 void 340 msk_setmulti(struct sk_if_softc *sc_if) 341 { 342 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 343 u_int32_t hashes[2] = { 0, 0 }; 344 int h; 345 struct ethercom *ec = &sc_if->sk_ethercom; 346 struct ether_multi *enm; 347 struct ether_multistep step; 348 u_int16_t reg; 349 350 /* First, zot all the existing filters. */ 351 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 352 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 353 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 354 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 355 356 357 /* Now program new ones. */ 358 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 359 reg |= YU_RCR_UFLEN; 360 allmulti: 361 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 362 if ((ifp->if_flags & IFF_PROMISC) != 0) 363 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 364 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 365 hashes[0] = 0xFFFFFFFF; 366 hashes[1] = 0xFFFFFFFF; 367 } 368 } else { 369 /* First find the tail of the list. */ 370 ETHER_FIRST_MULTI(step, ec, enm); 371 while (enm != NULL) { 372 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 373 ETHER_ADDR_LEN)) { 374 ifp->if_flags |= IFF_ALLMULTI; 375 goto allmulti; 376 } 377 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 378 ((1 << HASH_BITS) - 1); 379 if (h < 32) 380 hashes[0] |= (1 << h); 381 else 382 hashes[1] |= (1 << (h - 32)); 383 384 ETHER_NEXT_MULTI(step, enm); 385 } 386 reg |= YU_RCR_MUFLEN; 387 } 388 389 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 390 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 391 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 392 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 393 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 394 } 395 396 void 397 msk_setpromisc(struct sk_if_softc *sc_if) 398 { 399 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 400 401 if (ifp->if_flags & IFF_PROMISC) 402 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 403 YU_RCR_UFLEN | YU_RCR_MUFLEN); 404 else 405 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 406 YU_RCR_UFLEN | YU_RCR_MUFLEN); 407 } 408 409 int 410 msk_init_rx_ring(struct sk_if_softc *sc_if) 411 { 412 struct msk_chain_data *cd = &sc_if->sk_cdata; 413 struct msk_ring_data *rd = sc_if->sk_rdata; 414 int i, nexti; 415 416 bzero((char *)rd->sk_rx_ring, 417 sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 418 419 for (i = 0; i < MSK_RX_RING_CNT; i++) { 420 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 421 if (i == (MSK_RX_RING_CNT - 1)) 422 nexti = 0; 423 else 424 nexti = i + 1; 425 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 426 } 427 428 for (i = 0; i < MSK_RX_RING_CNT; i++) { 429 if (msk_newbuf(sc_if, i, NULL, 430 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 431 aprint_error("%s: failed alloc of %dth mbuf\n", 432 sc_if->sk_dev.dv_xname, i); 433 return (ENOBUFS); 434 } 435 } 436 437 sc_if->sk_cdata.sk_rx_prod = MSK_RX_RING_CNT - 1; 438 sc_if->sk_cdata.sk_rx_cons = 0; 439 440 return (0); 441 } 442 443 int 444 msk_init_tx_ring(struct sk_if_softc *sc_if) 445 { 446 struct sk_softc *sc = sc_if->sk_softc; 447 struct msk_chain_data *cd = &sc_if->sk_cdata; 448 struct msk_ring_data *rd = sc_if->sk_rdata; 449 bus_dmamap_t dmamap; 450 struct sk_txmap_entry *entry; 451 int i, nexti; 452 453 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 454 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 455 456 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 457 for (i = 0; i < MSK_TX_RING_CNT; i++) { 458 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 459 if (i == (MSK_TX_RING_CNT - 1)) 460 nexti = 0; 461 else 462 nexti = i + 1; 463 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 464 465 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 466 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 467 return (ENOBUFS); 468 469 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 470 if (!entry) { 471 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 472 return (ENOBUFS); 473 } 474 entry->dmamap = dmamap; 475 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 476 } 477 478 sc_if->sk_cdata.sk_tx_prod = 0; 479 sc_if->sk_cdata.sk_tx_cons = 0; 480 sc_if->sk_cdata.sk_tx_cnt = 0; 481 482 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 483 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 484 485 return (0); 486 } 487 488 int 489 msk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 490 bus_dmamap_t dmamap) 491 { 492 struct mbuf *m_new = NULL; 493 struct sk_chain *c; 494 struct msk_rx_desc *r; 495 496 if (m == NULL) { 497 void *buf = NULL; 498 499 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 500 if (m_new == NULL) 501 return (ENOBUFS); 502 503 /* Allocate the jumbo buffer */ 504 buf = msk_jalloc(sc_if); 505 if (buf == NULL) { 506 m_freem(m_new); 507 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 508 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 509 return (ENOBUFS); 510 } 511 512 /* Attach the buffer to the mbuf */ 513 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 514 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 515 } else { 516 /* 517 * We're re-using a previously allocated mbuf; 518 * be sure to re-init pointers and lengths to 519 * default values. 520 */ 521 m_new = m; 522 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 523 m_new->m_data = m_new->m_ext.ext_buf; 524 } 525 m_adj(m_new, ETHER_ALIGN); 526 527 c = &sc_if->sk_cdata.sk_rx_chain[i]; 528 r = c->sk_le; 529 c->sk_mbuf = m_new; 530 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + 531 (((vaddr_t)m_new->m_data 532 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 533 r->sk_len = htole16(SK_JLEN); 534 r->sk_ctl = 0; 535 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 536 537 MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 538 539 return (0); 540 } 541 542 /* 543 * Memory management for jumbo frames. 544 */ 545 546 int 547 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 548 { 549 struct sk_softc *sc = sc_if->sk_softc; 550 char *ptr, *kva; 551 bus_dma_segment_t seg; 552 int i, rseg, state, error; 553 struct sk_jpool_entry *entry; 554 555 state = error = 0; 556 557 /* Grab a big chunk o' storage. */ 558 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 559 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 560 aprint_error(": can't alloc rx buffers"); 561 return (ENOBUFS); 562 } 563 564 state = 1; 565 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, MSK_JMEM, (void **)&kva, 566 BUS_DMA_NOWAIT)) { 567 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 568 error = ENOBUFS; 569 goto out; 570 } 571 572 state = 2; 573 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 574 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 575 aprint_error(": can't create dma map"); 576 error = ENOBUFS; 577 goto out; 578 } 579 580 state = 3; 581 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 582 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 583 aprint_error(": can't load dma map"); 584 error = ENOBUFS; 585 goto out; 586 } 587 588 state = 4; 589 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 590 DPRINTFN(1,("msk_jumbo_buf = %p\n", (void *)sc_if->sk_cdata.sk_jumbo_buf)); 591 592 LIST_INIT(&sc_if->sk_jfree_listhead); 593 LIST_INIT(&sc_if->sk_jinuse_listhead); 594 595 /* 596 * Now divide it up into 9K pieces and save the addresses 597 * in an array. 598 */ 599 ptr = sc_if->sk_cdata.sk_jumbo_buf; 600 for (i = 0; i < MSK_JSLOTS; i++) { 601 sc_if->sk_cdata.sk_jslots[i] = ptr; 602 ptr += SK_JLEN; 603 entry = malloc(sizeof(struct sk_jpool_entry), 604 M_DEVBUF, M_NOWAIT); 605 if (entry == NULL) { 606 sc_if->sk_cdata.sk_jumbo_buf = NULL; 607 aprint_error(": no memory for jumbo buffer queue!"); 608 error = ENOBUFS; 609 goto out; 610 } 611 entry->slot = i; 612 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 613 entry, jpool_entries); 614 } 615 out: 616 if (error != 0) { 617 switch (state) { 618 case 4: 619 bus_dmamap_unload(sc->sc_dmatag, 620 sc_if->sk_cdata.sk_rx_jumbo_map); 621 case 3: 622 bus_dmamap_destroy(sc->sc_dmatag, 623 sc_if->sk_cdata.sk_rx_jumbo_map); 624 case 2: 625 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 626 case 1: 627 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 628 break; 629 default: 630 break; 631 } 632 } 633 634 return (error); 635 } 636 637 /* 638 * Allocate a jumbo buffer. 639 */ 640 void * 641 msk_jalloc(struct sk_if_softc *sc_if) 642 { 643 struct sk_jpool_entry *entry; 644 645 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 646 647 if (entry == NULL) 648 return (NULL); 649 650 LIST_REMOVE(entry, jpool_entries); 651 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 652 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 653 } 654 655 /* 656 * Release a jumbo buffer. 657 */ 658 void 659 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 660 { 661 struct sk_jpool_entry *entry; 662 struct sk_if_softc *sc; 663 int i, s; 664 665 /* Extract the softc struct pointer. */ 666 sc = (struct sk_if_softc *)arg; 667 668 if (sc == NULL) 669 panic("msk_jfree: can't find softc pointer!"); 670 671 /* calculate the slot this buffer belongs to */ 672 i = ((vaddr_t)buf 673 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 674 675 if ((i < 0) || (i >= MSK_JSLOTS)) 676 panic("msk_jfree: asked to free buffer that we don't manage!"); 677 678 s = splvm(); 679 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 680 if (entry == NULL) 681 panic("msk_jfree: buffer not in use!"); 682 entry->slot = i; 683 LIST_REMOVE(entry, jpool_entries); 684 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 685 686 if (__predict_true(m != NULL)) 687 pool_cache_put(&mbpool_cache, m); 688 splx(s); 689 } 690 691 /* 692 * Set media options. 693 */ 694 int 695 msk_ifmedia_upd(struct ifnet *ifp) 696 { 697 struct sk_if_softc *sc_if = ifp->if_softc; 698 699 mii_mediachg(&sc_if->sk_mii); 700 return (0); 701 } 702 703 /* 704 * Report current media status. 705 */ 706 void 707 msk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 708 { 709 struct sk_if_softc *sc_if = ifp->if_softc; 710 711 mii_pollstat(&sc_if->sk_mii); 712 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 713 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 714 } 715 716 int 717 msk_ioctl(struct ifnet *ifp, u_long command, void *data) 718 { 719 struct sk_if_softc *sc_if = ifp->if_softc; 720 struct ifreq *ifr = (struct ifreq *) data; 721 struct mii_data *mii; 722 int s, error = 0; 723 724 s = splnet(); 725 726 switch(command) { 727 case SIOCSIFMTU: 728 if (ifr->ifr_mtu < ETHERMIN) 729 return EINVAL; 730 else if (sc_if->sk_softc->sk_type != SK_YUKON_FE) { 731 if (ifr->ifr_mtu > SK_JUMBO_MTU) 732 error = EINVAL; 733 } else if (ifr->ifr_mtu > ETHERMTU) 734 error = EINVAL; 735 ifp->if_mtu = ifr->ifr_mtu; 736 break; 737 case SIOCGIFMEDIA: 738 case SIOCSIFMEDIA: 739 DPRINTFN(2,("msk_ioctl: SIOC[GS]IFMEDIA\n")); 740 mii = &sc_if->sk_mii; 741 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 742 DPRINTFN(2,("msk_ioctl: SIOC[GS]IFMEDIA done\n")); 743 break; 744 default: 745 DPRINTFN(2, ("msk_ioctl ETHER\n")); 746 error = ether_ioctl(ifp, command, data); 747 748 if (error == ENETRESET) { 749 /* 750 * Multicast list has changed; set the hardware 751 * filter accordingly. 752 */ 753 if (ifp->if_flags & IFF_RUNNING) 754 msk_setmulti(sc_if); 755 error = 0; 756 } 757 break; 758 } 759 760 splx(s); 761 return (error); 762 } 763 764 void 765 msk_update_int_mod(struct sk_softc *sc) 766 { 767 u_int32_t imtimer_ticks; 768 769 /* 770 * Configure interrupt moderation. The moderation timer 771 * defers interrupts specified in the interrupt moderation 772 * timer mask based on the timeout specified in the interrupt 773 * moderation timer init register. Each bit in the timer 774 * register represents one tick, so to specify a timeout in 775 * microseconds, we have to multiply by the correct number of 776 * ticks-per-microsecond. 777 */ 778 switch (sc->sk_type) { 779 case SK_YUKON_EC: 780 case SK_YUKON_EC_U: 781 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 782 break; 783 case SK_YUKON_FE: 784 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 785 break; 786 case SK_YUKON_XL: 787 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 788 break; 789 default: 790 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 791 } 792 aprint_verbose("%s: interrupt moderation is %d us\n", 793 sc->sk_dev.dv_xname, sc->sk_int_mod); 794 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 795 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 796 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 797 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 798 sc->sk_int_mod_pending = 0; 799 } 800 801 static int 802 msk_lookup(const struct pci_attach_args *pa) 803 { 804 const struct msk_product *pmsk; 805 806 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 807 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 808 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 809 return 1; 810 } 811 return 0; 812 } 813 814 /* 815 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 816 * IDs against our list and return a device name if we find a match. 817 */ 818 int 819 mskc_probe(struct device *parent, struct cfdata *match, 820 void *aux) 821 { 822 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 823 824 return msk_lookup(pa); 825 } 826 827 /* 828 * Force the GEnesis into reset, then bring it out of reset. 829 */ 830 void msk_reset(struct sk_softc *sc) 831 { 832 u_int32_t imtimer_ticks, reg1; 833 int reg; 834 835 DPRINTFN(2, ("msk_reset\n")); 836 837 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 838 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 839 840 DELAY(1000); 841 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 842 DELAY(2); 843 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 844 sk_win_write_1(sc, SK_TESTCTL1, 2); 845 846 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 847 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 848 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 849 else 850 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 851 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 852 853 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 854 sk_win_write_1(sc, SK_Y2_CLKGATE, 855 SK_Y2_CLKGATE_LINK1_GATE_DIS | 856 SK_Y2_CLKGATE_LINK2_GATE_DIS | 857 SK_Y2_CLKGATE_LINK1_CORE_DIS | 858 SK_Y2_CLKGATE_LINK2_CORE_DIS | 859 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 860 else 861 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 862 863 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 864 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 865 DELAY(1000); 866 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 867 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 868 869 sk_win_write_1(sc, SK_TESTCTL1, 1); 870 871 DPRINTFN(2, ("msk_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 872 DPRINTFN(2, ("msk_reset: sk_link_ctrl=%x\n", 873 CSR_READ_2(sc, SK_LINK_CTRL))); 874 875 /* Disable ASF */ 876 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 877 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 878 879 /* Clear I2C IRQ noise */ 880 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 881 882 /* Disable hardware timer */ 883 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 884 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 885 886 /* Disable descriptor polling */ 887 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 888 889 /* Disable time stamps */ 890 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 891 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 892 893 /* Enable RAM interface */ 894 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 895 for (reg = SK_TO0;reg <= SK_TO11; reg++) 896 sk_win_write_1(sc, reg, 36); 897 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 898 for (reg = SK_TO0;reg <= SK_TO11; reg++) 899 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 900 901 /* 902 * Configure interrupt moderation. The moderation timer 903 * defers interrupts specified in the interrupt moderation 904 * timer mask based on the timeout specified in the interrupt 905 * moderation timer init register. Each bit in the timer 906 * register represents one tick, so to specify a timeout in 907 * microseconds, we have to multiply by the correct number of 908 * ticks-per-microsecond. 909 */ 910 switch (sc->sk_type) { 911 case SK_YUKON_EC: 912 case SK_YUKON_EC_U: 913 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 914 break; 915 case SK_YUKON_FE: 916 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 917 break; 918 case SK_YUKON_XL: 919 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 920 break; 921 default: 922 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 923 } 924 925 /* Reset status ring. */ 926 bzero((char *)sc->sk_status_ring, 927 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 928 sc->sk_status_idx = 0; 929 930 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 931 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 932 933 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 934 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 935 sc->sk_status_map->dm_segs[0].ds_addr); 936 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 937 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 938 if ((sc->sk_workaround & SK_STAT_BMU_FIFOIWM) != 0) { 939 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK); 940 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 941 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 942 } else { 943 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 944 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 945 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 946 ((sc->sk_workaround & SK_WA_4109) != 0) ? 0x10 : 0x04); 947 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 948 } 949 950 #if 0 951 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 952 #endif 953 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 954 955 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 956 957 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 958 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 959 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 960 961 msk_update_int_mod(sc); 962 } 963 964 int 965 msk_probe(struct device *parent, struct cfdata *match, 966 void *aux) 967 { 968 struct skc_attach_args *sa = aux; 969 970 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 971 return (0); 972 973 switch (sa->skc_type) { 974 case SK_YUKON_XL: 975 case SK_YUKON_EC_U: 976 case SK_YUKON_EC: 977 case SK_YUKON_FE: 978 return (1); 979 } 980 981 return (0); 982 } 983 984 /* 985 * Each XMAC chip is attached as a separate logical IP interface. 986 * Single port cards will have only one logical interface of course. 987 */ 988 void 989 msk_attach(struct device *parent, struct device *self, void *aux) 990 { 991 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 992 struct sk_softc *sc = (struct sk_softc *)parent; 993 struct skc_attach_args *sa = aux; 994 struct ifnet *ifp; 995 void *kva; 996 bus_dma_segment_t seg; 997 int i, rseg; 998 u_int32_t chunk, val; 999 1000 sc_if->sk_port = sa->skc_port; 1001 sc_if->sk_softc = sc; 1002 sc->sk_if[sa->skc_port] = sc_if; 1003 1004 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1005 1006 /* 1007 * Get station address for this interface. Note that 1008 * dual port cards actually come with three station 1009 * addresses: one for each port, plus an extra. The 1010 * extra one is used by the SysKonnect driver software 1011 * as a 'virtual' station address for when both ports 1012 * are operating in failover mode. Currently we don't 1013 * use this extra address. 1014 */ 1015 for (i = 0; i < ETHER_ADDR_LEN; i++) 1016 sc_if->sk_enaddr[i] = 1017 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1018 1019 aprint_normal(": Ethernet address %s\n", 1020 ether_sprintf(sc_if->sk_enaddr)); 1021 1022 /* 1023 * Set up RAM buffer addresses. The NIC will have a certain 1024 * amount of SRAM on it, somewhere between 512K and 2MB. We 1025 * need to divide this up a) between the transmitter and 1026 * receiver and b) between the two XMACs, if this is a 1027 * dual port NIC. Our algorithm is to divide up the memory 1028 * evenly so that everyone gets a fair share. 1029 * 1030 * Just to be contrary, Yukon2 appears to have separate memory 1031 * for each MAC. 1032 */ 1033 chunk = sc->sk_ramsize - (sc->sk_ramsize + 2) / 3; 1034 val = sc->sk_rboff / sizeof(u_int64_t); 1035 sc_if->sk_rx_ramstart = val; 1036 val += (chunk / sizeof(u_int64_t)); 1037 sc_if->sk_rx_ramend = val - 1; 1038 chunk = sc->sk_ramsize - chunk; 1039 sc_if->sk_tx_ramstart = val; 1040 val += (chunk / sizeof(u_int64_t)); 1041 sc_if->sk_tx_ramend = val - 1; 1042 1043 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1044 " tx_ramstart=%#x tx_ramend=%#x\n", 1045 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1046 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1047 1048 /* Allocate the descriptor queues. */ 1049 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1050 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1051 aprint_error(": can't alloc rx buffers\n"); 1052 goto fail; 1053 } 1054 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1055 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1056 aprint_error(": can't map dma buffers (%zu bytes)\n", 1057 sizeof(struct msk_ring_data)); 1058 goto fail_1; 1059 } 1060 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1061 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1062 &sc_if->sk_ring_map)) { 1063 aprint_error(": can't create dma map\n"); 1064 goto fail_2; 1065 } 1066 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1067 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1068 aprint_error(": can't load dma map\n"); 1069 goto fail_3; 1070 } 1071 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1072 bzero(sc_if->sk_rdata, sizeof(struct msk_ring_data)); 1073 1074 ifp = &sc_if->sk_ethercom.ec_if; 1075 /* Try to allocate memory for jumbo buffers. */ 1076 if (msk_alloc_jumbo_mem(sc_if)) { 1077 aprint_error(": jumbo buffer allocation failed\n"); 1078 goto fail_3; 1079 } 1080 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1081 | ETHERCAP_JUMBO_MTU; 1082 1083 ifp->if_softc = sc_if; 1084 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1085 ifp->if_ioctl = msk_ioctl; 1086 ifp->if_start = msk_start; 1087 ifp->if_stop = msk_stop; 1088 ifp->if_init = msk_init; 1089 ifp->if_watchdog = msk_watchdog; 1090 ifp->if_baudrate = 1000000000; 1091 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1092 IFQ_SET_READY(&ifp->if_snd); 1093 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1094 1095 /* 1096 * Do miibus setup. 1097 */ 1098 msk_init_yukon(sc_if); 1099 1100 DPRINTFN(2, ("msk_attach: 1\n")); 1101 1102 sc_if->sk_mii.mii_ifp = ifp; 1103 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1104 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1105 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1106 1107 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1108 msk_ifmedia_upd, msk_ifmedia_sts); 1109 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1110 MII_OFFSET_ANY, MIIF_DOPAUSE|MIIF_FORCEANEG); 1111 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1112 aprint_error("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1113 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1114 0, NULL); 1115 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1116 } else 1117 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1118 1119 callout_init(&sc_if->sk_tick_ch, 0); 1120 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1121 callout_schedule(&sc_if->sk_tick_ch, hz); 1122 1123 /* 1124 * Call MI attach routines. 1125 */ 1126 if_attach(ifp); 1127 ether_ifattach(ifp, sc_if->sk_enaddr); 1128 1129 shutdownhook_establish(mskc_shutdown, sc); 1130 1131 #if NRND > 0 1132 rnd_attach_source(&sc->rnd_source, sc->sk_dev.dv_xname, 1133 RND_TYPE_NET, 0); 1134 #endif 1135 1136 DPRINTFN(2, ("msk_attach: end\n")); 1137 return; 1138 1139 fail_3: 1140 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1141 fail_2: 1142 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1143 fail_1: 1144 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1145 fail: 1146 sc->sk_if[sa->skc_port] = NULL; 1147 } 1148 1149 int 1150 mskcprint(void *aux, const char *pnp) 1151 { 1152 struct skc_attach_args *sa = aux; 1153 1154 if (pnp) 1155 aprint_normal("sk port %c at %s", 1156 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1157 else 1158 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1159 return (UNCONF); 1160 } 1161 1162 /* 1163 * Attach the interface. Allocate softc structures, do ifmedia 1164 * setup and ethernet/BPF attach. 1165 */ 1166 void 1167 mskc_attach(struct device *parent, struct device *self, void *aux) 1168 { 1169 struct sk_softc *sc = (struct sk_softc *)self; 1170 struct pci_attach_args *pa = aux; 1171 struct skc_attach_args skca; 1172 pci_chipset_tag_t pc = pa->pa_pc; 1173 pcireg_t command, memtype; 1174 pci_intr_handle_t ih; 1175 const char *intrstr = NULL; 1176 bus_size_t size; 1177 int rc, sk_nodenum; 1178 u_int8_t hw, skrs; 1179 const char *revstr = NULL; 1180 const struct sysctlnode *node; 1181 void *kva; 1182 bus_dma_segment_t seg; 1183 int rseg; 1184 1185 DPRINTFN(2, ("begin mskc_attach\n")); 1186 1187 /* 1188 * Handle power management nonsense. 1189 */ 1190 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1191 1192 if (command == 0x01) { 1193 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1194 if (command & SK_PSTATE_MASK) { 1195 u_int32_t iobase, membase, irq; 1196 1197 /* Save important PCI config data. */ 1198 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1199 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1200 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1201 1202 /* Reset the power state. */ 1203 aprint_normal("%s chip is in D%d power mode " 1204 "-- setting to D0\n", sc->sk_dev.dv_xname, 1205 command & SK_PSTATE_MASK); 1206 command &= 0xFFFFFFFC; 1207 pci_conf_write(pc, pa->pa_tag, 1208 SK_PCI_PWRMGMTCTRL, command); 1209 1210 /* Restore PCI config data. */ 1211 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1212 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1213 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1214 } 1215 } 1216 1217 /* 1218 * Map control/status registers. 1219 */ 1220 1221 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1222 switch (memtype) { 1223 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1224 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1225 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1226 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1227 NULL, &size) == 0) 1228 break; 1229 default: 1230 aprint_error(": can't map mem space\n"); 1231 return; 1232 } 1233 1234 sc->sc_dmatag = pa->pa_dmat; 1235 1236 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1237 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1238 1239 /* bail out here if chip is not recognized */ 1240 if (!(SK_IS_YUKON2(sc))) { 1241 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1242 goto fail_1; 1243 } 1244 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1245 1246 /* Allocate interrupt */ 1247 if (pci_intr_map(pa, &ih)) { 1248 aprint_error(": couldn't map interrupt\n"); 1249 goto fail_1; 1250 } 1251 1252 intrstr = pci_intr_string(pc, ih); 1253 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc); 1254 if (sc->sk_intrhand == NULL) { 1255 aprint_error(": couldn't establish interrupt"); 1256 if (intrstr != NULL) 1257 aprint_error(" at %s", intrstr); 1258 aprint_error("\n"); 1259 goto fail_1; 1260 } 1261 1262 if (bus_dmamem_alloc(sc->sc_dmatag, 1263 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1264 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1265 aprint_error(": can't alloc status buffers\n"); 1266 goto fail_2; 1267 } 1268 1269 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1270 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1271 &kva, BUS_DMA_NOWAIT)) { 1272 aprint_error(": can't map dma buffers (%zu bytes)\n", 1273 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1274 goto fail_3; 1275 } 1276 if (bus_dmamap_create(sc->sc_dmatag, 1277 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1278 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1279 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1280 aprint_error(": can't create dma map\n"); 1281 goto fail_4; 1282 } 1283 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1284 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1285 NULL, BUS_DMA_NOWAIT)) { 1286 aprint_error(": can't load dma map\n"); 1287 goto fail_5; 1288 } 1289 sc->sk_status_ring = (struct msk_status_desc *)kva; 1290 bzero(sc->sk_status_ring, 1291 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1292 1293 /* Reset the adapter. */ 1294 msk_reset(sc); 1295 1296 skrs = sk_win_read_1(sc, SK_EPROM0); 1297 if (skrs == 0x00) 1298 sc->sk_ramsize = 0x20000; 1299 else 1300 sc->sk_ramsize = skrs * (1<<12); 1301 sc->sk_rboff = SK_RBOFF_0; 1302 1303 DPRINTFN(2, ("mskc_attach: ramsize=%d (%dk), rboff=%d\n", 1304 sc->sk_ramsize, sc->sk_ramsize / 1024, 1305 sc->sk_rboff)); 1306 1307 switch (sc->sk_type) { 1308 case SK_YUKON_XL: 1309 sc->sk_name = "Yukon-2 XL"; 1310 break; 1311 case SK_YUKON_EC_U: 1312 sc->sk_name = "Yukon-2 EC Ultra"; 1313 break; 1314 case SK_YUKON_EC: 1315 sc->sk_name = "Yukon-2 EC"; 1316 break; 1317 case SK_YUKON_FE: 1318 sc->sk_name = "Yukon-2 FE"; 1319 break; 1320 default: 1321 sc->sk_name = "Yukon (Unknown)"; 1322 } 1323 1324 if (sc->sk_type == SK_YUKON_XL) { 1325 switch (sc->sk_rev) { 1326 case SK_YUKON_XL_REV_A0: 1327 sc->sk_workaround = 0; 1328 revstr = "A0"; 1329 break; 1330 case SK_YUKON_XL_REV_A1: 1331 sc->sk_workaround = SK_WA_4109; 1332 revstr = "A1"; 1333 break; 1334 case SK_YUKON_XL_REV_A2: 1335 sc->sk_workaround = SK_WA_4109; 1336 revstr = "A2"; 1337 break; 1338 case SK_YUKON_XL_REV_A3: 1339 sc->sk_workaround = SK_WA_4109; 1340 revstr = "A3"; 1341 break; 1342 default: 1343 sc->sk_workaround = 0; 1344 break; 1345 } 1346 } 1347 1348 if (sc->sk_type == SK_YUKON_EC) { 1349 switch (sc->sk_rev) { 1350 case SK_YUKON_EC_REV_A1: 1351 sc->sk_workaround = SK_WA_43_418 | SK_WA_4109; 1352 revstr = "A1"; 1353 break; 1354 case SK_YUKON_EC_REV_A2: 1355 sc->sk_workaround = SK_WA_4109; 1356 revstr = "A2"; 1357 break; 1358 case SK_YUKON_EC_REV_A3: 1359 sc->sk_workaround = SK_WA_4109; 1360 revstr = "A3"; 1361 break; 1362 default: 1363 sc->sk_workaround = 0; 1364 break; 1365 } 1366 } 1367 1368 if (sc->sk_type == SK_YUKON_FE) { 1369 sc->sk_workaround = SK_WA_4109; 1370 switch (sc->sk_rev) { 1371 case SK_YUKON_FE_REV_A1: 1372 revstr = "A1"; 1373 break; 1374 case SK_YUKON_FE_REV_A2: 1375 revstr = "A2"; 1376 break; 1377 default: 1378 sc->sk_workaround = 0; 1379 break; 1380 } 1381 } 1382 1383 if (sc->sk_type == SK_YUKON_EC_U) { 1384 sc->sk_workaround = SK_WA_4109; 1385 switch (sc->sk_rev) { 1386 case SK_YUKON_EC_U_REV_A0: 1387 revstr = "A0"; 1388 break; 1389 case SK_YUKON_EC_U_REV_A1: 1390 revstr = "A1"; 1391 break; 1392 case SK_YUKON_EC_U_REV_B0: 1393 revstr = "B0"; 1394 break; 1395 default: 1396 sc->sk_workaround = 0; 1397 break; 1398 } 1399 } 1400 1401 /* Announce the product name. */ 1402 aprint_normal(", %s", sc->sk_name); 1403 if (revstr != NULL) 1404 aprint_normal(" rev. %s", revstr); 1405 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1406 1407 sc->sk_macs = 1; 1408 1409 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1410 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1411 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1412 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1413 sc->sk_macs++; 1414 } 1415 1416 skca.skc_port = SK_PORT_A; 1417 skca.skc_type = sc->sk_type; 1418 skca.skc_rev = sc->sk_rev; 1419 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1420 1421 if (sc->sk_macs > 1) { 1422 skca.skc_port = SK_PORT_B; 1423 skca.skc_type = sc->sk_type; 1424 skca.skc_rev = sc->sk_rev; 1425 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1426 } 1427 1428 /* Turn on the 'driver is loaded' LED. */ 1429 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1430 1431 /* skc sysctl setup */ 1432 1433 sc->sk_int_mod = SK_IM_DEFAULT; 1434 sc->sk_int_mod_pending = 0; 1435 1436 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1437 0, CTLTYPE_NODE, sc->sk_dev.dv_xname, 1438 SYSCTL_DESCR("mskc per-controller controls"), 1439 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1440 CTL_EOL)) != 0) { 1441 aprint_normal("%s: couldn't create sysctl node\n", 1442 sc->sk_dev.dv_xname); 1443 goto fail_6; 1444 } 1445 1446 sk_nodenum = node->sysctl_num; 1447 1448 /* interrupt moderation time in usecs */ 1449 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1450 CTLFLAG_READWRITE, 1451 CTLTYPE_INT, "int_mod", 1452 SYSCTL_DESCR("msk interrupt moderation timer"), 1453 msk_sysctl_handler, 0, sc, 1454 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1455 CTL_EOL)) != 0) { 1456 aprint_normal("%s: couldn't create int_mod sysctl node\n", 1457 sc->sk_dev.dv_xname); 1458 goto fail_6; 1459 } 1460 1461 return; 1462 1463 fail_6: 1464 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1465 fail_5: 1466 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1467 fail_4: 1468 bus_dmamem_unmap(sc->sc_dmatag, kva, 1469 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1470 fail_3: 1471 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1472 fail_2: 1473 pci_intr_disestablish(pc, sc->sk_intrhand); 1474 fail_1: 1475 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1476 } 1477 1478 int 1479 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1480 { 1481 struct sk_softc *sc = sc_if->sk_softc; 1482 struct msk_tx_desc *f = NULL; 1483 u_int32_t frag, cur; 1484 int i; 1485 struct sk_txmap_entry *entry; 1486 bus_dmamap_t txmap; 1487 1488 DPRINTFN(2, ("msk_encap\n")); 1489 1490 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1491 if (entry == NULL) { 1492 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1493 return (ENOBUFS); 1494 } 1495 txmap = entry->dmamap; 1496 1497 cur = frag = *txidx; 1498 1499 #ifdef MSK_DEBUG 1500 if (mskdebug >= 2) 1501 msk_dump_mbuf(m_head); 1502 #endif 1503 1504 /* 1505 * Start packing the mbufs in this chain into 1506 * the fragment pointers. Stop when we run out 1507 * of fragments or hit the end of the mbuf chain. 1508 */ 1509 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1510 BUS_DMA_NOWAIT)) { 1511 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1512 return (ENOBUFS); 1513 } 1514 1515 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1516 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1517 bus_dmamap_unload(sc->sc_dmatag, txmap); 1518 return (ENOBUFS); 1519 } 1520 1521 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1522 1523 /* Sync the DMA map. */ 1524 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1525 BUS_DMASYNC_PREWRITE); 1526 1527 for (i = 0; i < txmap->dm_nsegs; i++) { 1528 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1529 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1530 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1531 f->sk_ctl = 0; 1532 if (i == 0) 1533 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1534 else 1535 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1536 cur = frag; 1537 SK_INC(frag, MSK_TX_RING_CNT); 1538 } 1539 1540 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1541 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1542 1543 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1544 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1545 1546 /* Sync descriptors before handing to chip */ 1547 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1548 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1549 1550 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1551 1552 /* Sync first descriptor to hand it off */ 1553 MSK_CDTXSYNC(sc_if, *txidx, 1, 1554 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1555 1556 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1557 1558 #ifdef MSK_DEBUG 1559 if (mskdebug >= 2) { 1560 struct msk_tx_desc *le; 1561 u_int32_t idx; 1562 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1563 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1564 msk_dump_txdesc(le, idx); 1565 } 1566 } 1567 #endif 1568 1569 *txidx = frag; 1570 1571 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1572 1573 return (0); 1574 } 1575 1576 void 1577 msk_start(struct ifnet *ifp) 1578 { 1579 struct sk_if_softc *sc_if = ifp->if_softc; 1580 struct mbuf *m_head = NULL; 1581 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1582 int pkts = 0; 1583 1584 DPRINTFN(2, ("msk_start\n")); 1585 1586 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1587 IFQ_POLL(&ifp->if_snd, m_head); 1588 if (m_head == NULL) 1589 break; 1590 1591 /* 1592 * Pack the data into the transmit ring. If we 1593 * don't have room, set the OACTIVE flag and wait 1594 * for the NIC to drain the ring. 1595 */ 1596 if (msk_encap(sc_if, m_head, &idx)) { 1597 ifp->if_flags |= IFF_OACTIVE; 1598 break; 1599 } 1600 1601 /* now we are committed to transmit the packet */ 1602 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1603 pkts++; 1604 1605 /* 1606 * If there's a BPF listener, bounce a copy of this frame 1607 * to him. 1608 */ 1609 #if NBPFILTER > 0 1610 if (ifp->if_bpf) 1611 bpf_mtap(ifp->if_bpf, m_head); 1612 #endif 1613 } 1614 if (pkts == 0) 1615 return; 1616 1617 /* Transmit */ 1618 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1619 sc_if->sk_cdata.sk_tx_prod = idx; 1620 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1621 1622 /* Set a timeout in case the chip goes out to lunch. */ 1623 ifp->if_timer = 5; 1624 } 1625 } 1626 1627 void 1628 msk_watchdog(struct ifnet *ifp) 1629 { 1630 struct sk_if_softc *sc_if = ifp->if_softc; 1631 u_int32_t reg; 1632 int idx; 1633 1634 /* 1635 * Reclaim first as there is a possibility of losing Tx completion 1636 * interrupts. 1637 */ 1638 if (sc_if->sk_port == SK_PORT_A) 1639 reg = SK_STAT_BMU_TXA1_RIDX; 1640 else 1641 reg = SK_STAT_BMU_TXA2_RIDX; 1642 1643 idx = sk_win_read_2(sc_if->sk_softc, reg); 1644 if (sc_if->sk_cdata.sk_tx_cons != idx) { 1645 msk_txeof(sc_if, idx); 1646 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1647 aprint_error("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1648 1649 ifp->if_oerrors++; 1650 1651 /* XXX Resets both ports; we shouldn't do that. */ 1652 msk_reset(sc_if->sk_softc); 1653 msk_init(ifp); 1654 } 1655 } 1656 } 1657 1658 void 1659 mskc_shutdown(void *v) 1660 { 1661 struct sk_softc *sc = v; 1662 1663 DPRINTFN(2, ("msk_shutdown\n")); 1664 1665 /* Turn off the 'driver is loaded' LED. */ 1666 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1667 1668 msk_reset(sc); 1669 } 1670 1671 __inline int 1672 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1673 { 1674 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1675 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1676 YU_RXSTAT_JABBER)) != 0 || 1677 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1678 YU_RXSTAT_BYTES(stat) != len) 1679 return (0); 1680 1681 return (1); 1682 } 1683 1684 void 1685 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1686 { 1687 struct sk_softc *sc = sc_if->sk_softc; 1688 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1689 struct mbuf *m; 1690 struct sk_chain *cur_rx; 1691 int cur, total_len = len; 1692 bus_dmamap_t dmamap; 1693 1694 DPRINTFN(2, ("msk_rxeof\n")); 1695 1696 cur = sc_if->sk_cdata.sk_rx_cons; 1697 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1698 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 1699 1700 /* Sync the descriptor */ 1701 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1702 1703 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1704 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1705 1706 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1707 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1708 1709 m = cur_rx->sk_mbuf; 1710 cur_rx->sk_mbuf = NULL; 1711 1712 if (total_len < SK_MIN_FRAMELEN || 1713 total_len > SK_JUMBO_FRAMELEN || 1714 msk_rxvalid(sc, rxstat, total_len) == 0) { 1715 ifp->if_ierrors++; 1716 msk_newbuf(sc_if, cur, m, dmamap); 1717 return; 1718 } 1719 1720 /* 1721 * Try to allocate a new jumbo buffer. If that fails, copy the 1722 * packet to mbufs and put the jumbo buffer back in the ring 1723 * so it can be re-used. If allocating mbufs fails, then we 1724 * have to drop the packet. 1725 */ 1726 if (msk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1727 struct mbuf *m0; 1728 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1729 total_len + ETHER_ALIGN, 0, ifp, NULL); 1730 msk_newbuf(sc_if, cur, m, dmamap); 1731 if (m0 == NULL) { 1732 ifp->if_ierrors++; 1733 return; 1734 } 1735 m_adj(m0, ETHER_ALIGN); 1736 m = m0; 1737 } else { 1738 m->m_pkthdr.rcvif = ifp; 1739 m->m_pkthdr.len = m->m_len = total_len; 1740 } 1741 1742 ifp->if_ipackets++; 1743 1744 #if NBPFILTER > 0 1745 if (ifp->if_bpf) 1746 bpf_mtap(ifp->if_bpf, m); 1747 #endif 1748 1749 /* pass it on. */ 1750 (*ifp->if_input)(ifp, m); 1751 } 1752 1753 void 1754 msk_txeof(struct sk_if_softc *sc_if, int idx) 1755 { 1756 struct sk_softc *sc = sc_if->sk_softc; 1757 struct msk_tx_desc *cur_tx; 1758 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1759 u_int32_t sk_ctl; 1760 struct sk_txmap_entry *entry; 1761 int cons, prog; 1762 1763 DPRINTFN(2, ("msk_txeof\n")); 1764 1765 /* 1766 * Go through our tx ring and free mbufs for those 1767 * frames that have been sent. 1768 */ 1769 cons = sc_if->sk_cdata.sk_tx_cons; 1770 prog = 0; 1771 while (cons != idx) { 1772 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 1773 break; 1774 prog++; 1775 MSK_CDTXSYNC(sc_if, cons, 1, 1776 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1777 1778 cur_tx = &sc_if->sk_rdata->sk_tx_ring[cons]; 1779 sk_ctl = cur_tx->sk_ctl; 1780 #ifdef MSK_DEBUG 1781 if (mskdebug >= 2) 1782 msk_dump_txdesc(cur_tx, cons); 1783 #endif 1784 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1785 ifp->if_opackets++; 1786 if (sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf != NULL) { 1787 entry = sc_if->sk_cdata.sk_tx_map[cons]; 1788 1789 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1790 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1791 1792 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1793 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1794 link); 1795 sc_if->sk_cdata.sk_tx_map[cons] = NULL; 1796 m_freem(sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf); 1797 sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf = NULL; 1798 } 1799 sc_if->sk_cdata.sk_tx_cnt--; 1800 SK_INC(cons, MSK_TX_RING_CNT); 1801 } 1802 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1803 1804 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 1805 ifp->if_flags &= ~IFF_OACTIVE; 1806 1807 if (prog > 0) 1808 sc_if->sk_cdata.sk_tx_cons = cons; 1809 } 1810 1811 void 1812 msk_tick(void *xsc_if) 1813 { 1814 struct sk_if_softc *sc_if = xsc_if; 1815 struct mii_data *mii = &sc_if->sk_mii; 1816 1817 mii_tick(mii); 1818 callout_schedule(&sc_if->sk_tick_ch, hz); 1819 } 1820 1821 void 1822 msk_intr_yukon(struct sk_if_softc *sc_if) 1823 { 1824 u_int8_t status; 1825 1826 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1827 /* RX overrun */ 1828 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1829 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1830 SK_RFCTL_RX_FIFO_OVER); 1831 } 1832 /* TX underrun */ 1833 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1834 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 1835 SK_TFCTL_TX_FIFO_UNDER); 1836 } 1837 1838 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1839 } 1840 1841 int 1842 msk_intr(void *xsc) 1843 { 1844 struct sk_softc *sc = xsc; 1845 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1846 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1847 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1848 int claimed = 0; 1849 u_int32_t status; 1850 struct msk_status_desc *cur_st; 1851 1852 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1853 if (status == 0) { 1854 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1855 return (0); 1856 } 1857 1858 status = CSR_READ_4(sc, SK_ISR); 1859 1860 if (sc_if0 != NULL) 1861 ifp0 = &sc_if0->sk_ethercom.ec_if; 1862 if (sc_if1 != NULL) 1863 ifp1 = &sc_if1->sk_ethercom.ec_if; 1864 1865 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1866 (ifp0->if_flags & IFF_RUNNING)) { 1867 msk_intr_yukon(sc_if0); 1868 } 1869 1870 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 1871 (ifp1->if_flags & IFF_RUNNING)) { 1872 msk_intr_yukon(sc_if1); 1873 } 1874 1875 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1876 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1877 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1878 1879 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 1880 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 1881 switch (cur_st->sk_opcode) { 1882 case SK_Y2_STOPC_RXSTAT: 1883 msk_rxeof(sc->sk_if[cur_st->sk_link], 1884 letoh16(cur_st->sk_len), 1885 letoh32(cur_st->sk_status)); 1886 SK_IF_WRITE_2(sc->sk_if[cur_st->sk_link], 0, 1887 SK_RXQ1_Y2_PREF_PUTIDX, 1888 sc->sk_if[cur_st->sk_link]->sk_cdata.sk_rx_prod); 1889 break; 1890 case SK_Y2_STOPC_TXSTAT: 1891 if (sc_if0) 1892 msk_txeof(sc_if0, 1893 letoh32(cur_st->sk_status) 1894 & SK_Y2_ST_TXA1_MSKL); 1895 if (sc_if1) 1896 msk_txeof(sc_if1, 1897 ((letoh32(cur_st->sk_status) 1898 & SK_Y2_ST_TXA2_MSKL) 1899 >> SK_Y2_ST_TXA2_SHIFTL) 1900 | ((letoh16(cur_st->sk_len) & SK_Y2_ST_TXA2_MSKH) << SK_Y2_ST_TXA2_SHIFTH)); 1901 break; 1902 default: 1903 aprint_error("opcode=0x%x\n", cur_st->sk_opcode); 1904 break; 1905 } 1906 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 1907 1908 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1909 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1910 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1911 } 1912 1913 if (status & SK_Y2_IMR_BMU) { 1914 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1915 claimed = 1; 1916 } 1917 1918 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1919 1920 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 1921 msk_start(ifp0); 1922 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 1923 msk_start(ifp1); 1924 1925 #if NRND > 0 1926 if (RND_ENABLED(&sc->rnd_source)) 1927 rnd_add_uint32(&sc->rnd_source, status); 1928 #endif 1929 1930 if (sc->sk_int_mod_pending) 1931 msk_update_int_mod(sc); 1932 1933 return claimed; 1934 } 1935 1936 void 1937 msk_init_yukon(struct sk_if_softc *sc_if) 1938 { 1939 u_int32_t v; 1940 u_int16_t reg; 1941 struct sk_softc *sc; 1942 int i; 1943 1944 sc = sc_if->sk_softc; 1945 1946 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 1947 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 1948 1949 DPRINTFN(6, ("msk_init_yukon: 1\n")); 1950 1951 /* GMAC and GPHY Reset */ 1952 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1953 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1954 DELAY(1000); 1955 1956 DPRINTFN(6, ("msk_init_yukon: 2\n")); 1957 1958 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1959 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1960 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1961 1962 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 1963 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 1964 1965 DPRINTFN(6, ("msk_init_yukon: 3\n")); 1966 1967 /* unused read of the interrupt source register */ 1968 DPRINTFN(6, ("msk_init_yukon: 4\n")); 1969 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1970 1971 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 1972 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 1973 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1974 1975 /* MIB Counter Clear Mode set */ 1976 reg |= YU_PAR_MIB_CLR; 1977 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1978 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 1979 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1980 1981 /* MIB Counter Clear Mode clear */ 1982 DPRINTFN(6, ("msk_init_yukon: 5\n")); 1983 reg &= ~YU_PAR_MIB_CLR; 1984 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1985 1986 /* receive control reg */ 1987 DPRINTFN(6, ("msk_init_yukon: 7\n")); 1988 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 1989 1990 /* transmit control register */ 1991 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 1992 1993 /* transmit flow control register */ 1994 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 1995 1996 /* transmit parameter register */ 1997 DPRINTFN(6, ("msk_init_yukon: 8\n")); 1998 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 1999 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2000 2001 /* serial mode register */ 2002 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2003 reg = YU_SMR_DATA_BLIND(0x1c) | 2004 YU_SMR_MFL_VLAN | 2005 YU_SMR_IPG_DATA(0x1e); 2006 2007 if (sc->sk_type != SK_YUKON_FE) 2008 reg |= YU_SMR_MFL_JUMBO; 2009 2010 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2011 2012 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2013 /* Setup Yukon's address */ 2014 for (i = 0; i < 3; i++) { 2015 /* Write Source Address 1 (unicast filter) */ 2016 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2017 sc_if->sk_enaddr[i * 2] | 2018 sc_if->sk_enaddr[i * 2 + 1] << 8); 2019 } 2020 2021 for (i = 0; i < 3; i++) { 2022 reg = sk_win_read_2(sc_if->sk_softc, 2023 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2024 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2025 } 2026 2027 /* Set promiscuous mode */ 2028 msk_setpromisc(sc_if); 2029 2030 /* Set multicast filter */ 2031 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2032 msk_setmulti(sc_if); 2033 2034 /* enable interrupt mask for counter overflows */ 2035 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2036 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2037 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2038 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2039 2040 /* Configure RX MAC FIFO Flush Mask */ 2041 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2042 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2043 YU_RXSTAT_JABBER; 2044 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2045 2046 /* Configure RX MAC FIFO */ 2047 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2048 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2049 SK_RFCTL_FIFO_FLUSH_ON); 2050 2051 /* Increase flush threshould to 64 bytes */ 2052 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2053 SK_RFCTL_FIFO_THRESHOLD + 1); 2054 2055 /* Configure TX MAC FIFO */ 2056 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2057 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2058 2059 #if 1 2060 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2061 #endif 2062 DPRINTFN(6, ("msk_init_yukon: end\n")); 2063 } 2064 2065 /* 2066 * Note that to properly initialize any part of the GEnesis chip, 2067 * you first have to take it out of reset mode. 2068 */ 2069 int 2070 msk_init(struct ifnet *ifp) 2071 { 2072 struct sk_if_softc *sc_if = ifp->if_softc; 2073 struct sk_softc *sc = sc_if->sk_softc; 2074 struct mii_data *mii = &sc_if->sk_mii; 2075 int s; 2076 uint32_t imr, imtimer_ticks; 2077 2078 2079 DPRINTFN(2, ("msk_init\n")); 2080 2081 s = splnet(); 2082 2083 /* Cancel pending I/O and free all RX/TX buffers. */ 2084 msk_stop(ifp,0); 2085 2086 /* Configure I2C registers */ 2087 2088 /* Configure XMAC(s) */ 2089 msk_init_yukon(sc_if); 2090 mii_mediachg(mii); 2091 2092 /* Configure transmit arbiter(s) */ 2093 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2094 #if 0 2095 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2096 #endif 2097 2098 /* Configure RAMbuffers */ 2099 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2100 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2101 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2102 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2103 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2104 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2105 2106 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2107 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2108 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2109 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2110 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2111 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2112 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2113 2114 /* Configure BMUs */ 2115 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2116 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2117 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2118 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2119 2120 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2121 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2122 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2123 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2124 2125 /* Make sure the sync transmit queue is disabled. */ 2126 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2127 2128 /* Init descriptors */ 2129 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2130 aprint_error("%s: initialization failed: no " 2131 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2132 msk_stop(ifp,0); 2133 splx(s); 2134 return ENOBUFS; 2135 } 2136 2137 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2138 aprint_error("%s: initialization failed: no " 2139 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2140 msk_stop(ifp,0); 2141 splx(s); 2142 return ENOBUFS; 2143 } 2144 2145 /* Set interrupt moderation if changed via sysctl. */ 2146 switch (sc->sk_type) { 2147 case SK_YUKON_EC: 2148 case SK_YUKON_EC_U: 2149 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2150 break; 2151 case SK_YUKON_FE: 2152 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2153 break; 2154 case SK_YUKON_XL: 2155 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2156 break; 2157 default: 2158 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2159 } 2160 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2161 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2162 sk_win_write_4(sc, SK_IMTIMERINIT, 2163 SK_IM_USECS(sc->sk_int_mod)); 2164 aprint_verbose("%s: interrupt moderation is %d us\n", 2165 sc->sk_dev.dv_xname, sc->sk_int_mod); 2166 } 2167 2168 /* Initialize prefetch engine. */ 2169 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2170 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2171 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2172 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2173 MSK_RX_RING_ADDR(sc_if, 0)); 2174 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2175 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2176 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2177 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2178 2179 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2180 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2181 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2182 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2183 MSK_TX_RING_ADDR(sc_if, 0)); 2184 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2185 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2186 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2187 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2188 2189 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2190 sc_if->sk_cdata.sk_rx_prod); 2191 2192 /* Configure interrupt handling */ 2193 if (sc_if->sk_port == SK_PORT_A) 2194 sc->sk_intrmask |= SK_Y2_INTRS1; 2195 else 2196 sc->sk_intrmask |= SK_Y2_INTRS2; 2197 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2198 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2199 2200 ifp->if_flags |= IFF_RUNNING; 2201 ifp->if_flags &= ~IFF_OACTIVE; 2202 2203 callout_schedule(&sc_if->sk_tick_ch, hz); 2204 2205 splx(s); 2206 return 0; 2207 } 2208 2209 void 2210 msk_stop(struct ifnet *ifp, int disable) 2211 { 2212 struct sk_if_softc *sc_if = ifp->if_softc; 2213 struct sk_softc *sc = sc_if->sk_softc; 2214 struct sk_txmap_entry *dma; 2215 int i; 2216 2217 DPRINTFN(2, ("msk_stop\n")); 2218 2219 callout_stop(&sc_if->sk_tick_ch); 2220 2221 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2222 2223 /* Stop transfer of Tx descriptors */ 2224 2225 /* Stop transfer of Rx descriptors */ 2226 2227 /* Turn off various components of this interface. */ 2228 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2229 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2230 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2231 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2232 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2233 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2234 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2235 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2236 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2237 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2238 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2239 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2240 2241 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2242 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2243 2244 /* Disable interrupts */ 2245 if (sc_if->sk_port == SK_PORT_A) 2246 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2247 else 2248 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2249 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2250 2251 SK_XM_READ_2(sc_if, XM_ISR); 2252 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2253 2254 /* Free RX and TX mbufs still in the queues. */ 2255 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2256 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2257 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2258 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2259 } 2260 } 2261 2262 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2263 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2264 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2265 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2266 #if 1 2267 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2268 sc_if->sk_cdata.sk_tx_map[i], link); 2269 sc_if->sk_cdata.sk_tx_map[i] = 0; 2270 #endif 2271 } 2272 } 2273 2274 #if 1 2275 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2276 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2277 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2278 free(dma, M_DEVBUF); 2279 } 2280 #endif 2281 } 2282 2283 CFATTACH_DECL(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2284 NULL, NULL); 2285 2286 CFATTACH_DECL(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2287 NULL, NULL); 2288 2289 #ifdef MSK_DEBUG 2290 void 2291 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2292 { 2293 #define DESC_PRINT(X) \ 2294 if (X) \ 2295 printf("txdesc[%d]." #X "=%#x\n", \ 2296 idx, X); 2297 2298 DESC_PRINT(letoh32(le->sk_addr)); 2299 DESC_PRINT(letoh16(le->sk_len)); 2300 DESC_PRINT(le->sk_ctl); 2301 DESC_PRINT(le->sk_opcode); 2302 #undef DESC_PRINT 2303 } 2304 2305 void 2306 msk_dump_bytes(const char *data, int len) 2307 { 2308 int c, i, j; 2309 2310 for (i = 0; i < len; i += 16) { 2311 printf("%08x ", i); 2312 c = len - i; 2313 if (c > 16) c = 16; 2314 2315 for (j = 0; j < c; j++) { 2316 printf("%02x ", data[i + j] & 0xff); 2317 if ((j & 0xf) == 7 && j > 0) 2318 printf(" "); 2319 } 2320 2321 for (; j < 16; j++) 2322 printf(" "); 2323 printf(" "); 2324 2325 for (j = 0; j < c; j++) { 2326 int ch = data[i + j] & 0xff; 2327 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2328 } 2329 2330 printf("\n"); 2331 2332 if (c < 16) 2333 break; 2334 } 2335 } 2336 2337 void 2338 msk_dump_mbuf(struct mbuf *m) 2339 { 2340 int count = m->m_pkthdr.len; 2341 2342 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2343 2344 while (count > 0 && m) { 2345 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2346 m, m->m_data, m->m_len); 2347 msk_dump_bytes(mtod(m, char *), m->m_len); 2348 2349 count -= m->m_len; 2350 m = m->m_next; 2351 } 2352 } 2353 #endif 2354 2355 static int 2356 msk_sysctl_handler(SYSCTLFN_ARGS) 2357 { 2358 int error, t; 2359 struct sysctlnode node; 2360 struct sk_softc *sc; 2361 2362 node = *rnode; 2363 sc = node.sysctl_data; 2364 t = sc->sk_int_mod; 2365 node.sysctl_data = &t; 2366 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2367 if (error || newp == NULL) 2368 return error; 2369 2370 if (t < SK_IM_MIN || t > SK_IM_MAX) 2371 return EINVAL; 2372 2373 /* update the softc with sysctl-changed value, and mark 2374 for hardware update */ 2375 sc->sk_int_mod = t; 2376 sc->sk_int_mod_pending = 1; 2377 return 0; 2378 } 2379 2380 /* 2381 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 2382 * set up in skc_attach() 2383 */ 2384 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2385 { 2386 int rc; 2387 const struct sysctlnode *node; 2388 2389 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 2390 0, CTLTYPE_NODE, "hw", NULL, 2391 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 2392 goto err; 2393 } 2394 2395 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2396 0, CTLTYPE_NODE, "msk", 2397 SYSCTL_DESCR("msk interface controls"), 2398 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2399 goto err; 2400 } 2401 2402 msk_root_num = node->sysctl_num; 2403 return; 2404 2405 err: 2406 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2407 } 2408
Indexes created Thu Oct 02 07:10:07 GMT 2025