if_msk.c revision 1.90
1 /* $NetBSD: if_msk.c,v 1.90 2019/05/28 07:41:49 msaitoh Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.79 2009/10/15 17:54:56 deraadt Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.90 2019/05/28 07:41:49 msaitoh Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/mutex.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/device.h> 66 #include <sys/queue.h> 67 #include <sys/callout.h> 68 #include <sys/sysctl.h> 69 #include <sys/endian.h> 70 #ifdef __NetBSD__ 71 #define letoh16 htole16 72 #define letoh32 htole32 73 #endif 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #include <net/if_media.h> 80 81 #include <net/bpf.h> 82 #include <sys/rndsource.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 #include <dev/mii/brgphyreg.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 92 #include <dev/pci/if_skreg.h> 93 #include <dev/pci/if_mskvar.h> 94 95 int mskc_probe(device_t, cfdata_t, void *); 96 void mskc_attach(device_t, device_t, void *); 97 int mskc_detach(device_t, int); 98 void mskc_reset(struct sk_softc *); 99 static bool mskc_suspend(device_t, const pmf_qual_t *); 100 static bool mskc_resume(device_t, const pmf_qual_t *); 101 int msk_probe(device_t, cfdata_t, void *); 102 void msk_attach(device_t, device_t, void *); 103 int msk_detach(device_t, int); 104 void msk_reset(struct sk_if_softc *); 105 int mskcprint(void *, const char *); 106 int msk_intr(void *); 107 void msk_intr_yukon(struct sk_if_softc *); 108 void msk_rxeof(struct sk_if_softc *, uint16_t, uint32_t); 109 void msk_txeof(struct sk_if_softc *); 110 int msk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 111 void msk_start(struct ifnet *); 112 int msk_ioctl(struct ifnet *, u_long, void *); 113 int msk_init(struct ifnet *); 114 void msk_init_yukon(struct sk_if_softc *); 115 void msk_stop(struct ifnet *, int); 116 void msk_watchdog(struct ifnet *); 117 int msk_newbuf(struct sk_if_softc *, bus_dmamap_t); 118 int msk_alloc_jumbo_mem(struct sk_if_softc *); 119 void *msk_jalloc(struct sk_if_softc *); 120 void msk_jfree(struct mbuf *, void *, size_t, void *); 121 int msk_init_rx_ring(struct sk_if_softc *); 122 int msk_init_tx_ring(struct sk_if_softc *); 123 void msk_fill_rx_ring(struct sk_if_softc *); 124 125 void msk_update_int_mod(struct sk_softc *, int); 126 127 int msk_miibus_readreg(device_t, int, int, uint16_t *); 128 int msk_miibus_writereg(device_t, int, int, uint16_t); 129 void msk_miibus_statchg(struct ifnet *); 130 131 void msk_setmulti(struct sk_if_softc *); 132 void msk_setpromisc(struct sk_if_softc *); 133 void msk_tick(void *); 134 static void msk_fill_rx_tick(void *); 135 136 /* #define MSK_DEBUG 1 */ 137 #ifdef MSK_DEBUG 138 #define DPRINTF(x) if (mskdebug) printf x 139 #define DPRINTFN(n, x) if (mskdebug >= (n)) printf x 140 int mskdebug = MSK_DEBUG; 141 142 void msk_dump_txdesc(struct msk_tx_desc *, int); 143 void msk_dump_mbuf(struct mbuf *); 144 void msk_dump_bytes(const char *, int); 145 #else 146 #define DPRINTF(x) 147 #define DPRINTFN(n, x) 148 #endif 149 150 static int msk_sysctl_handler(SYSCTLFN_PROTO); 151 static int msk_root_num; 152 153 #define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL) 154 #define MSK_ADDR_HI(x) ((uint64_t) (x) >> 32) 155 156 /* supported device vendors */ 157 static const struct msk_product { 158 pci_vendor_id_t msk_vendor; 159 pci_product_id_t msk_product; 160 } msk_products[] = { 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 163 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 164 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8079 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 197 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 198 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 199 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 200 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 201 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 }, 202 { 0, 0 } 203 }; 204 205 static inline uint32_t 206 sk_win_read_4(struct sk_softc *sc, uint32_t reg) 207 { 208 return CSR_READ_4(sc, reg); 209 } 210 211 static inline uint16_t 212 sk_win_read_2(struct sk_softc *sc, uint32_t reg) 213 { 214 return CSR_READ_2(sc, reg); 215 } 216 217 static inline uint8_t 218 sk_win_read_1(struct sk_softc *sc, uint32_t reg) 219 { 220 return CSR_READ_1(sc, reg); 221 } 222 223 static inline void 224 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x) 225 { 226 CSR_WRITE_4(sc, reg, x); 227 } 228 229 static inline void 230 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x) 231 { 232 CSR_WRITE_2(sc, reg, x); 233 } 234 235 static inline void 236 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x) 237 { 238 CSR_WRITE_1(sc, reg, x); 239 } 240 241 int 242 msk_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 243 { 244 struct sk_if_softc *sc_if = device_private(dev); 245 uint16_t data; 246 int i; 247 248 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 249 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 250 251 for (i = 0; i < SK_TIMEOUT; i++) { 252 DELAY(1); 253 data = SK_YU_READ_2(sc_if, YUKON_SMICR); 254 if (data & YU_SMICR_READ_VALID) 255 break; 256 } 257 258 if (i == SK_TIMEOUT) { 259 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 260 return ETIMEDOUT; 261 } 262 263 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, SK_TIMEOUT)); 264 265 *val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 266 267 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#hx\n", 268 phy, reg, *val)); 269 270 return 0; 271 } 272 273 int 274 msk_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 275 { 276 struct sk_if_softc *sc_if = device_private(dev); 277 int i; 278 279 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#hx\n", 280 phy, reg, val)); 281 282 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 283 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 284 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 285 286 for (i = 0; i < SK_TIMEOUT; i++) { 287 DELAY(1); 288 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 289 break; 290 } 291 292 if (i == SK_TIMEOUT) { 293 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 294 return ETIMEDOUT; 295 } 296 297 return 0; 298 } 299 300 void 301 msk_miibus_statchg(struct ifnet *ifp) 302 { 303 struct sk_if_softc *sc_if = ifp->if_softc; 304 struct mii_data *mii = &sc_if->sk_mii; 305 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 306 int gpcr; 307 308 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 309 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 310 311 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 312 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 313 /* Set speed. */ 314 gpcr |= YU_GPCR_SPEED_DIS; 315 switch (IFM_SUBTYPE(mii->mii_media_active)) { 316 case IFM_1000_SX: 317 case IFM_1000_LX: 318 case IFM_1000_CX: 319 case IFM_1000_T: 320 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 321 break; 322 case IFM_100_TX: 323 gpcr |= YU_GPCR_SPEED; 324 break; 325 } 326 327 /* Set duplex. */ 328 gpcr |= YU_GPCR_DPLX_DIS; 329 if ((mii->mii_media_active & IFM_FDX) != 0) 330 gpcr |= YU_GPCR_DUPLEX; 331 332 /* Disable flow control. */ 333 gpcr |= YU_GPCR_FCTL_DIS; 334 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 335 } 336 337 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 338 339 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 340 SK_YU_READ_2(sc_if, YUKON_GPCR))); 341 } 342 343 void 344 msk_setmulti(struct sk_if_softc *sc_if) 345 { 346 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 347 uint32_t hashes[2] = { 0, 0 }; 348 int h; 349 struct ethercom *ec = &sc_if->sk_ethercom; 350 struct ether_multi *enm; 351 struct ether_multistep step; 352 uint16_t reg; 353 354 /* First, zot all the existing filters. */ 355 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 356 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 357 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 358 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 359 360 361 /* Now program new ones. */ 362 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 363 reg |= YU_RCR_UFLEN; 364 allmulti: 365 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 366 if ((ifp->if_flags & IFF_PROMISC) != 0) 367 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 368 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 369 hashes[0] = 0xFFFFFFFF; 370 hashes[1] = 0xFFFFFFFF; 371 } 372 } else { 373 /* First find the tail of the list. */ 374 ETHER_LOCK(ec); 375 ETHER_FIRST_MULTI(step, ec, enm); 376 while (enm != NULL) { 377 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 378 ETHER_ADDR_LEN)) { 379 ifp->if_flags |= IFF_ALLMULTI; 380 ETHER_UNLOCK(ec); 381 goto allmulti; 382 } 383 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 384 ((1 << SK_HASH_BITS) - 1); 385 if (h < 32) 386 hashes[0] |= (1 << h); 387 else 388 hashes[1] |= (1 << (h - 32)); 389 390 ETHER_NEXT_MULTI(step, enm); 391 } 392 ETHER_UNLOCK(ec); 393 reg |= YU_RCR_MUFLEN; 394 } 395 396 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 397 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 398 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 399 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 400 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 401 } 402 403 void 404 msk_setpromisc(struct sk_if_softc *sc_if) 405 { 406 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 407 408 if (ifp->if_flags & IFF_PROMISC) 409 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 410 YU_RCR_UFLEN | YU_RCR_MUFLEN); 411 else 412 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 413 YU_RCR_UFLEN | YU_RCR_MUFLEN); 414 } 415 416 int 417 msk_init_rx_ring(struct sk_if_softc *sc_if) 418 { 419 struct msk_chain_data *cd = &sc_if->sk_cdata; 420 struct msk_ring_data *rd = sc_if->sk_rdata; 421 struct msk_rx_desc *r; 422 int i, nexti; 423 424 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 425 426 for (i = 0; i < MSK_RX_RING_CNT; i++) { 427 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 428 if (i == (MSK_RX_RING_CNT - 1)) 429 nexti = 0; 430 else 431 nexti = i + 1; 432 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 433 } 434 435 sc_if->sk_cdata.sk_rx_prod = 0; 436 sc_if->sk_cdata.sk_rx_cons = 0; 437 sc_if->sk_cdata.sk_rx_cnt = 0; 438 sc_if->sk_cdata.sk_rx_hiaddr = 0; 439 440 /* Mark the first ring element to initialize the high address. */ 441 sc_if->sk_cdata.sk_rx_hiaddr = 0; 442 r = &rd->sk_rx_ring[cd->sk_rx_prod]; 443 r->sk_addr = htole32(cd->sk_rx_hiaddr); 444 r->sk_len = 0; 445 r->sk_ctl = 0; 446 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN; 447 MSK_CDRXSYNC(sc_if, cd->sk_rx_prod, 448 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 449 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 450 sc_if->sk_cdata.sk_rx_cnt++; 451 452 msk_fill_rx_ring(sc_if); 453 return 0; 454 } 455 456 int 457 msk_init_tx_ring(struct sk_if_softc *sc_if) 458 { 459 struct sk_softc *sc = sc_if->sk_softc; 460 struct msk_chain_data *cd = &sc_if->sk_cdata; 461 struct msk_ring_data *rd = sc_if->sk_rdata; 462 struct msk_tx_desc *t; 463 bus_dmamap_t dmamap; 464 struct sk_txmap_entry *entry; 465 int i, nexti; 466 467 memset(rd->sk_tx_ring, 0, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 468 469 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 470 for (i = 0; i < MSK_TX_RING_CNT; i++) { 471 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 472 if (i == (MSK_TX_RING_CNT - 1)) 473 nexti = 0; 474 else 475 nexti = i + 1; 476 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 477 478 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 479 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 480 return ENOBUFS; 481 482 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 483 if (!entry) { 484 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 485 return ENOBUFS; 486 } 487 entry->dmamap = dmamap; 488 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 489 } 490 491 sc_if->sk_cdata.sk_tx_prod = 0; 492 sc_if->sk_cdata.sk_tx_cons = 0; 493 sc_if->sk_cdata.sk_tx_cnt = 0; 494 sc_if->sk_cdata.sk_tx_hiaddr = 0; 495 496 /* Mark the first ring element to initialize the high address. */ 497 sc_if->sk_cdata.sk_tx_hiaddr = 0; 498 t = &rd->sk_tx_ring[cd->sk_tx_prod]; 499 t->sk_addr = htole32(cd->sk_tx_hiaddr); 500 t->sk_len = 0; 501 t->sk_ctl = 0; 502 t->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 503 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 504 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 505 SK_INC(sc_if->sk_cdata.sk_tx_prod, MSK_TX_RING_CNT); 506 sc_if->sk_cdata.sk_tx_cnt++; 507 508 return 0; 509 } 510 511 int 512 msk_newbuf(struct sk_if_softc *sc_if, bus_dmamap_t dmamap) 513 { 514 struct mbuf *m_new = NULL; 515 struct sk_chain *c; 516 struct msk_rx_desc *r; 517 void *buf = NULL; 518 bus_addr_t addr; 519 520 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 521 if (m_new == NULL) 522 return ENOBUFS; 523 524 /* Allocate the jumbo buffer */ 525 buf = msk_jalloc(sc_if); 526 if (buf == NULL) { 527 m_freem(m_new); 528 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 529 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 530 return ENOBUFS; 531 } 532 533 /* Attach the buffer to the mbuf */ 534 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 535 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 536 537 m_adj(m_new, ETHER_ALIGN); 538 539 addr = dmamap->dm_segs[0].ds_addr + 540 ((vaddr_t)m_new->m_data - 541 (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf); 542 543 if (sc_if->sk_cdata.sk_rx_hiaddr != MSK_ADDR_HI(addr)) { 544 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 545 r = c->sk_le; 546 c->sk_mbuf = NULL; 547 r->sk_addr = htole32(MSK_ADDR_HI(addr)); 548 r->sk_len = 0; 549 r->sk_ctl = 0; 550 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN; 551 sc_if->sk_cdata.sk_rx_hiaddr = MSK_ADDR_HI(addr); 552 553 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 554 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 555 556 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 557 sc_if->sk_cdata.sk_rx_cnt++; 558 559 DPRINTFN(10, ("%s: rx ADDR64: %#x\n", 560 sc_if->sk_ethercom.ec_if.if_xname, 561 (unsigned)MSK_ADDR_HI(addr))); 562 } 563 564 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 565 r = c->sk_le; 566 c->sk_mbuf = m_new; 567 r->sk_addr = htole32(MSK_ADDR_LO(addr)); 568 r->sk_len = htole16(SK_JLEN); 569 r->sk_ctl = 0; 570 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 571 572 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 573 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 574 575 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 576 sc_if->sk_cdata.sk_rx_cnt++; 577 578 return 0; 579 } 580 581 /* 582 * Memory management for jumbo frames. 583 */ 584 585 int 586 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 587 { 588 struct sk_softc *sc = sc_if->sk_softc; 589 char *ptr, *kva; 590 int i, state, error; 591 struct sk_jpool_entry *entry; 592 593 state = error = 0; 594 595 /* Grab a big chunk o' storage. */ 596 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 597 &sc_if->sk_cdata.sk_jumbo_seg, 1, &sc_if->sk_cdata.sk_jumbo_nseg, 598 BUS_DMA_NOWAIT)) { 599 aprint_error(": can't alloc rx buffers"); 600 return ENOBUFS; 601 } 602 603 state = 1; 604 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 605 sc_if->sk_cdata.sk_jumbo_nseg, MSK_JMEM, (void **)&kva, 606 BUS_DMA_NOWAIT)) { 607 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 608 error = ENOBUFS; 609 goto out; 610 } 611 612 state = 2; 613 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 614 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 615 aprint_error(": can't create dma map"); 616 error = ENOBUFS; 617 goto out; 618 } 619 620 state = 3; 621 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 622 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 623 aprint_error(": can't load dma map"); 624 error = ENOBUFS; 625 goto out; 626 } 627 628 state = 4; 629 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 630 DPRINTFN(1,("msk_jumbo_buf = %p\n", 631 (void *)sc_if->sk_cdata.sk_jumbo_buf)); 632 633 LIST_INIT(&sc_if->sk_jfree_listhead); 634 LIST_INIT(&sc_if->sk_jinuse_listhead); 635 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 636 637 /* 638 * Now divide it up into 9K pieces and save the addresses 639 * in an array. 640 */ 641 ptr = sc_if->sk_cdata.sk_jumbo_buf; 642 for (i = 0; i < MSK_JSLOTS; i++) { 643 sc_if->sk_cdata.sk_jslots[i] = ptr; 644 ptr += SK_JLEN; 645 entry = malloc(sizeof(struct sk_jpool_entry), 646 M_DEVBUF, M_NOWAIT); 647 if (entry == NULL) { 648 sc_if->sk_cdata.sk_jumbo_buf = NULL; 649 aprint_error(": no memory for jumbo buffer queue!"); 650 error = ENOBUFS; 651 goto out; 652 } 653 entry->slot = i; 654 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 655 entry, jpool_entries); 656 } 657 out: 658 if (error != 0) { 659 switch (state) { 660 case 4: 661 bus_dmamap_unload(sc->sc_dmatag, 662 sc_if->sk_cdata.sk_rx_jumbo_map); 663 /* FALLTHROUGH */ 664 case 3: 665 bus_dmamap_destroy(sc->sc_dmatag, 666 sc_if->sk_cdata.sk_rx_jumbo_map); 667 /* FALLTHROUGH */ 668 case 2: 669 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 670 /* FALLTHROUGH */ 671 case 1: 672 bus_dmamem_free(sc->sc_dmatag, 673 &sc_if->sk_cdata.sk_jumbo_seg, 674 sc_if->sk_cdata.sk_jumbo_nseg); 675 break; 676 default: 677 break; 678 } 679 } 680 681 return error; 682 } 683 684 static void 685 msk_free_jumbo_mem(struct sk_if_softc *sc_if) 686 { 687 struct sk_softc *sc = sc_if->sk_softc; 688 689 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 690 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 691 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_cdata.sk_jumbo_buf, MSK_JMEM); 692 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 693 sc_if->sk_cdata.sk_jumbo_nseg); 694 } 695 696 /* 697 * Allocate a jumbo buffer. 698 */ 699 void * 700 msk_jalloc(struct sk_if_softc *sc_if) 701 { 702 struct sk_jpool_entry *entry; 703 704 mutex_enter(&sc_if->sk_jpool_mtx); 705 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 706 707 if (entry == NULL) { 708 mutex_exit(&sc_if->sk_jpool_mtx); 709 return NULL; 710 } 711 712 LIST_REMOVE(entry, jpool_entries); 713 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 714 mutex_exit(&sc_if->sk_jpool_mtx); 715 return sc_if->sk_cdata.sk_jslots[entry->slot]; 716 } 717 718 /* 719 * Release a jumbo buffer. 720 */ 721 void 722 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 723 { 724 struct sk_jpool_entry *entry; 725 struct sk_if_softc *sc; 726 int i; 727 728 /* Extract the softc struct pointer. */ 729 sc = (struct sk_if_softc *)arg; 730 731 if (sc == NULL) 732 panic("msk_jfree: can't find softc pointer!"); 733 734 /* calculate the slot this buffer belongs to */ 735 i = ((vaddr_t)buf 736 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 737 738 if ((i < 0) || (i >= MSK_JSLOTS)) 739 panic("msk_jfree: asked to free buffer that we don't manage!"); 740 741 mutex_enter(&sc->sk_jpool_mtx); 742 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 743 if (entry == NULL) 744 panic("msk_jfree: buffer not in use!"); 745 entry->slot = i; 746 LIST_REMOVE(entry, jpool_entries); 747 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 748 mutex_exit(&sc->sk_jpool_mtx); 749 750 if (__predict_true(m != NULL)) 751 pool_cache_put(mb_cache, m); 752 753 /* Now that we know we have a free RX buffer, refill if running out */ 754 if ((sc->sk_ethercom.ec_if.if_flags & IFF_RUNNING) != 0 755 && sc->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 756 callout_schedule(&sc->sk_tick_rx, 0); 757 } 758 759 int 760 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 761 { 762 struct sk_if_softc *sc = ifp->if_softc; 763 int s, error; 764 765 s = splnet(); 766 767 DPRINTFN(2, ("msk_ioctl ETHER cmd %lx\n", cmd)); 768 switch (cmd) { 769 case SIOCSIFFLAGS: 770 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 771 break; 772 773 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 774 case IFF_RUNNING: 775 msk_stop(ifp, 1); 776 break; 777 case IFF_UP: 778 msk_init(ifp); 779 break; 780 case IFF_UP | IFF_RUNNING: 781 if ((ifp->if_flags ^ sc->sk_if_flags) == IFF_PROMISC) { 782 msk_setpromisc(sc); 783 msk_setmulti(sc); 784 } else 785 msk_init(ifp); 786 break; 787 } 788 sc->sk_if_flags = ifp->if_flags; 789 break; 790 default: 791 error = ether_ioctl(ifp, cmd, data); 792 if (error == ENETRESET) { 793 error = 0; 794 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 795 ; 796 else if (ifp->if_flags & IFF_RUNNING) { 797 /* 798 * Multicast list has changed; set the hardware 799 * filter accordingly. 800 */ 801 msk_setmulti(sc); 802 } 803 } 804 break; 805 } 806 807 splx(s); 808 return error; 809 } 810 811 void 812 msk_update_int_mod(struct sk_softc *sc, int verbose) 813 { 814 uint32_t imtimer_ticks; 815 816 /* 817 * Configure interrupt moderation. The moderation timer 818 * defers interrupts specified in the interrupt moderation 819 * timer mask based on the timeout specified in the interrupt 820 * moderation timer init register. Each bit in the timer 821 * register represents one tick, so to specify a timeout in 822 * microseconds, we have to multiply by the correct number of 823 * ticks-per-microsecond. 824 */ 825 switch (sc->sk_type) { 826 case SK_YUKON_EC: 827 case SK_YUKON_EC_U: 828 case SK_YUKON_EX: 829 case SK_YUKON_SUPR: 830 case SK_YUKON_ULTRA2: 831 case SK_YUKON_OPTIMA: 832 case SK_YUKON_PRM: 833 case SK_YUKON_OPTIMA2: 834 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 835 break; 836 case SK_YUKON_FE: 837 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 838 break; 839 case SK_YUKON_FE_P: 840 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 841 break; 842 case SK_YUKON_XL: 843 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 844 break; 845 default: 846 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 847 } 848 if (verbose) 849 aprint_verbose_dev(sc->sk_dev, 850 "interrupt moderation is %d us\n", sc->sk_int_mod); 851 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 852 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF | SK_ISR_TX2_S_EOF | 853 SK_ISR_RX1_EOF | SK_ISR_RX2_EOF); 854 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 855 sc->sk_int_mod_pending = 0; 856 } 857 858 static int 859 msk_lookup(const struct pci_attach_args *pa) 860 { 861 const struct msk_product *pmsk; 862 863 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 864 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 865 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 866 return 1; 867 } 868 return 0; 869 } 870 871 /* 872 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 873 * IDs against our list and return a device name if we find a match. 874 */ 875 int 876 mskc_probe(device_t parent, cfdata_t match, void *aux) 877 { 878 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 879 880 return msk_lookup(pa); 881 } 882 883 /* 884 * Force the GEnesis into reset, then bring it out of reset. 885 */ 886 void 887 mskc_reset(struct sk_softc *sc) 888 { 889 uint32_t imtimer_ticks, reg1; 890 int reg; 891 892 DPRINTFN(2, ("mskc_reset\n")); 893 894 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 895 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 896 897 DELAY(1000); 898 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 899 DELAY(2); 900 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 901 sk_win_write_1(sc, SK_TESTCTL1, 2); 902 903 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 904 sc->sk_type >= SK_YUKON_FE_P) { 905 uint32_t our; 906 907 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 908 909 /* enable all clocks. */ 910 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 911 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 912 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST | 913 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN | 914 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY | 915 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 916 /* Set all bits to 0 except bits 15..12 */ 917 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 918 /* Set to default value */ 919 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 920 921 /* 922 * Disable status race, workaround for Yukon EC Ultra & 923 * Yukon EX. 924 */ 925 reg1 = sk_win_read_4(sc, SK_GPIO); 926 reg1 |= SK_Y2_GPIO_STAT_RACE_DIS; 927 sk_win_write_4(sc, SK_GPIO, reg1); 928 sk_win_read_4(sc, SK_GPIO); 929 } 930 931 /* release PHY from PowerDown/Coma mode. */ 932 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 933 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 934 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 935 else 936 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 937 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 938 939 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 940 sk_win_write_1(sc, SK_Y2_CLKGATE, 941 SK_Y2_CLKGATE_LINK1_GATE_DIS | 942 SK_Y2_CLKGATE_LINK2_GATE_DIS | 943 SK_Y2_CLKGATE_LINK1_CORE_DIS | 944 SK_Y2_CLKGATE_LINK2_CORE_DIS | 945 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 946 else 947 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 948 949 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 950 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 951 DELAY(1000); 952 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 953 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 954 955 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 956 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 957 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 958 } 959 960 sk_win_write_1(sc, SK_TESTCTL1, 1); 961 962 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 963 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 964 CSR_READ_2(sc, SK_LINK_CTRL))); 965 966 /* Disable ASF */ 967 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 968 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 969 970 /* Clear I2C IRQ noise */ 971 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 972 973 /* Disable hardware timer */ 974 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 975 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 976 977 /* Disable descriptor polling */ 978 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 979 980 /* Disable time stamps */ 981 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 982 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 983 984 /* Enable RAM interface */ 985 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 986 for (reg = SK_TO0;reg <= SK_TO11; reg++) 987 sk_win_write_1(sc, reg, 36); 988 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 989 for (reg = SK_TO0;reg <= SK_TO11; reg++) 990 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 991 992 /* 993 * Configure interrupt moderation. The moderation timer 994 * defers interrupts specified in the interrupt moderation 995 * timer mask based on the timeout specified in the interrupt 996 * moderation timer init register. Each bit in the timer 997 * register represents one tick, so to specify a timeout in 998 * microseconds, we have to multiply by the correct number of 999 * ticks-per-microsecond. 1000 */ 1001 switch (sc->sk_type) { 1002 case SK_YUKON_EC: 1003 case SK_YUKON_EC_U: 1004 case SK_YUKON_EX: 1005 case SK_YUKON_SUPR: 1006 case SK_YUKON_ULTRA2: 1007 case SK_YUKON_OPTIMA: 1008 case SK_YUKON_PRM: 1009 case SK_YUKON_OPTIMA2: 1010 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1011 break; 1012 case SK_YUKON_FE: 1013 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 1014 break; 1015 case SK_YUKON_FE_P: 1016 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 1017 break; 1018 case SK_YUKON_XL: 1019 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 1020 break; 1021 default: 1022 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1023 break; 1024 } 1025 1026 /* Reset status ring. */ 1027 memset(sc->sk_status_ring, 0, 1028 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1029 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 1030 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1031 sc->sk_status_idx = 0; 1032 1033 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 1034 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 1035 1036 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 1037 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 1038 MSK_ADDR_LO(sc->sk_status_map->dm_segs[0].ds_addr)); 1039 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 1040 MSK_ADDR_HI(sc->sk_status_map->dm_segs[0].ds_addr)); 1041 if (sc->sk_type == SK_YUKON_EC && 1042 sc->sk_rev == SK_YUKON_EC_REV_A1) { 1043 /* WA for dev. #4.3 */ 1044 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 1045 SK_STAT_BMU_TXTHIDX_MSK); 1046 /* WA for dev. #4.18 */ 1047 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 1048 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 1049 } else { 1050 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 1051 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 1052 if (sc->sk_type == SK_YUKON_XL) 1053 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x04); 1054 else 1055 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x10); 1056 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 1057 } 1058 1059 #if 0 1060 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 1061 #endif 1062 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 1063 1064 /* Enable status unit. */ 1065 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 1066 1067 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 1068 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 1069 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 1070 1071 msk_update_int_mod(sc, 0); 1072 } 1073 1074 int 1075 msk_probe(device_t parent, cfdata_t match, void *aux) 1076 { 1077 struct skc_attach_args *sa = aux; 1078 1079 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1080 return 0; 1081 1082 switch (sa->skc_type) { 1083 case SK_YUKON_XL: 1084 case SK_YUKON_EC_U: 1085 case SK_YUKON_EX: 1086 case SK_YUKON_EC: 1087 case SK_YUKON_FE: 1088 case SK_YUKON_FE_P: 1089 case SK_YUKON_SUPR: 1090 case SK_YUKON_ULTRA2: 1091 case SK_YUKON_OPTIMA: 1092 case SK_YUKON_PRM: 1093 case SK_YUKON_OPTIMA2: 1094 return 1; 1095 } 1096 1097 return 0; 1098 } 1099 1100 void 1101 msk_reset(struct sk_if_softc *sc_if) 1102 { 1103 /* GMAC and GPHY Reset */ 1104 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1105 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1106 DELAY(1000); 1107 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1108 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1109 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1110 } 1111 1112 static bool 1113 msk_resume(device_t dv, const pmf_qual_t *qual) 1114 { 1115 struct sk_if_softc *sc_if = device_private(dv); 1116 1117 msk_init_yukon(sc_if); 1118 return true; 1119 } 1120 1121 /* 1122 * Each XMAC chip is attached as a separate logical IP interface. 1123 * Single port cards will have only one logical interface of course. 1124 */ 1125 void 1126 msk_attach(device_t parent, device_t self, void *aux) 1127 { 1128 struct sk_if_softc *sc_if = device_private(self); 1129 struct sk_softc *sc = device_private(parent); 1130 struct skc_attach_args *sa = aux; 1131 struct ifnet *ifp; 1132 struct mii_data * const mii = &sc_if->sk_mii; 1133 void *kva; 1134 int i; 1135 uint32_t chunk; 1136 int mii_flags; 1137 1138 sc_if->sk_dev = self; 1139 sc_if->sk_port = sa->skc_port; 1140 sc_if->sk_softc = sc; 1141 sc->sk_if[sa->skc_port] = sc_if; 1142 1143 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1144 1145 /* 1146 * Get station address for this interface. Note that 1147 * dual port cards actually come with three station 1148 * addresses: one for each port, plus an extra. The 1149 * extra one is used by the SysKonnect driver software 1150 * as a 'virtual' station address for when both ports 1151 * are operating in failover mode. Currently we don't 1152 * use this extra address. 1153 */ 1154 for (i = 0; i < ETHER_ADDR_LEN; i++) 1155 sc_if->sk_enaddr[i] = 1156 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1157 1158 aprint_normal(": Ethernet address %s\n", 1159 ether_sprintf(sc_if->sk_enaddr)); 1160 1161 /* 1162 * Set up RAM buffer addresses. The Yukon2 has a small amount 1163 * of SRAM on it, somewhere between 4K and 48K. We need to 1164 * divide this up between the transmitter and receiver. We 1165 * give the receiver 2/3 of the memory (rounded down), and the 1166 * transmitter whatever remains. 1167 */ 1168 if (sc->sk_ramsize) { 1169 chunk = (2 * (sc->sk_ramsize / sizeof(uint64_t)) / 3) & ~0xff; 1170 sc_if->sk_rx_ramstart = 0; 1171 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 1172 chunk = (sc->sk_ramsize / sizeof(uint64_t)) - chunk; 1173 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 1174 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 1175 1176 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1177 " tx_ramstart=%#x tx_ramend=%#x\n", 1178 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1179 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1180 } 1181 1182 /* Allocate the descriptor queues. */ 1183 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1184 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 1185 BUS_DMA_NOWAIT)) { 1186 aprint_error(": can't alloc rx buffers\n"); 1187 goto fail; 1188 } 1189 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 1190 sc_if->sk_ring_nseg, 1191 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1192 aprint_error(": can't map dma buffers (%zu bytes)\n", 1193 sizeof(struct msk_ring_data)); 1194 goto fail_1; 1195 } 1196 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1197 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1198 &sc_if->sk_ring_map)) { 1199 aprint_error(": can't create dma map\n"); 1200 goto fail_2; 1201 } 1202 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1203 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1204 aprint_error(": can't load dma map\n"); 1205 goto fail_3; 1206 } 1207 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1208 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1209 1210 if (sc->sk_type != SK_YUKON_FE && 1211 sc->sk_type != SK_YUKON_FE_P) 1212 sc_if->sk_pktlen = SK_JLEN; 1213 else 1214 sc_if->sk_pktlen = MCLBYTES; 1215 1216 /* Try to allocate memory for jumbo buffers. */ 1217 if (msk_alloc_jumbo_mem(sc_if)) { 1218 aprint_error(": jumbo buffer allocation failed\n"); 1219 goto fail_3; 1220 } 1221 1222 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1223 if (sc->sk_type != SK_YUKON_FE && 1224 sc->sk_type != SK_YUKON_FE_P) 1225 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1226 1227 ifp = &sc_if->sk_ethercom.ec_if; 1228 ifp->if_softc = sc_if; 1229 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1230 ifp->if_ioctl = msk_ioctl; 1231 ifp->if_start = msk_start; 1232 ifp->if_stop = msk_stop; 1233 ifp->if_init = msk_init; 1234 ifp->if_watchdog = msk_watchdog; 1235 ifp->if_baudrate = 1000000000; 1236 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1237 IFQ_SET_READY(&ifp->if_snd); 1238 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1239 1240 msk_reset(sc_if); 1241 1242 /* 1243 * Do miibus setup. 1244 */ 1245 msk_init_yukon(sc_if); 1246 1247 DPRINTFN(2, ("msk_attach: 1\n")); 1248 1249 mii->mii_ifp = ifp; 1250 mii->mii_readreg = msk_miibus_readreg; 1251 mii->mii_writereg = msk_miibus_writereg; 1252 mii->mii_statchg = msk_miibus_statchg; 1253 1254 sc_if->sk_ethercom.ec_mii = mii; 1255 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1256 mii_flags = MIIF_DOPAUSE; 1257 if (sc->sk_fibertype) 1258 mii_flags |= MIIF_HAVEFIBER; 1259 mii_attach(self, mii, 0xffffffff, 0, MII_OFFSET_ANY, mii_flags); 1260 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1261 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1262 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 1263 0, NULL); 1264 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 1265 } else 1266 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1267 1268 callout_init(&sc_if->sk_tick_ch, 0); 1269 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1270 callout_schedule(&sc_if->sk_tick_ch, hz); 1271 1272 callout_init(&sc_if->sk_tick_rx, 0); 1273 callout_setfunc(&sc_if->sk_tick_rx, msk_fill_rx_tick, sc_if); 1274 1275 /* 1276 * Call MI attach routines. 1277 */ 1278 if_attach(ifp); 1279 if_deferred_start_init(ifp, NULL); 1280 ether_ifattach(ifp, sc_if->sk_enaddr); 1281 1282 if (pmf_device_register(self, NULL, msk_resume)) 1283 pmf_class_network_register(self, ifp); 1284 else 1285 aprint_error_dev(self, "couldn't establish power handler\n"); 1286 1287 if (sc->rnd_attached++ == 0) { 1288 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1289 RND_TYPE_NET, RND_FLAG_DEFAULT); 1290 } 1291 1292 DPRINTFN(2, ("msk_attach: end\n")); 1293 return; 1294 1295 fail_3: 1296 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1297 fail_2: 1298 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1299 fail_1: 1300 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1301 fail: 1302 sc->sk_if[sa->skc_port] = NULL; 1303 } 1304 1305 int 1306 msk_detach(device_t self, int flags) 1307 { 1308 struct sk_if_softc *sc_if = device_private(self); 1309 struct sk_softc *sc = sc_if->sk_softc; 1310 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1311 1312 if (sc->sk_if[sc_if->sk_port] == NULL) 1313 return 0; 1314 1315 msk_stop(ifp, 1); 1316 1317 if (--sc->rnd_attached == 0) 1318 rnd_detach_source(&sc->rnd_source); 1319 1320 callout_halt(&sc_if->sk_tick_ch, NULL); 1321 callout_destroy(&sc_if->sk_tick_ch); 1322 1323 callout_halt(&sc_if->sk_tick_rx, NULL); 1324 callout_destroy(&sc_if->sk_tick_rx); 1325 1326 /* Detach any PHYs we might have. */ 1327 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1328 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1329 1330 /* Delete any remaining media. */ 1331 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY); 1332 1333 pmf_device_deregister(self); 1334 1335 ether_ifdetach(ifp); 1336 if_detach(ifp); 1337 1338 msk_free_jumbo_mem(sc_if); 1339 1340 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_rdata, 1341 sizeof(struct msk_ring_data)); 1342 bus_dmamem_free(sc->sc_dmatag, 1343 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1344 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1345 sc->sk_if[sc_if->sk_port] = NULL; 1346 1347 return 0; 1348 } 1349 1350 int 1351 mskcprint(void *aux, const char *pnp) 1352 { 1353 struct skc_attach_args *sa = aux; 1354 1355 if (pnp) 1356 aprint_normal("msk port %c at %s", 1357 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1358 else 1359 aprint_normal(" port %c", 1360 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1361 return UNCONF; 1362 } 1363 1364 /* 1365 * Attach the interface. Allocate softc structures, do ifmedia 1366 * setup and ethernet/BPF attach. 1367 */ 1368 void 1369 mskc_attach(device_t parent, device_t self, void *aux) 1370 { 1371 struct sk_softc *sc = device_private(self); 1372 struct pci_attach_args *pa = aux; 1373 struct skc_attach_args skca; 1374 pci_chipset_tag_t pc = pa->pa_pc; 1375 pcireg_t command, memtype; 1376 const char *intrstr = NULL; 1377 int rc, sk_nodenum; 1378 uint8_t hw, pmd; 1379 const char *revstr = NULL; 1380 const struct sysctlnode *node; 1381 void *kva; 1382 char intrbuf[PCI_INTRSTR_LEN]; 1383 1384 DPRINTFN(2, ("begin mskc_attach\n")); 1385 1386 sc->sk_dev = self; 1387 /* 1388 * Handle power management nonsense. 1389 */ 1390 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1391 1392 if (command == 0x01) { 1393 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1394 if (command & SK_PSTATE_MASK) { 1395 uint32_t iobase, membase, irq; 1396 1397 /* Save important PCI config data. */ 1398 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1399 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1400 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1401 1402 /* Reset the power state. */ 1403 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1404 "mode -- setting to D0\n", 1405 command & SK_PSTATE_MASK); 1406 command &= 0xFFFFFFFC; 1407 pci_conf_write(pc, pa->pa_tag, 1408 SK_PCI_PWRMGMTCTRL, command); 1409 1410 /* Restore PCI config data. */ 1411 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1412 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1413 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1414 } 1415 } 1416 1417 /* 1418 * Map control/status registers. 1419 */ 1420 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1421 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1422 &sc->sk_bhandle, NULL, &sc->sk_bsize)) { 1423 aprint_error(": can't map mem space\n"); 1424 return; 1425 } 1426 1427 if (pci_dma64_available(pa)) 1428 sc->sc_dmatag = pa->pa_dmat64; 1429 else 1430 sc->sc_dmatag = pa->pa_dmat; 1431 1432 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1433 command |= PCI_COMMAND_MASTER_ENABLE; 1434 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1435 1436 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1437 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1438 1439 /* bail out here if chip is not recognized */ 1440 if (!(SK_IS_YUKON2(sc))) { 1441 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1442 goto fail_1; 1443 } 1444 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1445 1446 /* Allocate interrupt */ 1447 if (pci_intr_alloc(pa, &sc->sk_pihp, NULL, 0)) { 1448 aprint_error(": couldn't map interrupt\n"); 1449 goto fail_1; 1450 } 1451 1452 intrstr = pci_intr_string(pc, sc->sk_pihp[0], intrbuf, sizeof(intrbuf)); 1453 sc->sk_intrhand = pci_intr_establish_xname(pc, sc->sk_pihp[0], IPL_NET, 1454 msk_intr, sc, device_xname(sc->sk_dev)); 1455 if (sc->sk_intrhand == NULL) { 1456 aprint_error(": couldn't establish interrupt"); 1457 if (intrstr != NULL) 1458 aprint_error(" at %s", intrstr); 1459 aprint_error("\n"); 1460 goto fail_1; 1461 } 1462 sc->sk_pc = pc; 1463 1464 if (bus_dmamem_alloc(sc->sc_dmatag, 1465 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1466 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1467 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, BUS_DMA_NOWAIT)) { 1468 aprint_error(": can't alloc status buffers\n"); 1469 goto fail_2; 1470 } 1471 1472 if (bus_dmamem_map(sc->sc_dmatag, 1473 &sc->sk_status_seg, sc->sk_status_nseg, 1474 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1475 &kva, BUS_DMA_NOWAIT)) { 1476 aprint_error(": can't map dma buffers (%zu bytes)\n", 1477 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1478 goto fail_3; 1479 } 1480 if (bus_dmamap_create(sc->sc_dmatag, 1481 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1482 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1483 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1484 aprint_error(": can't create dma map\n"); 1485 goto fail_4; 1486 } 1487 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1488 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1489 NULL, BUS_DMA_NOWAIT)) { 1490 aprint_error(": can't load dma map\n"); 1491 goto fail_5; 1492 } 1493 sc->sk_status_ring = (struct msk_status_desc *)kva; 1494 1495 sc->sk_int_mod = SK_IM_DEFAULT; 1496 sc->sk_int_mod_pending = 0; 1497 1498 /* Reset the adapter. */ 1499 mskc_reset(sc); 1500 1501 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1502 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1503 1504 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1505 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1506 sc->sk_fibertype = 1; 1507 1508 switch (sc->sk_type) { 1509 case SK_YUKON_XL: 1510 sc->sk_name = "Yukon-2 XL"; 1511 break; 1512 case SK_YUKON_EC_U: 1513 sc->sk_name = "Yukon-2 EC Ultra"; 1514 break; 1515 case SK_YUKON_EX: 1516 sc->sk_name = "Yukon-2 Extreme"; 1517 break; 1518 case SK_YUKON_EC: 1519 sc->sk_name = "Yukon-2 EC"; 1520 break; 1521 case SK_YUKON_FE: 1522 sc->sk_name = "Yukon-2 FE"; 1523 break; 1524 case SK_YUKON_FE_P: 1525 sc->sk_name = "Yukon-2 FE+"; 1526 break; 1527 case SK_YUKON_SUPR: 1528 sc->sk_name = "Yukon-2 Supreme"; 1529 break; 1530 case SK_YUKON_ULTRA2: 1531 sc->sk_name = "Yukon-2 Ultra 2"; 1532 break; 1533 case SK_YUKON_OPTIMA: 1534 sc->sk_name = "Yukon-2 Optima"; 1535 break; 1536 case SK_YUKON_PRM: 1537 sc->sk_name = "Yukon-2 Optima Prime"; 1538 break; 1539 case SK_YUKON_OPTIMA2: 1540 sc->sk_name = "Yukon-2 Optima 2"; 1541 break; 1542 default: 1543 sc->sk_name = "Yukon (Unknown)"; 1544 } 1545 1546 if (sc->sk_type == SK_YUKON_XL) { 1547 switch (sc->sk_rev) { 1548 case SK_YUKON_XL_REV_A0: 1549 revstr = "A0"; 1550 break; 1551 case SK_YUKON_XL_REV_A1: 1552 revstr = "A1"; 1553 break; 1554 case SK_YUKON_XL_REV_A2: 1555 revstr = "A2"; 1556 break; 1557 case SK_YUKON_XL_REV_A3: 1558 revstr = "A3"; 1559 break; 1560 default: 1561 break; 1562 } 1563 } 1564 1565 if (sc->sk_type == SK_YUKON_EC) { 1566 switch (sc->sk_rev) { 1567 case SK_YUKON_EC_REV_A1: 1568 revstr = "A1"; 1569 break; 1570 case SK_YUKON_EC_REV_A2: 1571 revstr = "A2"; 1572 break; 1573 case SK_YUKON_EC_REV_A3: 1574 revstr = "A3"; 1575 break; 1576 default: 1577 break; 1578 } 1579 } 1580 1581 if (sc->sk_type == SK_YUKON_FE) { 1582 switch (sc->sk_rev) { 1583 case SK_YUKON_FE_REV_A1: 1584 revstr = "A1"; 1585 break; 1586 case SK_YUKON_FE_REV_A2: 1587 revstr = "A2"; 1588 break; 1589 default: 1590 break; 1591 } 1592 } 1593 1594 if (sc->sk_type == SK_YUKON_EC_U) { 1595 switch (sc->sk_rev) { 1596 case SK_YUKON_EC_U_REV_A0: 1597 revstr = "A0"; 1598 break; 1599 case SK_YUKON_EC_U_REV_A1: 1600 revstr = "A1"; 1601 break; 1602 case SK_YUKON_EC_U_REV_B0: 1603 revstr = "B0"; 1604 break; 1605 case SK_YUKON_EC_U_REV_B1: 1606 revstr = "B1"; 1607 break; 1608 default: 1609 break; 1610 } 1611 } 1612 1613 if (sc->sk_type == SK_YUKON_FE) { 1614 switch (sc->sk_rev) { 1615 case SK_YUKON_FE_REV_A1: 1616 revstr = "A1"; 1617 break; 1618 case SK_YUKON_FE_REV_A2: 1619 revstr = "A2"; 1620 break; 1621 default: 1622 ; 1623 } 1624 } 1625 1626 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1627 revstr = "A0"; 1628 1629 if (sc->sk_type == SK_YUKON_EX) { 1630 switch (sc->sk_rev) { 1631 case SK_YUKON_EX_REV_A0: 1632 revstr = "A0"; 1633 break; 1634 case SK_YUKON_EX_REV_B0: 1635 revstr = "B0"; 1636 break; 1637 default: 1638 ; 1639 } 1640 } 1641 1642 if (sc->sk_type == SK_YUKON_SUPR) { 1643 switch (sc->sk_rev) { 1644 case SK_YUKON_SUPR_REV_A0: 1645 revstr = "A0"; 1646 break; 1647 case SK_YUKON_SUPR_REV_B0: 1648 revstr = "B0"; 1649 break; 1650 case SK_YUKON_SUPR_REV_B1: 1651 revstr = "B1"; 1652 break; 1653 default: 1654 ; 1655 } 1656 } 1657 1658 if (sc->sk_type == SK_YUKON_PRM) { 1659 switch (sc->sk_rev) { 1660 case SK_YUKON_PRM_REV_Z1: 1661 revstr = "Z1"; 1662 break; 1663 case SK_YUKON_PRM_REV_A0: 1664 revstr = "A0"; 1665 break; 1666 default: 1667 ; 1668 } 1669 } 1670 1671 /* Announce the product name. */ 1672 aprint_normal(", %s", sc->sk_name); 1673 if (revstr != NULL) 1674 aprint_normal(" rev. %s", revstr); 1675 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1676 1677 sc->sk_macs = 1; 1678 1679 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1680 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1681 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1682 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1683 sc->sk_macs++; 1684 } 1685 1686 skca.skc_port = SK_PORT_A; 1687 skca.skc_type = sc->sk_type; 1688 skca.skc_rev = sc->sk_rev; 1689 (void)config_found(sc->sk_dev, &skca, mskcprint); 1690 1691 if (sc->sk_macs > 1) { 1692 skca.skc_port = SK_PORT_B; 1693 skca.skc_type = sc->sk_type; 1694 skca.skc_rev = sc->sk_rev; 1695 (void)config_found(sc->sk_dev, &skca, mskcprint); 1696 } 1697 1698 /* Turn on the 'driver is loaded' LED. */ 1699 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1700 1701 /* skc sysctl setup */ 1702 1703 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1704 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1705 SYSCTL_DESCR("mskc per-controller controls"), 1706 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1707 CTL_EOL)) != 0) { 1708 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1709 goto fail_6; 1710 } 1711 1712 sk_nodenum = node->sysctl_num; 1713 1714 /* interrupt moderation time in usecs */ 1715 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1716 CTLFLAG_READWRITE, 1717 CTLTYPE_INT, "int_mod", 1718 SYSCTL_DESCR("msk interrupt moderation timer"), 1719 msk_sysctl_handler, 0, (void *)sc, 1720 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1721 CTL_EOL)) != 0) { 1722 aprint_normal_dev(sc->sk_dev, 1723 "couldn't create int_mod sysctl node\n"); 1724 goto fail_6; 1725 } 1726 1727 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1728 aprint_error_dev(self, "couldn't establish power handler\n"); 1729 1730 return; 1731 1732 fail_6: 1733 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1734 fail_4: 1735 bus_dmamem_unmap(sc->sc_dmatag, kva, 1736 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1737 fail_3: 1738 bus_dmamem_free(sc->sc_dmatag, 1739 &sc->sk_status_seg, sc->sk_status_nseg); 1740 sc->sk_status_nseg = 0; 1741 fail_5: 1742 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1743 fail_2: 1744 pci_intr_disestablish(pc, sc->sk_intrhand); 1745 sc->sk_intrhand = NULL; 1746 fail_1: 1747 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1748 sc->sk_bsize = 0; 1749 } 1750 1751 int 1752 mskc_detach(device_t self, int flags) 1753 { 1754 struct sk_softc *sc = device_private(self); 1755 int rv; 1756 1757 if (sc->sk_intrhand) { 1758 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1759 sc->sk_intrhand = NULL; 1760 } 1761 1762 if (sc->sk_pihp != NULL) { 1763 pci_intr_release(sc->sk_pc, sc->sk_pihp, 1); 1764 sc->sk_pihp = NULL; 1765 } 1766 1767 rv = config_detach_children(self, flags); 1768 if (rv != 0) 1769 return rv; 1770 1771 if (sc->sk_status_nseg > 0) { 1772 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1773 bus_dmamem_unmap(sc->sc_dmatag, sc->sk_status_ring, 1774 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1775 bus_dmamem_free(sc->sc_dmatag, 1776 &sc->sk_status_seg, sc->sk_status_nseg); 1777 } 1778 1779 if (sc->sk_bsize > 0) 1780 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1781 1782 return 0; 1783 } 1784 1785 int 1786 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1787 { 1788 struct sk_softc *sc = sc_if->sk_softc; 1789 struct msk_tx_desc *f = NULL; 1790 uint32_t frag, cur, hiaddr, old_hiaddr, total; 1791 uint32_t entries = 0; 1792 size_t i; 1793 struct sk_txmap_entry *entry; 1794 bus_dmamap_t txmap; 1795 bus_addr_t addr; 1796 1797 DPRINTFN(2, ("msk_encap\n")); 1798 1799 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1800 if (entry == NULL) { 1801 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1802 return ENOBUFS; 1803 } 1804 txmap = entry->dmamap; 1805 1806 cur = frag = *txidx; 1807 1808 #ifdef MSK_DEBUG 1809 if (mskdebug >= 2) 1810 msk_dump_mbuf(m_head); 1811 #endif 1812 1813 /* 1814 * Start packing the mbufs in this chain into 1815 * the fragment pointers. Stop when we run out 1816 * of fragments or hit the end of the mbuf chain. 1817 */ 1818 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1819 BUS_DMA_NOWAIT)) { 1820 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1821 return ENOBUFS; 1822 } 1823 1824 /* Count how many tx descriptors needed. */ 1825 hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1826 for (total = i = 0; i < txmap->dm_nsegs; i++) { 1827 if (hiaddr != MSK_ADDR_HI(txmap->dm_segs[i].ds_addr)) { 1828 hiaddr = MSK_ADDR_HI(txmap->dm_segs[i].ds_addr); 1829 total++; 1830 } 1831 total++; 1832 } 1833 1834 if (total > MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2) { 1835 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1836 bus_dmamap_unload(sc->sc_dmatag, txmap); 1837 return ENOBUFS; 1838 } 1839 1840 DPRINTFN(2, ("msk_encap: dm_nsegs=%d total desc=%u\n", 1841 txmap->dm_nsegs, total)); 1842 1843 /* Sync the DMA map. */ 1844 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1845 BUS_DMASYNC_PREWRITE); 1846 1847 old_hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1848 for (i = 0; i < txmap->dm_nsegs; i++) { 1849 addr = txmap->dm_segs[i].ds_addr; 1850 DPRINTFN(2, ("msk_encap: addr %llx\n", 1851 (unsigned long long)addr)); 1852 hiaddr = MSK_ADDR_HI(addr); 1853 1854 if (sc_if->sk_cdata.sk_tx_hiaddr != hiaddr) { 1855 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1856 f->sk_addr = htole32(hiaddr); 1857 f->sk_len = 0; 1858 f->sk_ctl = 0; 1859 if (i == 0) 1860 f->sk_opcode = SK_Y2_BMUOPC_ADDR64; 1861 else 1862 f->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 1863 sc_if->sk_cdata.sk_tx_hiaddr = hiaddr; 1864 SK_INC(frag, MSK_TX_RING_CNT); 1865 entries++; 1866 DPRINTFN(10, ("%s: tx ADDR64: %#x\n", 1867 sc_if->sk_ethercom.ec_if.if_xname, hiaddr)); 1868 } 1869 1870 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1871 f->sk_addr = htole32(MSK_ADDR_LO(addr)); 1872 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1873 f->sk_ctl = 0; 1874 if (i == 0) { 1875 if (hiaddr != old_hiaddr) 1876 f->sk_opcode = SK_Y2_TXOPC_PACKET | SK_Y2_TXOPC_OWN; 1877 else 1878 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1879 } else 1880 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1881 cur = frag; 1882 SK_INC(frag, MSK_TX_RING_CNT); 1883 entries++; 1884 } 1885 KASSERTMSG(entries == total, "entries %u total %u", entries, total); 1886 1887 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1888 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1889 1890 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1891 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1892 1893 /* Sync descriptors before handing to chip */ 1894 MSK_CDTXSYNC(sc_if, *txidx, entries, 1895 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1896 1897 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1898 1899 /* Sync first descriptor to hand it off */ 1900 MSK_CDTXSYNC(sc_if, *txidx, 1, 1901 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1902 1903 sc_if->sk_cdata.sk_tx_cnt += entries; 1904 1905 #ifdef MSK_DEBUG 1906 if (mskdebug >= 2) { 1907 struct msk_tx_desc *le; 1908 uint32_t idx; 1909 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1910 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1911 msk_dump_txdesc(le, idx); 1912 } 1913 } 1914 #endif 1915 1916 *txidx = frag; 1917 1918 DPRINTFN(2, ("msk_encap: successful: %u entries\n", entries)); 1919 1920 return 0; 1921 } 1922 1923 void 1924 msk_start(struct ifnet *ifp) 1925 { 1926 struct sk_if_softc *sc_if = ifp->if_softc; 1927 struct mbuf *m_head = NULL; 1928 uint32_t idx = sc_if->sk_cdata.sk_tx_prod; 1929 int pkts = 0; 1930 1931 DPRINTFN(2, ("msk_start\n")); 1932 1933 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1934 IFQ_POLL(&ifp->if_snd, m_head); 1935 if (m_head == NULL) 1936 break; 1937 1938 /* 1939 * Pack the data into the transmit ring. If we 1940 * don't have room, set the OACTIVE flag and wait 1941 * for the NIC to drain the ring. 1942 */ 1943 if (msk_encap(sc_if, m_head, &idx)) { 1944 ifp->if_flags |= IFF_OACTIVE; 1945 break; 1946 } 1947 1948 /* now we are committed to transmit the packet */ 1949 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1950 pkts++; 1951 1952 /* 1953 * If there's a BPF listener, bounce a copy of this frame 1954 * to him. 1955 */ 1956 bpf_mtap(ifp, m_head, BPF_D_OUT); 1957 } 1958 if (pkts == 0) 1959 return; 1960 1961 /* Transmit */ 1962 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1963 sc_if->sk_cdata.sk_tx_prod = idx; 1964 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1965 1966 /* Set a timeout in case the chip goes out to lunch. */ 1967 ifp->if_timer = 5; 1968 } 1969 } 1970 1971 void 1972 msk_watchdog(struct ifnet *ifp) 1973 { 1974 struct sk_if_softc *sc_if = ifp->if_softc; 1975 1976 /* 1977 * Reclaim first as there is a possibility of losing Tx completion 1978 * interrupts. 1979 */ 1980 msk_txeof(sc_if); 1981 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1982 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1983 1984 ifp->if_oerrors++; 1985 1986 /* XXX Resets both ports; we shouldn't do that. */ 1987 mskc_reset(sc_if->sk_softc); 1988 msk_reset(sc_if); 1989 msk_init(ifp); 1990 } 1991 } 1992 1993 static bool 1994 mskc_suspend(device_t dv, const pmf_qual_t *qual) 1995 { 1996 struct sk_softc *sc = device_private(dv); 1997 1998 DPRINTFN(2, ("mskc_suspend\n")); 1999 2000 /* Turn off the 'driver is loaded' LED. */ 2001 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2002 2003 return true; 2004 } 2005 2006 static bool 2007 mskc_resume(device_t dv, const pmf_qual_t *qual) 2008 { 2009 struct sk_softc *sc = device_private(dv); 2010 2011 DPRINTFN(2, ("mskc_resume\n")); 2012 2013 mskc_reset(sc); 2014 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 2015 2016 return true; 2017 } 2018 2019 static __inline int 2020 msk_rxvalid(struct sk_softc *sc, uint32_t stat, uint32_t len) 2021 { 2022 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 2023 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 2024 YU_RXSTAT_JABBER)) != 0 || 2025 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 2026 YU_RXSTAT_BYTES(stat) != len) 2027 return 0; 2028 2029 return 1; 2030 } 2031 2032 void 2033 msk_rxeof(struct sk_if_softc *sc_if, uint16_t len, uint32_t rxstat) 2034 { 2035 struct sk_softc *sc = sc_if->sk_softc; 2036 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2037 struct mbuf *m; 2038 unsigned cur, prod, tail, total_len = len; 2039 bus_dmamap_t dmamap; 2040 2041 cur = sc_if->sk_cdata.sk_rx_cons; 2042 prod = sc_if->sk_cdata.sk_rx_prod; 2043 2044 /* Sync the descriptor */ 2045 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2046 2047 DPRINTFN(2, ("msk_rxeof: cur %u prod %u rx_cnt %u\n", cur, prod, 2048 sc_if->sk_cdata.sk_rx_cnt)); 2049 2050 while (prod != cur) { 2051 tail = cur; 2052 SK_INC(cur, MSK_RX_RING_CNT); 2053 2054 sc_if->sk_cdata.sk_rx_cnt--; 2055 m = sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf; 2056 sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf = NULL; 2057 if (m != NULL) 2058 break; /* found it */ 2059 } 2060 sc_if->sk_cdata.sk_rx_cons = cur; 2061 DPRINTFN(2, ("msk_rxeof: cur %u rx_cnt %u m %p\n", cur, 2062 sc_if->sk_cdata.sk_rx_cnt, m)); 2063 2064 if (m == NULL) 2065 return; 2066 2067 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2068 2069 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2070 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2071 2072 if (total_len < SK_MIN_FRAMELEN || 2073 total_len > ETHER_MAX_LEN_JUMBO || 2074 msk_rxvalid(sc, rxstat, total_len) == 0) { 2075 ifp->if_ierrors++; 2076 m_freem(m); 2077 return; 2078 } 2079 2080 m_set_rcvif(m, ifp); 2081 m->m_pkthdr.len = m->m_len = total_len; 2082 2083 /* pass it on. */ 2084 if_percpuq_enqueue(ifp->if_percpuq, m); 2085 } 2086 2087 void 2088 msk_txeof(struct sk_if_softc *sc_if) 2089 { 2090 struct sk_softc *sc = sc_if->sk_softc; 2091 struct msk_tx_desc *cur_tx; 2092 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2093 uint32_t idx, reg, sk_ctl; 2094 struct sk_txmap_entry *entry; 2095 2096 DPRINTFN(2, ("msk_txeof\n")); 2097 2098 if (sc_if->sk_port == SK_PORT_A) 2099 reg = SK_STAT_BMU_TXA1_RIDX; 2100 else 2101 reg = SK_STAT_BMU_TXA2_RIDX; 2102 2103 /* 2104 * Go through our tx ring and free mbufs for those 2105 * frames that have been sent. 2106 */ 2107 idx = sc_if->sk_cdata.sk_tx_cons; 2108 while (idx != sk_win_read_2(sc, reg)) { 2109 MSK_CDTXSYNC(sc_if, idx, 1, 2110 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2111 2112 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2113 sk_ctl = cur_tx->sk_ctl; 2114 #ifdef MSK_DEBUG 2115 if (mskdebug >= 2) 2116 msk_dump_txdesc(cur_tx, idx); 2117 #endif 2118 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 2119 ifp->if_opackets++; 2120 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2121 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2122 2123 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2124 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2125 2126 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2127 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2128 2129 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2130 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2131 link); 2132 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2133 } 2134 sc_if->sk_cdata.sk_tx_cnt--; 2135 SK_INC(idx, MSK_TX_RING_CNT); 2136 } 2137 if (idx == sc_if->sk_cdata.sk_tx_cons) 2138 return; 2139 2140 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2141 2142 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 2143 ifp->if_flags &= ~IFF_OACTIVE; 2144 2145 sc_if->sk_cdata.sk_tx_cons = idx; 2146 } 2147 2148 void 2149 msk_fill_rx_ring(struct sk_if_softc *sc_if) 2150 { 2151 /* Make sure to not completely wrap around */ 2152 while (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT - 1)) { 2153 if (msk_newbuf(sc_if, 2154 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 2155 goto schedretry; 2156 } 2157 } 2158 2159 return; 2160 2161 schedretry: 2162 /* Try later */ 2163 callout_schedule(&sc_if->sk_tick_rx, hz/2); 2164 } 2165 2166 static void 2167 msk_fill_rx_tick(void *xsc_if) 2168 { 2169 struct sk_if_softc *sc_if = xsc_if; 2170 int s, rx_prod; 2171 2172 KASSERT(KERNEL_LOCKED_P()); /* XXXSMP */ 2173 2174 s = splnet(); 2175 rx_prod = sc_if->sk_cdata.sk_rx_prod; 2176 msk_fill_rx_ring(sc_if); 2177 if (rx_prod != sc_if->sk_cdata.sk_rx_prod) { 2178 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2179 sc_if->sk_cdata.sk_rx_prod); 2180 } 2181 splx(s); 2182 } 2183 2184 void 2185 msk_tick(void *xsc_if) 2186 { 2187 struct sk_if_softc *sc_if = xsc_if; 2188 struct mii_data *mii = &sc_if->sk_mii; 2189 int s; 2190 2191 s = splnet(); 2192 mii_tick(mii); 2193 splx(s); 2194 2195 callout_schedule(&sc_if->sk_tick_ch, hz); 2196 } 2197 2198 void 2199 msk_intr_yukon(struct sk_if_softc *sc_if) 2200 { 2201 uint8_t status; 2202 2203 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2204 /* RX overrun */ 2205 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2206 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2207 SK_RFCTL_RX_FIFO_OVER); 2208 } 2209 /* TX underrun */ 2210 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2211 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 2212 SK_TFCTL_TX_FIFO_UNDER); 2213 } 2214 2215 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 2216 } 2217 2218 int 2219 msk_intr(void *xsc) 2220 { 2221 struct sk_softc *sc = xsc; 2222 struct sk_if_softc *sc_if; 2223 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2224 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2225 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2226 int claimed = 0; 2227 uint32_t status; 2228 struct msk_status_desc *cur_st; 2229 2230 status = CSR_READ_4(sc, SK_Y2_ISSR2); 2231 if (status == 0xffffffff) 2232 return 0; 2233 if (status == 0) { 2234 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2235 return 0; 2236 } 2237 2238 status = CSR_READ_4(sc, SK_ISR); 2239 2240 if (sc_if0 != NULL) 2241 ifp0 = &sc_if0->sk_ethercom.ec_if; 2242 if (sc_if1 != NULL) 2243 ifp1 = &sc_if1->sk_ethercom.ec_if; 2244 2245 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 2246 (ifp0->if_flags & IFF_RUNNING)) { 2247 msk_intr_yukon(sc_if0); 2248 } 2249 2250 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 2251 (ifp1->if_flags & IFF_RUNNING)) { 2252 msk_intr_yukon(sc_if1); 2253 } 2254 2255 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2256 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2257 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2258 2259 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 2260 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 2261 switch (cur_st->sk_opcode) { 2262 case SK_Y2_STOPC_RXSTAT: 2263 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 2264 if (sc_if) { 2265 msk_rxeof(sc_if, letoh16(cur_st->sk_len), 2266 letoh32(cur_st->sk_status)); 2267 if (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 2268 msk_fill_rx_tick(sc_if); 2269 } 2270 break; 2271 case SK_Y2_STOPC_TXSTAT: 2272 if (sc_if0) 2273 msk_txeof(sc_if0); 2274 if (sc_if1) 2275 msk_txeof(sc_if1); 2276 break; 2277 default: 2278 aprint_error("opcode=0x%x\n", cur_st->sk_opcode); 2279 break; 2280 } 2281 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 2282 2283 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2284 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2285 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2286 } 2287 2288 if (status & SK_Y2_IMR_BMU) { 2289 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 2290 claimed = 1; 2291 } 2292 2293 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2294 2295 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2296 if_schedule_deferred_start(ifp0); 2297 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2298 if_schedule_deferred_start(ifp1); 2299 2300 KASSERT(sc->rnd_attached > 0); 2301 rnd_add_uint32(&sc->rnd_source, status); 2302 2303 if (sc->sk_int_mod_pending) 2304 msk_update_int_mod(sc, 1); 2305 2306 return claimed; 2307 } 2308 2309 void 2310 msk_init_yukon(struct sk_if_softc *sc_if) 2311 { 2312 uint32_t v; 2313 uint16_t reg; 2314 struct sk_softc *sc; 2315 int i; 2316 2317 sc = sc_if->sk_softc; 2318 2319 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 2320 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2321 2322 DPRINTFN(6, ("msk_init_yukon: 1\n")); 2323 2324 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 2325 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2326 2327 DPRINTFN(6, ("msk_init_yukon: 3\n")); 2328 2329 /* unused read of the interrupt source register */ 2330 DPRINTFN(6, ("msk_init_yukon: 4\n")); 2331 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2332 2333 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2334 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2335 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2336 2337 /* MIB Counter Clear Mode set */ 2338 reg |= YU_PAR_MIB_CLR; 2339 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2340 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2341 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2342 2343 /* MIB Counter Clear Mode clear */ 2344 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2345 reg &= ~YU_PAR_MIB_CLR; 2346 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2347 2348 /* receive control reg */ 2349 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2350 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2351 2352 /* transmit control register */ 2353 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2354 2355 /* transmit flow control register */ 2356 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2357 2358 /* transmit parameter register */ 2359 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2360 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2361 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2362 2363 /* serial mode register */ 2364 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2365 reg = YU_SMR_DATA_BLIND(0x1c) | 2366 YU_SMR_MFL_VLAN | 2367 YU_SMR_IPG_DATA(0x1e); 2368 2369 if (sc->sk_type != SK_YUKON_FE && 2370 sc->sk_type != SK_YUKON_FE_P) 2371 reg |= YU_SMR_MFL_JUMBO; 2372 2373 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2374 2375 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2376 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2377 /* msk_attach calls me before ether_ifattach so check null */ 2378 if (ifp != NULL && ifp->if_sadl != NULL) 2379 memcpy(sc_if->sk_enaddr, CLLADDR(ifp->if_sadl), 2380 sizeof(sc_if->sk_enaddr)); 2381 /* Setup Yukon's address */ 2382 for (i = 0; i < 3; i++) { 2383 /* Write Source Address 1 (unicast filter) */ 2384 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2385 sc_if->sk_enaddr[i * 2] | 2386 sc_if->sk_enaddr[i * 2 + 1] << 8); 2387 } 2388 2389 for (i = 0; i < 3; i++) { 2390 reg = sk_win_read_2(sc_if->sk_softc, 2391 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2392 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2393 } 2394 2395 /* Set promiscuous mode */ 2396 msk_setpromisc(sc_if); 2397 2398 /* Set multicast filter */ 2399 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2400 msk_setmulti(sc_if); 2401 2402 /* enable interrupt mask for counter overflows */ 2403 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2404 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2405 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2406 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2407 2408 /* Configure RX MAC FIFO Flush Mask */ 2409 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2410 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2411 YU_RXSTAT_JABBER; 2412 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2413 2414 /* Configure RX MAC FIFO */ 2415 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2416 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2417 SK_RFCTL_FIFO_FLUSH_ON); 2418 2419 /* Increase flush threshold to 64 bytes */ 2420 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2421 SK_RFCTL_FIFO_THRESHOLD + 1); 2422 2423 /* Configure TX MAC FIFO */ 2424 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2425 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2426 2427 #if 1 2428 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2429 #endif 2430 DPRINTFN(6, ("msk_init_yukon: end\n")); 2431 } 2432 2433 /* 2434 * Note that to properly initialize any part of the GEnesis chip, 2435 * you first have to take it out of reset mode. 2436 */ 2437 int 2438 msk_init(struct ifnet *ifp) 2439 { 2440 struct sk_if_softc *sc_if = ifp->if_softc; 2441 struct sk_softc *sc = sc_if->sk_softc; 2442 int rc = 0, s; 2443 uint32_t imr, imtimer_ticks; 2444 2445 2446 DPRINTFN(2, ("msk_init\n")); 2447 2448 s = splnet(); 2449 2450 /* Cancel pending I/O and free all RX/TX buffers. */ 2451 msk_stop(ifp, 1); 2452 2453 /* Configure I2C registers */ 2454 2455 /* Configure XMAC(s) */ 2456 msk_init_yukon(sc_if); 2457 if ((rc = ether_mediachange(ifp)) != 0) 2458 goto out; 2459 2460 /* Configure transmit arbiter(s) */ 2461 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2462 #if 0 2463 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); 2464 #endif 2465 2466 if (sc->sk_ramsize) { 2467 /* Configure RAMbuffers */ 2468 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2469 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2470 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2471 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2472 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2473 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2474 2475 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2476 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2477 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2478 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2479 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2480 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2481 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2482 } 2483 2484 /* Configure BMUs */ 2485 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2486 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2487 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2488 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2489 2490 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2491 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2492 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2493 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2494 2495 /* Make sure the sync transmit queue is disabled. */ 2496 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2497 2498 /* Init descriptors */ 2499 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2500 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2501 "memory for rx buffers\n"); 2502 msk_stop(ifp, 1); 2503 splx(s); 2504 return ENOBUFS; 2505 } 2506 2507 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2508 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2509 "memory for tx buffers\n"); 2510 msk_stop(ifp, 1); 2511 splx(s); 2512 return ENOBUFS; 2513 } 2514 2515 /* Set interrupt moderation if changed via sysctl. */ 2516 switch (sc->sk_type) { 2517 case SK_YUKON_EC: 2518 case SK_YUKON_EC_U: 2519 case SK_YUKON_EX: 2520 case SK_YUKON_SUPR: 2521 case SK_YUKON_ULTRA2: 2522 case SK_YUKON_OPTIMA: 2523 case SK_YUKON_PRM: 2524 case SK_YUKON_OPTIMA2: 2525 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2526 break; 2527 case SK_YUKON_FE: 2528 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2529 break; 2530 case SK_YUKON_FE_P: 2531 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 2532 break; 2533 case SK_YUKON_XL: 2534 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2535 break; 2536 default: 2537 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2538 } 2539 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2540 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2541 sk_win_write_4(sc, SK_IMTIMERINIT, 2542 SK_IM_USECS(sc->sk_int_mod)); 2543 aprint_verbose_dev(sc->sk_dev, 2544 "interrupt moderation is %d us\n", sc->sk_int_mod); 2545 } 2546 2547 /* Initialize prefetch engine. */ 2548 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2549 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2550 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2551 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2552 MSK_RX_RING_ADDR(sc_if, 0)); 2553 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2554 (uint64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2555 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2556 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2557 2558 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2559 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2560 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2561 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2562 MSK_TX_RING_ADDR(sc_if, 0)); 2563 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2564 (uint64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2565 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2566 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2567 2568 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2569 sc_if->sk_cdata.sk_rx_prod); 2570 2571 /* Configure interrupt handling */ 2572 if (sc_if->sk_port == SK_PORT_A) 2573 sc->sk_intrmask |= SK_Y2_INTRS1; 2574 else 2575 sc->sk_intrmask |= SK_Y2_INTRS2; 2576 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2577 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2578 2579 ifp->if_flags |= IFF_RUNNING; 2580 ifp->if_flags &= ~IFF_OACTIVE; 2581 2582 callout_schedule(&sc_if->sk_tick_ch, hz); 2583 2584 out: 2585 splx(s); 2586 return rc; 2587 } 2588 2589 /* 2590 * Note: the logic of second parameter is inverted compared to OpenBSD 2591 * code, since this code uses the function as if_stop hook too. 2592 */ 2593 void 2594 msk_stop(struct ifnet *ifp, int disable) 2595 { 2596 struct sk_if_softc *sc_if = ifp->if_softc; 2597 struct sk_softc *sc = sc_if->sk_softc; 2598 struct sk_txmap_entry *dma; 2599 int i; 2600 2601 DPRINTFN(2, ("msk_stop\n")); 2602 2603 callout_stop(&sc_if->sk_tick_ch); 2604 callout_stop(&sc_if->sk_tick_rx); 2605 2606 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2607 2608 /* Stop transfer of Tx descriptors */ 2609 2610 /* Stop transfer of Rx descriptors */ 2611 2612 if (disable) { 2613 /* Turn off various components of this interface. */ 2614 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2615 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2616 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2617 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2618 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2619 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2620 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2621 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2622 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2623 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2624 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2625 2626 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2627 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2628 2629 /* Disable interrupts */ 2630 if (sc_if->sk_port == SK_PORT_A) 2631 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2632 else 2633 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2634 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2635 } 2636 2637 /* Free RX and TX mbufs still in the queues. */ 2638 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2639 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2640 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2641 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2642 } 2643 } 2644 2645 sc_if->sk_cdata.sk_rx_prod = 0; 2646 sc_if->sk_cdata.sk_rx_cons = 0; 2647 sc_if->sk_cdata.sk_rx_cnt = 0; 2648 2649 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2650 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2651 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2652 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2653 #if 1 2654 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2655 sc_if->sk_cdata.sk_tx_map[i], link); 2656 sc_if->sk_cdata.sk_tx_map[i] = 0; 2657 #endif 2658 } 2659 } 2660 2661 #if 1 2662 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2663 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2664 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2665 free(dma, M_DEVBUF); 2666 } 2667 #endif 2668 } 2669 2670 CFATTACH_DECL3_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2671 mskc_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2672 2673 CFATTACH_DECL3_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2674 msk_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2675 2676 #ifdef MSK_DEBUG 2677 void 2678 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2679 { 2680 #define DESC_PRINT(X) \ 2681 if (X) \ 2682 printf("txdesc[%d]." #X "=%#x\n", \ 2683 idx, X); 2684 2685 DESC_PRINT(letoh32(le->sk_addr)); 2686 DESC_PRINT(letoh16(le->sk_len)); 2687 DESC_PRINT(le->sk_ctl); 2688 DESC_PRINT(le->sk_opcode); 2689 #undef DESC_PRINT 2690 } 2691 2692 void 2693 msk_dump_bytes(const char *data, int len) 2694 { 2695 int c, i, j; 2696 2697 for (i = 0; i < len; i += 16) { 2698 printf("%08x ", i); 2699 c = len - i; 2700 if (c > 16) c = 16; 2701 2702 for (j = 0; j < c; j++) { 2703 printf("%02x ", data[i + j] & 0xff); 2704 if ((j & 0xf) == 7 && j > 0) 2705 printf(" "); 2706 } 2707 2708 for (; j < 16; j++) 2709 printf(" "); 2710 printf(" "); 2711 2712 for (j = 0; j < c; j++) { 2713 int ch = data[i + j] & 0xff; 2714 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2715 } 2716 2717 printf("\n"); 2718 2719 if (c < 16) 2720 break; 2721 } 2722 } 2723 2724 void 2725 msk_dump_mbuf(struct mbuf *m) 2726 { 2727 int count = m->m_pkthdr.len; 2728 2729 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2730 2731 while (count > 0 && m) { 2732 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2733 m, m->m_data, m->m_len); 2734 if (mskdebug >= 4) 2735 msk_dump_bytes(mtod(m, char *), m->m_len); 2736 2737 count -= m->m_len; 2738 m = m->m_next; 2739 } 2740 } 2741 #endif 2742 2743 static int 2744 msk_sysctl_handler(SYSCTLFN_ARGS) 2745 { 2746 int error, t; 2747 struct sysctlnode node; 2748 struct sk_softc *sc; 2749 2750 node = *rnode; 2751 sc = node.sysctl_data; 2752 t = sc->sk_int_mod; 2753 node.sysctl_data = &t; 2754 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2755 if (error || newp == NULL) 2756 return error; 2757 2758 if (t < SK_IM_MIN || t > SK_IM_MAX) 2759 return EINVAL; 2760 2761 /* update the softc with sysctl-changed value, and mark 2762 for hardware update */ 2763 sc->sk_int_mod = t; 2764 sc->sk_int_mod_pending = 1; 2765 return 0; 2766 } 2767 2768 /* 2769 * Set up sysctl(3) MIB, hw.msk.* - Individual controllers will be 2770 * set up in mskc_attach() 2771 */ 2772 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2773 { 2774 int rc; 2775 const struct sysctlnode *node; 2776 2777 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2778 0, CTLTYPE_NODE, "msk", 2779 SYSCTL_DESCR("msk interface controls"), 2780 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2781 goto err; 2782 } 2783 2784 msk_root_num = node->sysctl_num; 2785 return; 2786 2787 err: 2788 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2789 } 2790
Indexes created Wed Sep 24 05:09:52 GMT 2025