if_msk.c revision 1.91.2.2
1 /* $NetBSD: if_msk.c,v 1.91.2.2 2019/11/19 13:07:37 martin Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.79 2009/10/15 17:54:56 deraadt Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.91.2.2 2019/11/19 13:07:37 martin Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/mutex.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/device.h> 66 #include <sys/queue.h> 67 #include <sys/callout.h> 68 #include <sys/sysctl.h> 69 #include <sys/endian.h> 70 #ifdef __NetBSD__ 71 #define letoh16 htole16 72 #define letoh32 htole32 73 #endif 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #include <net/if_media.h> 80 81 #include <net/bpf.h> 82 #include <sys/rndsource.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 #include <dev/mii/brgphyreg.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 92 #include <dev/pci/if_skreg.h> 93 #include <dev/pci/if_mskvar.h> 94 95 int mskc_probe(device_t, cfdata_t, void *); 96 void mskc_attach(device_t, device_t, void *); 97 int mskc_detach(device_t, int); 98 void mskc_reset(struct sk_softc *); 99 static bool mskc_suspend(device_t, const pmf_qual_t *); 100 static bool mskc_resume(device_t, const pmf_qual_t *); 101 int msk_probe(device_t, cfdata_t, void *); 102 void msk_attach(device_t, device_t, void *); 103 int msk_detach(device_t, int); 104 void msk_reset(struct sk_if_softc *); 105 int mskcprint(void *, const char *); 106 int msk_intr(void *); 107 void msk_intr_yukon(struct sk_if_softc *); 108 void msk_rxeof(struct sk_if_softc *, uint16_t, uint32_t); 109 void msk_txeof(struct sk_if_softc *); 110 int msk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 111 void msk_start(struct ifnet *); 112 int msk_ioctl(struct ifnet *, u_long, void *); 113 int msk_init(struct ifnet *); 114 void msk_init_yukon(struct sk_if_softc *); 115 void msk_stop(struct ifnet *, int); 116 void msk_watchdog(struct ifnet *); 117 int msk_newbuf(struct sk_if_softc *, bus_dmamap_t); 118 int msk_alloc_jumbo_mem(struct sk_if_softc *); 119 void *msk_jalloc(struct sk_if_softc *); 120 void msk_jfree(struct mbuf *, void *, size_t, void *); 121 int msk_init_rx_ring(struct sk_if_softc *); 122 int msk_init_tx_ring(struct sk_if_softc *); 123 void msk_fill_rx_ring(struct sk_if_softc *); 124 125 void msk_update_int_mod(struct sk_softc *, int); 126 127 int msk_miibus_readreg(device_t, int, int, uint16_t *); 128 int msk_miibus_writereg(device_t, int, int, uint16_t); 129 void msk_miibus_statchg(struct ifnet *); 130 131 void msk_setmulti(struct sk_if_softc *); 132 void msk_setpromisc(struct sk_if_softc *); 133 void msk_tick(void *); 134 static void msk_fill_rx_tick(void *); 135 136 /* #define MSK_DEBUG 1 */ 137 #ifdef MSK_DEBUG 138 #define DPRINTF(x) if (mskdebug) printf x 139 #define DPRINTFN(n, x) if (mskdebug >= (n)) printf x 140 int mskdebug = MSK_DEBUG; 141 142 void msk_dump_txdesc(struct msk_tx_desc *, int); 143 void msk_dump_mbuf(struct mbuf *); 144 void msk_dump_bytes(const char *, int); 145 #else 146 #define DPRINTF(x) 147 #define DPRINTFN(n, x) 148 #endif 149 150 static int msk_sysctl_handler(SYSCTLFN_PROTO); 151 static int msk_root_num; 152 153 #define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL) 154 #define MSK_ADDR_HI(x) ((uint64_t) (x) >> 32) 155 156 /* supported device vendors */ 157 static const struct msk_product { 158 pci_vendor_id_t msk_vendor; 159 pci_product_id_t msk_product; 160 } msk_products[] = { 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 163 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 164 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8079 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 197 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 198 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 199 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 200 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 201 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 }, 202 { 0, 0 } 203 }; 204 205 static inline uint32_t 206 sk_win_read_4(struct sk_softc *sc, uint32_t reg) 207 { 208 return CSR_READ_4(sc, reg); 209 } 210 211 static inline uint16_t 212 sk_win_read_2(struct sk_softc *sc, uint32_t reg) 213 { 214 return CSR_READ_2(sc, reg); 215 } 216 217 static inline uint8_t 218 sk_win_read_1(struct sk_softc *sc, uint32_t reg) 219 { 220 return CSR_READ_1(sc, reg); 221 } 222 223 static inline void 224 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x) 225 { 226 CSR_WRITE_4(sc, reg, x); 227 } 228 229 static inline void 230 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x) 231 { 232 CSR_WRITE_2(sc, reg, x); 233 } 234 235 static inline void 236 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x) 237 { 238 CSR_WRITE_1(sc, reg, x); 239 } 240 241 int 242 msk_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 243 { 244 struct sk_if_softc *sc_if = device_private(dev); 245 uint16_t data; 246 int i; 247 248 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 249 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 250 251 for (i = 0; i < SK_TIMEOUT; i++) { 252 DELAY(1); 253 data = SK_YU_READ_2(sc_if, YUKON_SMICR); 254 if (data & YU_SMICR_READ_VALID) 255 break; 256 } 257 258 if (i == SK_TIMEOUT) { 259 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 260 return ETIMEDOUT; 261 } 262 263 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, SK_TIMEOUT)); 264 265 *val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 266 267 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#hx\n", 268 phy, reg, *val)); 269 270 return 0; 271 } 272 273 int 274 msk_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 275 { 276 struct sk_if_softc *sc_if = device_private(dev); 277 int i; 278 279 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#hx\n", 280 phy, reg, val)); 281 282 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 283 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 284 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 285 286 for (i = 0; i < SK_TIMEOUT; i++) { 287 DELAY(1); 288 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 289 break; 290 } 291 292 if (i == SK_TIMEOUT) { 293 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 294 return ETIMEDOUT; 295 } 296 297 return 0; 298 } 299 300 void 301 msk_miibus_statchg(struct ifnet *ifp) 302 { 303 struct sk_if_softc *sc_if = ifp->if_softc; 304 struct mii_data *mii = &sc_if->sk_mii; 305 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 306 int gpcr; 307 308 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 309 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 310 311 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 312 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 313 /* Set speed. */ 314 gpcr |= YU_GPCR_SPEED_DIS; 315 switch (IFM_SUBTYPE(mii->mii_media_active)) { 316 case IFM_1000_SX: 317 case IFM_1000_LX: 318 case IFM_1000_CX: 319 case IFM_1000_T: 320 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 321 break; 322 case IFM_100_TX: 323 gpcr |= YU_GPCR_SPEED; 324 break; 325 } 326 327 /* Set duplex. */ 328 gpcr |= YU_GPCR_DPLX_DIS; 329 if ((mii->mii_media_active & IFM_FDX) != 0) 330 gpcr |= YU_GPCR_DUPLEX; 331 332 /* Disable flow control. */ 333 gpcr |= YU_GPCR_FCTL_DIS; 334 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 335 } 336 337 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 338 339 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 340 SK_YU_READ_2(sc_if, YUKON_GPCR))); 341 } 342 343 void 344 msk_setmulti(struct sk_if_softc *sc_if) 345 { 346 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 347 uint32_t hashes[2] = { 0, 0 }; 348 int h; 349 struct ethercom *ec = &sc_if->sk_ethercom; 350 struct ether_multi *enm; 351 struct ether_multistep step; 352 uint16_t reg; 353 354 /* First, zot all the existing filters. */ 355 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 356 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 357 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 358 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 359 360 361 /* Now program new ones. */ 362 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 363 reg |= YU_RCR_UFLEN; 364 allmulti: 365 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 366 if ((ifp->if_flags & IFF_PROMISC) != 0) 367 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 368 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 369 hashes[0] = 0xFFFFFFFF; 370 hashes[1] = 0xFFFFFFFF; 371 } 372 } else { 373 /* First find the tail of the list. */ 374 ETHER_LOCK(ec); 375 ETHER_FIRST_MULTI(step, ec, enm); 376 while (enm != NULL) { 377 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 378 ETHER_ADDR_LEN)) { 379 ifp->if_flags |= IFF_ALLMULTI; 380 ETHER_UNLOCK(ec); 381 goto allmulti; 382 } 383 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 384 ((1 << SK_HASH_BITS) - 1); 385 if (h < 32) 386 hashes[0] |= (1 << h); 387 else 388 hashes[1] |= (1 << (h - 32)); 389 390 ETHER_NEXT_MULTI(step, enm); 391 } 392 ETHER_UNLOCK(ec); 393 reg |= YU_RCR_MUFLEN; 394 } 395 396 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 397 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 398 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 399 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 400 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 401 } 402 403 void 404 msk_setpromisc(struct sk_if_softc *sc_if) 405 { 406 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 407 408 if (ifp->if_flags & IFF_PROMISC) 409 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 410 YU_RCR_UFLEN | YU_RCR_MUFLEN); 411 else 412 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 413 YU_RCR_UFLEN | YU_RCR_MUFLEN); 414 } 415 416 int 417 msk_init_rx_ring(struct sk_if_softc *sc_if) 418 { 419 struct msk_chain_data *cd = &sc_if->sk_cdata; 420 struct msk_ring_data *rd = sc_if->sk_rdata; 421 struct msk_rx_desc *r; 422 int i, nexti; 423 424 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 425 426 for (i = 0; i < MSK_RX_RING_CNT; i++) { 427 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 428 if (i == (MSK_RX_RING_CNT - 1)) 429 nexti = 0; 430 else 431 nexti = i + 1; 432 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 433 } 434 435 sc_if->sk_cdata.sk_rx_prod = 0; 436 sc_if->sk_cdata.sk_rx_cons = 0; 437 sc_if->sk_cdata.sk_rx_cnt = 0; 438 sc_if->sk_cdata.sk_rx_hiaddr = 0; 439 440 /* Mark the first ring element to initialize the high address. */ 441 sc_if->sk_cdata.sk_rx_hiaddr = 0; 442 r = &rd->sk_rx_ring[cd->sk_rx_prod]; 443 r->sk_addr = htole32(cd->sk_rx_hiaddr); 444 r->sk_len = 0; 445 r->sk_ctl = 0; 446 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN; 447 MSK_CDRXSYNC(sc_if, cd->sk_rx_prod, 448 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 449 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 450 sc_if->sk_cdata.sk_rx_cnt++; 451 452 msk_fill_rx_ring(sc_if); 453 return 0; 454 } 455 456 int 457 msk_init_tx_ring(struct sk_if_softc *sc_if) 458 { 459 struct sk_softc *sc = sc_if->sk_softc; 460 struct msk_chain_data *cd = &sc_if->sk_cdata; 461 struct msk_ring_data *rd = sc_if->sk_rdata; 462 struct msk_tx_desc *t; 463 bus_dmamap_t dmamap; 464 struct sk_txmap_entry *entry; 465 int i, nexti; 466 467 memset(rd->sk_tx_ring, 0, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 468 469 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 470 for (i = 0; i < MSK_TX_RING_CNT; i++) { 471 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 472 if (i == (MSK_TX_RING_CNT - 1)) 473 nexti = 0; 474 else 475 nexti = i + 1; 476 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 477 478 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 479 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 480 return ENOBUFS; 481 482 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 483 if (!entry) { 484 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 485 return ENOBUFS; 486 } 487 entry->dmamap = dmamap; 488 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 489 } 490 491 sc_if->sk_cdata.sk_tx_prod = 0; 492 sc_if->sk_cdata.sk_tx_cons = 0; 493 sc_if->sk_cdata.sk_tx_cnt = 0; 494 sc_if->sk_cdata.sk_tx_hiaddr = 0; 495 496 /* Mark the first ring element to initialize the high address. */ 497 sc_if->sk_cdata.sk_tx_hiaddr = 0; 498 t = &rd->sk_tx_ring[cd->sk_tx_prod]; 499 t->sk_addr = htole32(cd->sk_tx_hiaddr); 500 t->sk_len = 0; 501 t->sk_ctl = 0; 502 t->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 503 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 504 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 505 SK_INC(sc_if->sk_cdata.sk_tx_prod, MSK_TX_RING_CNT); 506 sc_if->sk_cdata.sk_tx_cnt++; 507 508 return 0; 509 } 510 511 int 512 msk_newbuf(struct sk_if_softc *sc_if, bus_dmamap_t dmamap) 513 { 514 struct mbuf *m_new = NULL; 515 struct sk_chain *c; 516 struct msk_rx_desc *r; 517 void *buf = NULL; 518 bus_addr_t addr; 519 520 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 521 if (m_new == NULL) 522 return ENOBUFS; 523 524 /* Allocate the jumbo buffer */ 525 buf = msk_jalloc(sc_if); 526 if (buf == NULL) { 527 m_freem(m_new); 528 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 529 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 530 return ENOBUFS; 531 } 532 533 /* Attach the buffer to the mbuf */ 534 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 535 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 536 537 m_adj(m_new, ETHER_ALIGN); 538 539 addr = dmamap->dm_segs[0].ds_addr + 540 ((vaddr_t)m_new->m_data - 541 (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf); 542 543 if (sc_if->sk_cdata.sk_rx_hiaddr != MSK_ADDR_HI(addr)) { 544 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 545 r = c->sk_le; 546 c->sk_mbuf = NULL; 547 r->sk_addr = htole32(MSK_ADDR_HI(addr)); 548 r->sk_len = 0; 549 r->sk_ctl = 0; 550 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN; 551 sc_if->sk_cdata.sk_rx_hiaddr = MSK_ADDR_HI(addr); 552 553 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 554 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 555 556 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 557 sc_if->sk_cdata.sk_rx_cnt++; 558 559 DPRINTFN(10, ("%s: rx ADDR64: %#x\n", 560 sc_if->sk_ethercom.ec_if.if_xname, 561 (unsigned)MSK_ADDR_HI(addr))); 562 } 563 564 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 565 r = c->sk_le; 566 c->sk_mbuf = m_new; 567 r->sk_addr = htole32(MSK_ADDR_LO(addr)); 568 r->sk_len = htole16(SK_JLEN); 569 r->sk_ctl = 0; 570 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 571 572 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 573 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 574 575 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 576 sc_if->sk_cdata.sk_rx_cnt++; 577 578 return 0; 579 } 580 581 /* 582 * Memory management for jumbo frames. 583 */ 584 585 int 586 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 587 { 588 struct sk_softc *sc = sc_if->sk_softc; 589 char *ptr, *kva; 590 int i, state, error; 591 struct sk_jpool_entry *entry; 592 593 state = error = 0; 594 595 /* Grab a big chunk o' storage. */ 596 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 597 &sc_if->sk_cdata.sk_jumbo_seg, 1, &sc_if->sk_cdata.sk_jumbo_nseg, 598 BUS_DMA_NOWAIT)) { 599 aprint_error(": can't alloc rx buffers"); 600 return ENOBUFS; 601 } 602 603 state = 1; 604 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 605 sc_if->sk_cdata.sk_jumbo_nseg, MSK_JMEM, (void **)&kva, 606 BUS_DMA_NOWAIT)) { 607 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 608 error = ENOBUFS; 609 goto out; 610 } 611 612 state = 2; 613 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 614 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 615 aprint_error(": can't create dma map"); 616 error = ENOBUFS; 617 goto out; 618 } 619 620 state = 3; 621 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 622 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 623 aprint_error(": can't load dma map"); 624 error = ENOBUFS; 625 goto out; 626 } 627 628 state = 4; 629 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 630 DPRINTFN(1,("msk_jumbo_buf = %p\n", 631 (void *)sc_if->sk_cdata.sk_jumbo_buf)); 632 633 LIST_INIT(&sc_if->sk_jfree_listhead); 634 LIST_INIT(&sc_if->sk_jinuse_listhead); 635 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 636 637 /* 638 * Now divide it up into 9K pieces and save the addresses 639 * in an array. 640 */ 641 ptr = sc_if->sk_cdata.sk_jumbo_buf; 642 for (i = 0; i < MSK_JSLOTS; i++) { 643 sc_if->sk_cdata.sk_jslots[i] = ptr; 644 ptr += SK_JLEN; 645 entry = malloc(sizeof(struct sk_jpool_entry), 646 M_DEVBUF, M_NOWAIT); 647 if (entry == NULL) { 648 sc_if->sk_cdata.sk_jumbo_buf = NULL; 649 aprint_error(": no memory for jumbo buffer queue!"); 650 error = ENOBUFS; 651 goto out; 652 } 653 entry->slot = i; 654 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 655 entry, jpool_entries); 656 } 657 out: 658 if (error != 0) { 659 switch (state) { 660 case 4: 661 bus_dmamap_unload(sc->sc_dmatag, 662 sc_if->sk_cdata.sk_rx_jumbo_map); 663 /* FALLTHROUGH */ 664 case 3: 665 bus_dmamap_destroy(sc->sc_dmatag, 666 sc_if->sk_cdata.sk_rx_jumbo_map); 667 /* FALLTHROUGH */ 668 case 2: 669 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 670 /* FALLTHROUGH */ 671 case 1: 672 bus_dmamem_free(sc->sc_dmatag, 673 &sc_if->sk_cdata.sk_jumbo_seg, 674 sc_if->sk_cdata.sk_jumbo_nseg); 675 break; 676 default: 677 break; 678 } 679 } 680 681 return error; 682 } 683 684 static void 685 msk_free_jumbo_mem(struct sk_if_softc *sc_if) 686 { 687 struct sk_softc *sc = sc_if->sk_softc; 688 689 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 690 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 691 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_cdata.sk_jumbo_buf, MSK_JMEM); 692 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 693 sc_if->sk_cdata.sk_jumbo_nseg); 694 } 695 696 /* 697 * Allocate a jumbo buffer. 698 */ 699 void * 700 msk_jalloc(struct sk_if_softc *sc_if) 701 { 702 struct sk_jpool_entry *entry; 703 704 mutex_enter(&sc_if->sk_jpool_mtx); 705 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 706 707 if (entry == NULL) { 708 mutex_exit(&sc_if->sk_jpool_mtx); 709 return NULL; 710 } 711 712 LIST_REMOVE(entry, jpool_entries); 713 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 714 mutex_exit(&sc_if->sk_jpool_mtx); 715 return sc_if->sk_cdata.sk_jslots[entry->slot]; 716 } 717 718 /* 719 * Release a jumbo buffer. 720 */ 721 void 722 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 723 { 724 struct sk_jpool_entry *entry; 725 struct sk_if_softc *sc; 726 int i; 727 728 /* Extract the softc struct pointer. */ 729 sc = (struct sk_if_softc *)arg; 730 731 if (sc == NULL) 732 panic("msk_jfree: can't find softc pointer!"); 733 734 /* calculate the slot this buffer belongs to */ 735 i = ((vaddr_t)buf 736 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 737 738 if ((i < 0) || (i >= MSK_JSLOTS)) 739 panic("msk_jfree: asked to free buffer that we don't manage!"); 740 741 mutex_enter(&sc->sk_jpool_mtx); 742 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 743 if (entry == NULL) 744 panic("msk_jfree: buffer not in use!"); 745 entry->slot = i; 746 LIST_REMOVE(entry, jpool_entries); 747 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 748 mutex_exit(&sc->sk_jpool_mtx); 749 750 if (__predict_true(m != NULL)) 751 pool_cache_put(mb_cache, m); 752 753 /* Now that we know we have a free RX buffer, refill if running out */ 754 if ((sc->sk_ethercom.ec_if.if_flags & IFF_RUNNING) != 0 755 && sc->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 756 callout_schedule(&sc->sk_tick_rx, 0); 757 } 758 759 int 760 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 761 { 762 struct sk_if_softc *sc = ifp->if_softc; 763 int s, error; 764 765 s = splnet(); 766 767 DPRINTFN(2, ("msk_ioctl ETHER cmd %lx\n", cmd)); 768 switch (cmd) { 769 case SIOCSIFFLAGS: 770 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 771 break; 772 773 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 774 case IFF_RUNNING: 775 msk_stop(ifp, 1); 776 break; 777 case IFF_UP: 778 msk_init(ifp); 779 break; 780 case IFF_UP | IFF_RUNNING: 781 if ((ifp->if_flags ^ sc->sk_if_flags) == IFF_PROMISC) { 782 msk_setpromisc(sc); 783 msk_setmulti(sc); 784 } else 785 msk_init(ifp); 786 break; 787 } 788 sc->sk_if_flags = ifp->if_flags; 789 break; 790 default: 791 error = ether_ioctl(ifp, cmd, data); 792 if (error == ENETRESET) { 793 error = 0; 794 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 795 ; 796 else if (ifp->if_flags & IFF_RUNNING) { 797 /* 798 * Multicast list has changed; set the hardware 799 * filter accordingly. 800 */ 801 msk_setmulti(sc); 802 } 803 } 804 break; 805 } 806 807 splx(s); 808 return error; 809 } 810 811 void 812 msk_update_int_mod(struct sk_softc *sc, int verbose) 813 { 814 uint32_t imtimer_ticks; 815 816 /* 817 * Configure interrupt moderation. The moderation timer 818 * defers interrupts specified in the interrupt moderation 819 * timer mask based on the timeout specified in the interrupt 820 * moderation timer init register. Each bit in the timer 821 * register represents one tick, so to specify a timeout in 822 * microseconds, we have to multiply by the correct number of 823 * ticks-per-microsecond. 824 */ 825 switch (sc->sk_type) { 826 case SK_YUKON_EC: 827 case SK_YUKON_EC_U: 828 case SK_YUKON_EX: 829 case SK_YUKON_SUPR: 830 case SK_YUKON_ULTRA2: 831 case SK_YUKON_OPTIMA: 832 case SK_YUKON_PRM: 833 case SK_YUKON_OPTIMA2: 834 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 835 break; 836 case SK_YUKON_FE: 837 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 838 break; 839 case SK_YUKON_FE_P: 840 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 841 break; 842 case SK_YUKON_XL: 843 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 844 break; 845 default: 846 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 847 } 848 if (verbose) 849 aprint_verbose_dev(sc->sk_dev, 850 "interrupt moderation is %d us\n", sc->sk_int_mod); 851 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 852 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF | SK_ISR_TX2_S_EOF | 853 SK_ISR_RX1_EOF | SK_ISR_RX2_EOF); 854 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 855 sc->sk_int_mod_pending = 0; 856 } 857 858 static int 859 msk_lookup(const struct pci_attach_args *pa) 860 { 861 const struct msk_product *pmsk; 862 863 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 864 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 865 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 866 return 1; 867 } 868 return 0; 869 } 870 871 /* 872 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 873 * IDs against our list and return a device name if we find a match. 874 */ 875 int 876 mskc_probe(device_t parent, cfdata_t match, void *aux) 877 { 878 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 879 880 return msk_lookup(pa); 881 } 882 883 /* 884 * Force the GEnesis into reset, then bring it out of reset. 885 */ 886 void 887 mskc_reset(struct sk_softc *sc) 888 { 889 uint32_t imtimer_ticks, reg1; 890 uint16_t status; 891 int reg; 892 893 DPRINTFN(2, ("mskc_reset\n")); 894 895 /* Disable ASF */ 896 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_SUPR)) { 897 CSR_WRITE_4(sc, SK_Y2_CPU_WDOG, 0); 898 status = CSR_READ_2(sc, SK_Y2_ASF_HCU_CCSR); 899 /* Clear AHB bridge & microcontroller reset. */ 900 status &= ~(SK_Y2_ASF_HCU_CSSR_ARB_RST | 901 SK_Y2_ASF_HCU_CSSR_CPU_RST_MODE); 902 /* Clear ASF microcontroller state. */ 903 status &= ~SK_Y2_ASF_HCU_CSSR_UC_STATE_MSK; 904 status &= ~SK_Y2_ASF_HCU_CSSR_CPU_CLK_DIVIDE_MSK; 905 CSR_WRITE_2(sc, SK_Y2_ASF_HCU_CCSR, status); 906 CSR_WRITE_4(sc, SK_Y2_CPU_WDOG, 0); 907 } else 908 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 909 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 910 911 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 912 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 913 914 DELAY(1000); 915 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 916 DELAY(2); 917 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 918 sk_win_write_1(sc, SK_TESTCTL1, 2); 919 920 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 921 sc->sk_type >= SK_YUKON_FE_P) { 922 uint32_t our; 923 924 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 925 926 /* enable all clocks. */ 927 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 928 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 929 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST | 930 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN | 931 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY | 932 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 933 /* Set all bits to 0 except bits 15..12 */ 934 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 935 /* Set to default value */ 936 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 937 938 /* 939 * Disable status race, workaround for Yukon EC Ultra & 940 * Yukon EX. 941 */ 942 reg1 = sk_win_read_4(sc, SK_GPIO); 943 reg1 |= SK_Y2_GPIO_STAT_RACE_DIS; 944 sk_win_write_4(sc, SK_GPIO, reg1); 945 sk_win_read_4(sc, SK_GPIO); 946 } 947 948 /* release PHY from PowerDown/Coma mode. */ 949 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 950 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 951 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 952 else 953 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 954 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 955 956 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 957 sk_win_write_1(sc, SK_Y2_CLKGATE, 958 SK_Y2_CLKGATE_LINK1_GATE_DIS | 959 SK_Y2_CLKGATE_LINK2_GATE_DIS | 960 SK_Y2_CLKGATE_LINK1_CORE_DIS | 961 SK_Y2_CLKGATE_LINK2_CORE_DIS | 962 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 963 else 964 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 965 966 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 967 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 968 DELAY(1000); 969 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 970 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 971 972 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 973 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 974 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 975 } 976 977 sk_win_write_1(sc, SK_TESTCTL1, 1); 978 979 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 980 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 981 CSR_READ_2(sc, SK_LINK_CTRL))); 982 983 /* Clear I2C IRQ noise */ 984 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 985 986 /* Disable hardware timer */ 987 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 988 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 989 990 /* Disable descriptor polling */ 991 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 992 993 /* Disable time stamps */ 994 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 995 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 996 997 /* Enable RAM interface */ 998 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 999 for (reg = SK_TO0;reg <= SK_TO11; reg++) 1000 sk_win_write_1(sc, reg, 36); 1001 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 1002 for (reg = SK_TO0;reg <= SK_TO11; reg++) 1003 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 1004 1005 /* 1006 * Configure interrupt moderation. The moderation timer 1007 * defers interrupts specified in the interrupt moderation 1008 * timer mask based on the timeout specified in the interrupt 1009 * moderation timer init register. Each bit in the timer 1010 * register represents one tick, so to specify a timeout in 1011 * microseconds, we have to multiply by the correct number of 1012 * ticks-per-microsecond. 1013 */ 1014 switch (sc->sk_type) { 1015 case SK_YUKON_EC: 1016 case SK_YUKON_EC_U: 1017 case SK_YUKON_EX: 1018 case SK_YUKON_SUPR: 1019 case SK_YUKON_ULTRA2: 1020 case SK_YUKON_OPTIMA: 1021 case SK_YUKON_PRM: 1022 case SK_YUKON_OPTIMA2: 1023 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1024 break; 1025 case SK_YUKON_FE: 1026 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 1027 break; 1028 case SK_YUKON_FE_P: 1029 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 1030 break; 1031 case SK_YUKON_XL: 1032 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 1033 break; 1034 default: 1035 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1036 break; 1037 } 1038 1039 /* Reset status ring. */ 1040 memset(sc->sk_status_ring, 0, 1041 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1042 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 1043 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1044 sc->sk_status_idx = 0; 1045 1046 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 1047 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 1048 1049 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 1050 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 1051 MSK_ADDR_LO(sc->sk_status_map->dm_segs[0].ds_addr)); 1052 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 1053 MSK_ADDR_HI(sc->sk_status_map->dm_segs[0].ds_addr)); 1054 if (sc->sk_type == SK_YUKON_EC && 1055 sc->sk_rev == SK_YUKON_EC_REV_A1) { 1056 /* WA for dev. #4.3 */ 1057 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 1058 SK_STAT_BMU_TXTHIDX_MSK); 1059 /* WA for dev. #4.18 */ 1060 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 1061 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 1062 } else { 1063 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 1064 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 1065 if (sc->sk_type == SK_YUKON_XL) 1066 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x04); 1067 else 1068 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x10); 1069 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 1070 } 1071 1072 #if 0 1073 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 1074 #endif 1075 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 1076 1077 /* Enable status unit. */ 1078 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 1079 1080 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 1081 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 1082 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 1083 1084 msk_update_int_mod(sc, 0); 1085 } 1086 1087 int 1088 msk_probe(device_t parent, cfdata_t match, void *aux) 1089 { 1090 struct skc_attach_args *sa = aux; 1091 1092 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1093 return 0; 1094 1095 switch (sa->skc_type) { 1096 case SK_YUKON_XL: 1097 case SK_YUKON_EC_U: 1098 case SK_YUKON_EX: 1099 case SK_YUKON_EC: 1100 case SK_YUKON_FE: 1101 case SK_YUKON_FE_P: 1102 case SK_YUKON_SUPR: 1103 case SK_YUKON_ULTRA2: 1104 case SK_YUKON_OPTIMA: 1105 case SK_YUKON_PRM: 1106 case SK_YUKON_OPTIMA2: 1107 return 1; 1108 } 1109 1110 return 0; 1111 } 1112 1113 void 1114 msk_reset(struct sk_if_softc *sc_if) 1115 { 1116 /* GMAC and GPHY Reset */ 1117 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1118 SK_IF_WRITE_1(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1119 DELAY(1000); 1120 SK_IF_WRITE_1(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1121 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1122 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1123 } 1124 1125 static bool 1126 msk_resume(device_t dv, const pmf_qual_t *qual) 1127 { 1128 struct sk_if_softc *sc_if = device_private(dv); 1129 1130 msk_init_yukon(sc_if); 1131 return true; 1132 } 1133 1134 /* 1135 * Each XMAC chip is attached as a separate logical IP interface. 1136 * Single port cards will have only one logical interface of course. 1137 */ 1138 void 1139 msk_attach(device_t parent, device_t self, void *aux) 1140 { 1141 struct sk_if_softc *sc_if = device_private(self); 1142 struct sk_softc *sc = device_private(parent); 1143 struct skc_attach_args *sa = aux; 1144 struct ifnet *ifp; 1145 struct mii_data * const mii = &sc_if->sk_mii; 1146 void *kva; 1147 int i; 1148 uint32_t chunk; 1149 int mii_flags; 1150 1151 sc_if->sk_dev = self; 1152 sc_if->sk_port = sa->skc_port; 1153 sc_if->sk_softc = sc; 1154 sc->sk_if[sa->skc_port] = sc_if; 1155 1156 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1157 1158 /* 1159 * Get station address for this interface. Note that 1160 * dual port cards actually come with three station 1161 * addresses: one for each port, plus an extra. The 1162 * extra one is used by the SysKonnect driver software 1163 * as a 'virtual' station address for when both ports 1164 * are operating in failover mode. Currently we don't 1165 * use this extra address. 1166 */ 1167 for (i = 0; i < ETHER_ADDR_LEN; i++) 1168 sc_if->sk_enaddr[i] = 1169 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1170 1171 aprint_normal(": Ethernet address %s\n", 1172 ether_sprintf(sc_if->sk_enaddr)); 1173 1174 /* 1175 * Set up RAM buffer addresses. The Yukon2 has a small amount 1176 * of SRAM on it, somewhere between 4K and 48K. We need to 1177 * divide this up between the transmitter and receiver. We 1178 * give the receiver 2/3 of the memory (rounded down), and the 1179 * transmitter whatever remains. 1180 */ 1181 if (sc->sk_ramsize) { 1182 chunk = (2 * (sc->sk_ramsize / sizeof(uint64_t)) / 3) & ~0xff; 1183 sc_if->sk_rx_ramstart = 0; 1184 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 1185 chunk = (sc->sk_ramsize / sizeof(uint64_t)) - chunk; 1186 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 1187 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 1188 1189 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1190 " tx_ramstart=%#x tx_ramend=%#x\n", 1191 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1192 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1193 } 1194 1195 /* Allocate the descriptor queues. */ 1196 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1197 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 1198 BUS_DMA_NOWAIT)) { 1199 aprint_error(": can't alloc rx buffers\n"); 1200 goto fail; 1201 } 1202 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 1203 sc_if->sk_ring_nseg, 1204 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1205 aprint_error(": can't map dma buffers (%zu bytes)\n", 1206 sizeof(struct msk_ring_data)); 1207 goto fail_1; 1208 } 1209 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1210 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1211 &sc_if->sk_ring_map)) { 1212 aprint_error(": can't create dma map\n"); 1213 goto fail_2; 1214 } 1215 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1216 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1217 aprint_error(": can't load dma map\n"); 1218 goto fail_3; 1219 } 1220 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1221 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1222 1223 if (sc->sk_type != SK_YUKON_FE && 1224 sc->sk_type != SK_YUKON_FE_P) 1225 sc_if->sk_pktlen = SK_JLEN; 1226 else 1227 sc_if->sk_pktlen = MCLBYTES; 1228 1229 /* Try to allocate memory for jumbo buffers. */ 1230 if (msk_alloc_jumbo_mem(sc_if)) { 1231 aprint_error(": jumbo buffer allocation failed\n"); 1232 goto fail_3; 1233 } 1234 1235 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1236 if (sc->sk_type != SK_YUKON_FE && 1237 sc->sk_type != SK_YUKON_FE_P) 1238 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1239 1240 ifp = &sc_if->sk_ethercom.ec_if; 1241 ifp->if_softc = sc_if; 1242 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1243 ifp->if_ioctl = msk_ioctl; 1244 ifp->if_start = msk_start; 1245 ifp->if_stop = msk_stop; 1246 ifp->if_init = msk_init; 1247 ifp->if_watchdog = msk_watchdog; 1248 ifp->if_baudrate = 1000000000; 1249 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1250 IFQ_SET_READY(&ifp->if_snd); 1251 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1252 1253 msk_reset(sc_if); 1254 1255 /* 1256 * Do miibus setup. 1257 */ 1258 DPRINTFN(2, ("msk_attach: 1\n")); 1259 1260 mii->mii_ifp = ifp; 1261 mii->mii_readreg = msk_miibus_readreg; 1262 mii->mii_writereg = msk_miibus_writereg; 1263 mii->mii_statchg = msk_miibus_statchg; 1264 1265 sc_if->sk_ethercom.ec_mii = mii; 1266 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1267 mii_flags = MIIF_DOPAUSE; 1268 if (sc->sk_fibertype) 1269 mii_flags |= MIIF_HAVEFIBER; 1270 mii_attach(self, mii, 0xffffffff, 0, MII_OFFSET_ANY, mii_flags); 1271 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1272 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1273 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 1274 0, NULL); 1275 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 1276 } else 1277 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1278 1279 callout_init(&sc_if->sk_tick_ch, 0); 1280 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1281 callout_schedule(&sc_if->sk_tick_ch, hz); 1282 1283 callout_init(&sc_if->sk_tick_rx, 0); 1284 callout_setfunc(&sc_if->sk_tick_rx, msk_fill_rx_tick, sc_if); 1285 1286 /* 1287 * Call MI attach routines. 1288 */ 1289 if_attach(ifp); 1290 if_deferred_start_init(ifp, NULL); 1291 ether_ifattach(ifp, sc_if->sk_enaddr); 1292 1293 if (pmf_device_register(self, NULL, msk_resume)) 1294 pmf_class_network_register(self, ifp); 1295 else 1296 aprint_error_dev(self, "couldn't establish power handler\n"); 1297 1298 if (sc->rnd_attached++ == 0) { 1299 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1300 RND_TYPE_NET, RND_FLAG_DEFAULT); 1301 } 1302 1303 DPRINTFN(2, ("msk_attach: end\n")); 1304 return; 1305 1306 fail_3: 1307 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1308 fail_2: 1309 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1310 fail_1: 1311 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1312 fail: 1313 sc->sk_if[sa->skc_port] = NULL; 1314 } 1315 1316 int 1317 msk_detach(device_t self, int flags) 1318 { 1319 struct sk_if_softc *sc_if = device_private(self); 1320 struct sk_softc *sc = sc_if->sk_softc; 1321 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1322 1323 if (sc->sk_if[sc_if->sk_port] == NULL) 1324 return 0; 1325 1326 msk_stop(ifp, 1); 1327 1328 if (--sc->rnd_attached == 0) 1329 rnd_detach_source(&sc->rnd_source); 1330 1331 callout_halt(&sc_if->sk_tick_ch, NULL); 1332 callout_destroy(&sc_if->sk_tick_ch); 1333 1334 callout_halt(&sc_if->sk_tick_rx, NULL); 1335 callout_destroy(&sc_if->sk_tick_rx); 1336 1337 /* Detach any PHYs we might have. */ 1338 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1339 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1340 1341 /* Delete any remaining media. */ 1342 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY); 1343 1344 pmf_device_deregister(self); 1345 1346 ether_ifdetach(ifp); 1347 if_detach(ifp); 1348 1349 msk_free_jumbo_mem(sc_if); 1350 1351 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_rdata, 1352 sizeof(struct msk_ring_data)); 1353 bus_dmamem_free(sc->sc_dmatag, 1354 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1355 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1356 sc->sk_if[sc_if->sk_port] = NULL; 1357 1358 return 0; 1359 } 1360 1361 int 1362 mskcprint(void *aux, const char *pnp) 1363 { 1364 struct skc_attach_args *sa = aux; 1365 1366 if (pnp) 1367 aprint_normal("msk port %c at %s", 1368 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1369 else 1370 aprint_normal(" port %c", 1371 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1372 return UNCONF; 1373 } 1374 1375 /* 1376 * Attach the interface. Allocate softc structures, do ifmedia 1377 * setup and ethernet/BPF attach. 1378 */ 1379 void 1380 mskc_attach(device_t parent, device_t self, void *aux) 1381 { 1382 struct sk_softc *sc = device_private(self); 1383 struct pci_attach_args *pa = aux; 1384 struct skc_attach_args skca; 1385 pci_chipset_tag_t pc = pa->pa_pc; 1386 pcireg_t command, memtype; 1387 const char *intrstr = NULL; 1388 int rc, sk_nodenum; 1389 uint8_t hw, pmd; 1390 const char *revstr = NULL; 1391 const struct sysctlnode *node; 1392 void *kva; 1393 char intrbuf[PCI_INTRSTR_LEN]; 1394 1395 DPRINTFN(2, ("begin mskc_attach\n")); 1396 1397 sc->sk_dev = self; 1398 /* 1399 * Handle power management nonsense. 1400 */ 1401 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1402 1403 if (command == 0x01) { 1404 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1405 if (command & SK_PSTATE_MASK) { 1406 uint32_t iobase, membase, irq; 1407 1408 /* Save important PCI config data. */ 1409 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1410 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1411 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1412 1413 /* Reset the power state. */ 1414 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1415 "mode -- setting to D0\n", 1416 command & SK_PSTATE_MASK); 1417 command &= 0xFFFFFFFC; 1418 pci_conf_write(pc, pa->pa_tag, 1419 SK_PCI_PWRMGMTCTRL, command); 1420 1421 /* Restore PCI config data. */ 1422 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1423 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1424 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1425 } 1426 } 1427 1428 /* 1429 * Map control/status registers. 1430 */ 1431 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1432 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1433 &sc->sk_bhandle, NULL, &sc->sk_bsize)) { 1434 aprint_error(": can't map mem space\n"); 1435 return; 1436 } 1437 1438 if (pci_dma64_available(pa)) 1439 sc->sc_dmatag = pa->pa_dmat64; 1440 else 1441 sc->sc_dmatag = pa->pa_dmat; 1442 1443 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1444 command |= PCI_COMMAND_MASTER_ENABLE; 1445 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1446 1447 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1448 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1449 1450 /* bail out here if chip is not recognized */ 1451 if (!(SK_IS_YUKON2(sc))) { 1452 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1453 goto fail_1; 1454 } 1455 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1456 1457 /* Allocate interrupt */ 1458 if (pci_intr_alloc(pa, &sc->sk_pihp, NULL, 0)) { 1459 aprint_error(": couldn't map interrupt\n"); 1460 goto fail_1; 1461 } 1462 1463 intrstr = pci_intr_string(pc, sc->sk_pihp[0], intrbuf, sizeof(intrbuf)); 1464 sc->sk_intrhand = pci_intr_establish_xname(pc, sc->sk_pihp[0], IPL_NET, 1465 msk_intr, sc, device_xname(sc->sk_dev)); 1466 if (sc->sk_intrhand == NULL) { 1467 aprint_error(": couldn't establish interrupt"); 1468 if (intrstr != NULL) 1469 aprint_error(" at %s", intrstr); 1470 aprint_error("\n"); 1471 goto fail_1; 1472 } 1473 sc->sk_pc = pc; 1474 1475 if (bus_dmamem_alloc(sc->sc_dmatag, 1476 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1477 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1478 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, BUS_DMA_NOWAIT)) { 1479 aprint_error(": can't alloc status buffers\n"); 1480 goto fail_2; 1481 } 1482 1483 if (bus_dmamem_map(sc->sc_dmatag, 1484 &sc->sk_status_seg, sc->sk_status_nseg, 1485 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1486 &kva, BUS_DMA_NOWAIT)) { 1487 aprint_error(": can't map dma buffers (%zu bytes)\n", 1488 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1489 goto fail_3; 1490 } 1491 if (bus_dmamap_create(sc->sc_dmatag, 1492 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1493 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1494 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1495 aprint_error(": can't create dma map\n"); 1496 goto fail_4; 1497 } 1498 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1499 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1500 NULL, BUS_DMA_NOWAIT)) { 1501 aprint_error(": can't load dma map\n"); 1502 goto fail_5; 1503 } 1504 sc->sk_status_ring = (struct msk_status_desc *)kva; 1505 1506 sc->sk_int_mod = SK_IM_DEFAULT; 1507 sc->sk_int_mod_pending = 0; 1508 1509 /* Reset the adapter. */ 1510 mskc_reset(sc); 1511 1512 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1513 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1514 1515 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1516 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1517 sc->sk_fibertype = 1; 1518 1519 switch (sc->sk_type) { 1520 case SK_YUKON_XL: 1521 sc->sk_name = "Yukon-2 XL"; 1522 break; 1523 case SK_YUKON_EC_U: 1524 sc->sk_name = "Yukon-2 EC Ultra"; 1525 break; 1526 case SK_YUKON_EX: 1527 sc->sk_name = "Yukon-2 Extreme"; 1528 break; 1529 case SK_YUKON_EC: 1530 sc->sk_name = "Yukon-2 EC"; 1531 break; 1532 case SK_YUKON_FE: 1533 sc->sk_name = "Yukon-2 FE"; 1534 break; 1535 case SK_YUKON_FE_P: 1536 sc->sk_name = "Yukon-2 FE+"; 1537 break; 1538 case SK_YUKON_SUPR: 1539 sc->sk_name = "Yukon-2 Supreme"; 1540 break; 1541 case SK_YUKON_ULTRA2: 1542 sc->sk_name = "Yukon-2 Ultra 2"; 1543 break; 1544 case SK_YUKON_OPTIMA: 1545 sc->sk_name = "Yukon-2 Optima"; 1546 break; 1547 case SK_YUKON_PRM: 1548 sc->sk_name = "Yukon-2 Optima Prime"; 1549 break; 1550 case SK_YUKON_OPTIMA2: 1551 sc->sk_name = "Yukon-2 Optima 2"; 1552 break; 1553 default: 1554 sc->sk_name = "Yukon (Unknown)"; 1555 } 1556 1557 if (sc->sk_type == SK_YUKON_XL) { 1558 switch (sc->sk_rev) { 1559 case SK_YUKON_XL_REV_A0: 1560 revstr = "A0"; 1561 break; 1562 case SK_YUKON_XL_REV_A1: 1563 revstr = "A1"; 1564 break; 1565 case SK_YUKON_XL_REV_A2: 1566 revstr = "A2"; 1567 break; 1568 case SK_YUKON_XL_REV_A3: 1569 revstr = "A3"; 1570 break; 1571 default: 1572 break; 1573 } 1574 } 1575 1576 if (sc->sk_type == SK_YUKON_EC) { 1577 switch (sc->sk_rev) { 1578 case SK_YUKON_EC_REV_A1: 1579 revstr = "A1"; 1580 break; 1581 case SK_YUKON_EC_REV_A2: 1582 revstr = "A2"; 1583 break; 1584 case SK_YUKON_EC_REV_A3: 1585 revstr = "A3"; 1586 break; 1587 default: 1588 break; 1589 } 1590 } 1591 1592 if (sc->sk_type == SK_YUKON_FE) { 1593 switch (sc->sk_rev) { 1594 case SK_YUKON_FE_REV_A1: 1595 revstr = "A1"; 1596 break; 1597 case SK_YUKON_FE_REV_A2: 1598 revstr = "A2"; 1599 break; 1600 default: 1601 break; 1602 } 1603 } 1604 1605 if (sc->sk_type == SK_YUKON_EC_U) { 1606 switch (sc->sk_rev) { 1607 case SK_YUKON_EC_U_REV_A0: 1608 revstr = "A0"; 1609 break; 1610 case SK_YUKON_EC_U_REV_A1: 1611 revstr = "A1"; 1612 break; 1613 case SK_YUKON_EC_U_REV_B0: 1614 revstr = "B0"; 1615 break; 1616 case SK_YUKON_EC_U_REV_B1: 1617 revstr = "B1"; 1618 break; 1619 default: 1620 break; 1621 } 1622 } 1623 1624 if (sc->sk_type == SK_YUKON_FE) { 1625 switch (sc->sk_rev) { 1626 case SK_YUKON_FE_REV_A1: 1627 revstr = "A1"; 1628 break; 1629 case SK_YUKON_FE_REV_A2: 1630 revstr = "A2"; 1631 break; 1632 default: 1633 ; 1634 } 1635 } 1636 1637 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1638 revstr = "A0"; 1639 1640 if (sc->sk_type == SK_YUKON_EX) { 1641 switch (sc->sk_rev) { 1642 case SK_YUKON_EX_REV_A0: 1643 revstr = "A0"; 1644 break; 1645 case SK_YUKON_EX_REV_B0: 1646 revstr = "B0"; 1647 break; 1648 default: 1649 ; 1650 } 1651 } 1652 1653 if (sc->sk_type == SK_YUKON_SUPR) { 1654 switch (sc->sk_rev) { 1655 case SK_YUKON_SUPR_REV_A0: 1656 revstr = "A0"; 1657 break; 1658 case SK_YUKON_SUPR_REV_B0: 1659 revstr = "B0"; 1660 break; 1661 case SK_YUKON_SUPR_REV_B1: 1662 revstr = "B1"; 1663 break; 1664 default: 1665 ; 1666 } 1667 } 1668 1669 if (sc->sk_type == SK_YUKON_PRM) { 1670 switch (sc->sk_rev) { 1671 case SK_YUKON_PRM_REV_Z1: 1672 revstr = "Z1"; 1673 break; 1674 case SK_YUKON_PRM_REV_A0: 1675 revstr = "A0"; 1676 break; 1677 default: 1678 ; 1679 } 1680 } 1681 1682 /* Announce the product name. */ 1683 aprint_normal(", %s", sc->sk_name); 1684 if (revstr != NULL) 1685 aprint_normal(" rev. %s", revstr); 1686 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1687 1688 sc->sk_macs = 1; 1689 1690 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1691 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1692 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1693 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1694 sc->sk_macs++; 1695 } 1696 1697 skca.skc_port = SK_PORT_A; 1698 skca.skc_type = sc->sk_type; 1699 skca.skc_rev = sc->sk_rev; 1700 (void)config_found(sc->sk_dev, &skca, mskcprint); 1701 1702 if (sc->sk_macs > 1) { 1703 skca.skc_port = SK_PORT_B; 1704 skca.skc_type = sc->sk_type; 1705 skca.skc_rev = sc->sk_rev; 1706 (void)config_found(sc->sk_dev, &skca, mskcprint); 1707 } 1708 1709 /* Turn on the 'driver is loaded' LED. */ 1710 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1711 1712 /* skc sysctl setup */ 1713 1714 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1715 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1716 SYSCTL_DESCR("mskc per-controller controls"), 1717 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1718 CTL_EOL)) != 0) { 1719 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1720 goto fail_6; 1721 } 1722 1723 sk_nodenum = node->sysctl_num; 1724 1725 /* interrupt moderation time in usecs */ 1726 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1727 CTLFLAG_READWRITE, 1728 CTLTYPE_INT, "int_mod", 1729 SYSCTL_DESCR("msk interrupt moderation timer"), 1730 msk_sysctl_handler, 0, (void *)sc, 1731 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1732 CTL_EOL)) != 0) { 1733 aprint_normal_dev(sc->sk_dev, 1734 "couldn't create int_mod sysctl node\n"); 1735 goto fail_6; 1736 } 1737 1738 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1739 aprint_error_dev(self, "couldn't establish power handler\n"); 1740 1741 return; 1742 1743 fail_6: 1744 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1745 fail_4: 1746 bus_dmamem_unmap(sc->sc_dmatag, kva, 1747 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1748 fail_3: 1749 bus_dmamem_free(sc->sc_dmatag, 1750 &sc->sk_status_seg, sc->sk_status_nseg); 1751 sc->sk_status_nseg = 0; 1752 fail_5: 1753 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1754 fail_2: 1755 pci_intr_disestablish(pc, sc->sk_intrhand); 1756 sc->sk_intrhand = NULL; 1757 fail_1: 1758 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1759 sc->sk_bsize = 0; 1760 } 1761 1762 int 1763 mskc_detach(device_t self, int flags) 1764 { 1765 struct sk_softc *sc = device_private(self); 1766 int rv; 1767 1768 if (sc->sk_intrhand) { 1769 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1770 sc->sk_intrhand = NULL; 1771 } 1772 1773 if (sc->sk_pihp != NULL) { 1774 pci_intr_release(sc->sk_pc, sc->sk_pihp, 1); 1775 sc->sk_pihp = NULL; 1776 } 1777 1778 rv = config_detach_children(self, flags); 1779 if (rv != 0) 1780 return rv; 1781 1782 if (sc->sk_status_nseg > 0) { 1783 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1784 bus_dmamem_unmap(sc->sc_dmatag, sc->sk_status_ring, 1785 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1786 bus_dmamem_free(sc->sc_dmatag, 1787 &sc->sk_status_seg, sc->sk_status_nseg); 1788 } 1789 1790 if (sc->sk_bsize > 0) 1791 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1792 1793 return 0; 1794 } 1795 1796 int 1797 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1798 { 1799 struct sk_softc *sc = sc_if->sk_softc; 1800 struct msk_tx_desc *f = NULL; 1801 uint32_t frag, cur, hiaddr, old_hiaddr, total; 1802 uint32_t entries = 0; 1803 size_t i; 1804 struct sk_txmap_entry *entry; 1805 bus_dmamap_t txmap; 1806 bus_addr_t addr; 1807 1808 DPRINTFN(2, ("msk_encap\n")); 1809 1810 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1811 if (entry == NULL) { 1812 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1813 return ENOBUFS; 1814 } 1815 txmap = entry->dmamap; 1816 1817 cur = frag = *txidx; 1818 1819 #ifdef MSK_DEBUG 1820 if (mskdebug >= 2) 1821 msk_dump_mbuf(m_head); 1822 #endif 1823 1824 /* 1825 * Start packing the mbufs in this chain into 1826 * the fragment pointers. Stop when we run out 1827 * of fragments or hit the end of the mbuf chain. 1828 */ 1829 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1830 BUS_DMA_NOWAIT)) { 1831 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1832 return ENOBUFS; 1833 } 1834 1835 /* Count how many tx descriptors needed. */ 1836 hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1837 for (total = i = 0; i < txmap->dm_nsegs; i++) { 1838 if (hiaddr != MSK_ADDR_HI(txmap->dm_segs[i].ds_addr)) { 1839 hiaddr = MSK_ADDR_HI(txmap->dm_segs[i].ds_addr); 1840 total++; 1841 } 1842 total++; 1843 } 1844 1845 if (total > MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2) { 1846 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1847 bus_dmamap_unload(sc->sc_dmatag, txmap); 1848 return ENOBUFS; 1849 } 1850 1851 DPRINTFN(2, ("msk_encap: dm_nsegs=%d total desc=%u\n", 1852 txmap->dm_nsegs, total)); 1853 1854 /* Sync the DMA map. */ 1855 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1856 BUS_DMASYNC_PREWRITE); 1857 1858 old_hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1859 for (i = 0; i < txmap->dm_nsegs; i++) { 1860 addr = txmap->dm_segs[i].ds_addr; 1861 DPRINTFN(2, ("msk_encap: addr %llx\n", 1862 (unsigned long long)addr)); 1863 hiaddr = MSK_ADDR_HI(addr); 1864 1865 if (sc_if->sk_cdata.sk_tx_hiaddr != hiaddr) { 1866 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1867 f->sk_addr = htole32(hiaddr); 1868 f->sk_len = 0; 1869 f->sk_ctl = 0; 1870 if (i == 0) 1871 f->sk_opcode = SK_Y2_BMUOPC_ADDR64; 1872 else 1873 f->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 1874 sc_if->sk_cdata.sk_tx_hiaddr = hiaddr; 1875 SK_INC(frag, MSK_TX_RING_CNT); 1876 entries++; 1877 DPRINTFN(10, ("%s: tx ADDR64: %#x\n", 1878 sc_if->sk_ethercom.ec_if.if_xname, hiaddr)); 1879 } 1880 1881 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1882 f->sk_addr = htole32(MSK_ADDR_LO(addr)); 1883 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1884 f->sk_ctl = 0; 1885 if (i == 0) { 1886 if (hiaddr != old_hiaddr) 1887 f->sk_opcode = SK_Y2_TXOPC_PACKET | SK_Y2_TXOPC_OWN; 1888 else 1889 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1890 } else 1891 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1892 cur = frag; 1893 SK_INC(frag, MSK_TX_RING_CNT); 1894 entries++; 1895 } 1896 KASSERTMSG(entries == total, "entries %u total %u", entries, total); 1897 1898 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1899 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1900 1901 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1902 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1903 1904 /* Sync descriptors before handing to chip */ 1905 MSK_CDTXSYNC(sc_if, *txidx, entries, 1906 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1907 1908 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1909 1910 /* Sync first descriptor to hand it off */ 1911 MSK_CDTXSYNC(sc_if, *txidx, 1, 1912 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1913 1914 sc_if->sk_cdata.sk_tx_cnt += entries; 1915 1916 #ifdef MSK_DEBUG 1917 if (mskdebug >= 2) { 1918 struct msk_tx_desc *le; 1919 uint32_t idx; 1920 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1921 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1922 msk_dump_txdesc(le, idx); 1923 } 1924 } 1925 #endif 1926 1927 *txidx = frag; 1928 1929 DPRINTFN(2, ("msk_encap: successful: %u entries\n", entries)); 1930 1931 return 0; 1932 } 1933 1934 void 1935 msk_start(struct ifnet *ifp) 1936 { 1937 struct sk_if_softc *sc_if = ifp->if_softc; 1938 struct mbuf *m_head = NULL; 1939 uint32_t idx = sc_if->sk_cdata.sk_tx_prod; 1940 int pkts = 0; 1941 1942 DPRINTFN(2, ("msk_start\n")); 1943 1944 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1945 IFQ_POLL(&ifp->if_snd, m_head); 1946 if (m_head == NULL) 1947 break; 1948 1949 /* 1950 * Pack the data into the transmit ring. If we 1951 * don't have room, set the OACTIVE flag and wait 1952 * for the NIC to drain the ring. 1953 */ 1954 if (msk_encap(sc_if, m_head, &idx)) { 1955 ifp->if_flags |= IFF_OACTIVE; 1956 break; 1957 } 1958 1959 /* now we are committed to transmit the packet */ 1960 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1961 pkts++; 1962 1963 /* 1964 * If there's a BPF listener, bounce a copy of this frame 1965 * to him. 1966 */ 1967 bpf_mtap(ifp, m_head, BPF_D_OUT); 1968 } 1969 if (pkts == 0) 1970 return; 1971 1972 /* Transmit */ 1973 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1974 sc_if->sk_cdata.sk_tx_prod = idx; 1975 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1976 1977 /* Set a timeout in case the chip goes out to lunch. */ 1978 ifp->if_timer = 5; 1979 } 1980 } 1981 1982 void 1983 msk_watchdog(struct ifnet *ifp) 1984 { 1985 struct sk_if_softc *sc_if = ifp->if_softc; 1986 1987 /* 1988 * Reclaim first as there is a possibility of losing Tx completion 1989 * interrupts. 1990 */ 1991 msk_txeof(sc_if); 1992 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1993 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1994 1995 ifp->if_oerrors++; 1996 1997 /* XXX Resets both ports; we shouldn't do that. */ 1998 mskc_reset(sc_if->sk_softc); 1999 msk_reset(sc_if); 2000 msk_init(ifp); 2001 } 2002 } 2003 2004 static bool 2005 mskc_suspend(device_t dv, const pmf_qual_t *qual) 2006 { 2007 struct sk_softc *sc = device_private(dv); 2008 2009 DPRINTFN(2, ("mskc_suspend\n")); 2010 2011 /* Turn off the 'driver is loaded' LED. */ 2012 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2013 2014 return true; 2015 } 2016 2017 static bool 2018 mskc_resume(device_t dv, const pmf_qual_t *qual) 2019 { 2020 struct sk_softc *sc = device_private(dv); 2021 2022 DPRINTFN(2, ("mskc_resume\n")); 2023 2024 mskc_reset(sc); 2025 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 2026 2027 return true; 2028 } 2029 2030 static __inline int 2031 msk_rxvalid(struct sk_softc *sc, uint32_t stat, uint32_t len) 2032 { 2033 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 2034 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 2035 YU_RXSTAT_JABBER)) != 0 || 2036 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 2037 YU_RXSTAT_BYTES(stat) != len) 2038 return 0; 2039 2040 return 1; 2041 } 2042 2043 void 2044 msk_rxeof(struct sk_if_softc *sc_if, uint16_t len, uint32_t rxstat) 2045 { 2046 struct sk_softc *sc = sc_if->sk_softc; 2047 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2048 struct mbuf *m; 2049 unsigned cur, prod, tail, total_len = len; 2050 bus_dmamap_t dmamap; 2051 2052 cur = sc_if->sk_cdata.sk_rx_cons; 2053 prod = sc_if->sk_cdata.sk_rx_prod; 2054 2055 /* Sync the descriptor */ 2056 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2057 2058 DPRINTFN(2, ("msk_rxeof: cur %u prod %u rx_cnt %u\n", cur, prod, 2059 sc_if->sk_cdata.sk_rx_cnt)); 2060 2061 while (prod != cur) { 2062 tail = cur; 2063 SK_INC(cur, MSK_RX_RING_CNT); 2064 2065 sc_if->sk_cdata.sk_rx_cnt--; 2066 m = sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf; 2067 sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf = NULL; 2068 if (m != NULL) 2069 break; /* found it */ 2070 } 2071 sc_if->sk_cdata.sk_rx_cons = cur; 2072 DPRINTFN(2, ("msk_rxeof: cur %u rx_cnt %u m %p\n", cur, 2073 sc_if->sk_cdata.sk_rx_cnt, m)); 2074 2075 if (m == NULL) 2076 return; 2077 2078 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2079 2080 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2081 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2082 2083 if (total_len < SK_MIN_FRAMELEN || 2084 total_len > ETHER_MAX_LEN_JUMBO || 2085 msk_rxvalid(sc, rxstat, total_len) == 0) { 2086 ifp->if_ierrors++; 2087 m_freem(m); 2088 return; 2089 } 2090 2091 m_set_rcvif(m, ifp); 2092 m->m_pkthdr.len = m->m_len = total_len; 2093 2094 /* pass it on. */ 2095 if_percpuq_enqueue(ifp->if_percpuq, m); 2096 } 2097 2098 void 2099 msk_txeof(struct sk_if_softc *sc_if) 2100 { 2101 struct sk_softc *sc = sc_if->sk_softc; 2102 struct msk_tx_desc *cur_tx; 2103 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2104 uint32_t idx, reg, sk_ctl; 2105 struct sk_txmap_entry *entry; 2106 2107 DPRINTFN(2, ("msk_txeof\n")); 2108 2109 if (sc_if->sk_port == SK_PORT_A) 2110 reg = SK_STAT_BMU_TXA1_RIDX; 2111 else 2112 reg = SK_STAT_BMU_TXA2_RIDX; 2113 2114 /* 2115 * Go through our tx ring and free mbufs for those 2116 * frames that have been sent. 2117 */ 2118 idx = sc_if->sk_cdata.sk_tx_cons; 2119 while (idx != sk_win_read_2(sc, reg)) { 2120 MSK_CDTXSYNC(sc_if, idx, 1, 2121 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2122 2123 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2124 sk_ctl = cur_tx->sk_ctl; 2125 #ifdef MSK_DEBUG 2126 if (mskdebug >= 2) 2127 msk_dump_txdesc(cur_tx, idx); 2128 #endif 2129 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 2130 ifp->if_opackets++; 2131 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2132 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2133 2134 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2135 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2136 2137 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2138 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2139 link); 2140 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2141 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2142 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2143 } 2144 sc_if->sk_cdata.sk_tx_cnt--; 2145 SK_INC(idx, MSK_TX_RING_CNT); 2146 } 2147 if (idx == sc_if->sk_cdata.sk_tx_cons) 2148 return; 2149 2150 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2151 2152 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 2153 ifp->if_flags &= ~IFF_OACTIVE; 2154 2155 sc_if->sk_cdata.sk_tx_cons = idx; 2156 } 2157 2158 void 2159 msk_fill_rx_ring(struct sk_if_softc *sc_if) 2160 { 2161 /* Make sure to not completely wrap around */ 2162 while (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT - 1)) { 2163 if (msk_newbuf(sc_if, 2164 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 2165 goto schedretry; 2166 } 2167 } 2168 2169 return; 2170 2171 schedretry: 2172 /* Try later */ 2173 callout_schedule(&sc_if->sk_tick_rx, hz/2); 2174 } 2175 2176 static void 2177 msk_fill_rx_tick(void *xsc_if) 2178 { 2179 struct sk_if_softc *sc_if = xsc_if; 2180 int s, rx_prod; 2181 2182 KASSERT(KERNEL_LOCKED_P()); /* XXXSMP */ 2183 2184 s = splnet(); 2185 rx_prod = sc_if->sk_cdata.sk_rx_prod; 2186 msk_fill_rx_ring(sc_if); 2187 if (rx_prod != sc_if->sk_cdata.sk_rx_prod) { 2188 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2189 sc_if->sk_cdata.sk_rx_prod); 2190 } 2191 splx(s); 2192 } 2193 2194 void 2195 msk_tick(void *xsc_if) 2196 { 2197 struct sk_if_softc *sc_if = xsc_if; 2198 struct mii_data *mii = &sc_if->sk_mii; 2199 int s; 2200 2201 s = splnet(); 2202 mii_tick(mii); 2203 splx(s); 2204 2205 callout_schedule(&sc_if->sk_tick_ch, hz); 2206 } 2207 2208 void 2209 msk_intr_yukon(struct sk_if_softc *sc_if) 2210 { 2211 uint8_t status; 2212 2213 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2214 /* RX overrun */ 2215 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2216 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2217 SK_RFCTL_RX_FIFO_OVER); 2218 } 2219 /* TX underrun */ 2220 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2221 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 2222 SK_TFCTL_TX_FIFO_UNDER); 2223 } 2224 2225 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 2226 } 2227 2228 int 2229 msk_intr(void *xsc) 2230 { 2231 struct sk_softc *sc = xsc; 2232 struct sk_if_softc *sc_if; 2233 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2234 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2235 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2236 int claimed = 0; 2237 uint32_t status; 2238 struct msk_status_desc *cur_st; 2239 2240 status = CSR_READ_4(sc, SK_Y2_ISSR2); 2241 if (status == 0xffffffff) 2242 return 0; 2243 if (status == 0) { 2244 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2245 return 0; 2246 } 2247 2248 status = CSR_READ_4(sc, SK_ISR); 2249 2250 if (sc_if0 != NULL) 2251 ifp0 = &sc_if0->sk_ethercom.ec_if; 2252 if (sc_if1 != NULL) 2253 ifp1 = &sc_if1->sk_ethercom.ec_if; 2254 2255 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 2256 (ifp0->if_flags & IFF_RUNNING)) { 2257 msk_intr_yukon(sc_if0); 2258 } 2259 2260 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 2261 (ifp1->if_flags & IFF_RUNNING)) { 2262 msk_intr_yukon(sc_if1); 2263 } 2264 2265 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2266 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2267 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2268 2269 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 2270 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 2271 switch (cur_st->sk_opcode) { 2272 case SK_Y2_STOPC_RXSTAT: 2273 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 2274 if (sc_if) { 2275 msk_rxeof(sc_if, letoh16(cur_st->sk_len), 2276 letoh32(cur_st->sk_status)); 2277 if (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 2278 msk_fill_rx_tick(sc_if); 2279 } 2280 break; 2281 case SK_Y2_STOPC_TXSTAT: 2282 if (sc_if0) 2283 msk_txeof(sc_if0); 2284 if (sc_if1) 2285 msk_txeof(sc_if1); 2286 break; 2287 default: 2288 aprint_error("opcode=0x%x\n", cur_st->sk_opcode); 2289 break; 2290 } 2291 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 2292 2293 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2294 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2295 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2296 } 2297 2298 if (status & SK_Y2_IMR_BMU) { 2299 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 2300 claimed = 1; 2301 } 2302 2303 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2304 2305 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2306 if_schedule_deferred_start(ifp0); 2307 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2308 if_schedule_deferred_start(ifp1); 2309 2310 KASSERT(sc->rnd_attached > 0); 2311 rnd_add_uint32(&sc->rnd_source, status); 2312 2313 if (sc->sk_int_mod_pending) 2314 msk_update_int_mod(sc, 1); 2315 2316 return claimed; 2317 } 2318 2319 void 2320 msk_init_yukon(struct sk_if_softc *sc_if) 2321 { 2322 uint32_t v; 2323 uint16_t reg; 2324 struct sk_softc *sc; 2325 int i; 2326 2327 sc = sc_if->sk_softc; 2328 2329 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 2330 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2331 2332 DPRINTFN(6, ("msk_init_yukon: 1\n")); 2333 2334 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 2335 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2336 2337 DPRINTFN(6, ("msk_init_yukon: 3\n")); 2338 2339 /* unused read of the interrupt source register */ 2340 DPRINTFN(6, ("msk_init_yukon: 4\n")); 2341 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2342 2343 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2344 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2345 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2346 2347 /* MIB Counter Clear Mode set */ 2348 reg |= YU_PAR_MIB_CLR; 2349 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2350 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2351 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2352 2353 /* MIB Counter Clear Mode clear */ 2354 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2355 reg &= ~YU_PAR_MIB_CLR; 2356 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2357 2358 /* receive control reg */ 2359 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2360 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2361 2362 /* transmit control register */ 2363 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2364 2365 /* transmit flow control register */ 2366 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2367 2368 /* transmit parameter register */ 2369 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2370 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2371 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2372 2373 /* serial mode register */ 2374 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2375 reg = YU_SMR_DATA_BLIND(0x1c) | 2376 YU_SMR_MFL_VLAN | 2377 YU_SMR_IPG_DATA(0x1e); 2378 2379 if (sc->sk_type != SK_YUKON_FE && 2380 sc->sk_type != SK_YUKON_FE_P) 2381 reg |= YU_SMR_MFL_JUMBO; 2382 2383 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2384 2385 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2386 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2387 /* msk_attach calls me before ether_ifattach so check null */ 2388 if (ifp != NULL && ifp->if_sadl != NULL) 2389 memcpy(sc_if->sk_enaddr, CLLADDR(ifp->if_sadl), 2390 sizeof(sc_if->sk_enaddr)); 2391 /* Setup Yukon's address */ 2392 for (i = 0; i < 3; i++) { 2393 /* Write Source Address 1 (unicast filter) */ 2394 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2395 sc_if->sk_enaddr[i * 2] | 2396 sc_if->sk_enaddr[i * 2 + 1] << 8); 2397 } 2398 2399 for (i = 0; i < 3; i++) { 2400 reg = sk_win_read_2(sc_if->sk_softc, 2401 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2402 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2403 } 2404 2405 /* Set promiscuous mode */ 2406 msk_setpromisc(sc_if); 2407 2408 /* Set multicast filter */ 2409 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2410 msk_setmulti(sc_if); 2411 2412 /* enable interrupt mask for counter overflows */ 2413 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2414 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2415 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2416 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2417 2418 /* Configure RX MAC FIFO Flush Mask */ 2419 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2420 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2421 YU_RXSTAT_JABBER; 2422 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2423 2424 /* Configure RX MAC FIFO */ 2425 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2426 v = SK_RFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 2427 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_FE_P)) 2428 v |= SK_RFCTL_RX_OVER_ON; 2429 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 2430 2431 if ((sc->sk_type == SK_YUKON_FE_P) && 2432 (sc->sk_rev == SK_YUKON_FE_P_REV_A0)) 2433 v = 0x178; /* Magic value */ 2434 else { 2435 /* Increase flush threshold to 64 bytes */ 2436 v = SK_RFCTL_FIFO_THRESHOLD + 1; 2437 } 2438 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, v); 2439 2440 /* Configure TX MAC FIFO */ 2441 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2442 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2443 2444 if ((sc->sk_type == SK_YUKON_FE_P) && 2445 (sc->sk_rev == SK_YUKON_FE_P_REV_A0)) { 2446 v = SK_IF_READ_2(sc_if, 0, SK_TXMF1_END); 2447 v &= ~SK_TXEND_WM_ON; 2448 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_END, v); 2449 } 2450 2451 #if 1 2452 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2453 #endif 2454 DPRINTFN(6, ("msk_init_yukon: end\n")); 2455 } 2456 2457 /* 2458 * Note that to properly initialize any part of the GEnesis chip, 2459 * you first have to take it out of reset mode. 2460 */ 2461 int 2462 msk_init(struct ifnet *ifp) 2463 { 2464 struct sk_if_softc *sc_if = ifp->if_softc; 2465 struct sk_softc *sc = sc_if->sk_softc; 2466 int rc = 0, s; 2467 uint32_t imr, imtimer_ticks; 2468 2469 2470 DPRINTFN(2, ("msk_init\n")); 2471 2472 s = splnet(); 2473 2474 /* Cancel pending I/O and free all RX/TX buffers. */ 2475 msk_stop(ifp, 1); 2476 2477 /* Configure I2C registers */ 2478 2479 /* Configure XMAC(s) */ 2480 msk_init_yukon(sc_if); 2481 if ((rc = ether_mediachange(ifp)) != 0) 2482 goto out; 2483 2484 /* Configure transmit arbiter(s) */ 2485 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2486 #if 0 2487 /* SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); */ 2488 #endif 2489 2490 if (sc->sk_ramsize) { 2491 /* Configure RAMbuffers */ 2492 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2493 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2494 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2495 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2496 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2497 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2498 2499 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2500 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2501 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2502 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2503 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2504 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2505 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2506 } 2507 2508 /* Configure BMUs */ 2509 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2510 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2511 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2512 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2513 2514 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2515 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2516 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2517 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2518 2519 /* Make sure the sync transmit queue is disabled. */ 2520 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2521 2522 /* Init descriptors */ 2523 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2524 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2525 "memory for rx buffers\n"); 2526 msk_stop(ifp, 1); 2527 splx(s); 2528 return ENOBUFS; 2529 } 2530 2531 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2532 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2533 "memory for tx buffers\n"); 2534 msk_stop(ifp, 1); 2535 splx(s); 2536 return ENOBUFS; 2537 } 2538 2539 /* Set interrupt moderation if changed via sysctl. */ 2540 switch (sc->sk_type) { 2541 case SK_YUKON_EC: 2542 case SK_YUKON_EC_U: 2543 case SK_YUKON_EX: 2544 case SK_YUKON_SUPR: 2545 case SK_YUKON_ULTRA2: 2546 case SK_YUKON_OPTIMA: 2547 case SK_YUKON_PRM: 2548 case SK_YUKON_OPTIMA2: 2549 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2550 break; 2551 case SK_YUKON_FE: 2552 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2553 break; 2554 case SK_YUKON_FE_P: 2555 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 2556 break; 2557 case SK_YUKON_XL: 2558 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2559 break; 2560 default: 2561 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2562 } 2563 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2564 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2565 sk_win_write_4(sc, SK_IMTIMERINIT, 2566 SK_IM_USECS(sc->sk_int_mod)); 2567 aprint_verbose_dev(sc->sk_dev, 2568 "interrupt moderation is %d us\n", sc->sk_int_mod); 2569 } 2570 2571 /* Initialize prefetch engine. */ 2572 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2573 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2574 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2575 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2576 MSK_RX_RING_ADDR(sc_if, 0)); 2577 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2578 (uint64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2579 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2580 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2581 2582 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2583 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2584 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2585 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2586 MSK_TX_RING_ADDR(sc_if, 0)); 2587 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2588 (uint64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2589 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2590 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2591 2592 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2593 sc_if->sk_cdata.sk_rx_prod); 2594 2595 2596 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_SUPR)) { 2597 /* Disable flushing of non-ASF packets. */ 2598 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, 2599 SK_RFCTL_RX_MACSEC_FLUSH_OFF); 2600 } 2601 2602 /* Configure interrupt handling */ 2603 if (sc_if->sk_port == SK_PORT_A) 2604 sc->sk_intrmask |= SK_Y2_INTRS1; 2605 else 2606 sc->sk_intrmask |= SK_Y2_INTRS2; 2607 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2608 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2609 2610 ifp->if_flags |= IFF_RUNNING; 2611 ifp->if_flags &= ~IFF_OACTIVE; 2612 2613 callout_schedule(&sc_if->sk_tick_ch, hz); 2614 2615 out: 2616 splx(s); 2617 return rc; 2618 } 2619 2620 /* 2621 * Note: the logic of second parameter is inverted compared to OpenBSD 2622 * code, since this code uses the function as if_stop hook too. 2623 */ 2624 void 2625 msk_stop(struct ifnet *ifp, int disable) 2626 { 2627 struct sk_if_softc *sc_if = ifp->if_softc; 2628 struct sk_softc *sc = sc_if->sk_softc; 2629 struct sk_txmap_entry *dma; 2630 int i; 2631 2632 DPRINTFN(2, ("msk_stop\n")); 2633 2634 callout_stop(&sc_if->sk_tick_ch); 2635 callout_stop(&sc_if->sk_tick_rx); 2636 2637 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2638 2639 /* Stop transfer of Tx descriptors */ 2640 2641 /* Stop transfer of Rx descriptors */ 2642 2643 if (disable) { 2644 /* Turn off various components of this interface. */ 2645 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2646 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2647 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2648 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2649 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2650 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2651 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2652 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2653 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2654 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2655 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2656 2657 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2658 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2659 2660 /* Disable interrupts */ 2661 if (sc_if->sk_port == SK_PORT_A) 2662 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2663 else 2664 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2665 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2666 } 2667 2668 /* Free RX and TX mbufs still in the queues. */ 2669 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2670 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2671 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2672 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2673 } 2674 } 2675 2676 sc_if->sk_cdata.sk_rx_prod = 0; 2677 sc_if->sk_cdata.sk_rx_cons = 0; 2678 sc_if->sk_cdata.sk_rx_cnt = 0; 2679 2680 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2681 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2682 dma = sc_if->sk_cdata.sk_tx_map[i]; 2683 2684 bus_dmamap_sync(sc->sc_dmatag, dma->dmamap, 0, 2685 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2686 2687 bus_dmamap_unload(sc->sc_dmatag, dma->dmamap); 2688 #if 1 2689 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2690 sc_if->sk_cdata.sk_tx_map[i], link); 2691 sc_if->sk_cdata.sk_tx_map[i] = 0; 2692 #endif 2693 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2694 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2695 } 2696 } 2697 2698 #if 1 2699 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2700 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2701 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2702 free(dma, M_DEVBUF); 2703 } 2704 #endif 2705 } 2706 2707 CFATTACH_DECL3_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2708 mskc_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2709 2710 CFATTACH_DECL3_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2711 msk_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2712 2713 #ifdef MSK_DEBUG 2714 void 2715 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2716 { 2717 #define DESC_PRINT(X) \ 2718 if (X) \ 2719 printf("txdesc[%d]." #X "=%#x\n", \ 2720 idx, X); 2721 2722 DESC_PRINT(letoh32(le->sk_addr)); 2723 DESC_PRINT(letoh16(le->sk_len)); 2724 DESC_PRINT(le->sk_ctl); 2725 DESC_PRINT(le->sk_opcode); 2726 #undef DESC_PRINT 2727 } 2728 2729 void 2730 msk_dump_bytes(const char *data, int len) 2731 { 2732 int c, i, j; 2733 2734 for (i = 0; i < len; i += 16) { 2735 printf("%08x ", i); 2736 c = len - i; 2737 if (c > 16) c = 16; 2738 2739 for (j = 0; j < c; j++) { 2740 printf("%02x ", data[i + j] & 0xff); 2741 if ((j & 0xf) == 7 && j > 0) 2742 printf(" "); 2743 } 2744 2745 for (; j < 16; j++) 2746 printf(" "); 2747 printf(" "); 2748 2749 for (j = 0; j < c; j++) { 2750 int ch = data[i + j] & 0xff; 2751 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2752 } 2753 2754 printf("\n"); 2755 2756 if (c < 16) 2757 break; 2758 } 2759 } 2760 2761 void 2762 msk_dump_mbuf(struct mbuf *m) 2763 { 2764 int count = m->m_pkthdr.len; 2765 2766 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2767 2768 while (count > 0 && m) { 2769 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2770 m, m->m_data, m->m_len); 2771 if (mskdebug >= 4) 2772 msk_dump_bytes(mtod(m, char *), m->m_len); 2773 2774 count -= m->m_len; 2775 m = m->m_next; 2776 } 2777 } 2778 #endif 2779 2780 static int 2781 msk_sysctl_handler(SYSCTLFN_ARGS) 2782 { 2783 int error, t; 2784 struct sysctlnode node; 2785 struct sk_softc *sc; 2786 2787 node = *rnode; 2788 sc = node.sysctl_data; 2789 t = sc->sk_int_mod; 2790 node.sysctl_data = &t; 2791 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2792 if (error || newp == NULL) 2793 return error; 2794 2795 if (t < SK_IM_MIN || t > SK_IM_MAX) 2796 return EINVAL; 2797 2798 /* update the softc with sysctl-changed value, and mark 2799 for hardware update */ 2800 sc->sk_int_mod = t; 2801 sc->sk_int_mod_pending = 1; 2802 return 0; 2803 } 2804 2805 /* 2806 * Set up sysctl(3) MIB, hw.msk.* - Individual controllers will be 2807 * set up in mskc_attach() 2808 */ 2809 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2810 { 2811 int rc; 2812 const struct sysctlnode *node; 2813 2814 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2815 0, CTLTYPE_NODE, "msk", 2816 SYSCTL_DESCR("msk interface controls"), 2817 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2818 goto err; 2819 } 2820 2821 msk_root_num = node->sysctl_num; 2822 return; 2823 2824 err: 2825 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2826 } 2827
Indexes created Thu Oct 02 07:10:07 GMT 2025