if_msk.c revision 1.93
1 /* $NetBSD: if_msk.c,v 1.93 2019/11/10 21:16:36 chs Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.79 2009/10/15 17:54:56 deraadt Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.93 2019/11/10 21:16:36 chs Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/mutex.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/device.h> 66 #include <sys/queue.h> 67 #include <sys/callout.h> 68 #include <sys/sysctl.h> 69 #include <sys/endian.h> 70 #ifdef __NetBSD__ 71 #define letoh16 htole16 72 #define letoh32 htole32 73 #endif 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #include <net/if_media.h> 80 81 #include <net/bpf.h> 82 #include <sys/rndsource.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 #include <dev/mii/brgphyreg.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 92 #include <dev/pci/if_skreg.h> 93 #include <dev/pci/if_mskvar.h> 94 95 int mskc_probe(device_t, cfdata_t, void *); 96 void mskc_attach(device_t, device_t, void *); 97 int mskc_detach(device_t, int); 98 void mskc_reset(struct sk_softc *); 99 static bool mskc_suspend(device_t, const pmf_qual_t *); 100 static bool mskc_resume(device_t, const pmf_qual_t *); 101 int msk_probe(device_t, cfdata_t, void *); 102 void msk_attach(device_t, device_t, void *); 103 int msk_detach(device_t, int); 104 void msk_reset(struct sk_if_softc *); 105 int mskcprint(void *, const char *); 106 int msk_intr(void *); 107 void msk_intr_yukon(struct sk_if_softc *); 108 void msk_rxeof(struct sk_if_softc *, uint16_t, uint32_t); 109 void msk_txeof(struct sk_if_softc *); 110 int msk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 111 void msk_start(struct ifnet *); 112 int msk_ioctl(struct ifnet *, u_long, void *); 113 int msk_init(struct ifnet *); 114 void msk_init_yukon(struct sk_if_softc *); 115 void msk_stop(struct ifnet *, int); 116 void msk_watchdog(struct ifnet *); 117 int msk_newbuf(struct sk_if_softc *, bus_dmamap_t); 118 int msk_alloc_jumbo_mem(struct sk_if_softc *); 119 void *msk_jalloc(struct sk_if_softc *); 120 void msk_jfree(struct mbuf *, void *, size_t, void *); 121 int msk_init_rx_ring(struct sk_if_softc *); 122 int msk_init_tx_ring(struct sk_if_softc *); 123 void msk_fill_rx_ring(struct sk_if_softc *); 124 125 void msk_update_int_mod(struct sk_softc *, int); 126 127 int msk_miibus_readreg(device_t, int, int, uint16_t *); 128 int msk_miibus_writereg(device_t, int, int, uint16_t); 129 void msk_miibus_statchg(struct ifnet *); 130 131 void msk_setmulti(struct sk_if_softc *); 132 void msk_setpromisc(struct sk_if_softc *); 133 void msk_tick(void *); 134 static void msk_fill_rx_tick(void *); 135 136 /* #define MSK_DEBUG 1 */ 137 #ifdef MSK_DEBUG 138 #define DPRINTF(x) if (mskdebug) printf x 139 #define DPRINTFN(n, x) if (mskdebug >= (n)) printf x 140 int mskdebug = MSK_DEBUG; 141 142 void msk_dump_txdesc(struct msk_tx_desc *, int); 143 void msk_dump_mbuf(struct mbuf *); 144 void msk_dump_bytes(const char *, int); 145 #else 146 #define DPRINTF(x) 147 #define DPRINTFN(n, x) 148 #endif 149 150 static int msk_sysctl_handler(SYSCTLFN_PROTO); 151 static int msk_root_num; 152 153 #define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL) 154 #define MSK_ADDR_HI(x) ((uint64_t) (x) >> 32) 155 156 /* supported device vendors */ 157 static const struct msk_product { 158 pci_vendor_id_t msk_vendor; 159 pci_product_id_t msk_product; 160 } msk_products[] = { 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 163 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 164 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8079 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 197 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 198 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 199 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 200 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 201 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 }, 202 { 0, 0 } 203 }; 204 205 static inline uint32_t 206 sk_win_read_4(struct sk_softc *sc, uint32_t reg) 207 { 208 return CSR_READ_4(sc, reg); 209 } 210 211 static inline uint16_t 212 sk_win_read_2(struct sk_softc *sc, uint32_t reg) 213 { 214 return CSR_READ_2(sc, reg); 215 } 216 217 static inline uint8_t 218 sk_win_read_1(struct sk_softc *sc, uint32_t reg) 219 { 220 return CSR_READ_1(sc, reg); 221 } 222 223 static inline void 224 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x) 225 { 226 CSR_WRITE_4(sc, reg, x); 227 } 228 229 static inline void 230 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x) 231 { 232 CSR_WRITE_2(sc, reg, x); 233 } 234 235 static inline void 236 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x) 237 { 238 CSR_WRITE_1(sc, reg, x); 239 } 240 241 int 242 msk_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 243 { 244 struct sk_if_softc *sc_if = device_private(dev); 245 uint16_t data; 246 int i; 247 248 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 249 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 250 251 for (i = 0; i < SK_TIMEOUT; i++) { 252 DELAY(1); 253 data = SK_YU_READ_2(sc_if, YUKON_SMICR); 254 if (data & YU_SMICR_READ_VALID) 255 break; 256 } 257 258 if (i == SK_TIMEOUT) { 259 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 260 return ETIMEDOUT; 261 } 262 263 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, SK_TIMEOUT)); 264 265 *val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 266 267 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#hx\n", 268 phy, reg, *val)); 269 270 return 0; 271 } 272 273 int 274 msk_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 275 { 276 struct sk_if_softc *sc_if = device_private(dev); 277 int i; 278 279 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#hx\n", 280 phy, reg, val)); 281 282 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 283 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 284 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 285 286 for (i = 0; i < SK_TIMEOUT; i++) { 287 DELAY(1); 288 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 289 break; 290 } 291 292 if (i == SK_TIMEOUT) { 293 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 294 return ETIMEDOUT; 295 } 296 297 return 0; 298 } 299 300 void 301 msk_miibus_statchg(struct ifnet *ifp) 302 { 303 struct sk_if_softc *sc_if = ifp->if_softc; 304 struct mii_data *mii = &sc_if->sk_mii; 305 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 306 int gpcr; 307 308 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 309 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 310 311 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 312 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 313 /* Set speed. */ 314 gpcr |= YU_GPCR_SPEED_DIS; 315 switch (IFM_SUBTYPE(mii->mii_media_active)) { 316 case IFM_1000_SX: 317 case IFM_1000_LX: 318 case IFM_1000_CX: 319 case IFM_1000_T: 320 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 321 break; 322 case IFM_100_TX: 323 gpcr |= YU_GPCR_SPEED; 324 break; 325 } 326 327 /* Set duplex. */ 328 gpcr |= YU_GPCR_DPLX_DIS; 329 if ((mii->mii_media_active & IFM_FDX) != 0) 330 gpcr |= YU_GPCR_DUPLEX; 331 332 /* Disable flow control. */ 333 gpcr |= YU_GPCR_FCTL_DIS; 334 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 335 } 336 337 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 338 339 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 340 SK_YU_READ_2(sc_if, YUKON_GPCR))); 341 } 342 343 void 344 msk_setmulti(struct sk_if_softc *sc_if) 345 { 346 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 347 uint32_t hashes[2] = { 0, 0 }; 348 int h; 349 struct ethercom *ec = &sc_if->sk_ethercom; 350 struct ether_multi *enm; 351 struct ether_multistep step; 352 uint16_t reg; 353 354 /* First, zot all the existing filters. */ 355 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 356 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 357 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 358 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 359 360 361 /* Now program new ones. */ 362 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 363 reg |= YU_RCR_UFLEN; 364 allmulti: 365 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 366 if ((ifp->if_flags & IFF_PROMISC) != 0) 367 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 368 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 369 hashes[0] = 0xFFFFFFFF; 370 hashes[1] = 0xFFFFFFFF; 371 } 372 } else { 373 /* First find the tail of the list. */ 374 ETHER_LOCK(ec); 375 ETHER_FIRST_MULTI(step, ec, enm); 376 while (enm != NULL) { 377 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 378 ETHER_ADDR_LEN)) { 379 ifp->if_flags |= IFF_ALLMULTI; 380 ETHER_UNLOCK(ec); 381 goto allmulti; 382 } 383 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 384 ((1 << SK_HASH_BITS) - 1); 385 if (h < 32) 386 hashes[0] |= (1 << h); 387 else 388 hashes[1] |= (1 << (h - 32)); 389 390 ETHER_NEXT_MULTI(step, enm); 391 } 392 ETHER_UNLOCK(ec); 393 reg |= YU_RCR_MUFLEN; 394 } 395 396 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 397 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 398 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 399 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 400 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 401 } 402 403 void 404 msk_setpromisc(struct sk_if_softc *sc_if) 405 { 406 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 407 408 if (ifp->if_flags & IFF_PROMISC) 409 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 410 YU_RCR_UFLEN | YU_RCR_MUFLEN); 411 else 412 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 413 YU_RCR_UFLEN | YU_RCR_MUFLEN); 414 } 415 416 int 417 msk_init_rx_ring(struct sk_if_softc *sc_if) 418 { 419 struct msk_chain_data *cd = &sc_if->sk_cdata; 420 struct msk_ring_data *rd = sc_if->sk_rdata; 421 struct msk_rx_desc *r; 422 int i, nexti; 423 424 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 425 426 for (i = 0; i < MSK_RX_RING_CNT; i++) { 427 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 428 if (i == (MSK_RX_RING_CNT - 1)) 429 nexti = 0; 430 else 431 nexti = i + 1; 432 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 433 } 434 435 sc_if->sk_cdata.sk_rx_prod = 0; 436 sc_if->sk_cdata.sk_rx_cons = 0; 437 sc_if->sk_cdata.sk_rx_cnt = 0; 438 sc_if->sk_cdata.sk_rx_hiaddr = 0; 439 440 /* Mark the first ring element to initialize the high address. */ 441 sc_if->sk_cdata.sk_rx_hiaddr = 0; 442 r = &rd->sk_rx_ring[cd->sk_rx_prod]; 443 r->sk_addr = htole32(cd->sk_rx_hiaddr); 444 r->sk_len = 0; 445 r->sk_ctl = 0; 446 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN; 447 MSK_CDRXSYNC(sc_if, cd->sk_rx_prod, 448 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 449 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 450 sc_if->sk_cdata.sk_rx_cnt++; 451 452 msk_fill_rx_ring(sc_if); 453 return 0; 454 } 455 456 int 457 msk_init_tx_ring(struct sk_if_softc *sc_if) 458 { 459 struct sk_softc *sc = sc_if->sk_softc; 460 struct msk_chain_data *cd = &sc_if->sk_cdata; 461 struct msk_ring_data *rd = sc_if->sk_rdata; 462 struct msk_tx_desc *t; 463 bus_dmamap_t dmamap; 464 struct sk_txmap_entry *entry; 465 int i, nexti; 466 467 memset(rd->sk_tx_ring, 0, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 468 469 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 470 for (i = 0; i < MSK_TX_RING_CNT; i++) { 471 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 472 if (i == (MSK_TX_RING_CNT - 1)) 473 nexti = 0; 474 else 475 nexti = i + 1; 476 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 477 478 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 479 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 480 return ENOBUFS; 481 482 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 483 if (!entry) { 484 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 485 return ENOBUFS; 486 } 487 entry->dmamap = dmamap; 488 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 489 } 490 491 sc_if->sk_cdata.sk_tx_prod = 0; 492 sc_if->sk_cdata.sk_tx_cons = 0; 493 sc_if->sk_cdata.sk_tx_cnt = 0; 494 sc_if->sk_cdata.sk_tx_hiaddr = 0; 495 496 /* Mark the first ring element to initialize the high address. */ 497 sc_if->sk_cdata.sk_tx_hiaddr = 0; 498 t = &rd->sk_tx_ring[cd->sk_tx_prod]; 499 t->sk_addr = htole32(cd->sk_tx_hiaddr); 500 t->sk_len = 0; 501 t->sk_ctl = 0; 502 t->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 503 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 504 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 505 SK_INC(sc_if->sk_cdata.sk_tx_prod, MSK_TX_RING_CNT); 506 sc_if->sk_cdata.sk_tx_cnt++; 507 508 return 0; 509 } 510 511 int 512 msk_newbuf(struct sk_if_softc *sc_if, bus_dmamap_t dmamap) 513 { 514 struct mbuf *m_new = NULL; 515 struct sk_chain *c; 516 struct msk_rx_desc *r; 517 void *buf = NULL; 518 bus_addr_t addr; 519 520 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 521 if (m_new == NULL) 522 return ENOBUFS; 523 524 /* Allocate the jumbo buffer */ 525 buf = msk_jalloc(sc_if); 526 if (buf == NULL) { 527 m_freem(m_new); 528 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 529 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 530 return ENOBUFS; 531 } 532 533 /* Attach the buffer to the mbuf */ 534 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 535 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 536 537 m_adj(m_new, ETHER_ALIGN); 538 539 addr = dmamap->dm_segs[0].ds_addr + 540 ((vaddr_t)m_new->m_data - 541 (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf); 542 543 if (sc_if->sk_cdata.sk_rx_hiaddr != MSK_ADDR_HI(addr)) { 544 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 545 r = c->sk_le; 546 c->sk_mbuf = NULL; 547 r->sk_addr = htole32(MSK_ADDR_HI(addr)); 548 r->sk_len = 0; 549 r->sk_ctl = 0; 550 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN; 551 sc_if->sk_cdata.sk_rx_hiaddr = MSK_ADDR_HI(addr); 552 553 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 554 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 555 556 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 557 sc_if->sk_cdata.sk_rx_cnt++; 558 559 DPRINTFN(10, ("%s: rx ADDR64: %#x\n", 560 sc_if->sk_ethercom.ec_if.if_xname, 561 (unsigned)MSK_ADDR_HI(addr))); 562 } 563 564 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 565 r = c->sk_le; 566 c->sk_mbuf = m_new; 567 r->sk_addr = htole32(MSK_ADDR_LO(addr)); 568 r->sk_len = htole16(SK_JLEN); 569 r->sk_ctl = 0; 570 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 571 572 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 573 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 574 575 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 576 sc_if->sk_cdata.sk_rx_cnt++; 577 578 return 0; 579 } 580 581 /* 582 * Memory management for jumbo frames. 583 */ 584 585 int 586 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 587 { 588 struct sk_softc *sc = sc_if->sk_softc; 589 char *ptr, *kva; 590 int i, state, error; 591 struct sk_jpool_entry *entry; 592 593 state = error = 0; 594 595 /* Grab a big chunk o' storage. */ 596 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 597 &sc_if->sk_cdata.sk_jumbo_seg, 1, &sc_if->sk_cdata.sk_jumbo_nseg, 598 BUS_DMA_NOWAIT)) { 599 aprint_error(": can't alloc rx buffers"); 600 return ENOBUFS; 601 } 602 603 state = 1; 604 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 605 sc_if->sk_cdata.sk_jumbo_nseg, MSK_JMEM, (void **)&kva, 606 BUS_DMA_NOWAIT)) { 607 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 608 error = ENOBUFS; 609 goto out; 610 } 611 612 state = 2; 613 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 614 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 615 aprint_error(": can't create dma map"); 616 error = ENOBUFS; 617 goto out; 618 } 619 620 state = 3; 621 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 622 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 623 aprint_error(": can't load dma map"); 624 error = ENOBUFS; 625 goto out; 626 } 627 628 state = 4; 629 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 630 DPRINTFN(1,("msk_jumbo_buf = %p\n", 631 (void *)sc_if->sk_cdata.sk_jumbo_buf)); 632 633 LIST_INIT(&sc_if->sk_jfree_listhead); 634 LIST_INIT(&sc_if->sk_jinuse_listhead); 635 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 636 637 /* 638 * Now divide it up into 9K pieces and save the addresses 639 * in an array. 640 */ 641 ptr = sc_if->sk_cdata.sk_jumbo_buf; 642 for (i = 0; i < MSK_JSLOTS; i++) { 643 sc_if->sk_cdata.sk_jslots[i] = ptr; 644 ptr += SK_JLEN; 645 entry = malloc(sizeof(struct sk_jpool_entry), 646 M_DEVBUF, M_WAITOK); 647 entry->slot = i; 648 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 649 entry, jpool_entries); 650 } 651 out: 652 if (error != 0) { 653 switch (state) { 654 case 4: 655 bus_dmamap_unload(sc->sc_dmatag, 656 sc_if->sk_cdata.sk_rx_jumbo_map); 657 /* FALLTHROUGH */ 658 case 3: 659 bus_dmamap_destroy(sc->sc_dmatag, 660 sc_if->sk_cdata.sk_rx_jumbo_map); 661 /* FALLTHROUGH */ 662 case 2: 663 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 664 /* FALLTHROUGH */ 665 case 1: 666 bus_dmamem_free(sc->sc_dmatag, 667 &sc_if->sk_cdata.sk_jumbo_seg, 668 sc_if->sk_cdata.sk_jumbo_nseg); 669 break; 670 default: 671 break; 672 } 673 } 674 675 return error; 676 } 677 678 static void 679 msk_free_jumbo_mem(struct sk_if_softc *sc_if) 680 { 681 struct sk_softc *sc = sc_if->sk_softc; 682 683 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 684 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 685 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_cdata.sk_jumbo_buf, MSK_JMEM); 686 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 687 sc_if->sk_cdata.sk_jumbo_nseg); 688 } 689 690 /* 691 * Allocate a jumbo buffer. 692 */ 693 void * 694 msk_jalloc(struct sk_if_softc *sc_if) 695 { 696 struct sk_jpool_entry *entry; 697 698 mutex_enter(&sc_if->sk_jpool_mtx); 699 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 700 701 if (entry == NULL) { 702 mutex_exit(&sc_if->sk_jpool_mtx); 703 return NULL; 704 } 705 706 LIST_REMOVE(entry, jpool_entries); 707 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 708 mutex_exit(&sc_if->sk_jpool_mtx); 709 return sc_if->sk_cdata.sk_jslots[entry->slot]; 710 } 711 712 /* 713 * Release a jumbo buffer. 714 */ 715 void 716 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 717 { 718 struct sk_jpool_entry *entry; 719 struct sk_if_softc *sc; 720 int i; 721 722 /* Extract the softc struct pointer. */ 723 sc = (struct sk_if_softc *)arg; 724 725 if (sc == NULL) 726 panic("msk_jfree: can't find softc pointer!"); 727 728 /* calculate the slot this buffer belongs to */ 729 i = ((vaddr_t)buf 730 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 731 732 if ((i < 0) || (i >= MSK_JSLOTS)) 733 panic("msk_jfree: asked to free buffer that we don't manage!"); 734 735 mutex_enter(&sc->sk_jpool_mtx); 736 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 737 if (entry == NULL) 738 panic("msk_jfree: buffer not in use!"); 739 entry->slot = i; 740 LIST_REMOVE(entry, jpool_entries); 741 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 742 mutex_exit(&sc->sk_jpool_mtx); 743 744 if (__predict_true(m != NULL)) 745 pool_cache_put(mb_cache, m); 746 747 /* Now that we know we have a free RX buffer, refill if running out */ 748 if ((sc->sk_ethercom.ec_if.if_flags & IFF_RUNNING) != 0 749 && sc->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 750 callout_schedule(&sc->sk_tick_rx, 0); 751 } 752 753 int 754 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 755 { 756 struct sk_if_softc *sc = ifp->if_softc; 757 int s, error; 758 759 s = splnet(); 760 761 DPRINTFN(2, ("msk_ioctl ETHER cmd %lx\n", cmd)); 762 switch (cmd) { 763 case SIOCSIFFLAGS: 764 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 765 break; 766 767 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 768 case IFF_RUNNING: 769 msk_stop(ifp, 1); 770 break; 771 case IFF_UP: 772 msk_init(ifp); 773 break; 774 case IFF_UP | IFF_RUNNING: 775 if ((ifp->if_flags ^ sc->sk_if_flags) == IFF_PROMISC) { 776 msk_setpromisc(sc); 777 msk_setmulti(sc); 778 } else 779 msk_init(ifp); 780 break; 781 } 782 sc->sk_if_flags = ifp->if_flags; 783 break; 784 default: 785 error = ether_ioctl(ifp, cmd, data); 786 if (error == ENETRESET) { 787 error = 0; 788 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 789 ; 790 else if (ifp->if_flags & IFF_RUNNING) { 791 /* 792 * Multicast list has changed; set the hardware 793 * filter accordingly. 794 */ 795 msk_setmulti(sc); 796 } 797 } 798 break; 799 } 800 801 splx(s); 802 return error; 803 } 804 805 void 806 msk_update_int_mod(struct sk_softc *sc, int verbose) 807 { 808 uint32_t imtimer_ticks; 809 810 /* 811 * Configure interrupt moderation. The moderation timer 812 * defers interrupts specified in the interrupt moderation 813 * timer mask based on the timeout specified in the interrupt 814 * moderation timer init register. Each bit in the timer 815 * register represents one tick, so to specify a timeout in 816 * microseconds, we have to multiply by the correct number of 817 * ticks-per-microsecond. 818 */ 819 switch (sc->sk_type) { 820 case SK_YUKON_EC: 821 case SK_YUKON_EC_U: 822 case SK_YUKON_EX: 823 case SK_YUKON_SUPR: 824 case SK_YUKON_ULTRA2: 825 case SK_YUKON_OPTIMA: 826 case SK_YUKON_PRM: 827 case SK_YUKON_OPTIMA2: 828 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 829 break; 830 case SK_YUKON_FE: 831 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 832 break; 833 case SK_YUKON_FE_P: 834 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 835 break; 836 case SK_YUKON_XL: 837 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 838 break; 839 default: 840 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 841 } 842 if (verbose) 843 aprint_verbose_dev(sc->sk_dev, 844 "interrupt moderation is %d us\n", sc->sk_int_mod); 845 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 846 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF | SK_ISR_TX2_S_EOF | 847 SK_ISR_RX1_EOF | SK_ISR_RX2_EOF); 848 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 849 sc->sk_int_mod_pending = 0; 850 } 851 852 static int 853 msk_lookup(const struct pci_attach_args *pa) 854 { 855 const struct msk_product *pmsk; 856 857 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 858 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 859 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 860 return 1; 861 } 862 return 0; 863 } 864 865 /* 866 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 867 * IDs against our list and return a device name if we find a match. 868 */ 869 int 870 mskc_probe(device_t parent, cfdata_t match, void *aux) 871 { 872 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 873 874 return msk_lookup(pa); 875 } 876 877 /* 878 * Force the GEnesis into reset, then bring it out of reset. 879 */ 880 void 881 mskc_reset(struct sk_softc *sc) 882 { 883 uint32_t imtimer_ticks, reg1; 884 int reg; 885 886 DPRINTFN(2, ("mskc_reset\n")); 887 888 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 889 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 890 891 DELAY(1000); 892 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 893 DELAY(2); 894 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 895 sk_win_write_1(sc, SK_TESTCTL1, 2); 896 897 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 898 sc->sk_type >= SK_YUKON_FE_P) { 899 uint32_t our; 900 901 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 902 903 /* enable all clocks. */ 904 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 905 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 906 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST | 907 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN | 908 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY | 909 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 910 /* Set all bits to 0 except bits 15..12 */ 911 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 912 /* Set to default value */ 913 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 914 915 /* 916 * Disable status race, workaround for Yukon EC Ultra & 917 * Yukon EX. 918 */ 919 reg1 = sk_win_read_4(sc, SK_GPIO); 920 reg1 |= SK_Y2_GPIO_STAT_RACE_DIS; 921 sk_win_write_4(sc, SK_GPIO, reg1); 922 sk_win_read_4(sc, SK_GPIO); 923 } 924 925 /* release PHY from PowerDown/Coma mode. */ 926 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 927 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 928 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 929 else 930 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 931 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 932 933 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 934 sk_win_write_1(sc, SK_Y2_CLKGATE, 935 SK_Y2_CLKGATE_LINK1_GATE_DIS | 936 SK_Y2_CLKGATE_LINK2_GATE_DIS | 937 SK_Y2_CLKGATE_LINK1_CORE_DIS | 938 SK_Y2_CLKGATE_LINK2_CORE_DIS | 939 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 940 else 941 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 942 943 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 944 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 945 DELAY(1000); 946 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 947 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 948 949 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 950 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 951 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 952 } 953 954 sk_win_write_1(sc, SK_TESTCTL1, 1); 955 956 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 957 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 958 CSR_READ_2(sc, SK_LINK_CTRL))); 959 960 /* Disable ASF */ 961 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 962 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 963 964 /* Clear I2C IRQ noise */ 965 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 966 967 /* Disable hardware timer */ 968 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 969 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 970 971 /* Disable descriptor polling */ 972 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 973 974 /* Disable time stamps */ 975 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 976 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 977 978 /* Enable RAM interface */ 979 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 980 for (reg = SK_TO0;reg <= SK_TO11; reg++) 981 sk_win_write_1(sc, reg, 36); 982 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 983 for (reg = SK_TO0;reg <= SK_TO11; reg++) 984 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 985 986 /* 987 * Configure interrupt moderation. The moderation timer 988 * defers interrupts specified in the interrupt moderation 989 * timer mask based on the timeout specified in the interrupt 990 * moderation timer init register. Each bit in the timer 991 * register represents one tick, so to specify a timeout in 992 * microseconds, we have to multiply by the correct number of 993 * ticks-per-microsecond. 994 */ 995 switch (sc->sk_type) { 996 case SK_YUKON_EC: 997 case SK_YUKON_EC_U: 998 case SK_YUKON_EX: 999 case SK_YUKON_SUPR: 1000 case SK_YUKON_ULTRA2: 1001 case SK_YUKON_OPTIMA: 1002 case SK_YUKON_PRM: 1003 case SK_YUKON_OPTIMA2: 1004 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1005 break; 1006 case SK_YUKON_FE: 1007 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 1008 break; 1009 case SK_YUKON_FE_P: 1010 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 1011 break; 1012 case SK_YUKON_XL: 1013 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 1014 break; 1015 default: 1016 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1017 break; 1018 } 1019 1020 /* Reset status ring. */ 1021 memset(sc->sk_status_ring, 0, 1022 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1023 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 1024 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1025 sc->sk_status_idx = 0; 1026 1027 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 1028 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 1029 1030 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 1031 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 1032 MSK_ADDR_LO(sc->sk_status_map->dm_segs[0].ds_addr)); 1033 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 1034 MSK_ADDR_HI(sc->sk_status_map->dm_segs[0].ds_addr)); 1035 if (sc->sk_type == SK_YUKON_EC && 1036 sc->sk_rev == SK_YUKON_EC_REV_A1) { 1037 /* WA for dev. #4.3 */ 1038 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 1039 SK_STAT_BMU_TXTHIDX_MSK); 1040 /* WA for dev. #4.18 */ 1041 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 1042 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 1043 } else { 1044 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 1045 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 1046 if (sc->sk_type == SK_YUKON_XL) 1047 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x04); 1048 else 1049 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x10); 1050 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 1051 } 1052 1053 #if 0 1054 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 1055 #endif 1056 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 1057 1058 /* Enable status unit. */ 1059 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 1060 1061 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 1062 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 1063 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 1064 1065 msk_update_int_mod(sc, 0); 1066 } 1067 1068 int 1069 msk_probe(device_t parent, cfdata_t match, void *aux) 1070 { 1071 struct skc_attach_args *sa = aux; 1072 1073 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1074 return 0; 1075 1076 switch (sa->skc_type) { 1077 case SK_YUKON_XL: 1078 case SK_YUKON_EC_U: 1079 case SK_YUKON_EX: 1080 case SK_YUKON_EC: 1081 case SK_YUKON_FE: 1082 case SK_YUKON_FE_P: 1083 case SK_YUKON_SUPR: 1084 case SK_YUKON_ULTRA2: 1085 case SK_YUKON_OPTIMA: 1086 case SK_YUKON_PRM: 1087 case SK_YUKON_OPTIMA2: 1088 return 1; 1089 } 1090 1091 return 0; 1092 } 1093 1094 void 1095 msk_reset(struct sk_if_softc *sc_if) 1096 { 1097 /* GMAC and GPHY Reset */ 1098 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1099 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1100 DELAY(1000); 1101 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1102 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1103 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1104 } 1105 1106 static bool 1107 msk_resume(device_t dv, const pmf_qual_t *qual) 1108 { 1109 struct sk_if_softc *sc_if = device_private(dv); 1110 1111 msk_init_yukon(sc_if); 1112 return true; 1113 } 1114 1115 /* 1116 * Each XMAC chip is attached as a separate logical IP interface. 1117 * Single port cards will have only one logical interface of course. 1118 */ 1119 void 1120 msk_attach(device_t parent, device_t self, void *aux) 1121 { 1122 struct sk_if_softc *sc_if = device_private(self); 1123 struct sk_softc *sc = device_private(parent); 1124 struct skc_attach_args *sa = aux; 1125 struct ifnet *ifp; 1126 struct mii_data * const mii = &sc_if->sk_mii; 1127 void *kva; 1128 int i; 1129 uint32_t chunk; 1130 int mii_flags; 1131 1132 sc_if->sk_dev = self; 1133 sc_if->sk_port = sa->skc_port; 1134 sc_if->sk_softc = sc; 1135 sc->sk_if[sa->skc_port] = sc_if; 1136 1137 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1138 1139 /* 1140 * Get station address for this interface. Note that 1141 * dual port cards actually come with three station 1142 * addresses: one for each port, plus an extra. The 1143 * extra one is used by the SysKonnect driver software 1144 * as a 'virtual' station address for when both ports 1145 * are operating in failover mode. Currently we don't 1146 * use this extra address. 1147 */ 1148 for (i = 0; i < ETHER_ADDR_LEN; i++) 1149 sc_if->sk_enaddr[i] = 1150 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1151 1152 aprint_normal(": Ethernet address %s\n", 1153 ether_sprintf(sc_if->sk_enaddr)); 1154 1155 /* 1156 * Set up RAM buffer addresses. The Yukon2 has a small amount 1157 * of SRAM on it, somewhere between 4K and 48K. We need to 1158 * divide this up between the transmitter and receiver. We 1159 * give the receiver 2/3 of the memory (rounded down), and the 1160 * transmitter whatever remains. 1161 */ 1162 if (sc->sk_ramsize) { 1163 chunk = (2 * (sc->sk_ramsize / sizeof(uint64_t)) / 3) & ~0xff; 1164 sc_if->sk_rx_ramstart = 0; 1165 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 1166 chunk = (sc->sk_ramsize / sizeof(uint64_t)) - chunk; 1167 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 1168 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 1169 1170 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1171 " tx_ramstart=%#x tx_ramend=%#x\n", 1172 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1173 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1174 } 1175 1176 /* Allocate the descriptor queues. */ 1177 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1178 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 1179 BUS_DMA_NOWAIT)) { 1180 aprint_error(": can't alloc rx buffers\n"); 1181 goto fail; 1182 } 1183 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 1184 sc_if->sk_ring_nseg, 1185 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1186 aprint_error(": can't map dma buffers (%zu bytes)\n", 1187 sizeof(struct msk_ring_data)); 1188 goto fail_1; 1189 } 1190 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1191 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1192 &sc_if->sk_ring_map)) { 1193 aprint_error(": can't create dma map\n"); 1194 goto fail_2; 1195 } 1196 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1197 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1198 aprint_error(": can't load dma map\n"); 1199 goto fail_3; 1200 } 1201 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1202 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1203 1204 if (sc->sk_type != SK_YUKON_FE && 1205 sc->sk_type != SK_YUKON_FE_P) 1206 sc_if->sk_pktlen = SK_JLEN; 1207 else 1208 sc_if->sk_pktlen = MCLBYTES; 1209 1210 /* Try to allocate memory for jumbo buffers. */ 1211 if (msk_alloc_jumbo_mem(sc_if)) { 1212 aprint_error(": jumbo buffer allocation failed\n"); 1213 goto fail_3; 1214 } 1215 1216 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1217 if (sc->sk_type != SK_YUKON_FE && 1218 sc->sk_type != SK_YUKON_FE_P) 1219 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1220 1221 ifp = &sc_if->sk_ethercom.ec_if; 1222 ifp->if_softc = sc_if; 1223 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1224 ifp->if_ioctl = msk_ioctl; 1225 ifp->if_start = msk_start; 1226 ifp->if_stop = msk_stop; 1227 ifp->if_init = msk_init; 1228 ifp->if_watchdog = msk_watchdog; 1229 ifp->if_baudrate = 1000000000; 1230 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1231 IFQ_SET_READY(&ifp->if_snd); 1232 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1233 1234 msk_reset(sc_if); 1235 1236 /* 1237 * Do miibus setup. 1238 */ 1239 DPRINTFN(2, ("msk_attach: 1\n")); 1240 1241 mii->mii_ifp = ifp; 1242 mii->mii_readreg = msk_miibus_readreg; 1243 mii->mii_writereg = msk_miibus_writereg; 1244 mii->mii_statchg = msk_miibus_statchg; 1245 1246 sc_if->sk_ethercom.ec_mii = mii; 1247 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1248 mii_flags = MIIF_DOPAUSE; 1249 if (sc->sk_fibertype) 1250 mii_flags |= MIIF_HAVEFIBER; 1251 mii_attach(self, mii, 0xffffffff, 0, MII_OFFSET_ANY, mii_flags); 1252 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1253 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1254 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 1255 0, NULL); 1256 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 1257 } else 1258 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1259 1260 callout_init(&sc_if->sk_tick_ch, 0); 1261 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1262 callout_schedule(&sc_if->sk_tick_ch, hz); 1263 1264 callout_init(&sc_if->sk_tick_rx, 0); 1265 callout_setfunc(&sc_if->sk_tick_rx, msk_fill_rx_tick, sc_if); 1266 1267 /* 1268 * Call MI attach routines. 1269 */ 1270 if_attach(ifp); 1271 if_deferred_start_init(ifp, NULL); 1272 ether_ifattach(ifp, sc_if->sk_enaddr); 1273 1274 if (pmf_device_register(self, NULL, msk_resume)) 1275 pmf_class_network_register(self, ifp); 1276 else 1277 aprint_error_dev(self, "couldn't establish power handler\n"); 1278 1279 if (sc->rnd_attached++ == 0) { 1280 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1281 RND_TYPE_NET, RND_FLAG_DEFAULT); 1282 } 1283 1284 DPRINTFN(2, ("msk_attach: end\n")); 1285 return; 1286 1287 fail_3: 1288 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1289 fail_2: 1290 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1291 fail_1: 1292 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1293 fail: 1294 sc->sk_if[sa->skc_port] = NULL; 1295 } 1296 1297 int 1298 msk_detach(device_t self, int flags) 1299 { 1300 struct sk_if_softc *sc_if = device_private(self); 1301 struct sk_softc *sc = sc_if->sk_softc; 1302 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1303 1304 if (sc->sk_if[sc_if->sk_port] == NULL) 1305 return 0; 1306 1307 msk_stop(ifp, 1); 1308 1309 if (--sc->rnd_attached == 0) 1310 rnd_detach_source(&sc->rnd_source); 1311 1312 callout_halt(&sc_if->sk_tick_ch, NULL); 1313 callout_destroy(&sc_if->sk_tick_ch); 1314 1315 callout_halt(&sc_if->sk_tick_rx, NULL); 1316 callout_destroy(&sc_if->sk_tick_rx); 1317 1318 /* Detach any PHYs we might have. */ 1319 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1320 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1321 1322 /* Delete any remaining media. */ 1323 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY); 1324 1325 pmf_device_deregister(self); 1326 1327 ether_ifdetach(ifp); 1328 if_detach(ifp); 1329 1330 msk_free_jumbo_mem(sc_if); 1331 1332 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_rdata, 1333 sizeof(struct msk_ring_data)); 1334 bus_dmamem_free(sc->sc_dmatag, 1335 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1336 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1337 sc->sk_if[sc_if->sk_port] = NULL; 1338 1339 return 0; 1340 } 1341 1342 int 1343 mskcprint(void *aux, const char *pnp) 1344 { 1345 struct skc_attach_args *sa = aux; 1346 1347 if (pnp) 1348 aprint_normal("msk port %c at %s", 1349 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1350 else 1351 aprint_normal(" port %c", 1352 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1353 return UNCONF; 1354 } 1355 1356 /* 1357 * Attach the interface. Allocate softc structures, do ifmedia 1358 * setup and ethernet/BPF attach. 1359 */ 1360 void 1361 mskc_attach(device_t parent, device_t self, void *aux) 1362 { 1363 struct sk_softc *sc = device_private(self); 1364 struct pci_attach_args *pa = aux; 1365 struct skc_attach_args skca; 1366 pci_chipset_tag_t pc = pa->pa_pc; 1367 pcireg_t command, memtype; 1368 const char *intrstr = NULL; 1369 int rc, sk_nodenum; 1370 uint8_t hw, pmd; 1371 const char *revstr = NULL; 1372 const struct sysctlnode *node; 1373 void *kva; 1374 char intrbuf[PCI_INTRSTR_LEN]; 1375 1376 DPRINTFN(2, ("begin mskc_attach\n")); 1377 1378 sc->sk_dev = self; 1379 /* 1380 * Handle power management nonsense. 1381 */ 1382 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1383 1384 if (command == 0x01) { 1385 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1386 if (command & SK_PSTATE_MASK) { 1387 uint32_t iobase, membase, irq; 1388 1389 /* Save important PCI config data. */ 1390 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1391 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1392 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1393 1394 /* Reset the power state. */ 1395 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1396 "mode -- setting to D0\n", 1397 command & SK_PSTATE_MASK); 1398 command &= 0xFFFFFFFC; 1399 pci_conf_write(pc, pa->pa_tag, 1400 SK_PCI_PWRMGMTCTRL, command); 1401 1402 /* Restore PCI config data. */ 1403 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1404 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1405 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1406 } 1407 } 1408 1409 /* 1410 * Map control/status registers. 1411 */ 1412 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1413 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1414 &sc->sk_bhandle, NULL, &sc->sk_bsize)) { 1415 aprint_error(": can't map mem space\n"); 1416 return; 1417 } 1418 1419 if (pci_dma64_available(pa)) 1420 sc->sc_dmatag = pa->pa_dmat64; 1421 else 1422 sc->sc_dmatag = pa->pa_dmat; 1423 1424 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1425 command |= PCI_COMMAND_MASTER_ENABLE; 1426 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1427 1428 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1429 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1430 1431 /* bail out here if chip is not recognized */ 1432 if (!(SK_IS_YUKON2(sc))) { 1433 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1434 goto fail_1; 1435 } 1436 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1437 1438 /* Allocate interrupt */ 1439 if (pci_intr_alloc(pa, &sc->sk_pihp, NULL, 0)) { 1440 aprint_error(": couldn't map interrupt\n"); 1441 goto fail_1; 1442 } 1443 1444 intrstr = pci_intr_string(pc, sc->sk_pihp[0], intrbuf, sizeof(intrbuf)); 1445 sc->sk_intrhand = pci_intr_establish_xname(pc, sc->sk_pihp[0], IPL_NET, 1446 msk_intr, sc, device_xname(sc->sk_dev)); 1447 if (sc->sk_intrhand == NULL) { 1448 aprint_error(": couldn't establish interrupt"); 1449 if (intrstr != NULL) 1450 aprint_error(" at %s", intrstr); 1451 aprint_error("\n"); 1452 goto fail_1; 1453 } 1454 sc->sk_pc = pc; 1455 1456 if (bus_dmamem_alloc(sc->sc_dmatag, 1457 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1458 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1459 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, BUS_DMA_NOWAIT)) { 1460 aprint_error(": can't alloc status buffers\n"); 1461 goto fail_2; 1462 } 1463 1464 if (bus_dmamem_map(sc->sc_dmatag, 1465 &sc->sk_status_seg, sc->sk_status_nseg, 1466 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1467 &kva, BUS_DMA_NOWAIT)) { 1468 aprint_error(": can't map dma buffers (%zu bytes)\n", 1469 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1470 goto fail_3; 1471 } 1472 if (bus_dmamap_create(sc->sc_dmatag, 1473 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1474 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1475 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1476 aprint_error(": can't create dma map\n"); 1477 goto fail_4; 1478 } 1479 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1480 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1481 NULL, BUS_DMA_NOWAIT)) { 1482 aprint_error(": can't load dma map\n"); 1483 goto fail_5; 1484 } 1485 sc->sk_status_ring = (struct msk_status_desc *)kva; 1486 1487 sc->sk_int_mod = SK_IM_DEFAULT; 1488 sc->sk_int_mod_pending = 0; 1489 1490 /* Reset the adapter. */ 1491 mskc_reset(sc); 1492 1493 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1494 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1495 1496 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1497 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1498 sc->sk_fibertype = 1; 1499 1500 switch (sc->sk_type) { 1501 case SK_YUKON_XL: 1502 sc->sk_name = "Yukon-2 XL"; 1503 break; 1504 case SK_YUKON_EC_U: 1505 sc->sk_name = "Yukon-2 EC Ultra"; 1506 break; 1507 case SK_YUKON_EX: 1508 sc->sk_name = "Yukon-2 Extreme"; 1509 break; 1510 case SK_YUKON_EC: 1511 sc->sk_name = "Yukon-2 EC"; 1512 break; 1513 case SK_YUKON_FE: 1514 sc->sk_name = "Yukon-2 FE"; 1515 break; 1516 case SK_YUKON_FE_P: 1517 sc->sk_name = "Yukon-2 FE+"; 1518 break; 1519 case SK_YUKON_SUPR: 1520 sc->sk_name = "Yukon-2 Supreme"; 1521 break; 1522 case SK_YUKON_ULTRA2: 1523 sc->sk_name = "Yukon-2 Ultra 2"; 1524 break; 1525 case SK_YUKON_OPTIMA: 1526 sc->sk_name = "Yukon-2 Optima"; 1527 break; 1528 case SK_YUKON_PRM: 1529 sc->sk_name = "Yukon-2 Optima Prime"; 1530 break; 1531 case SK_YUKON_OPTIMA2: 1532 sc->sk_name = "Yukon-2 Optima 2"; 1533 break; 1534 default: 1535 sc->sk_name = "Yukon (Unknown)"; 1536 } 1537 1538 if (sc->sk_type == SK_YUKON_XL) { 1539 switch (sc->sk_rev) { 1540 case SK_YUKON_XL_REV_A0: 1541 revstr = "A0"; 1542 break; 1543 case SK_YUKON_XL_REV_A1: 1544 revstr = "A1"; 1545 break; 1546 case SK_YUKON_XL_REV_A2: 1547 revstr = "A2"; 1548 break; 1549 case SK_YUKON_XL_REV_A3: 1550 revstr = "A3"; 1551 break; 1552 default: 1553 break; 1554 } 1555 } 1556 1557 if (sc->sk_type == SK_YUKON_EC) { 1558 switch (sc->sk_rev) { 1559 case SK_YUKON_EC_REV_A1: 1560 revstr = "A1"; 1561 break; 1562 case SK_YUKON_EC_REV_A2: 1563 revstr = "A2"; 1564 break; 1565 case SK_YUKON_EC_REV_A3: 1566 revstr = "A3"; 1567 break; 1568 default: 1569 break; 1570 } 1571 } 1572 1573 if (sc->sk_type == SK_YUKON_FE) { 1574 switch (sc->sk_rev) { 1575 case SK_YUKON_FE_REV_A1: 1576 revstr = "A1"; 1577 break; 1578 case SK_YUKON_FE_REV_A2: 1579 revstr = "A2"; 1580 break; 1581 default: 1582 break; 1583 } 1584 } 1585 1586 if (sc->sk_type == SK_YUKON_EC_U) { 1587 switch (sc->sk_rev) { 1588 case SK_YUKON_EC_U_REV_A0: 1589 revstr = "A0"; 1590 break; 1591 case SK_YUKON_EC_U_REV_A1: 1592 revstr = "A1"; 1593 break; 1594 case SK_YUKON_EC_U_REV_B0: 1595 revstr = "B0"; 1596 break; 1597 case SK_YUKON_EC_U_REV_B1: 1598 revstr = "B1"; 1599 break; 1600 default: 1601 break; 1602 } 1603 } 1604 1605 if (sc->sk_type == SK_YUKON_FE) { 1606 switch (sc->sk_rev) { 1607 case SK_YUKON_FE_REV_A1: 1608 revstr = "A1"; 1609 break; 1610 case SK_YUKON_FE_REV_A2: 1611 revstr = "A2"; 1612 break; 1613 default: 1614 ; 1615 } 1616 } 1617 1618 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1619 revstr = "A0"; 1620 1621 if (sc->sk_type == SK_YUKON_EX) { 1622 switch (sc->sk_rev) { 1623 case SK_YUKON_EX_REV_A0: 1624 revstr = "A0"; 1625 break; 1626 case SK_YUKON_EX_REV_B0: 1627 revstr = "B0"; 1628 break; 1629 default: 1630 ; 1631 } 1632 } 1633 1634 if (sc->sk_type == SK_YUKON_SUPR) { 1635 switch (sc->sk_rev) { 1636 case SK_YUKON_SUPR_REV_A0: 1637 revstr = "A0"; 1638 break; 1639 case SK_YUKON_SUPR_REV_B0: 1640 revstr = "B0"; 1641 break; 1642 case SK_YUKON_SUPR_REV_B1: 1643 revstr = "B1"; 1644 break; 1645 default: 1646 ; 1647 } 1648 } 1649 1650 if (sc->sk_type == SK_YUKON_PRM) { 1651 switch (sc->sk_rev) { 1652 case SK_YUKON_PRM_REV_Z1: 1653 revstr = "Z1"; 1654 break; 1655 case SK_YUKON_PRM_REV_A0: 1656 revstr = "A0"; 1657 break; 1658 default: 1659 ; 1660 } 1661 } 1662 1663 /* Announce the product name. */ 1664 aprint_normal(", %s", sc->sk_name); 1665 if (revstr != NULL) 1666 aprint_normal(" rev. %s", revstr); 1667 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1668 1669 sc->sk_macs = 1; 1670 1671 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1672 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1673 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1674 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1675 sc->sk_macs++; 1676 } 1677 1678 skca.skc_port = SK_PORT_A; 1679 skca.skc_type = sc->sk_type; 1680 skca.skc_rev = sc->sk_rev; 1681 (void)config_found(sc->sk_dev, &skca, mskcprint); 1682 1683 if (sc->sk_macs > 1) { 1684 skca.skc_port = SK_PORT_B; 1685 skca.skc_type = sc->sk_type; 1686 skca.skc_rev = sc->sk_rev; 1687 (void)config_found(sc->sk_dev, &skca, mskcprint); 1688 } 1689 1690 /* Turn on the 'driver is loaded' LED. */ 1691 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1692 1693 /* skc sysctl setup */ 1694 1695 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1696 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1697 SYSCTL_DESCR("mskc per-controller controls"), 1698 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1699 CTL_EOL)) != 0) { 1700 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1701 goto fail_6; 1702 } 1703 1704 sk_nodenum = node->sysctl_num; 1705 1706 /* interrupt moderation time in usecs */ 1707 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1708 CTLFLAG_READWRITE, 1709 CTLTYPE_INT, "int_mod", 1710 SYSCTL_DESCR("msk interrupt moderation timer"), 1711 msk_sysctl_handler, 0, (void *)sc, 1712 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1713 CTL_EOL)) != 0) { 1714 aprint_normal_dev(sc->sk_dev, 1715 "couldn't create int_mod sysctl node\n"); 1716 goto fail_6; 1717 } 1718 1719 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1720 aprint_error_dev(self, "couldn't establish power handler\n"); 1721 1722 return; 1723 1724 fail_6: 1725 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1726 fail_4: 1727 bus_dmamem_unmap(sc->sc_dmatag, kva, 1728 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1729 fail_3: 1730 bus_dmamem_free(sc->sc_dmatag, 1731 &sc->sk_status_seg, sc->sk_status_nseg); 1732 sc->sk_status_nseg = 0; 1733 fail_5: 1734 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1735 fail_2: 1736 pci_intr_disestablish(pc, sc->sk_intrhand); 1737 sc->sk_intrhand = NULL; 1738 fail_1: 1739 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1740 sc->sk_bsize = 0; 1741 } 1742 1743 int 1744 mskc_detach(device_t self, int flags) 1745 { 1746 struct sk_softc *sc = device_private(self); 1747 int rv; 1748 1749 if (sc->sk_intrhand) { 1750 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1751 sc->sk_intrhand = NULL; 1752 } 1753 1754 if (sc->sk_pihp != NULL) { 1755 pci_intr_release(sc->sk_pc, sc->sk_pihp, 1); 1756 sc->sk_pihp = NULL; 1757 } 1758 1759 rv = config_detach_children(self, flags); 1760 if (rv != 0) 1761 return rv; 1762 1763 if (sc->sk_status_nseg > 0) { 1764 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1765 bus_dmamem_unmap(sc->sc_dmatag, sc->sk_status_ring, 1766 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1767 bus_dmamem_free(sc->sc_dmatag, 1768 &sc->sk_status_seg, sc->sk_status_nseg); 1769 } 1770 1771 if (sc->sk_bsize > 0) 1772 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1773 1774 return 0; 1775 } 1776 1777 int 1778 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1779 { 1780 struct sk_softc *sc = sc_if->sk_softc; 1781 struct msk_tx_desc *f = NULL; 1782 uint32_t frag, cur, hiaddr, old_hiaddr, total; 1783 uint32_t entries = 0; 1784 size_t i; 1785 struct sk_txmap_entry *entry; 1786 bus_dmamap_t txmap; 1787 bus_addr_t addr; 1788 1789 DPRINTFN(2, ("msk_encap\n")); 1790 1791 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1792 if (entry == NULL) { 1793 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1794 return ENOBUFS; 1795 } 1796 txmap = entry->dmamap; 1797 1798 cur = frag = *txidx; 1799 1800 #ifdef MSK_DEBUG 1801 if (mskdebug >= 2) 1802 msk_dump_mbuf(m_head); 1803 #endif 1804 1805 /* 1806 * Start packing the mbufs in this chain into 1807 * the fragment pointers. Stop when we run out 1808 * of fragments or hit the end of the mbuf chain. 1809 */ 1810 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1811 BUS_DMA_NOWAIT)) { 1812 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1813 return ENOBUFS; 1814 } 1815 1816 /* Count how many tx descriptors needed. */ 1817 hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1818 for (total = i = 0; i < txmap->dm_nsegs; i++) { 1819 if (hiaddr != MSK_ADDR_HI(txmap->dm_segs[i].ds_addr)) { 1820 hiaddr = MSK_ADDR_HI(txmap->dm_segs[i].ds_addr); 1821 total++; 1822 } 1823 total++; 1824 } 1825 1826 if (total > MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2) { 1827 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1828 bus_dmamap_unload(sc->sc_dmatag, txmap); 1829 return ENOBUFS; 1830 } 1831 1832 DPRINTFN(2, ("msk_encap: dm_nsegs=%d total desc=%u\n", 1833 txmap->dm_nsegs, total)); 1834 1835 /* Sync the DMA map. */ 1836 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1837 BUS_DMASYNC_PREWRITE); 1838 1839 old_hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1840 for (i = 0; i < txmap->dm_nsegs; i++) { 1841 addr = txmap->dm_segs[i].ds_addr; 1842 DPRINTFN(2, ("msk_encap: addr %llx\n", 1843 (unsigned long long)addr)); 1844 hiaddr = MSK_ADDR_HI(addr); 1845 1846 if (sc_if->sk_cdata.sk_tx_hiaddr != hiaddr) { 1847 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1848 f->sk_addr = htole32(hiaddr); 1849 f->sk_len = 0; 1850 f->sk_ctl = 0; 1851 if (i == 0) 1852 f->sk_opcode = SK_Y2_BMUOPC_ADDR64; 1853 else 1854 f->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 1855 sc_if->sk_cdata.sk_tx_hiaddr = hiaddr; 1856 SK_INC(frag, MSK_TX_RING_CNT); 1857 entries++; 1858 DPRINTFN(10, ("%s: tx ADDR64: %#x\n", 1859 sc_if->sk_ethercom.ec_if.if_xname, hiaddr)); 1860 } 1861 1862 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1863 f->sk_addr = htole32(MSK_ADDR_LO(addr)); 1864 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1865 f->sk_ctl = 0; 1866 if (i == 0) { 1867 if (hiaddr != old_hiaddr) 1868 f->sk_opcode = SK_Y2_TXOPC_PACKET | SK_Y2_TXOPC_OWN; 1869 else 1870 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1871 } else 1872 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1873 cur = frag; 1874 SK_INC(frag, MSK_TX_RING_CNT); 1875 entries++; 1876 } 1877 KASSERTMSG(entries == total, "entries %u total %u", entries, total); 1878 1879 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1880 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1881 1882 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1883 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1884 1885 /* Sync descriptors before handing to chip */ 1886 MSK_CDTXSYNC(sc_if, *txidx, entries, 1887 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1888 1889 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1890 1891 /* Sync first descriptor to hand it off */ 1892 MSK_CDTXSYNC(sc_if, *txidx, 1, 1893 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1894 1895 sc_if->sk_cdata.sk_tx_cnt += entries; 1896 1897 #ifdef MSK_DEBUG 1898 if (mskdebug >= 2) { 1899 struct msk_tx_desc *le; 1900 uint32_t idx; 1901 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1902 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1903 msk_dump_txdesc(le, idx); 1904 } 1905 } 1906 #endif 1907 1908 *txidx = frag; 1909 1910 DPRINTFN(2, ("msk_encap: successful: %u entries\n", entries)); 1911 1912 return 0; 1913 } 1914 1915 void 1916 msk_start(struct ifnet *ifp) 1917 { 1918 struct sk_if_softc *sc_if = ifp->if_softc; 1919 struct mbuf *m_head = NULL; 1920 uint32_t idx = sc_if->sk_cdata.sk_tx_prod; 1921 int pkts = 0; 1922 1923 DPRINTFN(2, ("msk_start\n")); 1924 1925 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1926 IFQ_POLL(&ifp->if_snd, m_head); 1927 if (m_head == NULL) 1928 break; 1929 1930 /* 1931 * Pack the data into the transmit ring. If we 1932 * don't have room, set the OACTIVE flag and wait 1933 * for the NIC to drain the ring. 1934 */ 1935 if (msk_encap(sc_if, m_head, &idx)) { 1936 ifp->if_flags |= IFF_OACTIVE; 1937 break; 1938 } 1939 1940 /* now we are committed to transmit the packet */ 1941 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1942 pkts++; 1943 1944 /* 1945 * If there's a BPF listener, bounce a copy of this frame 1946 * to him. 1947 */ 1948 bpf_mtap(ifp, m_head, BPF_D_OUT); 1949 } 1950 if (pkts == 0) 1951 return; 1952 1953 /* Transmit */ 1954 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1955 sc_if->sk_cdata.sk_tx_prod = idx; 1956 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1957 1958 /* Set a timeout in case the chip goes out to lunch. */ 1959 ifp->if_timer = 5; 1960 } 1961 } 1962 1963 void 1964 msk_watchdog(struct ifnet *ifp) 1965 { 1966 struct sk_if_softc *sc_if = ifp->if_softc; 1967 1968 /* 1969 * Reclaim first as there is a possibility of losing Tx completion 1970 * interrupts. 1971 */ 1972 msk_txeof(sc_if); 1973 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1974 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1975 1976 ifp->if_oerrors++; 1977 1978 /* XXX Resets both ports; we shouldn't do that. */ 1979 mskc_reset(sc_if->sk_softc); 1980 msk_reset(sc_if); 1981 msk_init(ifp); 1982 } 1983 } 1984 1985 static bool 1986 mskc_suspend(device_t dv, const pmf_qual_t *qual) 1987 { 1988 struct sk_softc *sc = device_private(dv); 1989 1990 DPRINTFN(2, ("mskc_suspend\n")); 1991 1992 /* Turn off the 'driver is loaded' LED. */ 1993 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1994 1995 return true; 1996 } 1997 1998 static bool 1999 mskc_resume(device_t dv, const pmf_qual_t *qual) 2000 { 2001 struct sk_softc *sc = device_private(dv); 2002 2003 DPRINTFN(2, ("mskc_resume\n")); 2004 2005 mskc_reset(sc); 2006 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 2007 2008 return true; 2009 } 2010 2011 static __inline int 2012 msk_rxvalid(struct sk_softc *sc, uint32_t stat, uint32_t len) 2013 { 2014 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 2015 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 2016 YU_RXSTAT_JABBER)) != 0 || 2017 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 2018 YU_RXSTAT_BYTES(stat) != len) 2019 return 0; 2020 2021 return 1; 2022 } 2023 2024 void 2025 msk_rxeof(struct sk_if_softc *sc_if, uint16_t len, uint32_t rxstat) 2026 { 2027 struct sk_softc *sc = sc_if->sk_softc; 2028 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2029 struct mbuf *m; 2030 unsigned cur, prod, tail, total_len = len; 2031 bus_dmamap_t dmamap; 2032 2033 cur = sc_if->sk_cdata.sk_rx_cons; 2034 prod = sc_if->sk_cdata.sk_rx_prod; 2035 2036 /* Sync the descriptor */ 2037 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2038 2039 DPRINTFN(2, ("msk_rxeof: cur %u prod %u rx_cnt %u\n", cur, prod, 2040 sc_if->sk_cdata.sk_rx_cnt)); 2041 2042 while (prod != cur) { 2043 tail = cur; 2044 SK_INC(cur, MSK_RX_RING_CNT); 2045 2046 sc_if->sk_cdata.sk_rx_cnt--; 2047 m = sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf; 2048 sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf = NULL; 2049 if (m != NULL) 2050 break; /* found it */ 2051 } 2052 sc_if->sk_cdata.sk_rx_cons = cur; 2053 DPRINTFN(2, ("msk_rxeof: cur %u rx_cnt %u m %p\n", cur, 2054 sc_if->sk_cdata.sk_rx_cnt, m)); 2055 2056 if (m == NULL) 2057 return; 2058 2059 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2060 2061 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2062 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2063 2064 if (total_len < SK_MIN_FRAMELEN || 2065 total_len > ETHER_MAX_LEN_JUMBO || 2066 msk_rxvalid(sc, rxstat, total_len) == 0) { 2067 ifp->if_ierrors++; 2068 m_freem(m); 2069 return; 2070 } 2071 2072 m_set_rcvif(m, ifp); 2073 m->m_pkthdr.len = m->m_len = total_len; 2074 2075 /* pass it on. */ 2076 if_percpuq_enqueue(ifp->if_percpuq, m); 2077 } 2078 2079 void 2080 msk_txeof(struct sk_if_softc *sc_if) 2081 { 2082 struct sk_softc *sc = sc_if->sk_softc; 2083 struct msk_tx_desc *cur_tx; 2084 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2085 uint32_t idx, reg, sk_ctl; 2086 struct sk_txmap_entry *entry; 2087 2088 DPRINTFN(2, ("msk_txeof\n")); 2089 2090 if (sc_if->sk_port == SK_PORT_A) 2091 reg = SK_STAT_BMU_TXA1_RIDX; 2092 else 2093 reg = SK_STAT_BMU_TXA2_RIDX; 2094 2095 /* 2096 * Go through our tx ring and free mbufs for those 2097 * frames that have been sent. 2098 */ 2099 idx = sc_if->sk_cdata.sk_tx_cons; 2100 while (idx != sk_win_read_2(sc, reg)) { 2101 MSK_CDTXSYNC(sc_if, idx, 1, 2102 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2103 2104 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2105 sk_ctl = cur_tx->sk_ctl; 2106 #ifdef MSK_DEBUG 2107 if (mskdebug >= 2) 2108 msk_dump_txdesc(cur_tx, idx); 2109 #endif 2110 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 2111 ifp->if_opackets++; 2112 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2113 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2114 2115 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2116 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2117 2118 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2119 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2120 link); 2121 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2122 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2123 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2124 } 2125 sc_if->sk_cdata.sk_tx_cnt--; 2126 SK_INC(idx, MSK_TX_RING_CNT); 2127 } 2128 if (idx == sc_if->sk_cdata.sk_tx_cons) 2129 return; 2130 2131 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2132 2133 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 2134 ifp->if_flags &= ~IFF_OACTIVE; 2135 2136 sc_if->sk_cdata.sk_tx_cons = idx; 2137 } 2138 2139 void 2140 msk_fill_rx_ring(struct sk_if_softc *sc_if) 2141 { 2142 /* Make sure to not completely wrap around */ 2143 while (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT - 1)) { 2144 if (msk_newbuf(sc_if, 2145 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 2146 goto schedretry; 2147 } 2148 } 2149 2150 return; 2151 2152 schedretry: 2153 /* Try later */ 2154 callout_schedule(&sc_if->sk_tick_rx, hz/2); 2155 } 2156 2157 static void 2158 msk_fill_rx_tick(void *xsc_if) 2159 { 2160 struct sk_if_softc *sc_if = xsc_if; 2161 int s, rx_prod; 2162 2163 KASSERT(KERNEL_LOCKED_P()); /* XXXSMP */ 2164 2165 s = splnet(); 2166 rx_prod = sc_if->sk_cdata.sk_rx_prod; 2167 msk_fill_rx_ring(sc_if); 2168 if (rx_prod != sc_if->sk_cdata.sk_rx_prod) { 2169 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2170 sc_if->sk_cdata.sk_rx_prod); 2171 } 2172 splx(s); 2173 } 2174 2175 void 2176 msk_tick(void *xsc_if) 2177 { 2178 struct sk_if_softc *sc_if = xsc_if; 2179 struct mii_data *mii = &sc_if->sk_mii; 2180 int s; 2181 2182 s = splnet(); 2183 mii_tick(mii); 2184 splx(s); 2185 2186 callout_schedule(&sc_if->sk_tick_ch, hz); 2187 } 2188 2189 void 2190 msk_intr_yukon(struct sk_if_softc *sc_if) 2191 { 2192 uint8_t status; 2193 2194 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2195 /* RX overrun */ 2196 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2197 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2198 SK_RFCTL_RX_FIFO_OVER); 2199 } 2200 /* TX underrun */ 2201 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2202 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 2203 SK_TFCTL_TX_FIFO_UNDER); 2204 } 2205 2206 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 2207 } 2208 2209 int 2210 msk_intr(void *xsc) 2211 { 2212 struct sk_softc *sc = xsc; 2213 struct sk_if_softc *sc_if; 2214 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2215 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2216 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2217 int claimed = 0; 2218 uint32_t status; 2219 struct msk_status_desc *cur_st; 2220 2221 status = CSR_READ_4(sc, SK_Y2_ISSR2); 2222 if (status == 0xffffffff) 2223 return 0; 2224 if (status == 0) { 2225 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2226 return 0; 2227 } 2228 2229 status = CSR_READ_4(sc, SK_ISR); 2230 2231 if (sc_if0 != NULL) 2232 ifp0 = &sc_if0->sk_ethercom.ec_if; 2233 if (sc_if1 != NULL) 2234 ifp1 = &sc_if1->sk_ethercom.ec_if; 2235 2236 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 2237 (ifp0->if_flags & IFF_RUNNING)) { 2238 msk_intr_yukon(sc_if0); 2239 } 2240 2241 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 2242 (ifp1->if_flags & IFF_RUNNING)) { 2243 msk_intr_yukon(sc_if1); 2244 } 2245 2246 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2247 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2248 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2249 2250 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 2251 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 2252 switch (cur_st->sk_opcode) { 2253 case SK_Y2_STOPC_RXSTAT: 2254 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 2255 if (sc_if) { 2256 msk_rxeof(sc_if, letoh16(cur_st->sk_len), 2257 letoh32(cur_st->sk_status)); 2258 if (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 2259 msk_fill_rx_tick(sc_if); 2260 } 2261 break; 2262 case SK_Y2_STOPC_TXSTAT: 2263 if (sc_if0) 2264 msk_txeof(sc_if0); 2265 if (sc_if1) 2266 msk_txeof(sc_if1); 2267 break; 2268 default: 2269 aprint_error("opcode=0x%x\n", cur_st->sk_opcode); 2270 break; 2271 } 2272 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 2273 2274 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2275 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2276 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2277 } 2278 2279 if (status & SK_Y2_IMR_BMU) { 2280 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 2281 claimed = 1; 2282 } 2283 2284 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2285 2286 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2287 if_schedule_deferred_start(ifp0); 2288 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2289 if_schedule_deferred_start(ifp1); 2290 2291 KASSERT(sc->rnd_attached > 0); 2292 rnd_add_uint32(&sc->rnd_source, status); 2293 2294 if (sc->sk_int_mod_pending) 2295 msk_update_int_mod(sc, 1); 2296 2297 return claimed; 2298 } 2299 2300 void 2301 msk_init_yukon(struct sk_if_softc *sc_if) 2302 { 2303 uint32_t v; 2304 uint16_t reg; 2305 struct sk_softc *sc; 2306 int i; 2307 2308 sc = sc_if->sk_softc; 2309 2310 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 2311 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2312 2313 DPRINTFN(6, ("msk_init_yukon: 1\n")); 2314 2315 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 2316 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2317 2318 DPRINTFN(6, ("msk_init_yukon: 3\n")); 2319 2320 /* unused read of the interrupt source register */ 2321 DPRINTFN(6, ("msk_init_yukon: 4\n")); 2322 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2323 2324 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2325 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2326 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2327 2328 /* MIB Counter Clear Mode set */ 2329 reg |= YU_PAR_MIB_CLR; 2330 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2331 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2332 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2333 2334 /* MIB Counter Clear Mode clear */ 2335 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2336 reg &= ~YU_PAR_MIB_CLR; 2337 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2338 2339 /* receive control reg */ 2340 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2341 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2342 2343 /* transmit control register */ 2344 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2345 2346 /* transmit flow control register */ 2347 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2348 2349 /* transmit parameter register */ 2350 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2351 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2352 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2353 2354 /* serial mode register */ 2355 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2356 reg = YU_SMR_DATA_BLIND(0x1c) | 2357 YU_SMR_MFL_VLAN | 2358 YU_SMR_IPG_DATA(0x1e); 2359 2360 if (sc->sk_type != SK_YUKON_FE && 2361 sc->sk_type != SK_YUKON_FE_P) 2362 reg |= YU_SMR_MFL_JUMBO; 2363 2364 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2365 2366 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2367 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2368 /* msk_attach calls me before ether_ifattach so check null */ 2369 if (ifp != NULL && ifp->if_sadl != NULL) 2370 memcpy(sc_if->sk_enaddr, CLLADDR(ifp->if_sadl), 2371 sizeof(sc_if->sk_enaddr)); 2372 /* Setup Yukon's address */ 2373 for (i = 0; i < 3; i++) { 2374 /* Write Source Address 1 (unicast filter) */ 2375 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2376 sc_if->sk_enaddr[i * 2] | 2377 sc_if->sk_enaddr[i * 2 + 1] << 8); 2378 } 2379 2380 for (i = 0; i < 3; i++) { 2381 reg = sk_win_read_2(sc_if->sk_softc, 2382 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2383 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2384 } 2385 2386 /* Set promiscuous mode */ 2387 msk_setpromisc(sc_if); 2388 2389 /* Set multicast filter */ 2390 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2391 msk_setmulti(sc_if); 2392 2393 /* enable interrupt mask for counter overflows */ 2394 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2395 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2396 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2397 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2398 2399 /* Configure RX MAC FIFO Flush Mask */ 2400 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2401 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2402 YU_RXSTAT_JABBER; 2403 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2404 2405 /* Configure RX MAC FIFO */ 2406 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2407 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2408 SK_RFCTL_FIFO_FLUSH_ON); 2409 2410 /* Increase flush threshold to 64 bytes */ 2411 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2412 SK_RFCTL_FIFO_THRESHOLD + 1); 2413 2414 /* Configure TX MAC FIFO */ 2415 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2416 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2417 2418 #if 1 2419 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2420 #endif 2421 DPRINTFN(6, ("msk_init_yukon: end\n")); 2422 } 2423 2424 /* 2425 * Note that to properly initialize any part of the GEnesis chip, 2426 * you first have to take it out of reset mode. 2427 */ 2428 int 2429 msk_init(struct ifnet *ifp) 2430 { 2431 struct sk_if_softc *sc_if = ifp->if_softc; 2432 struct sk_softc *sc = sc_if->sk_softc; 2433 int rc = 0, s; 2434 uint32_t imr, imtimer_ticks; 2435 2436 2437 DPRINTFN(2, ("msk_init\n")); 2438 2439 s = splnet(); 2440 2441 /* Cancel pending I/O and free all RX/TX buffers. */ 2442 msk_stop(ifp, 1); 2443 2444 /* Configure I2C registers */ 2445 2446 /* Configure XMAC(s) */ 2447 msk_init_yukon(sc_if); 2448 if ((rc = ether_mediachange(ifp)) != 0) 2449 goto out; 2450 2451 /* Configure transmit arbiter(s) */ 2452 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2453 #if 0 2454 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); 2455 #endif 2456 2457 if (sc->sk_ramsize) { 2458 /* Configure RAMbuffers */ 2459 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2460 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2461 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2462 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2463 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2464 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2465 2466 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2467 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2468 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2469 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2470 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2471 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2472 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2473 } 2474 2475 /* Configure BMUs */ 2476 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2477 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2478 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2479 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2480 2481 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2482 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2483 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2484 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2485 2486 /* Make sure the sync transmit queue is disabled. */ 2487 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2488 2489 /* Init descriptors */ 2490 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2491 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2492 "memory for rx buffers\n"); 2493 msk_stop(ifp, 1); 2494 splx(s); 2495 return ENOBUFS; 2496 } 2497 2498 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2499 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2500 "memory for tx buffers\n"); 2501 msk_stop(ifp, 1); 2502 splx(s); 2503 return ENOBUFS; 2504 } 2505 2506 /* Set interrupt moderation if changed via sysctl. */ 2507 switch (sc->sk_type) { 2508 case SK_YUKON_EC: 2509 case SK_YUKON_EC_U: 2510 case SK_YUKON_EX: 2511 case SK_YUKON_SUPR: 2512 case SK_YUKON_ULTRA2: 2513 case SK_YUKON_OPTIMA: 2514 case SK_YUKON_PRM: 2515 case SK_YUKON_OPTIMA2: 2516 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2517 break; 2518 case SK_YUKON_FE: 2519 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2520 break; 2521 case SK_YUKON_FE_P: 2522 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 2523 break; 2524 case SK_YUKON_XL: 2525 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2526 break; 2527 default: 2528 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2529 } 2530 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2531 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2532 sk_win_write_4(sc, SK_IMTIMERINIT, 2533 SK_IM_USECS(sc->sk_int_mod)); 2534 aprint_verbose_dev(sc->sk_dev, 2535 "interrupt moderation is %d us\n", sc->sk_int_mod); 2536 } 2537 2538 /* Initialize prefetch engine. */ 2539 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2540 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2541 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2542 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2543 MSK_RX_RING_ADDR(sc_if, 0)); 2544 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2545 (uint64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2546 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2547 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2548 2549 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2550 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2551 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2552 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2553 MSK_TX_RING_ADDR(sc_if, 0)); 2554 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2555 (uint64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2556 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2557 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2558 2559 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2560 sc_if->sk_cdata.sk_rx_prod); 2561 2562 /* Configure interrupt handling */ 2563 if (sc_if->sk_port == SK_PORT_A) 2564 sc->sk_intrmask |= SK_Y2_INTRS1; 2565 else 2566 sc->sk_intrmask |= SK_Y2_INTRS2; 2567 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2568 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2569 2570 ifp->if_flags |= IFF_RUNNING; 2571 ifp->if_flags &= ~IFF_OACTIVE; 2572 2573 callout_schedule(&sc_if->sk_tick_ch, hz); 2574 2575 out: 2576 splx(s); 2577 return rc; 2578 } 2579 2580 /* 2581 * Note: the logic of second parameter is inverted compared to OpenBSD 2582 * code, since this code uses the function as if_stop hook too. 2583 */ 2584 void 2585 msk_stop(struct ifnet *ifp, int disable) 2586 { 2587 struct sk_if_softc *sc_if = ifp->if_softc; 2588 struct sk_softc *sc = sc_if->sk_softc; 2589 struct sk_txmap_entry *dma; 2590 int i; 2591 2592 DPRINTFN(2, ("msk_stop\n")); 2593 2594 callout_stop(&sc_if->sk_tick_ch); 2595 callout_stop(&sc_if->sk_tick_rx); 2596 2597 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2598 2599 /* Stop transfer of Tx descriptors */ 2600 2601 /* Stop transfer of Rx descriptors */ 2602 2603 if (disable) { 2604 /* Turn off various components of this interface. */ 2605 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2606 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2607 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2608 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2609 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2610 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2611 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2612 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2613 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2614 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2615 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2616 2617 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2618 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2619 2620 /* Disable interrupts */ 2621 if (sc_if->sk_port == SK_PORT_A) 2622 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2623 else 2624 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2625 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2626 } 2627 2628 /* Free RX and TX mbufs still in the queues. */ 2629 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2630 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2631 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2632 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2633 } 2634 } 2635 2636 sc_if->sk_cdata.sk_rx_prod = 0; 2637 sc_if->sk_cdata.sk_rx_cons = 0; 2638 sc_if->sk_cdata.sk_rx_cnt = 0; 2639 2640 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2641 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2642 dma = sc_if->sk_cdata.sk_tx_map[i]; 2643 2644 bus_dmamap_sync(sc->sc_dmatag, dma->dmamap, 0, 2645 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2646 2647 bus_dmamap_unload(sc->sc_dmatag, dma->dmamap); 2648 #if 1 2649 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2650 sc_if->sk_cdata.sk_tx_map[i], link); 2651 sc_if->sk_cdata.sk_tx_map[i] = 0; 2652 #endif 2653 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2654 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2655 } 2656 } 2657 2658 #if 1 2659 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2660 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2661 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2662 free(dma, M_DEVBUF); 2663 } 2664 #endif 2665 } 2666 2667 CFATTACH_DECL3_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2668 mskc_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2669 2670 CFATTACH_DECL3_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2671 msk_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2672 2673 #ifdef MSK_DEBUG 2674 void 2675 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2676 { 2677 #define DESC_PRINT(X) \ 2678 if (X) \ 2679 printf("txdesc[%d]." #X "=%#x\n", \ 2680 idx, X); 2681 2682 DESC_PRINT(letoh32(le->sk_addr)); 2683 DESC_PRINT(letoh16(le->sk_len)); 2684 DESC_PRINT(le->sk_ctl); 2685 DESC_PRINT(le->sk_opcode); 2686 #undef DESC_PRINT 2687 } 2688 2689 void 2690 msk_dump_bytes(const char *data, int len) 2691 { 2692 int c, i, j; 2693 2694 for (i = 0; i < len; i += 16) { 2695 printf("%08x ", i); 2696 c = len - i; 2697 if (c > 16) c = 16; 2698 2699 for (j = 0; j < c; j++) { 2700 printf("%02x ", data[i + j] & 0xff); 2701 if ((j & 0xf) == 7 && j > 0) 2702 printf(" "); 2703 } 2704 2705 for (; j < 16; j++) 2706 printf(" "); 2707 printf(" "); 2708 2709 for (j = 0; j < c; j++) { 2710 int ch = data[i + j] & 0xff; 2711 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2712 } 2713 2714 printf("\n"); 2715 2716 if (c < 16) 2717 break; 2718 } 2719 } 2720 2721 void 2722 msk_dump_mbuf(struct mbuf *m) 2723 { 2724 int count = m->m_pkthdr.len; 2725 2726 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2727 2728 while (count > 0 && m) { 2729 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2730 m, m->m_data, m->m_len); 2731 if (mskdebug >= 4) 2732 msk_dump_bytes(mtod(m, char *), m->m_len); 2733 2734 count -= m->m_len; 2735 m = m->m_next; 2736 } 2737 } 2738 #endif 2739 2740 static int 2741 msk_sysctl_handler(SYSCTLFN_ARGS) 2742 { 2743 int error, t; 2744 struct sysctlnode node; 2745 struct sk_softc *sc; 2746 2747 node = *rnode; 2748 sc = node.sysctl_data; 2749 t = sc->sk_int_mod; 2750 node.sysctl_data = &t; 2751 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2752 if (error || newp == NULL) 2753 return error; 2754 2755 if (t < SK_IM_MIN || t > SK_IM_MAX) 2756 return EINVAL; 2757 2758 /* update the softc with sysctl-changed value, and mark 2759 for hardware update */ 2760 sc->sk_int_mod = t; 2761 sc->sk_int_mod_pending = 1; 2762 return 0; 2763 } 2764 2765 /* 2766 * Set up sysctl(3) MIB, hw.msk.* - Individual controllers will be 2767 * set up in mskc_attach() 2768 */ 2769 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2770 { 2771 int rc; 2772 const struct sysctlnode *node; 2773 2774 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2775 0, CTLTYPE_NODE, "msk", 2776 SYSCTL_DESCR("msk interface controls"), 2777 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2778 goto err; 2779 } 2780 2781 msk_root_num = node->sysctl_num; 2782 return; 2783 2784 err: 2785 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2786 } 2787
Indexes created Thu Oct 02 10:09:58 GMT 2025