if_msk.c revision 1.96
1 /* $NetBSD: if_msk.c,v 1.96 2019/12/01 12:47:10 maxv Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.79 2009/10/15 17:54:56 deraadt Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.96 2019/12/01 12:47:10 maxv Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/mutex.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/device.h> 66 #include <sys/queue.h> 67 #include <sys/callout.h> 68 #include <sys/sysctl.h> 69 #include <sys/endian.h> 70 #ifdef __NetBSD__ 71 #define letoh16 htole16 72 #define letoh32 htole32 73 #endif 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #include <net/if_media.h> 80 81 #include <net/bpf.h> 82 #include <sys/rndsource.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 #include <dev/mii/brgphyreg.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 92 #include <dev/pci/if_skreg.h> 93 #include <dev/pci/if_mskvar.h> 94 95 static int mskc_probe(device_t, cfdata_t, void *); 96 static void mskc_attach(device_t, device_t, void *); 97 static int mskc_detach(device_t, int); 98 static void mskc_reset(struct sk_softc *); 99 static bool mskc_suspend(device_t, const pmf_qual_t *); 100 static bool mskc_resume(device_t, const pmf_qual_t *); 101 static int msk_probe(device_t, cfdata_t, void *); 102 static void msk_attach(device_t, device_t, void *); 103 static int msk_detach(device_t, int); 104 static void msk_reset(struct sk_if_softc *); 105 static int mskcprint(void *, const char *); 106 static int msk_intr(void *); 107 static void msk_intr_yukon(struct sk_if_softc *); 108 static void msk_rxeof(struct sk_if_softc *, uint16_t, uint32_t); 109 static void msk_txeof(struct sk_if_softc *); 110 static int msk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 111 static void msk_start(struct ifnet *); 112 static int msk_ioctl(struct ifnet *, u_long, void *); 113 static int msk_init(struct ifnet *); 114 static void msk_init_yukon(struct sk_if_softc *); 115 static void msk_stop(struct ifnet *, int); 116 static void msk_watchdog(struct ifnet *); 117 static int msk_newbuf(struct sk_if_softc *, bus_dmamap_t); 118 static int msk_alloc_jumbo_mem(struct sk_if_softc *); 119 static void *msk_jalloc(struct sk_if_softc *); 120 static void msk_jfree(struct mbuf *, void *, size_t, void *); 121 static int msk_init_rx_ring(struct sk_if_softc *); 122 static int msk_init_tx_ring(struct sk_if_softc *); 123 static void msk_fill_rx_ring(struct sk_if_softc *); 124 125 static void msk_update_int_mod(struct sk_softc *, int); 126 127 static int msk_miibus_readreg(device_t, int, int, uint16_t *); 128 static int msk_miibus_writereg(device_t, int, int, uint16_t); 129 static void msk_miibus_statchg(struct ifnet *); 130 131 static void msk_setmulti(struct sk_if_softc *); 132 static void msk_setpromisc(struct sk_if_softc *); 133 static void msk_tick(void *); 134 static void msk_fill_rx_tick(void *); 135 136 /* #define MSK_DEBUG 1 */ 137 #ifdef MSK_DEBUG 138 #define DPRINTF(x) if (mskdebug) printf x 139 #define DPRINTFN(n, x) if (mskdebug >= (n)) printf x 140 int mskdebug = MSK_DEBUG; 141 142 static void msk_dump_txdesc(struct msk_tx_desc *, int); 143 static void msk_dump_mbuf(struct mbuf *); 144 static void msk_dump_bytes(const char *, int); 145 #else 146 #define DPRINTF(x) 147 #define DPRINTFN(n, x) 148 #endif 149 150 static int msk_sysctl_handler(SYSCTLFN_PROTO); 151 static int msk_root_num; 152 153 #define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL) 154 #define MSK_ADDR_HI(x) ((uint64_t) (x) >> 32) 155 156 /* supported device vendors */ 157 static const struct msk_product { 158 pci_vendor_id_t msk_vendor; 159 pci_product_id_t msk_product; 160 } msk_products[] = { 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 163 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 164 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8079 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 197 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 198 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 199 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 200 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 201 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 }, 202 { 0, 0 } 203 }; 204 205 static inline uint32_t 206 sk_win_read_4(struct sk_softc *sc, uint32_t reg) 207 { 208 return CSR_READ_4(sc, reg); 209 } 210 211 static inline uint16_t 212 sk_win_read_2(struct sk_softc *sc, uint32_t reg) 213 { 214 return CSR_READ_2(sc, reg); 215 } 216 217 static inline uint8_t 218 sk_win_read_1(struct sk_softc *sc, uint32_t reg) 219 { 220 return CSR_READ_1(sc, reg); 221 } 222 223 static inline void 224 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x) 225 { 226 CSR_WRITE_4(sc, reg, x); 227 } 228 229 static inline void 230 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x) 231 { 232 CSR_WRITE_2(sc, reg, x); 233 } 234 235 static inline void 236 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x) 237 { 238 CSR_WRITE_1(sc, reg, x); 239 } 240 241 static int 242 msk_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 243 { 244 struct sk_if_softc *sc_if = device_private(dev); 245 uint16_t data; 246 int i; 247 248 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 249 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 250 251 for (i = 0; i < SK_TIMEOUT; i++) { 252 DELAY(1); 253 data = SK_YU_READ_2(sc_if, YUKON_SMICR); 254 if (data & YU_SMICR_READ_VALID) 255 break; 256 } 257 258 if (i == SK_TIMEOUT) { 259 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 260 return ETIMEDOUT; 261 } 262 263 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, SK_TIMEOUT)); 264 265 *val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 266 267 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#hx\n", 268 phy, reg, *val)); 269 270 return 0; 271 } 272 273 static int 274 msk_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 275 { 276 struct sk_if_softc *sc_if = device_private(dev); 277 int i; 278 279 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#hx\n", 280 phy, reg, val)); 281 282 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 283 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 284 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 285 286 for (i = 0; i < SK_TIMEOUT; i++) { 287 DELAY(1); 288 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 289 break; 290 } 291 292 if (i == SK_TIMEOUT) { 293 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 294 return ETIMEDOUT; 295 } 296 297 return 0; 298 } 299 300 static void 301 msk_miibus_statchg(struct ifnet *ifp) 302 { 303 struct sk_if_softc *sc_if = ifp->if_softc; 304 struct mii_data *mii = &sc_if->sk_mii; 305 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 306 int gpcr; 307 308 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 309 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 310 311 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 312 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 313 /* Set speed. */ 314 gpcr |= YU_GPCR_SPEED_DIS; 315 switch (IFM_SUBTYPE(mii->mii_media_active)) { 316 case IFM_1000_SX: 317 case IFM_1000_LX: 318 case IFM_1000_CX: 319 case IFM_1000_T: 320 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 321 break; 322 case IFM_100_TX: 323 gpcr |= YU_GPCR_SPEED; 324 break; 325 } 326 327 /* Set duplex. */ 328 gpcr |= YU_GPCR_DPLX_DIS; 329 if ((mii->mii_media_active & IFM_FDX) != 0) 330 gpcr |= YU_GPCR_DUPLEX; 331 332 /* Disable flow control. */ 333 gpcr |= YU_GPCR_FCTL_DIS; 334 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 335 } 336 337 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 338 339 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 340 SK_YU_READ_2(sc_if, YUKON_GPCR))); 341 } 342 343 static void 344 msk_setmulti(struct sk_if_softc *sc_if) 345 { 346 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 347 uint32_t hashes[2] = { 0, 0 }; 348 int h; 349 struct ethercom *ec = &sc_if->sk_ethercom; 350 struct ether_multi *enm; 351 struct ether_multistep step; 352 uint16_t reg; 353 354 /* First, zot all the existing filters. */ 355 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 356 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 357 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 358 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 359 360 361 /* Now program new ones. */ 362 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 363 reg |= YU_RCR_UFLEN; 364 allmulti: 365 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 366 if ((ifp->if_flags & IFF_PROMISC) != 0) 367 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 368 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 369 hashes[0] = 0xFFFFFFFF; 370 hashes[1] = 0xFFFFFFFF; 371 } 372 } else { 373 /* First find the tail of the list. */ 374 ETHER_LOCK(ec); 375 ETHER_FIRST_MULTI(step, ec, enm); 376 while (enm != NULL) { 377 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 378 ETHER_ADDR_LEN)) { 379 ifp->if_flags |= IFF_ALLMULTI; 380 ETHER_UNLOCK(ec); 381 goto allmulti; 382 } 383 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 384 ((1 << SK_HASH_BITS) - 1); 385 if (h < 32) 386 hashes[0] |= (1 << h); 387 else 388 hashes[1] |= (1 << (h - 32)); 389 390 ETHER_NEXT_MULTI(step, enm); 391 } 392 ETHER_UNLOCK(ec); 393 reg |= YU_RCR_MUFLEN; 394 } 395 396 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 397 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 398 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 399 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 400 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 401 } 402 403 static void 404 msk_setpromisc(struct sk_if_softc *sc_if) 405 { 406 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 407 408 if (ifp->if_flags & IFF_PROMISC) 409 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 410 YU_RCR_UFLEN | YU_RCR_MUFLEN); 411 else 412 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 413 YU_RCR_UFLEN | YU_RCR_MUFLEN); 414 } 415 416 static int 417 msk_init_rx_ring(struct sk_if_softc *sc_if) 418 { 419 struct msk_chain_data *cd = &sc_if->sk_cdata; 420 struct msk_ring_data *rd = sc_if->sk_rdata; 421 struct msk_rx_desc *r; 422 int i, nexti; 423 424 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 425 426 for (i = 0; i < MSK_RX_RING_CNT; i++) { 427 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 428 if (i == (MSK_RX_RING_CNT - 1)) 429 nexti = 0; 430 else 431 nexti = i + 1; 432 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 433 } 434 435 sc_if->sk_cdata.sk_rx_prod = 0; 436 sc_if->sk_cdata.sk_rx_cons = 0; 437 sc_if->sk_cdata.sk_rx_cnt = 0; 438 sc_if->sk_cdata.sk_rx_hiaddr = 0; 439 440 /* Mark the first ring element to initialize the high address. */ 441 sc_if->sk_cdata.sk_rx_hiaddr = 0; 442 r = &rd->sk_rx_ring[cd->sk_rx_prod]; 443 r->sk_addr = htole32(cd->sk_rx_hiaddr); 444 r->sk_len = 0; 445 r->sk_ctl = 0; 446 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN; 447 MSK_CDRXSYNC(sc_if, cd->sk_rx_prod, 448 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 449 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 450 sc_if->sk_cdata.sk_rx_cnt++; 451 452 msk_fill_rx_ring(sc_if); 453 return 0; 454 } 455 456 static int 457 msk_init_tx_ring(struct sk_if_softc *sc_if) 458 { 459 struct sk_softc *sc = sc_if->sk_softc; 460 struct msk_chain_data *cd = &sc_if->sk_cdata; 461 struct msk_ring_data *rd = sc_if->sk_rdata; 462 struct msk_tx_desc *t; 463 bus_dmamap_t dmamap; 464 struct sk_txmap_entry *entry; 465 int i, nexti; 466 467 memset(rd->sk_tx_ring, 0, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 468 469 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 470 for (i = 0; i < MSK_TX_RING_CNT; i++) { 471 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 472 if (i == (MSK_TX_RING_CNT - 1)) 473 nexti = 0; 474 else 475 nexti = i + 1; 476 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 477 478 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 479 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 480 return ENOBUFS; 481 482 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 483 if (!entry) { 484 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 485 return ENOBUFS; 486 } 487 entry->dmamap = dmamap; 488 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 489 } 490 491 sc_if->sk_cdata.sk_tx_prod = 0; 492 sc_if->sk_cdata.sk_tx_cons = 0; 493 sc_if->sk_cdata.sk_tx_cnt = 0; 494 sc_if->sk_cdata.sk_tx_hiaddr = 0; 495 496 /* Mark the first ring element to initialize the high address. */ 497 sc_if->sk_cdata.sk_tx_hiaddr = 0; 498 t = &rd->sk_tx_ring[cd->sk_tx_prod]; 499 t->sk_addr = htole32(cd->sk_tx_hiaddr); 500 t->sk_len = 0; 501 t->sk_ctl = 0; 502 t->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 503 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 504 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 505 SK_INC(sc_if->sk_cdata.sk_tx_prod, MSK_TX_RING_CNT); 506 sc_if->sk_cdata.sk_tx_cnt++; 507 508 return 0; 509 } 510 511 static int 512 msk_newbuf(struct sk_if_softc *sc_if, bus_dmamap_t dmamap) 513 { 514 struct mbuf *m_new = NULL; 515 struct sk_chain *c; 516 struct msk_rx_desc *r; 517 void *buf = NULL; 518 bus_addr_t addr; 519 520 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 521 if (m_new == NULL) 522 return ENOBUFS; 523 524 /* Allocate the jumbo buffer */ 525 buf = msk_jalloc(sc_if); 526 if (buf == NULL) { 527 m_freem(m_new); 528 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 529 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 530 return ENOBUFS; 531 } 532 533 /* Attach the buffer to the mbuf */ 534 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 535 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 536 537 m_adj(m_new, ETHER_ALIGN); 538 539 addr = dmamap->dm_segs[0].ds_addr + 540 ((vaddr_t)m_new->m_data - 541 (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf); 542 543 if (sc_if->sk_cdata.sk_rx_hiaddr != MSK_ADDR_HI(addr)) { 544 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 545 r = c->sk_le; 546 c->sk_mbuf = NULL; 547 r->sk_addr = htole32(MSK_ADDR_HI(addr)); 548 r->sk_len = 0; 549 r->sk_ctl = 0; 550 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN; 551 sc_if->sk_cdata.sk_rx_hiaddr = MSK_ADDR_HI(addr); 552 553 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 554 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 555 556 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 557 sc_if->sk_cdata.sk_rx_cnt++; 558 559 DPRINTFN(10, ("%s: rx ADDR64: %#x\n", 560 sc_if->sk_ethercom.ec_if.if_xname, 561 (unsigned)MSK_ADDR_HI(addr))); 562 } 563 564 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 565 r = c->sk_le; 566 c->sk_mbuf = m_new; 567 r->sk_addr = htole32(MSK_ADDR_LO(addr)); 568 r->sk_len = htole16(SK_JLEN); 569 r->sk_ctl = 0; 570 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 571 572 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 573 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 574 575 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 576 sc_if->sk_cdata.sk_rx_cnt++; 577 578 return 0; 579 } 580 581 /* 582 * Memory management for jumbo frames. 583 */ 584 585 static int 586 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 587 { 588 struct sk_softc *sc = sc_if->sk_softc; 589 char *ptr, *kva; 590 int i, state, error; 591 struct sk_jpool_entry *entry; 592 593 state = error = 0; 594 595 /* Grab a big chunk o' storage. */ 596 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 597 &sc_if->sk_cdata.sk_jumbo_seg, 1, &sc_if->sk_cdata.sk_jumbo_nseg, 598 BUS_DMA_NOWAIT)) { 599 aprint_error(": can't alloc rx buffers"); 600 return ENOBUFS; 601 } 602 603 state = 1; 604 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 605 sc_if->sk_cdata.sk_jumbo_nseg, MSK_JMEM, (void **)&kva, 606 BUS_DMA_NOWAIT)) { 607 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 608 error = ENOBUFS; 609 goto out; 610 } 611 612 state = 2; 613 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 614 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 615 aprint_error(": can't create dma map"); 616 error = ENOBUFS; 617 goto out; 618 } 619 620 state = 3; 621 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 622 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 623 aprint_error(": can't load dma map"); 624 error = ENOBUFS; 625 goto out; 626 } 627 628 state = 4; 629 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 630 DPRINTFN(1,("msk_jumbo_buf = %p\n", 631 (void *)sc_if->sk_cdata.sk_jumbo_buf)); 632 633 LIST_INIT(&sc_if->sk_jfree_listhead); 634 LIST_INIT(&sc_if->sk_jinuse_listhead); 635 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 636 637 /* 638 * Now divide it up into 9K pieces and save the addresses 639 * in an array. 640 */ 641 ptr = sc_if->sk_cdata.sk_jumbo_buf; 642 for (i = 0; i < MSK_JSLOTS; i++) { 643 sc_if->sk_cdata.sk_jslots[i] = ptr; 644 ptr += SK_JLEN; 645 entry = malloc(sizeof(struct sk_jpool_entry), 646 M_DEVBUF, M_WAITOK); 647 entry->slot = i; 648 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 649 entry, jpool_entries); 650 } 651 out: 652 if (error != 0) { 653 switch (state) { 654 case 4: 655 bus_dmamap_unload(sc->sc_dmatag, 656 sc_if->sk_cdata.sk_rx_jumbo_map); 657 /* FALLTHROUGH */ 658 case 3: 659 bus_dmamap_destroy(sc->sc_dmatag, 660 sc_if->sk_cdata.sk_rx_jumbo_map); 661 /* FALLTHROUGH */ 662 case 2: 663 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 664 /* FALLTHROUGH */ 665 case 1: 666 bus_dmamem_free(sc->sc_dmatag, 667 &sc_if->sk_cdata.sk_jumbo_seg, 668 sc_if->sk_cdata.sk_jumbo_nseg); 669 break; 670 default: 671 break; 672 } 673 } 674 675 return error; 676 } 677 678 static void 679 msk_free_jumbo_mem(struct sk_if_softc *sc_if) 680 { 681 struct sk_softc *sc = sc_if->sk_softc; 682 683 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 684 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 685 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_cdata.sk_jumbo_buf, MSK_JMEM); 686 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 687 sc_if->sk_cdata.sk_jumbo_nseg); 688 } 689 690 /* 691 * Allocate a jumbo buffer. 692 */ 693 static void * 694 msk_jalloc(struct sk_if_softc *sc_if) 695 { 696 struct sk_jpool_entry *entry; 697 698 mutex_enter(&sc_if->sk_jpool_mtx); 699 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 700 701 if (entry == NULL) { 702 mutex_exit(&sc_if->sk_jpool_mtx); 703 return NULL; 704 } 705 706 LIST_REMOVE(entry, jpool_entries); 707 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 708 mutex_exit(&sc_if->sk_jpool_mtx); 709 return sc_if->sk_cdata.sk_jslots[entry->slot]; 710 } 711 712 /* 713 * Release a jumbo buffer. 714 */ 715 static void 716 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 717 { 718 struct sk_jpool_entry *entry; 719 struct sk_if_softc *sc; 720 int i; 721 722 /* Extract the softc struct pointer. */ 723 sc = (struct sk_if_softc *)arg; 724 725 if (sc == NULL) 726 panic("msk_jfree: can't find softc pointer!"); 727 728 /* calculate the slot this buffer belongs to */ 729 i = ((vaddr_t)buf 730 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 731 732 if ((i < 0) || (i >= MSK_JSLOTS)) 733 panic("msk_jfree: asked to free buffer that we don't manage!"); 734 735 mutex_enter(&sc->sk_jpool_mtx); 736 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 737 if (entry == NULL) 738 panic("msk_jfree: buffer not in use!"); 739 entry->slot = i; 740 LIST_REMOVE(entry, jpool_entries); 741 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 742 mutex_exit(&sc->sk_jpool_mtx); 743 744 if (__predict_true(m != NULL)) 745 pool_cache_put(mb_cache, m); 746 747 /* Now that we know we have a free RX buffer, refill if running out */ 748 if ((sc->sk_ethercom.ec_if.if_flags & IFF_RUNNING) != 0 749 && sc->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 750 callout_schedule(&sc->sk_tick_rx, 0); 751 } 752 753 static int 754 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 755 { 756 struct sk_if_softc *sc = ifp->if_softc; 757 int s, error; 758 759 s = splnet(); 760 761 DPRINTFN(2, ("msk_ioctl ETHER cmd %lx\n", cmd)); 762 switch (cmd) { 763 case SIOCSIFFLAGS: 764 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 765 break; 766 767 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 768 case IFF_RUNNING: 769 msk_stop(ifp, 1); 770 break; 771 case IFF_UP: 772 msk_init(ifp); 773 break; 774 case IFF_UP | IFF_RUNNING: 775 if ((ifp->if_flags ^ sc->sk_if_flags) == IFF_PROMISC) { 776 msk_setpromisc(sc); 777 msk_setmulti(sc); 778 } else 779 msk_init(ifp); 780 break; 781 } 782 sc->sk_if_flags = ifp->if_flags; 783 break; 784 default: 785 error = ether_ioctl(ifp, cmd, data); 786 if (error == ENETRESET) { 787 error = 0; 788 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 789 ; 790 else if (ifp->if_flags & IFF_RUNNING) { 791 /* 792 * Multicast list has changed; set the hardware 793 * filter accordingly. 794 */ 795 msk_setmulti(sc); 796 } 797 } 798 break; 799 } 800 801 splx(s); 802 return error; 803 } 804 805 static void 806 msk_update_int_mod(struct sk_softc *sc, int verbose) 807 { 808 uint32_t imtimer_ticks; 809 810 /* 811 * Configure interrupt moderation. The moderation timer 812 * defers interrupts specified in the interrupt moderation 813 * timer mask based on the timeout specified in the interrupt 814 * moderation timer init register. Each bit in the timer 815 * register represents one tick, so to specify a timeout in 816 * microseconds, we have to multiply by the correct number of 817 * ticks-per-microsecond. 818 */ 819 switch (sc->sk_type) { 820 case SK_YUKON_EC: 821 case SK_YUKON_EC_U: 822 case SK_YUKON_EX: 823 case SK_YUKON_SUPR: 824 case SK_YUKON_ULTRA2: 825 case SK_YUKON_OPTIMA: 826 case SK_YUKON_PRM: 827 case SK_YUKON_OPTIMA2: 828 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 829 break; 830 case SK_YUKON_FE: 831 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 832 break; 833 case SK_YUKON_FE_P: 834 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 835 break; 836 case SK_YUKON_XL: 837 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 838 break; 839 default: 840 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 841 } 842 if (verbose) 843 aprint_verbose_dev(sc->sk_dev, 844 "interrupt moderation is %d us\n", sc->sk_int_mod); 845 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 846 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF | SK_ISR_TX2_S_EOF | 847 SK_ISR_RX1_EOF | SK_ISR_RX2_EOF); 848 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 849 sc->sk_int_mod_pending = 0; 850 } 851 852 static int 853 msk_lookup(const struct pci_attach_args *pa) 854 { 855 const struct msk_product *pmsk; 856 857 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 858 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 859 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 860 return 1; 861 } 862 return 0; 863 } 864 865 /* 866 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 867 * IDs against our list and return a device name if we find a match. 868 */ 869 static int 870 mskc_probe(device_t parent, cfdata_t match, void *aux) 871 { 872 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 873 874 return msk_lookup(pa); 875 } 876 877 /* 878 * Force the GEnesis into reset, then bring it out of reset. 879 */ 880 static void 881 mskc_reset(struct sk_softc *sc) 882 { 883 uint32_t imtimer_ticks, reg1; 884 uint16_t status; 885 int reg; 886 887 DPRINTFN(2, ("mskc_reset\n")); 888 889 /* Disable ASF */ 890 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_SUPR)) { 891 CSR_WRITE_4(sc, SK_Y2_CPU_WDOG, 0); 892 status = CSR_READ_2(sc, SK_Y2_ASF_HCU_CCSR); 893 /* Clear AHB bridge & microcontroller reset. */ 894 status &= ~(SK_Y2_ASF_HCU_CSSR_ARB_RST | 895 SK_Y2_ASF_HCU_CSSR_CPU_RST_MODE); 896 /* Clear ASF microcontroller state. */ 897 status &= ~SK_Y2_ASF_HCU_CSSR_UC_STATE_MSK; 898 status &= ~SK_Y2_ASF_HCU_CSSR_CPU_CLK_DIVIDE_MSK; 899 CSR_WRITE_2(sc, SK_Y2_ASF_HCU_CCSR, status); 900 CSR_WRITE_4(sc, SK_Y2_CPU_WDOG, 0); 901 } else 902 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 903 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 904 905 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 906 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 907 908 DELAY(1000); 909 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 910 DELAY(2); 911 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 912 sk_win_write_1(sc, SK_TESTCTL1, 2); 913 914 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 915 sc->sk_type >= SK_YUKON_FE_P) { 916 uint32_t our; 917 918 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 919 920 /* enable all clocks. */ 921 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 922 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 923 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST | 924 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN | 925 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY | 926 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 927 /* Set all bits to 0 except bits 15..12 */ 928 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 929 /* Set to default value */ 930 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 931 932 /* 933 * Disable status race, workaround for Yukon EC Ultra & 934 * Yukon EX. 935 */ 936 reg1 = sk_win_read_4(sc, SK_GPIO); 937 reg1 |= SK_Y2_GPIO_STAT_RACE_DIS; 938 sk_win_write_4(sc, SK_GPIO, reg1); 939 sk_win_read_4(sc, SK_GPIO); 940 } 941 942 /* release PHY from PowerDown/Coma mode. */ 943 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 944 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 945 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 946 else 947 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 948 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 949 950 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 951 sk_win_write_1(sc, SK_Y2_CLKGATE, 952 SK_Y2_CLKGATE_LINK1_GATE_DIS | 953 SK_Y2_CLKGATE_LINK2_GATE_DIS | 954 SK_Y2_CLKGATE_LINK1_CORE_DIS | 955 SK_Y2_CLKGATE_LINK2_CORE_DIS | 956 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 957 else 958 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 959 960 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 961 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 962 DELAY(1000); 963 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 964 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 965 966 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 967 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 968 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 969 } 970 971 sk_win_write_1(sc, SK_TESTCTL1, 1); 972 973 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 974 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 975 CSR_READ_2(sc, SK_LINK_CTRL))); 976 977 /* Clear I2C IRQ noise */ 978 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 979 980 /* Disable hardware timer */ 981 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 982 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 983 984 /* Disable descriptor polling */ 985 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 986 987 /* Disable time stamps */ 988 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 989 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 990 991 /* Enable RAM interface */ 992 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 993 for (reg = SK_TO0;reg <= SK_TO11; reg++) 994 sk_win_write_1(sc, reg, 36); 995 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 996 for (reg = SK_TO0;reg <= SK_TO11; reg++) 997 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 998 999 /* 1000 * Configure interrupt moderation. The moderation timer 1001 * defers interrupts specified in the interrupt moderation 1002 * timer mask based on the timeout specified in the interrupt 1003 * moderation timer init register. Each bit in the timer 1004 * register represents one tick, so to specify a timeout in 1005 * microseconds, we have to multiply by the correct number of 1006 * ticks-per-microsecond. 1007 */ 1008 switch (sc->sk_type) { 1009 case SK_YUKON_EC: 1010 case SK_YUKON_EC_U: 1011 case SK_YUKON_EX: 1012 case SK_YUKON_SUPR: 1013 case SK_YUKON_ULTRA2: 1014 case SK_YUKON_OPTIMA: 1015 case SK_YUKON_PRM: 1016 case SK_YUKON_OPTIMA2: 1017 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1018 break; 1019 case SK_YUKON_FE: 1020 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 1021 break; 1022 case SK_YUKON_FE_P: 1023 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 1024 break; 1025 case SK_YUKON_XL: 1026 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 1027 break; 1028 default: 1029 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1030 break; 1031 } 1032 1033 /* Reset status ring. */ 1034 memset(sc->sk_status_ring, 0, 1035 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1036 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 1037 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1038 sc->sk_status_idx = 0; 1039 1040 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 1041 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 1042 1043 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 1044 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 1045 MSK_ADDR_LO(sc->sk_status_map->dm_segs[0].ds_addr)); 1046 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 1047 MSK_ADDR_HI(sc->sk_status_map->dm_segs[0].ds_addr)); 1048 if (sc->sk_type == SK_YUKON_EC && 1049 sc->sk_rev == SK_YUKON_EC_REV_A1) { 1050 /* WA for dev. #4.3 */ 1051 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 1052 SK_STAT_BMU_TXTHIDX_MSK); 1053 /* WA for dev. #4.18 */ 1054 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 1055 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 1056 } else { 1057 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 1058 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 1059 if (sc->sk_type == SK_YUKON_XL) 1060 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x04); 1061 else 1062 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x10); 1063 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 1064 } 1065 1066 #if 0 1067 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 1068 #endif 1069 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 1070 1071 /* Enable status unit. */ 1072 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 1073 1074 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 1075 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 1076 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 1077 1078 msk_update_int_mod(sc, 0); 1079 } 1080 1081 static int 1082 msk_probe(device_t parent, cfdata_t match, void *aux) 1083 { 1084 struct skc_attach_args *sa = aux; 1085 1086 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1087 return 0; 1088 1089 switch (sa->skc_type) { 1090 case SK_YUKON_XL: 1091 case SK_YUKON_EC_U: 1092 case SK_YUKON_EX: 1093 case SK_YUKON_EC: 1094 case SK_YUKON_FE: 1095 case SK_YUKON_FE_P: 1096 case SK_YUKON_SUPR: 1097 case SK_YUKON_ULTRA2: 1098 case SK_YUKON_OPTIMA: 1099 case SK_YUKON_PRM: 1100 case SK_YUKON_OPTIMA2: 1101 return 1; 1102 } 1103 1104 return 0; 1105 } 1106 1107 static void 1108 msk_reset(struct sk_if_softc *sc_if) 1109 { 1110 /* GMAC and GPHY Reset */ 1111 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1112 SK_IF_WRITE_1(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1113 DELAY(1000); 1114 SK_IF_WRITE_1(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1115 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1116 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1117 } 1118 1119 static bool 1120 msk_resume(device_t dv, const pmf_qual_t *qual) 1121 { 1122 struct sk_if_softc *sc_if = device_private(dv); 1123 1124 msk_init_yukon(sc_if); 1125 return true; 1126 } 1127 1128 /* 1129 * Each XMAC chip is attached as a separate logical IP interface. 1130 * Single port cards will have only one logical interface of course. 1131 */ 1132 static void 1133 msk_attach(device_t parent, device_t self, void *aux) 1134 { 1135 struct sk_if_softc *sc_if = device_private(self); 1136 struct sk_softc *sc = device_private(parent); 1137 struct skc_attach_args *sa = aux; 1138 struct ifnet *ifp; 1139 struct mii_data * const mii = &sc_if->sk_mii; 1140 void *kva; 1141 int i; 1142 uint32_t chunk; 1143 int mii_flags; 1144 1145 sc_if->sk_dev = self; 1146 sc_if->sk_port = sa->skc_port; 1147 sc_if->sk_softc = sc; 1148 sc->sk_if[sa->skc_port] = sc_if; 1149 1150 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1151 1152 /* 1153 * Get station address for this interface. Note that 1154 * dual port cards actually come with three station 1155 * addresses: one for each port, plus an extra. The 1156 * extra one is used by the SysKonnect driver software 1157 * as a 'virtual' station address for when both ports 1158 * are operating in failover mode. Currently we don't 1159 * use this extra address. 1160 */ 1161 for (i = 0; i < ETHER_ADDR_LEN; i++) 1162 sc_if->sk_enaddr[i] = 1163 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1164 1165 aprint_normal(": Ethernet address %s\n", 1166 ether_sprintf(sc_if->sk_enaddr)); 1167 1168 /* 1169 * Set up RAM buffer addresses. The Yukon2 has a small amount 1170 * of SRAM on it, somewhere between 4K and 48K. We need to 1171 * divide this up between the transmitter and receiver. We 1172 * give the receiver 2/3 of the memory (rounded down), and the 1173 * transmitter whatever remains. 1174 */ 1175 if (sc->sk_ramsize) { 1176 chunk = (2 * (sc->sk_ramsize / sizeof(uint64_t)) / 3) & ~0xff; 1177 sc_if->sk_rx_ramstart = 0; 1178 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 1179 chunk = (sc->sk_ramsize / sizeof(uint64_t)) - chunk; 1180 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 1181 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 1182 1183 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1184 " tx_ramstart=%#x tx_ramend=%#x\n", 1185 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1186 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1187 } 1188 1189 /* Allocate the descriptor queues. */ 1190 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1191 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 1192 BUS_DMA_NOWAIT)) { 1193 aprint_error(": can't alloc rx buffers\n"); 1194 goto fail; 1195 } 1196 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 1197 sc_if->sk_ring_nseg, 1198 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1199 aprint_error(": can't map dma buffers (%zu bytes)\n", 1200 sizeof(struct msk_ring_data)); 1201 goto fail_1; 1202 } 1203 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1204 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1205 &sc_if->sk_ring_map)) { 1206 aprint_error(": can't create dma map\n"); 1207 goto fail_2; 1208 } 1209 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1210 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1211 aprint_error(": can't load dma map\n"); 1212 goto fail_3; 1213 } 1214 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1215 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1216 1217 if (sc->sk_type != SK_YUKON_FE && 1218 sc->sk_type != SK_YUKON_FE_P) 1219 sc_if->sk_pktlen = SK_JLEN; 1220 else 1221 sc_if->sk_pktlen = MCLBYTES; 1222 1223 /* Try to allocate memory for jumbo buffers. */ 1224 if (msk_alloc_jumbo_mem(sc_if)) { 1225 aprint_error(": jumbo buffer allocation failed\n"); 1226 goto fail_3; 1227 } 1228 1229 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1230 if (sc->sk_type != SK_YUKON_FE && 1231 sc->sk_type != SK_YUKON_FE_P) 1232 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1233 1234 ifp = &sc_if->sk_ethercom.ec_if; 1235 ifp->if_softc = sc_if; 1236 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1237 ifp->if_ioctl = msk_ioctl; 1238 ifp->if_start = msk_start; 1239 ifp->if_stop = msk_stop; 1240 ifp->if_init = msk_init; 1241 ifp->if_watchdog = msk_watchdog; 1242 ifp->if_baudrate = 1000000000; 1243 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1244 IFQ_SET_READY(&ifp->if_snd); 1245 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1246 1247 msk_reset(sc_if); 1248 1249 /* 1250 * Do miibus setup. 1251 */ 1252 DPRINTFN(2, ("msk_attach: 1\n")); 1253 1254 mii->mii_ifp = ifp; 1255 mii->mii_readreg = msk_miibus_readreg; 1256 mii->mii_writereg = msk_miibus_writereg; 1257 mii->mii_statchg = msk_miibus_statchg; 1258 1259 sc_if->sk_ethercom.ec_mii = mii; 1260 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1261 mii_flags = MIIF_DOPAUSE; 1262 if (sc->sk_fibertype) 1263 mii_flags |= MIIF_HAVEFIBER; 1264 mii_attach(self, mii, 0xffffffff, 0, MII_OFFSET_ANY, mii_flags); 1265 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1266 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1267 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 1268 0, NULL); 1269 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 1270 } else 1271 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1272 1273 callout_init(&sc_if->sk_tick_ch, 0); 1274 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1275 callout_schedule(&sc_if->sk_tick_ch, hz); 1276 1277 callout_init(&sc_if->sk_tick_rx, 0); 1278 callout_setfunc(&sc_if->sk_tick_rx, msk_fill_rx_tick, sc_if); 1279 1280 /* 1281 * Call MI attach routines. 1282 */ 1283 if_attach(ifp); 1284 if_deferred_start_init(ifp, NULL); 1285 ether_ifattach(ifp, sc_if->sk_enaddr); 1286 1287 if (pmf_device_register(self, NULL, msk_resume)) 1288 pmf_class_network_register(self, ifp); 1289 else 1290 aprint_error_dev(self, "couldn't establish power handler\n"); 1291 1292 if (sc->rnd_attached++ == 0) { 1293 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1294 RND_TYPE_NET, RND_FLAG_DEFAULT); 1295 } 1296 1297 DPRINTFN(2, ("msk_attach: end\n")); 1298 return; 1299 1300 fail_3: 1301 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1302 fail_2: 1303 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1304 fail_1: 1305 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1306 fail: 1307 sc->sk_if[sa->skc_port] = NULL; 1308 } 1309 1310 static int 1311 msk_detach(device_t self, int flags) 1312 { 1313 struct sk_if_softc *sc_if = device_private(self); 1314 struct sk_softc *sc = sc_if->sk_softc; 1315 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1316 1317 if (sc->sk_if[sc_if->sk_port] == NULL) 1318 return 0; 1319 1320 msk_stop(ifp, 1); 1321 1322 if (--sc->rnd_attached == 0) 1323 rnd_detach_source(&sc->rnd_source); 1324 1325 callout_halt(&sc_if->sk_tick_ch, NULL); 1326 callout_destroy(&sc_if->sk_tick_ch); 1327 1328 callout_halt(&sc_if->sk_tick_rx, NULL); 1329 callout_destroy(&sc_if->sk_tick_rx); 1330 1331 /* Detach any PHYs we might have. */ 1332 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1333 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1334 1335 /* Delete any remaining media. */ 1336 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY); 1337 1338 pmf_device_deregister(self); 1339 1340 ether_ifdetach(ifp); 1341 if_detach(ifp); 1342 1343 msk_free_jumbo_mem(sc_if); 1344 1345 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_rdata, 1346 sizeof(struct msk_ring_data)); 1347 bus_dmamem_free(sc->sc_dmatag, 1348 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1349 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1350 sc->sk_if[sc_if->sk_port] = NULL; 1351 1352 return 0; 1353 } 1354 1355 static int 1356 mskcprint(void *aux, const char *pnp) 1357 { 1358 struct skc_attach_args *sa = aux; 1359 1360 if (pnp) 1361 aprint_normal("msk port %c at %s", 1362 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1363 else 1364 aprint_normal(" port %c", 1365 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1366 return UNCONF; 1367 } 1368 1369 /* 1370 * Attach the interface. Allocate softc structures, do ifmedia 1371 * setup and ethernet/BPF attach. 1372 */ 1373 static void 1374 mskc_attach(device_t parent, device_t self, void *aux) 1375 { 1376 struct sk_softc *sc = device_private(self); 1377 struct pci_attach_args *pa = aux; 1378 struct skc_attach_args skca; 1379 pci_chipset_tag_t pc = pa->pa_pc; 1380 pcireg_t command, memtype; 1381 const char *intrstr = NULL; 1382 int rc, sk_nodenum; 1383 uint8_t hw, pmd; 1384 const char *revstr = NULL; 1385 const struct sysctlnode *node; 1386 void *kva; 1387 char intrbuf[PCI_INTRSTR_LEN]; 1388 1389 DPRINTFN(2, ("begin mskc_attach\n")); 1390 1391 sc->sk_dev = self; 1392 /* 1393 * Handle power management nonsense. 1394 */ 1395 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1396 1397 if (command == 0x01) { 1398 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1399 if (command & SK_PSTATE_MASK) { 1400 uint32_t iobase, membase, irq; 1401 1402 /* Save important PCI config data. */ 1403 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1404 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1405 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1406 1407 /* Reset the power state. */ 1408 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1409 "mode -- setting to D0\n", 1410 command & SK_PSTATE_MASK); 1411 command &= 0xFFFFFFFC; 1412 pci_conf_write(pc, pa->pa_tag, 1413 SK_PCI_PWRMGMTCTRL, command); 1414 1415 /* Restore PCI config data. */ 1416 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1417 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1418 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1419 } 1420 } 1421 1422 /* 1423 * Map control/status registers. 1424 */ 1425 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1426 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1427 &sc->sk_bhandle, NULL, &sc->sk_bsize)) { 1428 aprint_error(": can't map mem space\n"); 1429 return; 1430 } 1431 1432 if (pci_dma64_available(pa)) 1433 sc->sc_dmatag = pa->pa_dmat64; 1434 else 1435 sc->sc_dmatag = pa->pa_dmat; 1436 1437 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1438 command |= PCI_COMMAND_MASTER_ENABLE; 1439 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1440 1441 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1442 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1443 1444 /* bail out here if chip is not recognized */ 1445 if (!(SK_IS_YUKON2(sc))) { 1446 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1447 goto fail_1; 1448 } 1449 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1450 1451 /* Allocate interrupt */ 1452 if (pci_intr_alloc(pa, &sc->sk_pihp, NULL, 0)) { 1453 aprint_error(": couldn't map interrupt\n"); 1454 goto fail_1; 1455 } 1456 1457 intrstr = pci_intr_string(pc, sc->sk_pihp[0], intrbuf, sizeof(intrbuf)); 1458 sc->sk_intrhand = pci_intr_establish_xname(pc, sc->sk_pihp[0], IPL_NET, 1459 msk_intr, sc, device_xname(sc->sk_dev)); 1460 if (sc->sk_intrhand == NULL) { 1461 aprint_error(": couldn't establish interrupt"); 1462 if (intrstr != NULL) 1463 aprint_error(" at %s", intrstr); 1464 aprint_error("\n"); 1465 goto fail_1; 1466 } 1467 sc->sk_pc = pc; 1468 1469 if (bus_dmamem_alloc(sc->sc_dmatag, 1470 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1471 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1472 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, BUS_DMA_NOWAIT)) { 1473 aprint_error(": can't alloc status buffers\n"); 1474 goto fail_2; 1475 } 1476 1477 if (bus_dmamem_map(sc->sc_dmatag, 1478 &sc->sk_status_seg, sc->sk_status_nseg, 1479 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1480 &kva, BUS_DMA_NOWAIT)) { 1481 aprint_error(": can't map dma buffers (%zu bytes)\n", 1482 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1483 goto fail_3; 1484 } 1485 if (bus_dmamap_create(sc->sc_dmatag, 1486 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1487 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1488 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1489 aprint_error(": can't create dma map\n"); 1490 goto fail_4; 1491 } 1492 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1493 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1494 NULL, BUS_DMA_NOWAIT)) { 1495 aprint_error(": can't load dma map\n"); 1496 goto fail_5; 1497 } 1498 sc->sk_status_ring = (struct msk_status_desc *)kva; 1499 1500 sc->sk_int_mod = SK_IM_DEFAULT; 1501 sc->sk_int_mod_pending = 0; 1502 1503 /* Reset the adapter. */ 1504 mskc_reset(sc); 1505 1506 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1507 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1508 1509 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1510 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1511 sc->sk_fibertype = 1; 1512 1513 switch (sc->sk_type) { 1514 case SK_YUKON_XL: 1515 sc->sk_name = "Yukon-2 XL"; 1516 break; 1517 case SK_YUKON_EC_U: 1518 sc->sk_name = "Yukon-2 EC Ultra"; 1519 break; 1520 case SK_YUKON_EX: 1521 sc->sk_name = "Yukon-2 Extreme"; 1522 break; 1523 case SK_YUKON_EC: 1524 sc->sk_name = "Yukon-2 EC"; 1525 break; 1526 case SK_YUKON_FE: 1527 sc->sk_name = "Yukon-2 FE"; 1528 break; 1529 case SK_YUKON_FE_P: 1530 sc->sk_name = "Yukon-2 FE+"; 1531 break; 1532 case SK_YUKON_SUPR: 1533 sc->sk_name = "Yukon-2 Supreme"; 1534 break; 1535 case SK_YUKON_ULTRA2: 1536 sc->sk_name = "Yukon-2 Ultra 2"; 1537 break; 1538 case SK_YUKON_OPTIMA: 1539 sc->sk_name = "Yukon-2 Optima"; 1540 break; 1541 case SK_YUKON_PRM: 1542 sc->sk_name = "Yukon-2 Optima Prime"; 1543 break; 1544 case SK_YUKON_OPTIMA2: 1545 sc->sk_name = "Yukon-2 Optima 2"; 1546 break; 1547 default: 1548 sc->sk_name = "Yukon (Unknown)"; 1549 } 1550 1551 if (sc->sk_type == SK_YUKON_XL) { 1552 switch (sc->sk_rev) { 1553 case SK_YUKON_XL_REV_A0: 1554 revstr = "A0"; 1555 break; 1556 case SK_YUKON_XL_REV_A1: 1557 revstr = "A1"; 1558 break; 1559 case SK_YUKON_XL_REV_A2: 1560 revstr = "A2"; 1561 break; 1562 case SK_YUKON_XL_REV_A3: 1563 revstr = "A3"; 1564 break; 1565 default: 1566 break; 1567 } 1568 } 1569 1570 if (sc->sk_type == SK_YUKON_EC) { 1571 switch (sc->sk_rev) { 1572 case SK_YUKON_EC_REV_A1: 1573 revstr = "A1"; 1574 break; 1575 case SK_YUKON_EC_REV_A2: 1576 revstr = "A2"; 1577 break; 1578 case SK_YUKON_EC_REV_A3: 1579 revstr = "A3"; 1580 break; 1581 default: 1582 break; 1583 } 1584 } 1585 1586 if (sc->sk_type == SK_YUKON_FE) { 1587 switch (sc->sk_rev) { 1588 case SK_YUKON_FE_REV_A1: 1589 revstr = "A1"; 1590 break; 1591 case SK_YUKON_FE_REV_A2: 1592 revstr = "A2"; 1593 break; 1594 default: 1595 break; 1596 } 1597 } 1598 1599 if (sc->sk_type == SK_YUKON_EC_U) { 1600 switch (sc->sk_rev) { 1601 case SK_YUKON_EC_U_REV_A0: 1602 revstr = "A0"; 1603 break; 1604 case SK_YUKON_EC_U_REV_A1: 1605 revstr = "A1"; 1606 break; 1607 case SK_YUKON_EC_U_REV_B0: 1608 revstr = "B0"; 1609 break; 1610 case SK_YUKON_EC_U_REV_B1: 1611 revstr = "B1"; 1612 break; 1613 default: 1614 break; 1615 } 1616 } 1617 1618 if (sc->sk_type == SK_YUKON_FE) { 1619 switch (sc->sk_rev) { 1620 case SK_YUKON_FE_REV_A1: 1621 revstr = "A1"; 1622 break; 1623 case SK_YUKON_FE_REV_A2: 1624 revstr = "A2"; 1625 break; 1626 default: 1627 ; 1628 } 1629 } 1630 1631 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1632 revstr = "A0"; 1633 1634 if (sc->sk_type == SK_YUKON_EX) { 1635 switch (sc->sk_rev) { 1636 case SK_YUKON_EX_REV_A0: 1637 revstr = "A0"; 1638 break; 1639 case SK_YUKON_EX_REV_B0: 1640 revstr = "B0"; 1641 break; 1642 default: 1643 ; 1644 } 1645 } 1646 1647 if (sc->sk_type == SK_YUKON_SUPR) { 1648 switch (sc->sk_rev) { 1649 case SK_YUKON_SUPR_REV_A0: 1650 revstr = "A0"; 1651 break; 1652 case SK_YUKON_SUPR_REV_B0: 1653 revstr = "B0"; 1654 break; 1655 case SK_YUKON_SUPR_REV_B1: 1656 revstr = "B1"; 1657 break; 1658 default: 1659 ; 1660 } 1661 } 1662 1663 if (sc->sk_type == SK_YUKON_PRM) { 1664 switch (sc->sk_rev) { 1665 case SK_YUKON_PRM_REV_Z1: 1666 revstr = "Z1"; 1667 break; 1668 case SK_YUKON_PRM_REV_A0: 1669 revstr = "A0"; 1670 break; 1671 default: 1672 ; 1673 } 1674 } 1675 1676 /* Announce the product name. */ 1677 aprint_normal(", %s", sc->sk_name); 1678 if (revstr != NULL) 1679 aprint_normal(" rev. %s", revstr); 1680 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1681 1682 sc->sk_macs = 1; 1683 1684 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1685 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1686 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1687 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1688 sc->sk_macs++; 1689 } 1690 1691 skca.skc_port = SK_PORT_A; 1692 skca.skc_type = sc->sk_type; 1693 skca.skc_rev = sc->sk_rev; 1694 (void)config_found(sc->sk_dev, &skca, mskcprint); 1695 1696 if (sc->sk_macs > 1) { 1697 skca.skc_port = SK_PORT_B; 1698 skca.skc_type = sc->sk_type; 1699 skca.skc_rev = sc->sk_rev; 1700 (void)config_found(sc->sk_dev, &skca, mskcprint); 1701 } 1702 1703 /* Turn on the 'driver is loaded' LED. */ 1704 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1705 1706 /* skc sysctl setup */ 1707 1708 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1709 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1710 SYSCTL_DESCR("mskc per-controller controls"), 1711 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1712 CTL_EOL)) != 0) { 1713 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1714 goto fail_6; 1715 } 1716 1717 sk_nodenum = node->sysctl_num; 1718 1719 /* interrupt moderation time in usecs */ 1720 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1721 CTLFLAG_READWRITE, 1722 CTLTYPE_INT, "int_mod", 1723 SYSCTL_DESCR("msk interrupt moderation timer"), 1724 msk_sysctl_handler, 0, (void *)sc, 1725 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1726 CTL_EOL)) != 0) { 1727 aprint_normal_dev(sc->sk_dev, 1728 "couldn't create int_mod sysctl node\n"); 1729 goto fail_6; 1730 } 1731 1732 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1733 aprint_error_dev(self, "couldn't establish power handler\n"); 1734 1735 return; 1736 1737 fail_6: 1738 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1739 fail_4: 1740 bus_dmamem_unmap(sc->sc_dmatag, kva, 1741 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1742 fail_3: 1743 bus_dmamem_free(sc->sc_dmatag, 1744 &sc->sk_status_seg, sc->sk_status_nseg); 1745 sc->sk_status_nseg = 0; 1746 fail_5: 1747 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1748 fail_2: 1749 pci_intr_disestablish(pc, sc->sk_intrhand); 1750 sc->sk_intrhand = NULL; 1751 fail_1: 1752 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1753 sc->sk_bsize = 0; 1754 } 1755 1756 static int 1757 mskc_detach(device_t self, int flags) 1758 { 1759 struct sk_softc *sc = device_private(self); 1760 int rv; 1761 1762 if (sc->sk_intrhand) { 1763 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1764 sc->sk_intrhand = NULL; 1765 } 1766 1767 if (sc->sk_pihp != NULL) { 1768 pci_intr_release(sc->sk_pc, sc->sk_pihp, 1); 1769 sc->sk_pihp = NULL; 1770 } 1771 1772 rv = config_detach_children(self, flags); 1773 if (rv != 0) 1774 return rv; 1775 1776 if (sc->sk_status_nseg > 0) { 1777 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1778 bus_dmamem_unmap(sc->sc_dmatag, sc->sk_status_ring, 1779 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1780 bus_dmamem_free(sc->sc_dmatag, 1781 &sc->sk_status_seg, sc->sk_status_nseg); 1782 } 1783 1784 if (sc->sk_bsize > 0) 1785 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1786 1787 return 0; 1788 } 1789 1790 static int 1791 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1792 { 1793 struct sk_softc *sc = sc_if->sk_softc; 1794 struct msk_tx_desc *f = NULL; 1795 uint32_t frag, cur, hiaddr, old_hiaddr, total; 1796 uint32_t entries = 0; 1797 size_t i; 1798 struct sk_txmap_entry *entry; 1799 bus_dmamap_t txmap; 1800 bus_addr_t addr; 1801 1802 DPRINTFN(2, ("msk_encap\n")); 1803 1804 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1805 if (entry == NULL) { 1806 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1807 return ENOBUFS; 1808 } 1809 txmap = entry->dmamap; 1810 1811 cur = frag = *txidx; 1812 1813 #ifdef MSK_DEBUG 1814 if (mskdebug >= 2) 1815 msk_dump_mbuf(m_head); 1816 #endif 1817 1818 /* 1819 * Start packing the mbufs in this chain into 1820 * the fragment pointers. Stop when we run out 1821 * of fragments or hit the end of the mbuf chain. 1822 */ 1823 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1824 BUS_DMA_NOWAIT)) { 1825 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1826 return ENOBUFS; 1827 } 1828 1829 /* Count how many tx descriptors needed. */ 1830 hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1831 for (total = i = 0; i < txmap->dm_nsegs; i++) { 1832 if (hiaddr != MSK_ADDR_HI(txmap->dm_segs[i].ds_addr)) { 1833 hiaddr = MSK_ADDR_HI(txmap->dm_segs[i].ds_addr); 1834 total++; 1835 } 1836 total++; 1837 } 1838 1839 if (total > MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2) { 1840 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1841 bus_dmamap_unload(sc->sc_dmatag, txmap); 1842 return ENOBUFS; 1843 } 1844 1845 DPRINTFN(2, ("msk_encap: dm_nsegs=%d total desc=%u\n", 1846 txmap->dm_nsegs, total)); 1847 1848 /* Sync the DMA map. */ 1849 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1850 BUS_DMASYNC_PREWRITE); 1851 1852 old_hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1853 for (i = 0; i < txmap->dm_nsegs; i++) { 1854 addr = txmap->dm_segs[i].ds_addr; 1855 DPRINTFN(2, ("msk_encap: addr %llx\n", 1856 (unsigned long long)addr)); 1857 hiaddr = MSK_ADDR_HI(addr); 1858 1859 if (sc_if->sk_cdata.sk_tx_hiaddr != hiaddr) { 1860 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1861 f->sk_addr = htole32(hiaddr); 1862 f->sk_len = 0; 1863 f->sk_ctl = 0; 1864 if (i == 0) 1865 f->sk_opcode = SK_Y2_BMUOPC_ADDR64; 1866 else 1867 f->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 1868 sc_if->sk_cdata.sk_tx_hiaddr = hiaddr; 1869 SK_INC(frag, MSK_TX_RING_CNT); 1870 entries++; 1871 DPRINTFN(10, ("%s: tx ADDR64: %#x\n", 1872 sc_if->sk_ethercom.ec_if.if_xname, hiaddr)); 1873 } 1874 1875 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1876 f->sk_addr = htole32(MSK_ADDR_LO(addr)); 1877 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1878 f->sk_ctl = 0; 1879 if (i == 0) { 1880 if (hiaddr != old_hiaddr) 1881 f->sk_opcode = SK_Y2_TXOPC_PACKET | SK_Y2_TXOPC_OWN; 1882 else 1883 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1884 } else 1885 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1886 cur = frag; 1887 SK_INC(frag, MSK_TX_RING_CNT); 1888 entries++; 1889 } 1890 KASSERTMSG(entries == total, "entries %u total %u", entries, total); 1891 1892 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1893 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1894 1895 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1896 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1897 1898 /* Sync descriptors before handing to chip */ 1899 MSK_CDTXSYNC(sc_if, *txidx, entries, 1900 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1901 1902 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1903 1904 /* Sync first descriptor to hand it off */ 1905 MSK_CDTXSYNC(sc_if, *txidx, 1, 1906 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1907 1908 sc_if->sk_cdata.sk_tx_cnt += entries; 1909 1910 #ifdef MSK_DEBUG 1911 if (mskdebug >= 2) { 1912 struct msk_tx_desc *le; 1913 uint32_t idx; 1914 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1915 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1916 msk_dump_txdesc(le, idx); 1917 } 1918 } 1919 #endif 1920 1921 *txidx = frag; 1922 1923 DPRINTFN(2, ("msk_encap: successful: %u entries\n", entries)); 1924 1925 return 0; 1926 } 1927 1928 static void 1929 msk_start(struct ifnet *ifp) 1930 { 1931 struct sk_if_softc *sc_if = ifp->if_softc; 1932 struct mbuf *m_head = NULL; 1933 uint32_t idx = sc_if->sk_cdata.sk_tx_prod; 1934 int pkts = 0; 1935 1936 DPRINTFN(2, ("msk_start\n")); 1937 1938 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1939 IFQ_POLL(&ifp->if_snd, m_head); 1940 if (m_head == NULL) 1941 break; 1942 1943 /* 1944 * Pack the data into the transmit ring. If we 1945 * don't have room, set the OACTIVE flag and wait 1946 * for the NIC to drain the ring. 1947 */ 1948 if (msk_encap(sc_if, m_head, &idx)) { 1949 ifp->if_flags |= IFF_OACTIVE; 1950 break; 1951 } 1952 1953 /* now we are committed to transmit the packet */ 1954 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1955 pkts++; 1956 1957 /* 1958 * If there's a BPF listener, bounce a copy of this frame 1959 * to him. 1960 */ 1961 bpf_mtap(ifp, m_head, BPF_D_OUT); 1962 } 1963 if (pkts == 0) 1964 return; 1965 1966 /* Transmit */ 1967 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1968 sc_if->sk_cdata.sk_tx_prod = idx; 1969 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1970 1971 /* Set a timeout in case the chip goes out to lunch. */ 1972 ifp->if_timer = 5; 1973 } 1974 } 1975 1976 static void 1977 msk_watchdog(struct ifnet *ifp) 1978 { 1979 struct sk_if_softc *sc_if = ifp->if_softc; 1980 1981 /* 1982 * Reclaim first as there is a possibility of losing Tx completion 1983 * interrupts. 1984 */ 1985 msk_txeof(sc_if); 1986 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1987 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1988 1989 ifp->if_oerrors++; 1990 1991 /* XXX Resets both ports; we shouldn't do that. */ 1992 mskc_reset(sc_if->sk_softc); 1993 msk_reset(sc_if); 1994 msk_init(ifp); 1995 } 1996 } 1997 1998 static bool 1999 mskc_suspend(device_t dv, const pmf_qual_t *qual) 2000 { 2001 struct sk_softc *sc = device_private(dv); 2002 2003 DPRINTFN(2, ("mskc_suspend\n")); 2004 2005 /* Turn off the 'driver is loaded' LED. */ 2006 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2007 2008 return true; 2009 } 2010 2011 static bool 2012 mskc_resume(device_t dv, const pmf_qual_t *qual) 2013 { 2014 struct sk_softc *sc = device_private(dv); 2015 2016 DPRINTFN(2, ("mskc_resume\n")); 2017 2018 mskc_reset(sc); 2019 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 2020 2021 return true; 2022 } 2023 2024 static __inline int 2025 msk_rxvalid(struct sk_softc *sc, uint32_t stat, uint32_t len) 2026 { 2027 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 2028 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 2029 YU_RXSTAT_JABBER)) != 0 || 2030 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 2031 YU_RXSTAT_BYTES(stat) != len) 2032 return 0; 2033 2034 return 1; 2035 } 2036 2037 static void 2038 msk_rxeof(struct sk_if_softc *sc_if, uint16_t len, uint32_t rxstat) 2039 { 2040 struct sk_softc *sc = sc_if->sk_softc; 2041 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2042 struct mbuf *m; 2043 unsigned cur, prod, tail, total_len = len; 2044 bus_dmamap_t dmamap; 2045 2046 cur = sc_if->sk_cdata.sk_rx_cons; 2047 prod = sc_if->sk_cdata.sk_rx_prod; 2048 2049 /* Sync the descriptor */ 2050 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2051 2052 DPRINTFN(2, ("msk_rxeof: cur %u prod %u rx_cnt %u\n", cur, prod, 2053 sc_if->sk_cdata.sk_rx_cnt)); 2054 2055 while (prod != cur) { 2056 tail = cur; 2057 SK_INC(cur, MSK_RX_RING_CNT); 2058 2059 sc_if->sk_cdata.sk_rx_cnt--; 2060 m = sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf; 2061 sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf = NULL; 2062 if (m != NULL) 2063 break; /* found it */ 2064 } 2065 sc_if->sk_cdata.sk_rx_cons = cur; 2066 DPRINTFN(2, ("msk_rxeof: cur %u rx_cnt %u m %p\n", cur, 2067 sc_if->sk_cdata.sk_rx_cnt, m)); 2068 2069 if (m == NULL) 2070 return; 2071 2072 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2073 2074 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2075 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2076 2077 if (total_len < SK_MIN_FRAMELEN || 2078 total_len > ETHER_MAX_LEN_JUMBO || 2079 msk_rxvalid(sc, rxstat, total_len) == 0) { 2080 ifp->if_ierrors++; 2081 m_freem(m); 2082 return; 2083 } 2084 2085 m_set_rcvif(m, ifp); 2086 m->m_pkthdr.len = m->m_len = total_len; 2087 2088 /* pass it on. */ 2089 if_percpuq_enqueue(ifp->if_percpuq, m); 2090 } 2091 2092 static void 2093 msk_txeof(struct sk_if_softc *sc_if) 2094 { 2095 struct sk_softc *sc = sc_if->sk_softc; 2096 struct msk_tx_desc *cur_tx; 2097 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2098 uint32_t idx, reg, sk_ctl; 2099 struct sk_txmap_entry *entry; 2100 2101 DPRINTFN(2, ("msk_txeof\n")); 2102 2103 if (sc_if->sk_port == SK_PORT_A) 2104 reg = SK_STAT_BMU_TXA1_RIDX; 2105 else 2106 reg = SK_STAT_BMU_TXA2_RIDX; 2107 2108 /* 2109 * Go through our tx ring and free mbufs for those 2110 * frames that have been sent. 2111 */ 2112 idx = sc_if->sk_cdata.sk_tx_cons; 2113 while (idx != sk_win_read_2(sc, reg)) { 2114 MSK_CDTXSYNC(sc_if, idx, 1, 2115 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2116 2117 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2118 sk_ctl = cur_tx->sk_ctl; 2119 #ifdef MSK_DEBUG 2120 if (mskdebug >= 2) 2121 msk_dump_txdesc(cur_tx, idx); 2122 #endif 2123 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 2124 ifp->if_opackets++; 2125 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2126 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2127 2128 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2129 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2130 2131 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2132 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2133 link); 2134 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2135 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2136 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2137 } 2138 sc_if->sk_cdata.sk_tx_cnt--; 2139 SK_INC(idx, MSK_TX_RING_CNT); 2140 } 2141 if (idx == sc_if->sk_cdata.sk_tx_cons) 2142 return; 2143 2144 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2145 2146 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 2147 ifp->if_flags &= ~IFF_OACTIVE; 2148 2149 sc_if->sk_cdata.sk_tx_cons = idx; 2150 } 2151 2152 static void 2153 msk_fill_rx_ring(struct sk_if_softc *sc_if) 2154 { 2155 /* Make sure to not completely wrap around */ 2156 while (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT - 1)) { 2157 if (msk_newbuf(sc_if, 2158 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 2159 goto schedretry; 2160 } 2161 } 2162 2163 return; 2164 2165 schedretry: 2166 /* Try later */ 2167 callout_schedule(&sc_if->sk_tick_rx, hz/2); 2168 } 2169 2170 static void 2171 msk_fill_rx_tick(void *xsc_if) 2172 { 2173 struct sk_if_softc *sc_if = xsc_if; 2174 int s, rx_prod; 2175 2176 KASSERT(KERNEL_LOCKED_P()); /* XXXSMP */ 2177 2178 s = splnet(); 2179 rx_prod = sc_if->sk_cdata.sk_rx_prod; 2180 msk_fill_rx_ring(sc_if); 2181 if (rx_prod != sc_if->sk_cdata.sk_rx_prod) { 2182 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2183 sc_if->sk_cdata.sk_rx_prod); 2184 } 2185 splx(s); 2186 } 2187 2188 static void 2189 msk_tick(void *xsc_if) 2190 { 2191 struct sk_if_softc *sc_if = xsc_if; 2192 struct mii_data *mii = &sc_if->sk_mii; 2193 int s; 2194 2195 s = splnet(); 2196 mii_tick(mii); 2197 splx(s); 2198 2199 callout_schedule(&sc_if->sk_tick_ch, hz); 2200 } 2201 2202 static void 2203 msk_intr_yukon(struct sk_if_softc *sc_if) 2204 { 2205 uint8_t status; 2206 2207 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2208 /* RX overrun */ 2209 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2210 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2211 SK_RFCTL_RX_FIFO_OVER); 2212 } 2213 /* TX underrun */ 2214 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2215 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 2216 SK_TFCTL_TX_FIFO_UNDER); 2217 } 2218 2219 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 2220 } 2221 2222 static int 2223 msk_intr(void *xsc) 2224 { 2225 struct sk_softc *sc = xsc; 2226 struct sk_if_softc *sc_if; 2227 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2228 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2229 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2230 int claimed = 0; 2231 uint32_t status; 2232 struct msk_status_desc *cur_st; 2233 2234 status = CSR_READ_4(sc, SK_Y2_ISSR2); 2235 if (status == 0xffffffff) 2236 return 0; 2237 if (status == 0) { 2238 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2239 return 0; 2240 } 2241 2242 status = CSR_READ_4(sc, SK_ISR); 2243 2244 if (sc_if0 != NULL) 2245 ifp0 = &sc_if0->sk_ethercom.ec_if; 2246 if (sc_if1 != NULL) 2247 ifp1 = &sc_if1->sk_ethercom.ec_if; 2248 2249 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 2250 (ifp0->if_flags & IFF_RUNNING)) { 2251 msk_intr_yukon(sc_if0); 2252 } 2253 2254 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 2255 (ifp1->if_flags & IFF_RUNNING)) { 2256 msk_intr_yukon(sc_if1); 2257 } 2258 2259 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2260 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2261 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2262 2263 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 2264 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 2265 switch (cur_st->sk_opcode) { 2266 case SK_Y2_STOPC_RXSTAT: 2267 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 2268 if (sc_if) { 2269 msk_rxeof(sc_if, letoh16(cur_st->sk_len), 2270 letoh32(cur_st->sk_status)); 2271 if (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 2272 msk_fill_rx_tick(sc_if); 2273 } 2274 break; 2275 case SK_Y2_STOPC_TXSTAT: 2276 if (sc_if0) 2277 msk_txeof(sc_if0); 2278 if (sc_if1) 2279 msk_txeof(sc_if1); 2280 break; 2281 default: 2282 aprint_error("opcode=0x%x\n", cur_st->sk_opcode); 2283 break; 2284 } 2285 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 2286 2287 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2288 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2289 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2290 } 2291 2292 if (status & SK_Y2_IMR_BMU) { 2293 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 2294 claimed = 1; 2295 } 2296 2297 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2298 2299 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2300 if_schedule_deferred_start(ifp0); 2301 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2302 if_schedule_deferred_start(ifp1); 2303 2304 KASSERT(sc->rnd_attached > 0); 2305 rnd_add_uint32(&sc->rnd_source, status); 2306 2307 if (sc->sk_int_mod_pending) 2308 msk_update_int_mod(sc, 1); 2309 2310 return claimed; 2311 } 2312 2313 static void 2314 msk_init_yukon(struct sk_if_softc *sc_if) 2315 { 2316 uint32_t v; 2317 uint16_t reg; 2318 struct sk_softc *sc; 2319 int i; 2320 2321 sc = sc_if->sk_softc; 2322 2323 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 2324 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2325 2326 DPRINTFN(6, ("msk_init_yukon: 1\n")); 2327 2328 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 2329 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2330 2331 DPRINTFN(6, ("msk_init_yukon: 3\n")); 2332 2333 /* unused read of the interrupt source register */ 2334 DPRINTFN(6, ("msk_init_yukon: 4\n")); 2335 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2336 2337 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2338 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2339 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2340 2341 /* MIB Counter Clear Mode set */ 2342 reg |= YU_PAR_MIB_CLR; 2343 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2344 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2345 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2346 2347 /* MIB Counter Clear Mode clear */ 2348 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2349 reg &= ~YU_PAR_MIB_CLR; 2350 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2351 2352 /* receive control reg */ 2353 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2354 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2355 2356 /* transmit control register */ 2357 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2358 2359 /* transmit flow control register */ 2360 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2361 2362 /* transmit parameter register */ 2363 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2364 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2365 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2366 2367 /* serial mode register */ 2368 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2369 reg = YU_SMR_DATA_BLIND(0x1c) | 2370 YU_SMR_MFL_VLAN | 2371 YU_SMR_IPG_DATA(0x1e); 2372 2373 if (sc->sk_type != SK_YUKON_FE && 2374 sc->sk_type != SK_YUKON_FE_P) 2375 reg |= YU_SMR_MFL_JUMBO; 2376 2377 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2378 2379 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2380 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2381 /* msk_attach calls me before ether_ifattach so check null */ 2382 if (ifp != NULL && ifp->if_sadl != NULL) 2383 memcpy(sc_if->sk_enaddr, CLLADDR(ifp->if_sadl), 2384 sizeof(sc_if->sk_enaddr)); 2385 /* Setup Yukon's address */ 2386 for (i = 0; i < 3; i++) { 2387 /* Write Source Address 1 (unicast filter) */ 2388 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2389 sc_if->sk_enaddr[i * 2] | 2390 sc_if->sk_enaddr[i * 2 + 1] << 8); 2391 } 2392 2393 for (i = 0; i < 3; i++) { 2394 reg = sk_win_read_2(sc_if->sk_softc, 2395 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2396 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2397 } 2398 2399 /* Set promiscuous mode */ 2400 msk_setpromisc(sc_if); 2401 2402 /* Set multicast filter */ 2403 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2404 msk_setmulti(sc_if); 2405 2406 /* enable interrupt mask for counter overflows */ 2407 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2408 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2409 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2410 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2411 2412 /* Configure RX MAC FIFO Flush Mask */ 2413 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2414 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2415 YU_RXSTAT_JABBER; 2416 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2417 2418 /* Configure RX MAC FIFO */ 2419 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2420 v = SK_RFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 2421 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_FE_P)) 2422 v |= SK_RFCTL_RX_OVER_ON; 2423 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 2424 2425 if ((sc->sk_type == SK_YUKON_FE_P) && 2426 (sc->sk_rev == SK_YUKON_FE_P_REV_A0)) 2427 v = 0x178; /* Magic value */ 2428 else { 2429 /* Increase flush threshold to 64 bytes */ 2430 v = SK_RFCTL_FIFO_THRESHOLD + 1; 2431 } 2432 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, v); 2433 2434 /* Configure TX MAC FIFO */ 2435 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2436 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2437 2438 if ((sc->sk_type == SK_YUKON_FE_P) && 2439 (sc->sk_rev == SK_YUKON_FE_P_REV_A0)) { 2440 v = SK_IF_READ_2(sc_if, 0, SK_TXMF1_END); 2441 v &= ~SK_TXEND_WM_ON; 2442 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_END, v); 2443 } 2444 2445 #if 1 2446 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2447 #endif 2448 DPRINTFN(6, ("msk_init_yukon: end\n")); 2449 } 2450 2451 /* 2452 * Note that to properly initialize any part of the GEnesis chip, 2453 * you first have to take it out of reset mode. 2454 */ 2455 static int 2456 msk_init(struct ifnet *ifp) 2457 { 2458 struct sk_if_softc *sc_if = ifp->if_softc; 2459 struct sk_softc *sc = sc_if->sk_softc; 2460 int rc = 0, s; 2461 uint32_t imr, imtimer_ticks; 2462 2463 2464 DPRINTFN(2, ("msk_init\n")); 2465 2466 s = splnet(); 2467 2468 /* Cancel pending I/O and free all RX/TX buffers. */ 2469 msk_stop(ifp, 1); 2470 2471 /* Configure I2C registers */ 2472 2473 /* Configure XMAC(s) */ 2474 msk_init_yukon(sc_if); 2475 if ((rc = ether_mediachange(ifp)) != 0) 2476 goto out; 2477 2478 /* Configure transmit arbiter(s) */ 2479 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2480 #if 0 2481 /* SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); */ 2482 #endif 2483 2484 if (sc->sk_ramsize) { 2485 /* Configure RAMbuffers */ 2486 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2487 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2488 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2489 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2490 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2491 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2492 2493 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2494 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2495 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2496 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2497 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2498 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2499 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2500 } 2501 2502 /* Configure BMUs */ 2503 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2504 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2505 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2506 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2507 2508 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2509 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2510 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2511 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2512 2513 /* Make sure the sync transmit queue is disabled. */ 2514 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2515 2516 /* Init descriptors */ 2517 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2518 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2519 "memory for rx buffers\n"); 2520 msk_stop(ifp, 1); 2521 splx(s); 2522 return ENOBUFS; 2523 } 2524 2525 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2526 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2527 "memory for tx buffers\n"); 2528 msk_stop(ifp, 1); 2529 splx(s); 2530 return ENOBUFS; 2531 } 2532 2533 /* Set interrupt moderation if changed via sysctl. */ 2534 switch (sc->sk_type) { 2535 case SK_YUKON_EC: 2536 case SK_YUKON_EC_U: 2537 case SK_YUKON_EX: 2538 case SK_YUKON_SUPR: 2539 case SK_YUKON_ULTRA2: 2540 case SK_YUKON_OPTIMA: 2541 case SK_YUKON_PRM: 2542 case SK_YUKON_OPTIMA2: 2543 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2544 break; 2545 case SK_YUKON_FE: 2546 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2547 break; 2548 case SK_YUKON_FE_P: 2549 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 2550 break; 2551 case SK_YUKON_XL: 2552 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2553 break; 2554 default: 2555 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2556 } 2557 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2558 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2559 sk_win_write_4(sc, SK_IMTIMERINIT, 2560 SK_IM_USECS(sc->sk_int_mod)); 2561 aprint_verbose_dev(sc->sk_dev, 2562 "interrupt moderation is %d us\n", sc->sk_int_mod); 2563 } 2564 2565 /* Initialize prefetch engine. */ 2566 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2567 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2568 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2569 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2570 MSK_RX_RING_ADDR(sc_if, 0)); 2571 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2572 (uint64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2573 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2574 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2575 2576 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2577 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2578 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2579 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2580 MSK_TX_RING_ADDR(sc_if, 0)); 2581 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2582 (uint64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2583 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2584 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2585 2586 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2587 sc_if->sk_cdata.sk_rx_prod); 2588 2589 2590 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_SUPR)) { 2591 /* Disable flushing of non-ASF packets. */ 2592 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, 2593 SK_RFCTL_RX_MACSEC_FLUSH_OFF); 2594 } 2595 2596 /* Configure interrupt handling */ 2597 if (sc_if->sk_port == SK_PORT_A) 2598 sc->sk_intrmask |= SK_Y2_INTRS1; 2599 else 2600 sc->sk_intrmask |= SK_Y2_INTRS2; 2601 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2602 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2603 2604 ifp->if_flags |= IFF_RUNNING; 2605 ifp->if_flags &= ~IFF_OACTIVE; 2606 2607 callout_schedule(&sc_if->sk_tick_ch, hz); 2608 2609 out: 2610 splx(s); 2611 return rc; 2612 } 2613 2614 /* 2615 * Note: the logic of second parameter is inverted compared to OpenBSD 2616 * code, since this code uses the function as if_stop hook too. 2617 */ 2618 static void 2619 msk_stop(struct ifnet *ifp, int disable) 2620 { 2621 struct sk_if_softc *sc_if = ifp->if_softc; 2622 struct sk_softc *sc = sc_if->sk_softc; 2623 struct sk_txmap_entry *dma; 2624 int i; 2625 2626 DPRINTFN(2, ("msk_stop\n")); 2627 2628 callout_stop(&sc_if->sk_tick_ch); 2629 callout_stop(&sc_if->sk_tick_rx); 2630 2631 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2632 2633 /* Stop transfer of Tx descriptors */ 2634 2635 /* Stop transfer of Rx descriptors */ 2636 2637 if (disable) { 2638 /* Turn off various components of this interface. */ 2639 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2640 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2641 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2642 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2643 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2644 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2645 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2646 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2647 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2648 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2649 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2650 2651 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2652 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2653 2654 /* Disable interrupts */ 2655 if (sc_if->sk_port == SK_PORT_A) 2656 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2657 else 2658 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2659 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2660 } 2661 2662 /* Free RX and TX mbufs still in the queues. */ 2663 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2664 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2665 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2666 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2667 } 2668 } 2669 2670 sc_if->sk_cdata.sk_rx_prod = 0; 2671 sc_if->sk_cdata.sk_rx_cons = 0; 2672 sc_if->sk_cdata.sk_rx_cnt = 0; 2673 2674 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2675 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2676 dma = sc_if->sk_cdata.sk_tx_map[i]; 2677 2678 bus_dmamap_sync(sc->sc_dmatag, dma->dmamap, 0, 2679 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2680 2681 bus_dmamap_unload(sc->sc_dmatag, dma->dmamap); 2682 #if 1 2683 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2684 sc_if->sk_cdata.sk_tx_map[i], link); 2685 sc_if->sk_cdata.sk_tx_map[i] = 0; 2686 #endif 2687 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2688 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2689 } 2690 } 2691 2692 #if 1 2693 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2694 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2695 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2696 free(dma, M_DEVBUF); 2697 } 2698 #endif 2699 } 2700 2701 CFATTACH_DECL3_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2702 mskc_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2703 2704 CFATTACH_DECL3_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2705 msk_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2706 2707 #ifdef MSK_DEBUG 2708 static void 2709 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2710 { 2711 #define DESC_PRINT(X) \ 2712 if (X) \ 2713 printf("txdesc[%d]." #X "=%#x\n", \ 2714 idx, X); 2715 2716 DESC_PRINT(letoh32(le->sk_addr)); 2717 DESC_PRINT(letoh16(le->sk_len)); 2718 DESC_PRINT(le->sk_ctl); 2719 DESC_PRINT(le->sk_opcode); 2720 #undef DESC_PRINT 2721 } 2722 2723 static void 2724 msk_dump_bytes(const char *data, int len) 2725 { 2726 int c, i, j; 2727 2728 for (i = 0; i < len; i += 16) { 2729 printf("%08x ", i); 2730 c = len - i; 2731 if (c > 16) c = 16; 2732 2733 for (j = 0; j < c; j++) { 2734 printf("%02x ", data[i + j] & 0xff); 2735 if ((j & 0xf) == 7 && j > 0) 2736 printf(" "); 2737 } 2738 2739 for (; j < 16; j++) 2740 printf(" "); 2741 printf(" "); 2742 2743 for (j = 0; j < c; j++) { 2744 int ch = data[i + j] & 0xff; 2745 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2746 } 2747 2748 printf("\n"); 2749 2750 if (c < 16) 2751 break; 2752 } 2753 } 2754 2755 static void 2756 msk_dump_mbuf(struct mbuf *m) 2757 { 2758 int count = m->m_pkthdr.len; 2759 2760 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2761 2762 while (count > 0 && m) { 2763 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2764 m, m->m_data, m->m_len); 2765 if (mskdebug >= 4) 2766 msk_dump_bytes(mtod(m, char *), m->m_len); 2767 2768 count -= m->m_len; 2769 m = m->m_next; 2770 } 2771 } 2772 #endif 2773 2774 static int 2775 msk_sysctl_handler(SYSCTLFN_ARGS) 2776 { 2777 int error, t; 2778 struct sysctlnode node; 2779 struct sk_softc *sc; 2780 2781 node = *rnode; 2782 sc = node.sysctl_data; 2783 t = sc->sk_int_mod; 2784 node.sysctl_data = &t; 2785 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2786 if (error || newp == NULL) 2787 return error; 2788 2789 if (t < SK_IM_MIN || t > SK_IM_MAX) 2790 return EINVAL; 2791 2792 /* update the softc with sysctl-changed value, and mark 2793 for hardware update */ 2794 sc->sk_int_mod = t; 2795 sc->sk_int_mod_pending = 1; 2796 return 0; 2797 } 2798 2799 /* 2800 * Set up sysctl(3) MIB, hw.msk.* - Individual controllers will be 2801 * set up in mskc_attach() 2802 */ 2803 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2804 { 2805 int rc; 2806 const struct sysctlnode *node; 2807 2808 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2809 0, CTLTYPE_NODE, "msk", 2810 SYSCTL_DESCR("msk interface controls"), 2811 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2812 goto err; 2813 } 2814 2815 msk_root_num = node->sysctl_num; 2816 return; 2817 2818 err: 2819 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2820 } 2821
Indexes created Sun Sep 21 20:09:37 GMT 2025