if_msk.c revision 1.99
1 /* $NetBSD: if_msk.c,v 1.99 2020/04/18 17:31:52 jakllsch Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.79 2009/10/15 17:54:56 deraadt Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.99 2020/04/18 17:31:52 jakllsch Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/mutex.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/device.h> 66 #include <sys/queue.h> 67 #include <sys/callout.h> 68 #include <sys/sysctl.h> 69 #include <sys/endian.h> 70 #ifdef __NetBSD__ 71 #define letoh16 htole16 72 #define letoh32 htole32 73 #endif 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #include <net/if_media.h> 80 81 #include <net/bpf.h> 82 #include <sys/rndsource.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 #include <dev/mii/brgphyreg.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 92 #include <dev/pci/if_skreg.h> 93 #include <dev/pci/if_mskvar.h> 94 95 static int mskc_probe(device_t, cfdata_t, void *); 96 static void mskc_attach(device_t, device_t, void *); 97 static int mskc_detach(device_t, int); 98 static void mskc_reset(struct sk_softc *); 99 static bool mskc_suspend(device_t, const pmf_qual_t *); 100 static bool mskc_resume(device_t, const pmf_qual_t *); 101 static int msk_probe(device_t, cfdata_t, void *); 102 static void msk_attach(device_t, device_t, void *); 103 static int msk_detach(device_t, int); 104 static void msk_reset(struct sk_if_softc *); 105 static int mskcprint(void *, const char *); 106 static int msk_intr(void *); 107 static void msk_intr_yukon(struct sk_if_softc *); 108 static void msk_rxeof(struct sk_if_softc *, uint16_t, uint32_t); 109 static void msk_txeof(struct sk_if_softc *); 110 static int msk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 111 static void msk_start(struct ifnet *); 112 static int msk_ioctl(struct ifnet *, u_long, void *); 113 static int msk_init(struct ifnet *); 114 static void msk_init_yukon(struct sk_if_softc *); 115 static void msk_stop(struct ifnet *, int); 116 static void msk_watchdog(struct ifnet *); 117 static int msk_newbuf(struct sk_if_softc *, bus_dmamap_t); 118 static int msk_alloc_jumbo_mem(struct sk_if_softc *); 119 static void *msk_jalloc(struct sk_if_softc *); 120 static void msk_jfree(struct mbuf *, void *, size_t, void *); 121 static int msk_init_rx_ring(struct sk_if_softc *); 122 static int msk_init_tx_ring(struct sk_if_softc *); 123 static void msk_fill_rx_ring(struct sk_if_softc *); 124 125 static void msk_update_int_mod(struct sk_softc *, int); 126 127 static int msk_miibus_readreg(device_t, int, int, uint16_t *); 128 static int msk_miibus_writereg(device_t, int, int, uint16_t); 129 static void msk_miibus_statchg(struct ifnet *); 130 131 static void msk_setmulti(struct sk_if_softc *); 132 static void msk_setpromisc(struct sk_if_softc *); 133 static void msk_tick(void *); 134 static void msk_fill_rx_tick(void *); 135 136 /* #define MSK_DEBUG 1 */ 137 #ifdef MSK_DEBUG 138 #define DPRINTF(x) if (mskdebug) printf x 139 #define DPRINTFN(n, x) if (mskdebug >= (n)) printf x 140 int mskdebug = MSK_DEBUG; 141 142 static void msk_dump_txdesc(struct msk_tx_desc *, int); 143 static void msk_dump_mbuf(struct mbuf *); 144 static void msk_dump_bytes(const char *, int); 145 #else 146 #define DPRINTF(x) 147 #define DPRINTFN(n, x) 148 #endif 149 150 static int msk_sysctl_handler(SYSCTLFN_PROTO); 151 static int msk_root_num; 152 153 #define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL) 154 #define MSK_ADDR_HI(x) ((uint64_t) (x) >> 32) 155 156 /* supported device vendors */ 157 static const struct msk_product { 158 pci_vendor_id_t msk_vendor; 159 pci_product_id_t msk_product; 160 } msk_products[] = { 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 163 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 164 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8079 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 197 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 198 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 199 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 200 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 201 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 }, 202 { 0, 0 } 203 }; 204 205 static inline uint32_t 206 sk_win_read_4(struct sk_softc *sc, uint32_t reg) 207 { 208 return CSR_READ_4(sc, reg); 209 } 210 211 static inline uint16_t 212 sk_win_read_2(struct sk_softc *sc, uint32_t reg) 213 { 214 return CSR_READ_2(sc, reg); 215 } 216 217 static inline uint8_t 218 sk_win_read_1(struct sk_softc *sc, uint32_t reg) 219 { 220 return CSR_READ_1(sc, reg); 221 } 222 223 static inline void 224 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x) 225 { 226 CSR_WRITE_4(sc, reg, x); 227 } 228 229 static inline void 230 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x) 231 { 232 CSR_WRITE_2(sc, reg, x); 233 } 234 235 static inline void 236 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x) 237 { 238 CSR_WRITE_1(sc, reg, x); 239 } 240 241 static int 242 msk_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 243 { 244 struct sk_if_softc *sc_if = device_private(dev); 245 uint16_t data; 246 int i; 247 248 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 249 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 250 251 for (i = 0; i < SK_TIMEOUT; i++) { 252 DELAY(1); 253 data = SK_YU_READ_2(sc_if, YUKON_SMICR); 254 if (data & YU_SMICR_READ_VALID) 255 break; 256 } 257 258 if (i == SK_TIMEOUT) { 259 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 260 return ETIMEDOUT; 261 } 262 263 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, SK_TIMEOUT)); 264 265 *val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 266 267 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#hx\n", 268 phy, reg, *val)); 269 270 return 0; 271 } 272 273 static int 274 msk_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 275 { 276 struct sk_if_softc *sc_if = device_private(dev); 277 int i; 278 279 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#hx\n", 280 phy, reg, val)); 281 282 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 283 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 284 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 285 286 for (i = 0; i < SK_TIMEOUT; i++) { 287 DELAY(1); 288 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 289 break; 290 } 291 292 if (i == SK_TIMEOUT) { 293 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 294 return ETIMEDOUT; 295 } 296 297 return 0; 298 } 299 300 static void 301 msk_miibus_statchg(struct ifnet *ifp) 302 { 303 struct sk_if_softc *sc_if = ifp->if_softc; 304 struct mii_data *mii = &sc_if->sk_mii; 305 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 306 int gpcr; 307 308 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 309 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 310 311 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 312 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 313 /* Set speed. */ 314 gpcr |= YU_GPCR_SPEED_DIS; 315 switch (IFM_SUBTYPE(mii->mii_media_active)) { 316 case IFM_1000_SX: 317 case IFM_1000_LX: 318 case IFM_1000_CX: 319 case IFM_1000_T: 320 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 321 break; 322 case IFM_100_TX: 323 gpcr |= YU_GPCR_SPEED; 324 break; 325 } 326 327 /* Set duplex. */ 328 gpcr |= YU_GPCR_DPLX_DIS; 329 if ((mii->mii_media_active & IFM_FDX) != 0) 330 gpcr |= YU_GPCR_DUPLEX; 331 332 /* Disable flow control. */ 333 gpcr |= YU_GPCR_FCTL_DIS; 334 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 335 } 336 337 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 338 339 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 340 SK_YU_READ_2(sc_if, YUKON_GPCR))); 341 } 342 343 static void 344 msk_setmulti(struct sk_if_softc *sc_if) 345 { 346 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 347 uint32_t hashes[2] = { 0, 0 }; 348 int h; 349 struct ethercom *ec = &sc_if->sk_ethercom; 350 struct ether_multi *enm; 351 struct ether_multistep step; 352 uint16_t reg; 353 354 /* First, zot all the existing filters. */ 355 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 356 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 357 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 358 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 359 360 361 /* Now program new ones. */ 362 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 363 reg |= YU_RCR_UFLEN; 364 allmulti: 365 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 366 if ((ifp->if_flags & IFF_PROMISC) != 0) 367 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 368 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 369 hashes[0] = 0xFFFFFFFF; 370 hashes[1] = 0xFFFFFFFF; 371 } 372 } else { 373 /* First find the tail of the list. */ 374 ETHER_LOCK(ec); 375 ETHER_FIRST_MULTI(step, ec, enm); 376 while (enm != NULL) { 377 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 378 ETHER_ADDR_LEN)) { 379 ifp->if_flags |= IFF_ALLMULTI; 380 ETHER_UNLOCK(ec); 381 goto allmulti; 382 } 383 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 384 ((1 << SK_HASH_BITS) - 1); 385 if (h < 32) 386 hashes[0] |= (1 << h); 387 else 388 hashes[1] |= (1 << (h - 32)); 389 390 ETHER_NEXT_MULTI(step, enm); 391 } 392 ETHER_UNLOCK(ec); 393 reg |= YU_RCR_MUFLEN; 394 } 395 396 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 397 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 398 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 399 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 400 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 401 } 402 403 static void 404 msk_setpromisc(struct sk_if_softc *sc_if) 405 { 406 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 407 408 if (ifp->if_flags & IFF_PROMISC) 409 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 410 YU_RCR_UFLEN | YU_RCR_MUFLEN); 411 else 412 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 413 YU_RCR_UFLEN | YU_RCR_MUFLEN); 414 } 415 416 static int 417 msk_init_rx_ring(struct sk_if_softc *sc_if) 418 { 419 struct msk_chain_data *cd = &sc_if->sk_cdata; 420 struct msk_ring_data *rd = sc_if->sk_rdata; 421 struct msk_rx_desc *r; 422 int i, nexti; 423 424 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 425 426 for (i = 0; i < MSK_RX_RING_CNT; i++) { 427 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 428 if (i == (MSK_RX_RING_CNT - 1)) 429 nexti = 0; 430 else 431 nexti = i + 1; 432 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 433 } 434 435 sc_if->sk_cdata.sk_rx_prod = 0; 436 sc_if->sk_cdata.sk_rx_cons = 0; 437 sc_if->sk_cdata.sk_rx_cnt = 0; 438 sc_if->sk_cdata.sk_rx_hiaddr = 0; 439 440 /* Mark the first ring element to initialize the high address. */ 441 sc_if->sk_cdata.sk_rx_hiaddr = 0; 442 r = &rd->sk_rx_ring[cd->sk_rx_prod]; 443 r->sk_addr = htole32(cd->sk_rx_hiaddr); 444 r->sk_len = 0; 445 r->sk_ctl = 0; 446 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN; 447 MSK_CDRXSYNC(sc_if, cd->sk_rx_prod, 448 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 449 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 450 sc_if->sk_cdata.sk_rx_cnt++; 451 452 msk_fill_rx_ring(sc_if); 453 return 0; 454 } 455 456 static int 457 msk_init_tx_ring(struct sk_if_softc *sc_if) 458 { 459 struct msk_chain_data *cd = &sc_if->sk_cdata; 460 struct msk_ring_data *rd = sc_if->sk_rdata; 461 struct msk_tx_desc *t; 462 int i, nexti; 463 464 memset(rd->sk_tx_ring, 0, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 465 466 for (i = 0; i < MSK_TX_RING_CNT; i++) { 467 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 468 if (i == (MSK_TX_RING_CNT - 1)) 469 nexti = 0; 470 else 471 nexti = i + 1; 472 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 473 } 474 475 sc_if->sk_cdata.sk_tx_prod = 0; 476 sc_if->sk_cdata.sk_tx_cons = 0; 477 sc_if->sk_cdata.sk_tx_cnt = 0; 478 sc_if->sk_cdata.sk_tx_hiaddr = 0; 479 480 /* Mark the first ring element to initialize the high address. */ 481 sc_if->sk_cdata.sk_tx_hiaddr = 0; 482 t = &rd->sk_tx_ring[cd->sk_tx_prod]; 483 t->sk_addr = htole32(cd->sk_tx_hiaddr); 484 t->sk_len = 0; 485 t->sk_ctl = 0; 486 t->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 487 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 488 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 489 SK_INC(sc_if->sk_cdata.sk_tx_prod, MSK_TX_RING_CNT); 490 sc_if->sk_cdata.sk_tx_cnt++; 491 492 return 0; 493 } 494 495 static int 496 msk_newbuf(struct sk_if_softc *sc_if, bus_dmamap_t dmamap) 497 { 498 struct mbuf *m_new = NULL; 499 struct sk_chain *c; 500 struct msk_rx_desc *r; 501 void *buf = NULL; 502 bus_addr_t addr; 503 504 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 505 if (m_new == NULL) 506 return ENOBUFS; 507 508 /* Allocate the jumbo buffer */ 509 buf = msk_jalloc(sc_if); 510 if (buf == NULL) { 511 m_freem(m_new); 512 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 513 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 514 return ENOBUFS; 515 } 516 517 /* Attach the buffer to the mbuf */ 518 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 519 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 520 521 m_adj(m_new, ETHER_ALIGN); 522 523 addr = dmamap->dm_segs[0].ds_addr + 524 ((vaddr_t)m_new->m_data - 525 (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf); 526 527 if (sc_if->sk_cdata.sk_rx_hiaddr != MSK_ADDR_HI(addr)) { 528 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 529 r = c->sk_le; 530 c->sk_mbuf = NULL; 531 r->sk_addr = htole32(MSK_ADDR_HI(addr)); 532 r->sk_len = 0; 533 r->sk_ctl = 0; 534 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN; 535 sc_if->sk_cdata.sk_rx_hiaddr = MSK_ADDR_HI(addr); 536 537 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 538 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 539 540 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 541 sc_if->sk_cdata.sk_rx_cnt++; 542 543 DPRINTFN(10, ("%s: rx ADDR64: %#x\n", 544 sc_if->sk_ethercom.ec_if.if_xname, 545 (unsigned)MSK_ADDR_HI(addr))); 546 } 547 548 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 549 r = c->sk_le; 550 c->sk_mbuf = m_new; 551 r->sk_addr = htole32(MSK_ADDR_LO(addr)); 552 r->sk_len = htole16(SK_JLEN); 553 r->sk_ctl = 0; 554 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 555 556 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 557 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 558 559 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 560 sc_if->sk_cdata.sk_rx_cnt++; 561 562 return 0; 563 } 564 565 /* 566 * Memory management for jumbo frames. 567 */ 568 569 static int 570 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 571 { 572 struct sk_softc *sc = sc_if->sk_softc; 573 char *ptr, *kva; 574 int i, state, error; 575 struct sk_jpool_entry *entry; 576 577 state = error = 0; 578 579 /* Grab a big chunk o' storage. */ 580 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 581 &sc_if->sk_cdata.sk_jumbo_seg, 1, &sc_if->sk_cdata.sk_jumbo_nseg, 582 BUS_DMA_NOWAIT)) { 583 aprint_error(": can't alloc rx buffers"); 584 return ENOBUFS; 585 } 586 587 state = 1; 588 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 589 sc_if->sk_cdata.sk_jumbo_nseg, MSK_JMEM, (void **)&kva, 590 BUS_DMA_NOWAIT)) { 591 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 592 error = ENOBUFS; 593 goto out; 594 } 595 596 state = 2; 597 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 598 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 599 aprint_error(": can't create dma map"); 600 error = ENOBUFS; 601 goto out; 602 } 603 604 state = 3; 605 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 606 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 607 aprint_error(": can't load dma map"); 608 error = ENOBUFS; 609 goto out; 610 } 611 612 state = 4; 613 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 614 DPRINTFN(1,("msk_jumbo_buf = %p\n", 615 (void *)sc_if->sk_cdata.sk_jumbo_buf)); 616 617 LIST_INIT(&sc_if->sk_jfree_listhead); 618 LIST_INIT(&sc_if->sk_jinuse_listhead); 619 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 620 621 /* 622 * Now divide it up into 9K pieces and save the addresses 623 * in an array. 624 */ 625 ptr = sc_if->sk_cdata.sk_jumbo_buf; 626 for (i = 0; i < MSK_JSLOTS; i++) { 627 sc_if->sk_cdata.sk_jslots[i] = ptr; 628 ptr += SK_JLEN; 629 entry = malloc(sizeof(struct sk_jpool_entry), 630 M_DEVBUF, M_WAITOK); 631 entry->slot = i; 632 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 633 entry, jpool_entries); 634 } 635 out: 636 if (error != 0) { 637 switch (state) { 638 case 4: 639 bus_dmamap_unload(sc->sc_dmatag, 640 sc_if->sk_cdata.sk_rx_jumbo_map); 641 /* FALLTHROUGH */ 642 case 3: 643 bus_dmamap_destroy(sc->sc_dmatag, 644 sc_if->sk_cdata.sk_rx_jumbo_map); 645 /* FALLTHROUGH */ 646 case 2: 647 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 648 /* FALLTHROUGH */ 649 case 1: 650 bus_dmamem_free(sc->sc_dmatag, 651 &sc_if->sk_cdata.sk_jumbo_seg, 652 sc_if->sk_cdata.sk_jumbo_nseg); 653 break; 654 default: 655 break; 656 } 657 } 658 659 return error; 660 } 661 662 static void 663 msk_free_jumbo_mem(struct sk_if_softc *sc_if) 664 { 665 struct sk_softc *sc = sc_if->sk_softc; 666 667 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 668 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 669 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_cdata.sk_jumbo_buf, MSK_JMEM); 670 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 671 sc_if->sk_cdata.sk_jumbo_nseg); 672 } 673 674 /* 675 * Allocate a jumbo buffer. 676 */ 677 static void * 678 msk_jalloc(struct sk_if_softc *sc_if) 679 { 680 struct sk_jpool_entry *entry; 681 682 mutex_enter(&sc_if->sk_jpool_mtx); 683 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 684 685 if (entry == NULL) { 686 mutex_exit(&sc_if->sk_jpool_mtx); 687 return NULL; 688 } 689 690 LIST_REMOVE(entry, jpool_entries); 691 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 692 mutex_exit(&sc_if->sk_jpool_mtx); 693 return sc_if->sk_cdata.sk_jslots[entry->slot]; 694 } 695 696 /* 697 * Release a jumbo buffer. 698 */ 699 static void 700 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 701 { 702 struct sk_jpool_entry *entry; 703 struct sk_if_softc *sc; 704 int i; 705 706 /* Extract the softc struct pointer. */ 707 sc = (struct sk_if_softc *)arg; 708 709 if (sc == NULL) 710 panic("msk_jfree: can't find softc pointer!"); 711 712 /* calculate the slot this buffer belongs to */ 713 i = ((vaddr_t)buf 714 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 715 716 if ((i < 0) || (i >= MSK_JSLOTS)) 717 panic("msk_jfree: asked to free buffer that we don't manage!"); 718 719 mutex_enter(&sc->sk_jpool_mtx); 720 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 721 if (entry == NULL) 722 panic("msk_jfree: buffer not in use!"); 723 entry->slot = i; 724 LIST_REMOVE(entry, jpool_entries); 725 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 726 mutex_exit(&sc->sk_jpool_mtx); 727 728 if (__predict_true(m != NULL)) 729 pool_cache_put(mb_cache, m); 730 731 /* Now that we know we have a free RX buffer, refill if running out */ 732 if ((sc->sk_ethercom.ec_if.if_flags & IFF_RUNNING) != 0 733 && sc->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 734 callout_schedule(&sc->sk_tick_rx, 0); 735 } 736 737 static int 738 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 739 { 740 struct sk_if_softc *sc = ifp->if_softc; 741 int s, error; 742 743 s = splnet(); 744 745 DPRINTFN(2, ("msk_ioctl ETHER cmd %lx\n", cmd)); 746 switch (cmd) { 747 case SIOCSIFFLAGS: 748 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 749 break; 750 751 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 752 case IFF_RUNNING: 753 msk_stop(ifp, 1); 754 break; 755 case IFF_UP: 756 msk_init(ifp); 757 break; 758 case IFF_UP | IFF_RUNNING: 759 if ((ifp->if_flags ^ sc->sk_if_flags) == IFF_PROMISC) { 760 msk_setpromisc(sc); 761 msk_setmulti(sc); 762 } else 763 msk_init(ifp); 764 break; 765 } 766 sc->sk_if_flags = ifp->if_flags; 767 break; 768 default: 769 error = ether_ioctl(ifp, cmd, data); 770 if (error == ENETRESET) { 771 error = 0; 772 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 773 ; 774 else if (ifp->if_flags & IFF_RUNNING) { 775 /* 776 * Multicast list has changed; set the hardware 777 * filter accordingly. 778 */ 779 msk_setmulti(sc); 780 } 781 } 782 break; 783 } 784 785 splx(s); 786 return error; 787 } 788 789 static void 790 msk_update_int_mod(struct sk_softc *sc, int verbose) 791 { 792 uint32_t imtimer_ticks; 793 794 /* 795 * Configure interrupt moderation. The moderation timer 796 * defers interrupts specified in the interrupt moderation 797 * timer mask based on the timeout specified in the interrupt 798 * moderation timer init register. Each bit in the timer 799 * register represents one tick, so to specify a timeout in 800 * microseconds, we have to multiply by the correct number of 801 * ticks-per-microsecond. 802 */ 803 switch (sc->sk_type) { 804 case SK_YUKON_EC: 805 case SK_YUKON_EC_U: 806 case SK_YUKON_EX: 807 case SK_YUKON_SUPR: 808 case SK_YUKON_ULTRA2: 809 case SK_YUKON_OPTIMA: 810 case SK_YUKON_PRM: 811 case SK_YUKON_OPTIMA2: 812 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 813 break; 814 case SK_YUKON_FE: 815 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 816 break; 817 case SK_YUKON_FE_P: 818 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 819 break; 820 case SK_YUKON_XL: 821 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 822 break; 823 default: 824 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 825 } 826 if (verbose) 827 aprint_verbose_dev(sc->sk_dev, 828 "interrupt moderation is %d us\n", sc->sk_int_mod); 829 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 830 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF | SK_ISR_TX2_S_EOF | 831 SK_ISR_RX1_EOF | SK_ISR_RX2_EOF); 832 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 833 sc->sk_int_mod_pending = 0; 834 } 835 836 static int 837 msk_lookup(const struct pci_attach_args *pa) 838 { 839 const struct msk_product *pmsk; 840 841 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 842 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 843 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 844 return 1; 845 } 846 return 0; 847 } 848 849 /* 850 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 851 * IDs against our list and return a device name if we find a match. 852 */ 853 static int 854 mskc_probe(device_t parent, cfdata_t match, void *aux) 855 { 856 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 857 858 return msk_lookup(pa); 859 } 860 861 /* 862 * Force the GEnesis into reset, then bring it out of reset. 863 */ 864 static void 865 mskc_reset(struct sk_softc *sc) 866 { 867 uint32_t imtimer_ticks, reg1; 868 uint16_t status; 869 int reg; 870 871 DPRINTFN(2, ("mskc_reset\n")); 872 873 /* Disable ASF */ 874 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_SUPR)) { 875 CSR_WRITE_4(sc, SK_Y2_CPU_WDOG, 0); 876 status = CSR_READ_2(sc, SK_Y2_ASF_HCU_CCSR); 877 /* Clear AHB bridge & microcontroller reset. */ 878 status &= ~(SK_Y2_ASF_HCU_CSSR_ARB_RST | 879 SK_Y2_ASF_HCU_CSSR_CPU_RST_MODE); 880 /* Clear ASF microcontroller state. */ 881 status &= ~SK_Y2_ASF_HCU_CSSR_UC_STATE_MSK; 882 status &= ~SK_Y2_ASF_HCU_CSSR_CPU_CLK_DIVIDE_MSK; 883 CSR_WRITE_2(sc, SK_Y2_ASF_HCU_CCSR, status); 884 CSR_WRITE_4(sc, SK_Y2_CPU_WDOG, 0); 885 } else 886 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 887 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 888 889 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 890 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 891 892 DELAY(1000); 893 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 894 DELAY(2); 895 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 896 sk_win_write_1(sc, SK_TESTCTL1, 2); 897 898 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 899 sc->sk_type >= SK_YUKON_FE_P) { 900 uint32_t our; 901 902 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 903 904 /* enable all clocks. */ 905 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 906 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 907 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST | 908 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN | 909 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY | 910 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 911 /* Set all bits to 0 except bits 15..12 */ 912 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 913 /* Set to default value */ 914 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 915 916 /* 917 * Disable status race, workaround for Yukon EC Ultra & 918 * Yukon EX. 919 */ 920 reg1 = sk_win_read_4(sc, SK_GPIO); 921 reg1 |= SK_Y2_GPIO_STAT_RACE_DIS; 922 sk_win_write_4(sc, SK_GPIO, reg1); 923 sk_win_read_4(sc, SK_GPIO); 924 } 925 926 /* release PHY from PowerDown/Coma mode. */ 927 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 928 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 929 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 930 else 931 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 932 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 933 934 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 935 sk_win_write_1(sc, SK_Y2_CLKGATE, 936 SK_Y2_CLKGATE_LINK1_GATE_DIS | 937 SK_Y2_CLKGATE_LINK2_GATE_DIS | 938 SK_Y2_CLKGATE_LINK1_CORE_DIS | 939 SK_Y2_CLKGATE_LINK2_CORE_DIS | 940 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 941 else 942 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 943 944 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 945 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 946 DELAY(1000); 947 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 948 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 949 950 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 951 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 952 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 953 } 954 955 sk_win_write_1(sc, SK_TESTCTL1, 1); 956 957 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 958 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 959 CSR_READ_2(sc, SK_LINK_CTRL))); 960 961 /* Clear I2C IRQ noise */ 962 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 963 964 /* Disable hardware timer */ 965 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 966 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 967 968 /* Disable descriptor polling */ 969 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 970 971 /* Disable time stamps */ 972 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 973 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 974 975 /* Enable RAM interface */ 976 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 977 for (reg = SK_TO0;reg <= SK_TO11; reg++) 978 sk_win_write_1(sc, reg, 36); 979 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 980 for (reg = SK_TO0;reg <= SK_TO11; reg++) 981 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 982 983 /* 984 * Configure interrupt moderation. The moderation timer 985 * defers interrupts specified in the interrupt moderation 986 * timer mask based on the timeout specified in the interrupt 987 * moderation timer init register. Each bit in the timer 988 * register represents one tick, so to specify a timeout in 989 * microseconds, we have to multiply by the correct number of 990 * ticks-per-microsecond. 991 */ 992 switch (sc->sk_type) { 993 case SK_YUKON_EC: 994 case SK_YUKON_EC_U: 995 case SK_YUKON_EX: 996 case SK_YUKON_SUPR: 997 case SK_YUKON_ULTRA2: 998 case SK_YUKON_OPTIMA: 999 case SK_YUKON_PRM: 1000 case SK_YUKON_OPTIMA2: 1001 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1002 break; 1003 case SK_YUKON_FE: 1004 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 1005 break; 1006 case SK_YUKON_FE_P: 1007 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 1008 break; 1009 case SK_YUKON_XL: 1010 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 1011 break; 1012 default: 1013 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1014 break; 1015 } 1016 1017 /* Reset status ring. */ 1018 memset(sc->sk_status_ring, 0, 1019 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1020 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 1021 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1022 sc->sk_status_idx = 0; 1023 1024 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 1025 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 1026 1027 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 1028 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 1029 MSK_ADDR_LO(sc->sk_status_map->dm_segs[0].ds_addr)); 1030 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 1031 MSK_ADDR_HI(sc->sk_status_map->dm_segs[0].ds_addr)); 1032 if (sc->sk_type == SK_YUKON_EC && 1033 sc->sk_rev == SK_YUKON_EC_REV_A1) { 1034 /* WA for dev. #4.3 */ 1035 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 1036 SK_STAT_BMU_TXTHIDX_MSK); 1037 /* WA for dev. #4.18 */ 1038 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 1039 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 1040 } else { 1041 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 1042 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 1043 if (sc->sk_type == SK_YUKON_XL) 1044 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x04); 1045 else 1046 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x10); 1047 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 1048 } 1049 1050 #if 0 1051 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 1052 #endif 1053 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 1054 1055 /* Enable status unit. */ 1056 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 1057 1058 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 1059 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 1060 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 1061 1062 msk_update_int_mod(sc, 0); 1063 } 1064 1065 static int 1066 msk_probe(device_t parent, cfdata_t match, void *aux) 1067 { 1068 struct skc_attach_args *sa = aux; 1069 1070 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1071 return 0; 1072 1073 switch (sa->skc_type) { 1074 case SK_YUKON_XL: 1075 case SK_YUKON_EC_U: 1076 case SK_YUKON_EX: 1077 case SK_YUKON_EC: 1078 case SK_YUKON_FE: 1079 case SK_YUKON_FE_P: 1080 case SK_YUKON_SUPR: 1081 case SK_YUKON_ULTRA2: 1082 case SK_YUKON_OPTIMA: 1083 case SK_YUKON_PRM: 1084 case SK_YUKON_OPTIMA2: 1085 return 1; 1086 } 1087 1088 return 0; 1089 } 1090 1091 static void 1092 msk_reset(struct sk_if_softc *sc_if) 1093 { 1094 /* GMAC and GPHY Reset */ 1095 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1096 SK_IF_WRITE_1(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1097 DELAY(1000); 1098 SK_IF_WRITE_1(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1099 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1100 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1101 } 1102 1103 static bool 1104 msk_resume(device_t dv, const pmf_qual_t *qual) 1105 { 1106 struct sk_if_softc *sc_if = device_private(dv); 1107 1108 msk_init_yukon(sc_if); 1109 return true; 1110 } 1111 1112 /* 1113 * Each XMAC chip is attached as a separate logical IP interface. 1114 * Single port cards will have only one logical interface of course. 1115 */ 1116 static void 1117 msk_attach(device_t parent, device_t self, void *aux) 1118 { 1119 struct sk_if_softc *sc_if = device_private(self); 1120 struct sk_softc *sc = device_private(parent); 1121 struct skc_attach_args *sa = aux; 1122 bus_dmamap_t dmamap; 1123 struct sk_txmap_entry *entry; 1124 struct ifnet *ifp; 1125 struct mii_data * const mii = &sc_if->sk_mii; 1126 void *kva; 1127 int i; 1128 uint32_t chunk; 1129 int mii_flags; 1130 1131 sc_if->sk_dev = self; 1132 sc_if->sk_port = sa->skc_port; 1133 sc_if->sk_softc = sc; 1134 sc->sk_if[sa->skc_port] = sc_if; 1135 1136 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1137 1138 /* 1139 * Get station address for this interface. Note that 1140 * dual port cards actually come with three station 1141 * addresses: one for each port, plus an extra. The 1142 * extra one is used by the SysKonnect driver software 1143 * as a 'virtual' station address for when both ports 1144 * are operating in failover mode. Currently we don't 1145 * use this extra address. 1146 */ 1147 for (i = 0; i < ETHER_ADDR_LEN; i++) 1148 sc_if->sk_enaddr[i] = 1149 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1150 1151 aprint_normal(": Ethernet address %s\n", 1152 ether_sprintf(sc_if->sk_enaddr)); 1153 1154 /* 1155 * Set up RAM buffer addresses. The Yukon2 has a small amount 1156 * of SRAM on it, somewhere between 4K and 48K. We need to 1157 * divide this up between the transmitter and receiver. We 1158 * give the receiver 2/3 of the memory (rounded down), and the 1159 * transmitter whatever remains. 1160 */ 1161 if (sc->sk_ramsize) { 1162 chunk = (2 * (sc->sk_ramsize / sizeof(uint64_t)) / 3) & ~0xff; 1163 sc_if->sk_rx_ramstart = 0; 1164 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 1165 chunk = (sc->sk_ramsize / sizeof(uint64_t)) - chunk; 1166 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 1167 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 1168 1169 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1170 " tx_ramstart=%#x tx_ramend=%#x\n", 1171 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1172 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1173 } 1174 1175 /* Allocate the descriptor queues. */ 1176 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1177 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 1178 BUS_DMA_NOWAIT)) { 1179 aprint_error(": can't alloc rx buffers\n"); 1180 goto fail; 1181 } 1182 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 1183 sc_if->sk_ring_nseg, 1184 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1185 aprint_error(": can't map dma buffers (%zu bytes)\n", 1186 sizeof(struct msk_ring_data)); 1187 goto fail_1; 1188 } 1189 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1190 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1191 &sc_if->sk_ring_map)) { 1192 aprint_error(": can't create dma map\n"); 1193 goto fail_2; 1194 } 1195 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1196 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1197 aprint_error(": can't load dma map\n"); 1198 goto fail_3; 1199 } 1200 1201 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1202 for (i = 0; i < MSK_TX_RING_CNT; i++) { 1203 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1204 1205 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1206 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1207 aprint_error_dev(sc_if->sk_dev, 1208 "Can't create TX dmamap\n"); 1209 goto fail_3; 1210 } 1211 1212 entry = malloc(sizeof(*entry), M_DEVBUF, M_WAITOK); 1213 entry->dmamap = dmamap; 1214 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1215 } 1216 1217 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1218 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1219 1220 if (sc->sk_type != SK_YUKON_FE && 1221 sc->sk_type != SK_YUKON_FE_P) 1222 sc_if->sk_pktlen = SK_JLEN; 1223 else 1224 sc_if->sk_pktlen = MCLBYTES; 1225 1226 /* Try to allocate memory for jumbo buffers. */ 1227 if (msk_alloc_jumbo_mem(sc_if)) { 1228 aprint_error(": jumbo buffer allocation failed\n"); 1229 goto fail_3; 1230 } 1231 1232 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1233 if (sc->sk_type != SK_YUKON_FE && 1234 sc->sk_type != SK_YUKON_FE_P) 1235 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1236 1237 ifp = &sc_if->sk_ethercom.ec_if; 1238 ifp->if_softc = sc_if; 1239 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1240 ifp->if_ioctl = msk_ioctl; 1241 ifp->if_start = msk_start; 1242 ifp->if_stop = msk_stop; 1243 ifp->if_init = msk_init; 1244 ifp->if_watchdog = msk_watchdog; 1245 ifp->if_baudrate = 1000000000; 1246 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1247 IFQ_SET_READY(&ifp->if_snd); 1248 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1249 1250 msk_reset(sc_if); 1251 1252 /* 1253 * Do miibus setup. 1254 */ 1255 DPRINTFN(2, ("msk_attach: 1\n")); 1256 1257 mii->mii_ifp = ifp; 1258 mii->mii_readreg = msk_miibus_readreg; 1259 mii->mii_writereg = msk_miibus_writereg; 1260 mii->mii_statchg = msk_miibus_statchg; 1261 1262 sc_if->sk_ethercom.ec_mii = mii; 1263 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1264 mii_flags = MIIF_DOPAUSE; 1265 if (sc->sk_fibertype) 1266 mii_flags |= MIIF_HAVEFIBER; 1267 mii_attach(self, mii, 0xffffffff, 0, MII_OFFSET_ANY, mii_flags); 1268 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1269 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1270 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 1271 0, NULL); 1272 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 1273 } else 1274 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1275 1276 callout_init(&sc_if->sk_tick_ch, 0); 1277 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1278 callout_schedule(&sc_if->sk_tick_ch, hz); 1279 1280 callout_init(&sc_if->sk_tick_rx, 0); 1281 callout_setfunc(&sc_if->sk_tick_rx, msk_fill_rx_tick, sc_if); 1282 1283 /* 1284 * Call MI attach routines. 1285 */ 1286 if_attach(ifp); 1287 if_deferred_start_init(ifp, NULL); 1288 ether_ifattach(ifp, sc_if->sk_enaddr); 1289 1290 if (pmf_device_register(self, NULL, msk_resume)) 1291 pmf_class_network_register(self, ifp); 1292 else 1293 aprint_error_dev(self, "couldn't establish power handler\n"); 1294 1295 if (sc->rnd_attached++ == 0) { 1296 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1297 RND_TYPE_NET, RND_FLAG_DEFAULT); 1298 } 1299 1300 DPRINTFN(2, ("msk_attach: end\n")); 1301 return; 1302 1303 fail_3: 1304 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1305 fail_2: 1306 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1307 fail_1: 1308 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1309 fail: 1310 sc->sk_if[sa->skc_port] = NULL; 1311 } 1312 1313 static int 1314 msk_detach(device_t self, int flags) 1315 { 1316 struct sk_if_softc *sc_if = device_private(self); 1317 struct sk_softc *sc = sc_if->sk_softc; 1318 struct sk_txmap_entry *entry; 1319 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1320 1321 if (sc->sk_if[sc_if->sk_port] == NULL) 1322 return 0; 1323 1324 msk_stop(ifp, 1); 1325 1326 while ((entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 1327 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1328 bus_dmamap_destroy(sc->sc_dmatag, entry->dmamap); 1329 free(entry, M_DEVBUF); 1330 } 1331 1332 if (--sc->rnd_attached == 0) 1333 rnd_detach_source(&sc->rnd_source); 1334 1335 callout_halt(&sc_if->sk_tick_ch, NULL); 1336 callout_destroy(&sc_if->sk_tick_ch); 1337 1338 callout_halt(&sc_if->sk_tick_rx, NULL); 1339 callout_destroy(&sc_if->sk_tick_rx); 1340 1341 /* Detach any PHYs we might have. */ 1342 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1343 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1344 1345 pmf_device_deregister(self); 1346 1347 ether_ifdetach(ifp); 1348 if_detach(ifp); 1349 1350 /* Delete any remaining media. */ 1351 ifmedia_fini(&sc_if->sk_mii.mii_media); 1352 1353 msk_free_jumbo_mem(sc_if); 1354 1355 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_rdata, 1356 sizeof(struct msk_ring_data)); 1357 bus_dmamem_free(sc->sc_dmatag, 1358 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1359 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1360 sc->sk_if[sc_if->sk_port] = NULL; 1361 1362 return 0; 1363 } 1364 1365 static int 1366 mskcprint(void *aux, const char *pnp) 1367 { 1368 struct skc_attach_args *sa = aux; 1369 1370 if (pnp) 1371 aprint_normal("msk port %c at %s", 1372 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1373 else 1374 aprint_normal(" port %c", 1375 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1376 return UNCONF; 1377 } 1378 1379 /* 1380 * Attach the interface. Allocate softc structures, do ifmedia 1381 * setup and ethernet/BPF attach. 1382 */ 1383 static void 1384 mskc_attach(device_t parent, device_t self, void *aux) 1385 { 1386 struct sk_softc *sc = device_private(self); 1387 struct pci_attach_args *pa = aux; 1388 struct skc_attach_args skca; 1389 pci_chipset_tag_t pc = pa->pa_pc; 1390 pcireg_t command, memtype; 1391 const char *intrstr = NULL; 1392 int rc, sk_nodenum; 1393 uint8_t hw, pmd; 1394 const char *revstr = NULL; 1395 const struct sysctlnode *node; 1396 void *kva; 1397 char intrbuf[PCI_INTRSTR_LEN]; 1398 1399 DPRINTFN(2, ("begin mskc_attach\n")); 1400 1401 sc->sk_dev = self; 1402 /* 1403 * Handle power management nonsense. 1404 */ 1405 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1406 1407 if (command == 0x01) { 1408 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1409 if (command & SK_PSTATE_MASK) { 1410 uint32_t iobase, membase, irq; 1411 1412 /* Save important PCI config data. */ 1413 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1414 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1415 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1416 1417 /* Reset the power state. */ 1418 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1419 "mode -- setting to D0\n", 1420 command & SK_PSTATE_MASK); 1421 command &= 0xFFFFFFFC; 1422 pci_conf_write(pc, pa->pa_tag, 1423 SK_PCI_PWRMGMTCTRL, command); 1424 1425 /* Restore PCI config data. */ 1426 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1427 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1428 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1429 } 1430 } 1431 1432 /* 1433 * Map control/status registers. 1434 */ 1435 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1436 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1437 &sc->sk_bhandle, NULL, &sc->sk_bsize)) { 1438 aprint_error(": can't map mem space\n"); 1439 return; 1440 } 1441 1442 if (pci_dma64_available(pa)) 1443 sc->sc_dmatag = pa->pa_dmat64; 1444 else 1445 sc->sc_dmatag = pa->pa_dmat; 1446 1447 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1448 command |= PCI_COMMAND_MASTER_ENABLE; 1449 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1450 1451 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1452 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1453 1454 /* bail out here if chip is not recognized */ 1455 if (!(SK_IS_YUKON2(sc))) { 1456 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1457 goto fail_1; 1458 } 1459 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1460 1461 /* Allocate interrupt */ 1462 if (pci_intr_alloc(pa, &sc->sk_pihp, NULL, 0)) { 1463 aprint_error(": couldn't map interrupt\n"); 1464 goto fail_1; 1465 } 1466 1467 intrstr = pci_intr_string(pc, sc->sk_pihp[0], intrbuf, sizeof(intrbuf)); 1468 sc->sk_intrhand = pci_intr_establish_xname(pc, sc->sk_pihp[0], IPL_NET, 1469 msk_intr, sc, device_xname(sc->sk_dev)); 1470 if (sc->sk_intrhand == NULL) { 1471 aprint_error(": couldn't establish interrupt"); 1472 if (intrstr != NULL) 1473 aprint_error(" at %s", intrstr); 1474 aprint_error("\n"); 1475 goto fail_1; 1476 } 1477 sc->sk_pc = pc; 1478 1479 if (bus_dmamem_alloc(sc->sc_dmatag, 1480 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1481 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1482 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, BUS_DMA_NOWAIT)) { 1483 aprint_error(": can't alloc status buffers\n"); 1484 goto fail_2; 1485 } 1486 1487 if (bus_dmamem_map(sc->sc_dmatag, 1488 &sc->sk_status_seg, sc->sk_status_nseg, 1489 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1490 &kva, BUS_DMA_NOWAIT)) { 1491 aprint_error(": can't map dma buffers (%zu bytes)\n", 1492 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1493 goto fail_3; 1494 } 1495 if (bus_dmamap_create(sc->sc_dmatag, 1496 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1497 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1498 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1499 aprint_error(": can't create dma map\n"); 1500 goto fail_4; 1501 } 1502 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1503 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1504 NULL, BUS_DMA_NOWAIT)) { 1505 aprint_error(": can't load dma map\n"); 1506 goto fail_5; 1507 } 1508 sc->sk_status_ring = (struct msk_status_desc *)kva; 1509 1510 sc->sk_int_mod = SK_IM_DEFAULT; 1511 sc->sk_int_mod_pending = 0; 1512 1513 /* Reset the adapter. */ 1514 mskc_reset(sc); 1515 1516 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1517 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1518 1519 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1520 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1521 sc->sk_fibertype = 1; 1522 1523 switch (sc->sk_type) { 1524 case SK_YUKON_XL: 1525 sc->sk_name = "Yukon-2 XL"; 1526 break; 1527 case SK_YUKON_EC_U: 1528 sc->sk_name = "Yukon-2 EC Ultra"; 1529 break; 1530 case SK_YUKON_EX: 1531 sc->sk_name = "Yukon-2 Extreme"; 1532 break; 1533 case SK_YUKON_EC: 1534 sc->sk_name = "Yukon-2 EC"; 1535 break; 1536 case SK_YUKON_FE: 1537 sc->sk_name = "Yukon-2 FE"; 1538 break; 1539 case SK_YUKON_FE_P: 1540 sc->sk_name = "Yukon-2 FE+"; 1541 break; 1542 case SK_YUKON_SUPR: 1543 sc->sk_name = "Yukon-2 Supreme"; 1544 break; 1545 case SK_YUKON_ULTRA2: 1546 sc->sk_name = "Yukon-2 Ultra 2"; 1547 break; 1548 case SK_YUKON_OPTIMA: 1549 sc->sk_name = "Yukon-2 Optima"; 1550 break; 1551 case SK_YUKON_PRM: 1552 sc->sk_name = "Yukon-2 Optima Prime"; 1553 break; 1554 case SK_YUKON_OPTIMA2: 1555 sc->sk_name = "Yukon-2 Optima 2"; 1556 break; 1557 default: 1558 sc->sk_name = "Yukon (Unknown)"; 1559 } 1560 1561 if (sc->sk_type == SK_YUKON_XL) { 1562 switch (sc->sk_rev) { 1563 case SK_YUKON_XL_REV_A0: 1564 revstr = "A0"; 1565 break; 1566 case SK_YUKON_XL_REV_A1: 1567 revstr = "A1"; 1568 break; 1569 case SK_YUKON_XL_REV_A2: 1570 revstr = "A2"; 1571 break; 1572 case SK_YUKON_XL_REV_A3: 1573 revstr = "A3"; 1574 break; 1575 default: 1576 break; 1577 } 1578 } 1579 1580 if (sc->sk_type == SK_YUKON_EC) { 1581 switch (sc->sk_rev) { 1582 case SK_YUKON_EC_REV_A1: 1583 revstr = "A1"; 1584 break; 1585 case SK_YUKON_EC_REV_A2: 1586 revstr = "A2"; 1587 break; 1588 case SK_YUKON_EC_REV_A3: 1589 revstr = "A3"; 1590 break; 1591 default: 1592 break; 1593 } 1594 } 1595 1596 if (sc->sk_type == SK_YUKON_FE) { 1597 switch (sc->sk_rev) { 1598 case SK_YUKON_FE_REV_A1: 1599 revstr = "A1"; 1600 break; 1601 case SK_YUKON_FE_REV_A2: 1602 revstr = "A2"; 1603 break; 1604 default: 1605 break; 1606 } 1607 } 1608 1609 if (sc->sk_type == SK_YUKON_EC_U) { 1610 switch (sc->sk_rev) { 1611 case SK_YUKON_EC_U_REV_A0: 1612 revstr = "A0"; 1613 break; 1614 case SK_YUKON_EC_U_REV_A1: 1615 revstr = "A1"; 1616 break; 1617 case SK_YUKON_EC_U_REV_B0: 1618 revstr = "B0"; 1619 break; 1620 case SK_YUKON_EC_U_REV_B1: 1621 revstr = "B1"; 1622 break; 1623 default: 1624 break; 1625 } 1626 } 1627 1628 if (sc->sk_type == SK_YUKON_FE) { 1629 switch (sc->sk_rev) { 1630 case SK_YUKON_FE_REV_A1: 1631 revstr = "A1"; 1632 break; 1633 case SK_YUKON_FE_REV_A2: 1634 revstr = "A2"; 1635 break; 1636 default: 1637 ; 1638 } 1639 } 1640 1641 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1642 revstr = "A0"; 1643 1644 if (sc->sk_type == SK_YUKON_EX) { 1645 switch (sc->sk_rev) { 1646 case SK_YUKON_EX_REV_A0: 1647 revstr = "A0"; 1648 break; 1649 case SK_YUKON_EX_REV_B0: 1650 revstr = "B0"; 1651 break; 1652 default: 1653 ; 1654 } 1655 } 1656 1657 if (sc->sk_type == SK_YUKON_SUPR) { 1658 switch (sc->sk_rev) { 1659 case SK_YUKON_SUPR_REV_A0: 1660 revstr = "A0"; 1661 break; 1662 case SK_YUKON_SUPR_REV_B0: 1663 revstr = "B0"; 1664 break; 1665 case SK_YUKON_SUPR_REV_B1: 1666 revstr = "B1"; 1667 break; 1668 default: 1669 ; 1670 } 1671 } 1672 1673 if (sc->sk_type == SK_YUKON_PRM) { 1674 switch (sc->sk_rev) { 1675 case SK_YUKON_PRM_REV_Z1: 1676 revstr = "Z1"; 1677 break; 1678 case SK_YUKON_PRM_REV_A0: 1679 revstr = "A0"; 1680 break; 1681 default: 1682 ; 1683 } 1684 } 1685 1686 /* Announce the product name. */ 1687 aprint_normal(", %s", sc->sk_name); 1688 if (revstr != NULL) 1689 aprint_normal(" rev. %s", revstr); 1690 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1691 1692 sc->sk_macs = 1; 1693 1694 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1695 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1696 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1697 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1698 sc->sk_macs++; 1699 } 1700 1701 skca.skc_port = SK_PORT_A; 1702 skca.skc_type = sc->sk_type; 1703 skca.skc_rev = sc->sk_rev; 1704 (void)config_found(sc->sk_dev, &skca, mskcprint); 1705 1706 if (sc->sk_macs > 1) { 1707 skca.skc_port = SK_PORT_B; 1708 skca.skc_type = sc->sk_type; 1709 skca.skc_rev = sc->sk_rev; 1710 (void)config_found(sc->sk_dev, &skca, mskcprint); 1711 } 1712 1713 /* Turn on the 'driver is loaded' LED. */ 1714 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1715 1716 /* skc sysctl setup */ 1717 1718 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1719 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1720 SYSCTL_DESCR("mskc per-controller controls"), 1721 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1722 CTL_EOL)) != 0) { 1723 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1724 goto fail_6; 1725 } 1726 1727 sk_nodenum = node->sysctl_num; 1728 1729 /* interrupt moderation time in usecs */ 1730 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1731 CTLFLAG_READWRITE, 1732 CTLTYPE_INT, "int_mod", 1733 SYSCTL_DESCR("msk interrupt moderation timer"), 1734 msk_sysctl_handler, 0, (void *)sc, 1735 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1736 CTL_EOL)) != 0) { 1737 aprint_normal_dev(sc->sk_dev, 1738 "couldn't create int_mod sysctl node\n"); 1739 goto fail_6; 1740 } 1741 1742 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1743 aprint_error_dev(self, "couldn't establish power handler\n"); 1744 1745 return; 1746 1747 fail_6: 1748 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1749 fail_4: 1750 bus_dmamem_unmap(sc->sc_dmatag, kva, 1751 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1752 fail_3: 1753 bus_dmamem_free(sc->sc_dmatag, 1754 &sc->sk_status_seg, sc->sk_status_nseg); 1755 sc->sk_status_nseg = 0; 1756 fail_5: 1757 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1758 fail_2: 1759 pci_intr_disestablish(pc, sc->sk_intrhand); 1760 sc->sk_intrhand = NULL; 1761 fail_1: 1762 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1763 sc->sk_bsize = 0; 1764 } 1765 1766 static int 1767 mskc_detach(device_t self, int flags) 1768 { 1769 struct sk_softc *sc = device_private(self); 1770 int rv; 1771 1772 if (sc->sk_intrhand) { 1773 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1774 sc->sk_intrhand = NULL; 1775 } 1776 1777 if (sc->sk_pihp != NULL) { 1778 pci_intr_release(sc->sk_pc, sc->sk_pihp, 1); 1779 sc->sk_pihp = NULL; 1780 } 1781 1782 rv = config_detach_children(self, flags); 1783 if (rv != 0) 1784 return rv; 1785 1786 if (sc->sk_status_nseg > 0) { 1787 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1788 bus_dmamem_unmap(sc->sc_dmatag, sc->sk_status_ring, 1789 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1790 bus_dmamem_free(sc->sc_dmatag, 1791 &sc->sk_status_seg, sc->sk_status_nseg); 1792 } 1793 1794 if (sc->sk_bsize > 0) 1795 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1796 1797 return 0; 1798 } 1799 1800 static int 1801 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1802 { 1803 struct sk_softc *sc = sc_if->sk_softc; 1804 struct msk_tx_desc *f = NULL; 1805 uint32_t frag, cur, hiaddr, old_hiaddr, total; 1806 uint32_t entries = 0; 1807 size_t i; 1808 struct sk_txmap_entry *entry; 1809 bus_dmamap_t txmap; 1810 bus_addr_t addr; 1811 1812 DPRINTFN(2, ("msk_encap\n")); 1813 1814 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1815 if (entry == NULL) { 1816 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1817 return ENOBUFS; 1818 } 1819 txmap = entry->dmamap; 1820 1821 cur = frag = *txidx; 1822 1823 #ifdef MSK_DEBUG 1824 if (mskdebug >= 2) 1825 msk_dump_mbuf(m_head); 1826 #endif 1827 1828 /* 1829 * Start packing the mbufs in this chain into 1830 * the fragment pointers. Stop when we run out 1831 * of fragments or hit the end of the mbuf chain. 1832 */ 1833 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1834 BUS_DMA_NOWAIT)) { 1835 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1836 return ENOBUFS; 1837 } 1838 1839 /* Count how many tx descriptors needed. */ 1840 hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1841 for (total = i = 0; i < txmap->dm_nsegs; i++) { 1842 if (hiaddr != MSK_ADDR_HI(txmap->dm_segs[i].ds_addr)) { 1843 hiaddr = MSK_ADDR_HI(txmap->dm_segs[i].ds_addr); 1844 total++; 1845 } 1846 total++; 1847 } 1848 1849 if (total > MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2) { 1850 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1851 bus_dmamap_unload(sc->sc_dmatag, txmap); 1852 return ENOBUFS; 1853 } 1854 1855 DPRINTFN(2, ("msk_encap: dm_nsegs=%d total desc=%u\n", 1856 txmap->dm_nsegs, total)); 1857 1858 /* Sync the DMA map. */ 1859 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1860 BUS_DMASYNC_PREWRITE); 1861 1862 old_hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1863 for (i = 0; i < txmap->dm_nsegs; i++) { 1864 addr = txmap->dm_segs[i].ds_addr; 1865 DPRINTFN(2, ("msk_encap: addr %llx\n", 1866 (unsigned long long)addr)); 1867 hiaddr = MSK_ADDR_HI(addr); 1868 1869 if (sc_if->sk_cdata.sk_tx_hiaddr != hiaddr) { 1870 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1871 f->sk_addr = htole32(hiaddr); 1872 f->sk_len = 0; 1873 f->sk_ctl = 0; 1874 if (i == 0) 1875 f->sk_opcode = SK_Y2_BMUOPC_ADDR64; 1876 else 1877 f->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 1878 sc_if->sk_cdata.sk_tx_hiaddr = hiaddr; 1879 SK_INC(frag, MSK_TX_RING_CNT); 1880 entries++; 1881 DPRINTFN(10, ("%s: tx ADDR64: %#x\n", 1882 sc_if->sk_ethercom.ec_if.if_xname, hiaddr)); 1883 } 1884 1885 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1886 f->sk_addr = htole32(MSK_ADDR_LO(addr)); 1887 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1888 f->sk_ctl = 0; 1889 if (i == 0) { 1890 if (hiaddr != old_hiaddr) 1891 f->sk_opcode = SK_Y2_TXOPC_PACKET | SK_Y2_TXOPC_OWN; 1892 else 1893 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1894 } else 1895 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1896 cur = frag; 1897 SK_INC(frag, MSK_TX_RING_CNT); 1898 entries++; 1899 } 1900 KASSERTMSG(entries == total, "entries %u total %u", entries, total); 1901 1902 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1903 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1904 1905 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1906 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1907 1908 /* Sync descriptors before handing to chip */ 1909 MSK_CDTXSYNC(sc_if, *txidx, entries, 1910 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1911 1912 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1913 1914 /* Sync first descriptor to hand it off */ 1915 MSK_CDTXSYNC(sc_if, *txidx, 1, 1916 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1917 1918 sc_if->sk_cdata.sk_tx_cnt += entries; 1919 1920 #ifdef MSK_DEBUG 1921 if (mskdebug >= 2) { 1922 struct msk_tx_desc *le; 1923 uint32_t idx; 1924 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1925 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1926 msk_dump_txdesc(le, idx); 1927 } 1928 } 1929 #endif 1930 1931 *txidx = frag; 1932 1933 DPRINTFN(2, ("msk_encap: successful: %u entries\n", entries)); 1934 1935 return 0; 1936 } 1937 1938 static void 1939 msk_start(struct ifnet *ifp) 1940 { 1941 struct sk_if_softc *sc_if = ifp->if_softc; 1942 struct mbuf *m_head = NULL; 1943 uint32_t idx = sc_if->sk_cdata.sk_tx_prod; 1944 int pkts = 0; 1945 1946 DPRINTFN(2, ("msk_start\n")); 1947 1948 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1949 IFQ_POLL(&ifp->if_snd, m_head); 1950 if (m_head == NULL) 1951 break; 1952 1953 /* 1954 * Pack the data into the transmit ring. If we 1955 * don't have room, set the OACTIVE flag and wait 1956 * for the NIC to drain the ring. 1957 */ 1958 if (msk_encap(sc_if, m_head, &idx)) { 1959 ifp->if_flags |= IFF_OACTIVE; 1960 break; 1961 } 1962 1963 /* now we are committed to transmit the packet */ 1964 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1965 pkts++; 1966 1967 /* 1968 * If there's a BPF listener, bounce a copy of this frame 1969 * to him. 1970 */ 1971 bpf_mtap(ifp, m_head, BPF_D_OUT); 1972 } 1973 if (pkts == 0) 1974 return; 1975 1976 /* Transmit */ 1977 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1978 sc_if->sk_cdata.sk_tx_prod = idx; 1979 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1980 1981 /* Set a timeout in case the chip goes out to lunch. */ 1982 ifp->if_timer = 5; 1983 } 1984 } 1985 1986 static void 1987 msk_watchdog(struct ifnet *ifp) 1988 { 1989 struct sk_if_softc *sc_if = ifp->if_softc; 1990 1991 /* 1992 * Reclaim first as there is a possibility of losing Tx completion 1993 * interrupts. 1994 */ 1995 msk_txeof(sc_if); 1996 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1997 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1998 1999 if_statinc(ifp, if_oerrors); 2000 2001 /* XXX Resets both ports; we shouldn't do that. */ 2002 mskc_reset(sc_if->sk_softc); 2003 msk_reset(sc_if); 2004 msk_init(ifp); 2005 } 2006 } 2007 2008 static bool 2009 mskc_suspend(device_t dv, const pmf_qual_t *qual) 2010 { 2011 struct sk_softc *sc = device_private(dv); 2012 2013 DPRINTFN(2, ("mskc_suspend\n")); 2014 2015 /* Turn off the 'driver is loaded' LED. */ 2016 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2017 2018 return true; 2019 } 2020 2021 static bool 2022 mskc_resume(device_t dv, const pmf_qual_t *qual) 2023 { 2024 struct sk_softc *sc = device_private(dv); 2025 2026 DPRINTFN(2, ("mskc_resume\n")); 2027 2028 mskc_reset(sc); 2029 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 2030 2031 return true; 2032 } 2033 2034 static __inline int 2035 msk_rxvalid(struct sk_softc *sc, uint32_t stat, uint32_t len) 2036 { 2037 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 2038 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 2039 YU_RXSTAT_JABBER)) != 0 || 2040 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 2041 YU_RXSTAT_BYTES(stat) != len) 2042 return 0; 2043 2044 return 1; 2045 } 2046 2047 static void 2048 msk_rxeof(struct sk_if_softc *sc_if, uint16_t len, uint32_t rxstat) 2049 { 2050 struct sk_softc *sc = sc_if->sk_softc; 2051 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2052 struct mbuf *m; 2053 unsigned cur, prod, tail, total_len = len; 2054 bus_dmamap_t dmamap; 2055 2056 cur = sc_if->sk_cdata.sk_rx_cons; 2057 prod = sc_if->sk_cdata.sk_rx_prod; 2058 2059 /* Sync the descriptor */ 2060 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2061 2062 DPRINTFN(2, ("msk_rxeof: cur %u prod %u rx_cnt %u\n", cur, prod, 2063 sc_if->sk_cdata.sk_rx_cnt)); 2064 2065 while (prod != cur) { 2066 tail = cur; 2067 SK_INC(cur, MSK_RX_RING_CNT); 2068 2069 sc_if->sk_cdata.sk_rx_cnt--; 2070 m = sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf; 2071 sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf = NULL; 2072 if (m != NULL) 2073 break; /* found it */ 2074 } 2075 sc_if->sk_cdata.sk_rx_cons = cur; 2076 DPRINTFN(2, ("msk_rxeof: cur %u rx_cnt %u m %p\n", cur, 2077 sc_if->sk_cdata.sk_rx_cnt, m)); 2078 2079 if (m == NULL) 2080 return; 2081 2082 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2083 2084 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2085 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2086 2087 if (total_len < SK_MIN_FRAMELEN || 2088 total_len > ETHER_MAX_LEN_JUMBO || 2089 msk_rxvalid(sc, rxstat, total_len) == 0) { 2090 if_statinc(ifp, if_ierrors); 2091 m_freem(m); 2092 return; 2093 } 2094 2095 m_set_rcvif(m, ifp); 2096 m->m_pkthdr.len = m->m_len = total_len; 2097 2098 /* pass it on. */ 2099 if_percpuq_enqueue(ifp->if_percpuq, m); 2100 } 2101 2102 static void 2103 msk_txeof(struct sk_if_softc *sc_if) 2104 { 2105 struct sk_softc *sc = sc_if->sk_softc; 2106 struct msk_tx_desc *cur_tx; 2107 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2108 uint32_t idx, reg, sk_ctl; 2109 struct sk_txmap_entry *entry; 2110 2111 DPRINTFN(2, ("msk_txeof\n")); 2112 2113 if (sc_if->sk_port == SK_PORT_A) 2114 reg = SK_STAT_BMU_TXA1_RIDX; 2115 else 2116 reg = SK_STAT_BMU_TXA2_RIDX; 2117 2118 /* 2119 * Go through our tx ring and free mbufs for those 2120 * frames that have been sent. 2121 */ 2122 idx = sc_if->sk_cdata.sk_tx_cons; 2123 while (idx != sk_win_read_2(sc, reg)) { 2124 MSK_CDTXSYNC(sc_if, idx, 1, 2125 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2126 2127 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2128 sk_ctl = cur_tx->sk_ctl; 2129 #ifdef MSK_DEBUG 2130 if (mskdebug >= 2) 2131 msk_dump_txdesc(cur_tx, idx); 2132 #endif 2133 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 2134 if_statinc(ifp, if_opackets); 2135 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2136 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2137 2138 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2139 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2140 2141 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2142 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2143 link); 2144 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2145 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2146 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2147 } 2148 sc_if->sk_cdata.sk_tx_cnt--; 2149 SK_INC(idx, MSK_TX_RING_CNT); 2150 } 2151 if (idx == sc_if->sk_cdata.sk_tx_cons) 2152 return; 2153 2154 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2155 2156 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 2157 ifp->if_flags &= ~IFF_OACTIVE; 2158 2159 sc_if->sk_cdata.sk_tx_cons = idx; 2160 } 2161 2162 static void 2163 msk_fill_rx_ring(struct sk_if_softc *sc_if) 2164 { 2165 /* Make sure to not completely wrap around */ 2166 while (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT - 1)) { 2167 if (msk_newbuf(sc_if, 2168 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 2169 goto schedretry; 2170 } 2171 } 2172 2173 return; 2174 2175 schedretry: 2176 /* Try later */ 2177 callout_schedule(&sc_if->sk_tick_rx, hz/2); 2178 } 2179 2180 static void 2181 msk_fill_rx_tick(void *xsc_if) 2182 { 2183 struct sk_if_softc *sc_if = xsc_if; 2184 int s, rx_prod; 2185 2186 KASSERT(KERNEL_LOCKED_P()); /* XXXSMP */ 2187 2188 s = splnet(); 2189 rx_prod = sc_if->sk_cdata.sk_rx_prod; 2190 msk_fill_rx_ring(sc_if); 2191 if (rx_prod != sc_if->sk_cdata.sk_rx_prod) { 2192 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2193 sc_if->sk_cdata.sk_rx_prod); 2194 } 2195 splx(s); 2196 } 2197 2198 static void 2199 msk_tick(void *xsc_if) 2200 { 2201 struct sk_if_softc *sc_if = xsc_if; 2202 struct mii_data *mii = &sc_if->sk_mii; 2203 int s; 2204 2205 s = splnet(); 2206 mii_tick(mii); 2207 splx(s); 2208 2209 callout_schedule(&sc_if->sk_tick_ch, hz); 2210 } 2211 2212 static void 2213 msk_intr_yukon(struct sk_if_softc *sc_if) 2214 { 2215 uint8_t status; 2216 2217 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2218 /* RX overrun */ 2219 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2220 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2221 SK_RFCTL_RX_FIFO_OVER); 2222 } 2223 /* TX underrun */ 2224 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2225 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 2226 SK_TFCTL_TX_FIFO_UNDER); 2227 } 2228 2229 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 2230 } 2231 2232 static int 2233 msk_intr(void *xsc) 2234 { 2235 struct sk_softc *sc = xsc; 2236 struct sk_if_softc *sc_if; 2237 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2238 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2239 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2240 int claimed = 0; 2241 uint32_t status; 2242 struct msk_status_desc *cur_st; 2243 2244 status = CSR_READ_4(sc, SK_Y2_ISSR2); 2245 if (status == 0xffffffff) 2246 return 0; 2247 if (status == 0) { 2248 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2249 return 0; 2250 } 2251 2252 status = CSR_READ_4(sc, SK_ISR); 2253 2254 if (sc_if0 != NULL) 2255 ifp0 = &sc_if0->sk_ethercom.ec_if; 2256 if (sc_if1 != NULL) 2257 ifp1 = &sc_if1->sk_ethercom.ec_if; 2258 2259 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 2260 (ifp0->if_flags & IFF_RUNNING)) { 2261 msk_intr_yukon(sc_if0); 2262 } 2263 2264 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 2265 (ifp1->if_flags & IFF_RUNNING)) { 2266 msk_intr_yukon(sc_if1); 2267 } 2268 2269 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2270 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2271 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2272 2273 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 2274 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 2275 switch (cur_st->sk_opcode) { 2276 case SK_Y2_STOPC_RXSTAT: 2277 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 2278 if (sc_if) { 2279 msk_rxeof(sc_if, letoh16(cur_st->sk_len), 2280 letoh32(cur_st->sk_status)); 2281 if (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 2282 msk_fill_rx_tick(sc_if); 2283 } 2284 break; 2285 case SK_Y2_STOPC_TXSTAT: 2286 if (sc_if0) 2287 msk_txeof(sc_if0); 2288 if (sc_if1) 2289 msk_txeof(sc_if1); 2290 break; 2291 default: 2292 aprint_error("opcode=0x%x\n", cur_st->sk_opcode); 2293 break; 2294 } 2295 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 2296 2297 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2298 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2299 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2300 } 2301 2302 if (status & SK_Y2_IMR_BMU) { 2303 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 2304 claimed = 1; 2305 } 2306 2307 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2308 2309 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2310 if_schedule_deferred_start(ifp0); 2311 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2312 if_schedule_deferred_start(ifp1); 2313 2314 KASSERT(sc->rnd_attached > 0); 2315 rnd_add_uint32(&sc->rnd_source, status); 2316 2317 if (sc->sk_int_mod_pending) 2318 msk_update_int_mod(sc, 1); 2319 2320 return claimed; 2321 } 2322 2323 static void 2324 msk_init_yukon(struct sk_if_softc *sc_if) 2325 { 2326 uint32_t v; 2327 uint16_t reg; 2328 struct sk_softc *sc; 2329 int i; 2330 2331 sc = sc_if->sk_softc; 2332 2333 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 2334 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2335 2336 DPRINTFN(6, ("msk_init_yukon: 1\n")); 2337 2338 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 2339 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2340 2341 DPRINTFN(6, ("msk_init_yukon: 3\n")); 2342 2343 /* unused read of the interrupt source register */ 2344 DPRINTFN(6, ("msk_init_yukon: 4\n")); 2345 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2346 2347 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2348 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2349 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2350 2351 /* MIB Counter Clear Mode set */ 2352 reg |= YU_PAR_MIB_CLR; 2353 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2354 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2355 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2356 2357 /* MIB Counter Clear Mode clear */ 2358 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2359 reg &= ~YU_PAR_MIB_CLR; 2360 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2361 2362 /* receive control reg */ 2363 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2364 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2365 2366 /* transmit control register */ 2367 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2368 2369 /* transmit flow control register */ 2370 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2371 2372 /* transmit parameter register */ 2373 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2374 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2375 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2376 2377 /* serial mode register */ 2378 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2379 reg = YU_SMR_DATA_BLIND(0x1c) | 2380 YU_SMR_MFL_VLAN | 2381 YU_SMR_IPG_DATA(0x1e); 2382 2383 if (sc->sk_type != SK_YUKON_FE && 2384 sc->sk_type != SK_YUKON_FE_P) 2385 reg |= YU_SMR_MFL_JUMBO; 2386 2387 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2388 2389 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2390 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2391 /* msk_attach calls me before ether_ifattach so check null */ 2392 if (ifp != NULL && ifp->if_sadl != NULL) 2393 memcpy(sc_if->sk_enaddr, CLLADDR(ifp->if_sadl), 2394 sizeof(sc_if->sk_enaddr)); 2395 /* Setup Yukon's address */ 2396 for (i = 0; i < 3; i++) { 2397 /* Write Source Address 1 (unicast filter) */ 2398 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2399 sc_if->sk_enaddr[i * 2] | 2400 sc_if->sk_enaddr[i * 2 + 1] << 8); 2401 } 2402 2403 for (i = 0; i < 3; i++) { 2404 reg = sk_win_read_2(sc_if->sk_softc, 2405 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2406 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2407 } 2408 2409 /* Set promiscuous mode */ 2410 msk_setpromisc(sc_if); 2411 2412 /* Set multicast filter */ 2413 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2414 msk_setmulti(sc_if); 2415 2416 /* enable interrupt mask for counter overflows */ 2417 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2418 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2419 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2420 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2421 2422 /* Configure RX MAC FIFO Flush Mask */ 2423 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2424 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2425 YU_RXSTAT_JABBER; 2426 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2427 2428 /* Configure RX MAC FIFO */ 2429 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2430 v = SK_RFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 2431 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_FE_P)) 2432 v |= SK_RFCTL_RX_OVER_ON; 2433 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 2434 2435 if ((sc->sk_type == SK_YUKON_FE_P) && 2436 (sc->sk_rev == SK_YUKON_FE_P_REV_A0)) 2437 v = 0x178; /* Magic value */ 2438 else { 2439 /* Increase flush threshold to 64 bytes */ 2440 v = SK_RFCTL_FIFO_THRESHOLD + 1; 2441 } 2442 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, v); 2443 2444 /* Configure TX MAC FIFO */ 2445 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2446 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2447 2448 if ((sc->sk_type == SK_YUKON_FE_P) && 2449 (sc->sk_rev == SK_YUKON_FE_P_REV_A0)) { 2450 v = SK_IF_READ_2(sc_if, 0, SK_TXMF1_END); 2451 v &= ~SK_TXEND_WM_ON; 2452 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_END, v); 2453 } 2454 2455 #if 1 2456 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2457 #endif 2458 DPRINTFN(6, ("msk_init_yukon: end\n")); 2459 } 2460 2461 /* 2462 * Note that to properly initialize any part of the GEnesis chip, 2463 * you first have to take it out of reset mode. 2464 */ 2465 static int 2466 msk_init(struct ifnet *ifp) 2467 { 2468 struct sk_if_softc *sc_if = ifp->if_softc; 2469 struct sk_softc *sc = sc_if->sk_softc; 2470 int rc = 0, s; 2471 uint32_t imr, imtimer_ticks; 2472 2473 2474 DPRINTFN(2, ("msk_init\n")); 2475 2476 s = splnet(); 2477 2478 /* Cancel pending I/O and free all RX/TX buffers. */ 2479 msk_stop(ifp, 1); 2480 2481 /* Configure I2C registers */ 2482 2483 /* Configure XMAC(s) */ 2484 msk_init_yukon(sc_if); 2485 if ((rc = ether_mediachange(ifp)) != 0) 2486 goto out; 2487 2488 /* Configure transmit arbiter(s) */ 2489 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2490 #if 0 2491 /* SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); */ 2492 #endif 2493 2494 if (sc->sk_ramsize) { 2495 /* Configure RAMbuffers */ 2496 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2497 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2498 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2499 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2500 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2501 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2502 2503 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2504 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2505 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2506 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2507 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2508 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2509 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2510 } 2511 2512 /* Configure BMUs */ 2513 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2514 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2515 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2516 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2517 2518 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2519 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2520 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2521 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2522 2523 /* Make sure the sync transmit queue is disabled. */ 2524 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2525 2526 /* Init descriptors */ 2527 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2528 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2529 "memory for rx buffers\n"); 2530 msk_stop(ifp, 1); 2531 splx(s); 2532 return ENOBUFS; 2533 } 2534 2535 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2536 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2537 "memory for tx buffers\n"); 2538 msk_stop(ifp, 1); 2539 splx(s); 2540 return ENOBUFS; 2541 } 2542 2543 /* Set interrupt moderation if changed via sysctl. */ 2544 switch (sc->sk_type) { 2545 case SK_YUKON_EC: 2546 case SK_YUKON_EC_U: 2547 case SK_YUKON_EX: 2548 case SK_YUKON_SUPR: 2549 case SK_YUKON_ULTRA2: 2550 case SK_YUKON_OPTIMA: 2551 case SK_YUKON_PRM: 2552 case SK_YUKON_OPTIMA2: 2553 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2554 break; 2555 case SK_YUKON_FE: 2556 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2557 break; 2558 case SK_YUKON_FE_P: 2559 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 2560 break; 2561 case SK_YUKON_XL: 2562 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2563 break; 2564 default: 2565 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2566 } 2567 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2568 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2569 sk_win_write_4(sc, SK_IMTIMERINIT, 2570 SK_IM_USECS(sc->sk_int_mod)); 2571 aprint_verbose_dev(sc->sk_dev, 2572 "interrupt moderation is %d us\n", sc->sk_int_mod); 2573 } 2574 2575 /* Initialize prefetch engine. */ 2576 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2577 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2578 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2579 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2580 MSK_RX_RING_ADDR(sc_if, 0)); 2581 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2582 (uint64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2583 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2584 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2585 2586 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2587 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2588 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2589 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2590 MSK_TX_RING_ADDR(sc_if, 0)); 2591 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2592 (uint64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2593 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2594 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2595 2596 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2597 sc_if->sk_cdata.sk_rx_prod); 2598 2599 2600 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_SUPR)) { 2601 /* Disable flushing of non-ASF packets. */ 2602 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, 2603 SK_RFCTL_RX_MACSEC_FLUSH_OFF); 2604 } 2605 2606 /* Configure interrupt handling */ 2607 if (sc_if->sk_port == SK_PORT_A) 2608 sc->sk_intrmask |= SK_Y2_INTRS1; 2609 else 2610 sc->sk_intrmask |= SK_Y2_INTRS2; 2611 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2612 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2613 2614 ifp->if_flags |= IFF_RUNNING; 2615 ifp->if_flags &= ~IFF_OACTIVE; 2616 2617 callout_schedule(&sc_if->sk_tick_ch, hz); 2618 2619 out: 2620 splx(s); 2621 return rc; 2622 } 2623 2624 /* 2625 * Note: the logic of second parameter is inverted compared to OpenBSD 2626 * code, since this code uses the function as if_stop hook too. 2627 */ 2628 static void 2629 msk_stop(struct ifnet *ifp, int disable) 2630 { 2631 struct sk_if_softc *sc_if = ifp->if_softc; 2632 struct sk_softc *sc = sc_if->sk_softc; 2633 struct sk_txmap_entry *dma; 2634 int i; 2635 2636 DPRINTFN(2, ("msk_stop\n")); 2637 2638 callout_stop(&sc_if->sk_tick_ch); 2639 callout_stop(&sc_if->sk_tick_rx); 2640 2641 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2642 2643 /* Stop transfer of Tx descriptors */ 2644 2645 /* Stop transfer of Rx descriptors */ 2646 2647 if (disable) { 2648 /* Turn off various components of this interface. */ 2649 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2650 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2651 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2652 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2653 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2654 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2655 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2656 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2657 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2658 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2659 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2660 2661 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2662 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2663 2664 /* Disable interrupts */ 2665 if (sc_if->sk_port == SK_PORT_A) 2666 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2667 else 2668 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2669 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2670 } 2671 2672 /* Free RX and TX mbufs still in the queues. */ 2673 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2674 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2675 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2676 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2677 } 2678 } 2679 2680 sc_if->sk_cdata.sk_rx_prod = 0; 2681 sc_if->sk_cdata.sk_rx_cons = 0; 2682 sc_if->sk_cdata.sk_rx_cnt = 0; 2683 2684 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2685 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2686 dma = sc_if->sk_cdata.sk_tx_map[i]; 2687 2688 bus_dmamap_sync(sc->sc_dmatag, dma->dmamap, 0, 2689 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2690 2691 bus_dmamap_unload(sc->sc_dmatag, dma->dmamap); 2692 2693 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2694 sc_if->sk_cdata.sk_tx_map[i], link); 2695 sc_if->sk_cdata.sk_tx_map[i] = 0; 2696 2697 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2698 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2699 } 2700 } 2701 } 2702 2703 CFATTACH_DECL3_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2704 mskc_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2705 2706 CFATTACH_DECL3_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2707 msk_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2708 2709 #ifdef MSK_DEBUG 2710 static void 2711 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2712 { 2713 #define DESC_PRINT(X) \ 2714 if (X) \ 2715 printf("txdesc[%d]." #X "=%#x\n", \ 2716 idx, X); 2717 2718 DESC_PRINT(letoh32(le->sk_addr)); 2719 DESC_PRINT(letoh16(le->sk_len)); 2720 DESC_PRINT(le->sk_ctl); 2721 DESC_PRINT(le->sk_opcode); 2722 #undef DESC_PRINT 2723 } 2724 2725 static void 2726 msk_dump_bytes(const char *data, int len) 2727 { 2728 int c, i, j; 2729 2730 for (i = 0; i < len; i += 16) { 2731 printf("%08x ", i); 2732 c = len - i; 2733 if (c > 16) c = 16; 2734 2735 for (j = 0; j < c; j++) { 2736 printf("%02x ", data[i + j] & 0xff); 2737 if ((j & 0xf) == 7 && j > 0) 2738 printf(" "); 2739 } 2740 2741 for (; j < 16; j++) 2742 printf(" "); 2743 printf(" "); 2744 2745 for (j = 0; j < c; j++) { 2746 int ch = data[i + j] & 0xff; 2747 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2748 } 2749 2750 printf("\n"); 2751 2752 if (c < 16) 2753 break; 2754 } 2755 } 2756 2757 static void 2758 msk_dump_mbuf(struct mbuf *m) 2759 { 2760 int count = m->m_pkthdr.len; 2761 2762 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2763 2764 while (count > 0 && m) { 2765 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2766 m, m->m_data, m->m_len); 2767 if (mskdebug >= 4) 2768 msk_dump_bytes(mtod(m, char *), m->m_len); 2769 2770 count -= m->m_len; 2771 m = m->m_next; 2772 } 2773 } 2774 #endif 2775 2776 static int 2777 msk_sysctl_handler(SYSCTLFN_ARGS) 2778 { 2779 int error, t; 2780 struct sysctlnode node; 2781 struct sk_softc *sc; 2782 2783 node = *rnode; 2784 sc = node.sysctl_data; 2785 t = sc->sk_int_mod; 2786 node.sysctl_data = &t; 2787 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2788 if (error || newp == NULL) 2789 return error; 2790 2791 if (t < SK_IM_MIN || t > SK_IM_MAX) 2792 return EINVAL; 2793 2794 /* update the softc with sysctl-changed value, and mark 2795 for hardware update */ 2796 sc->sk_int_mod = t; 2797 sc->sk_int_mod_pending = 1; 2798 return 0; 2799 } 2800 2801 /* 2802 * Set up sysctl(3) MIB, hw.msk.* - Individual controllers will be 2803 * set up in mskc_attach() 2804 */ 2805 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2806 { 2807 int rc; 2808 const struct sysctlnode *node; 2809 2810 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2811 0, CTLTYPE_NODE, "msk", 2812 SYSCTL_DESCR("msk interface controls"), 2813 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2814 goto err; 2815 } 2816 2817 msk_root_num = node->sysctl_num; 2818 return; 2819 2820 err: 2821 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2822 } 2823
Indexes created Wed Sep 24 05:09:52 GMT 2025