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if_mskvar.h revision 1.12.16.5
      1        1.2   msaitoh /*	$OpenBSD: if_mskvar.h,v 1.3 2006/12/28 16:34:42 kettenis Exp $	*/
      2  1.12.16.5  pgoyette /*	$NetBSD: if_mskvar.h,v 1.12.16.5 2019/01/18 08:50:27 pgoyette Exp $	*/
      3        1.1       riz 
      4        1.1       riz /*-
      5        1.1       riz  * Copyright (c) 2003 The NetBSD Foundation, Inc.
      6        1.1       riz  * All rights reserved.
      7        1.1       riz  *
      8        1.1       riz  * Redistribution and use in source and binary forms, with or without
      9        1.1       riz  * modification, are permitted provided that the following conditions
     10        1.1       riz  * are met:
     11        1.1       riz  * 1. Redistributions of source code must retain the above copyright
     12        1.1       riz  *    notice, this list of conditions and the following disclaimer.
     13        1.1       riz  * 2. Redistributions in binary form must reproduce the above copyright
     14        1.1       riz  *    notice, this list of conditions and the following disclaimer in the
     15        1.1       riz  *    documentation and/or other materials provided with the distribution.
     16        1.1       riz  *
     17        1.1       riz  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     18        1.1       riz  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     19        1.1       riz  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     20        1.1       riz  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     21        1.1       riz  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     22        1.1       riz  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     23        1.1       riz  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     24        1.1       riz  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     25        1.1       riz  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     26        1.1       riz  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     27        1.1       riz  * POSSIBILITY OF SUCH DAMAGE.
     28        1.1       riz  */
     29        1.1       riz /*	$OpenBSD: if_mskvar.h,v 1.1 2006/08/16 21:06:23 kettenis Exp $	*/
     30        1.1       riz 
     31        1.1       riz /*
     32        1.1       riz  * Copyright (c) 1997, 1998, 1999, 2000
     33        1.1       riz  *	Bill Paul <wpaul (at) ctr.columbia.edu>.  All rights reserved.
     34        1.1       riz  *
     35        1.1       riz  * Redistribution and use in source and binary forms, with or without
     36        1.1       riz  * modification, are permitted provided that the following conditions
     37        1.1       riz  * are met:
     38        1.1       riz  * 1. Redistributions of source code must retain the above copyright
     39        1.1       riz  *    notice, this list of conditions and the following disclaimer.
     40        1.1       riz  * 2. Redistributions in binary form must reproduce the above copyright
     41        1.1       riz  *    notice, this list of conditions and the following disclaimer in the
     42        1.1       riz  *    documentation and/or other materials provided with the distribution.
     43        1.1       riz  * 3. All advertising materials mentioning features or use of this software
     44        1.1       riz  *    must display the following acknowledgement:
     45        1.1       riz  *	This product includes software developed by Bill Paul.
     46        1.1       riz  * 4. Neither the name of the author nor the names of any co-contributors
     47        1.1       riz  *    may be used to endorse or promote products derived from this software
     48        1.1       riz  *    without specific prior written permission.
     49        1.1       riz  *
     50        1.1       riz  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
     51        1.1       riz  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     52        1.1       riz  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     53        1.1       riz  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
     54        1.1       riz  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     55        1.1       riz  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     56        1.1       riz  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     57        1.1       riz  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     58        1.1       riz  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     59        1.1       riz  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
     60        1.1       riz  * THE POSSIBILITY OF SUCH DAMAGE.
     61        1.1       riz  *
     62        1.1       riz  * $FreeBSD: /c/ncvs/src/sys/pci/if_skreg.h,v 1.9 2000/04/22 02:16:37 wpaul Exp $
     63        1.1       riz  */
     64        1.1       riz 
     65        1.1       riz /*
     66        1.1       riz  * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu>
     67        1.1       riz  *
     68        1.1       riz  * Permission to use, copy, modify, and distribute this software for any
     69        1.1       riz  * purpose with or without fee is hereby granted, provided that the above
     70        1.1       riz  * copyright notice and this permission notice appear in all copies.
     71        1.1       riz  *
     72        1.1       riz  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
     73        1.1       riz  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
     74        1.1       riz  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
     75        1.1       riz  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
     76        1.1       riz  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
     77        1.1       riz  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
     78        1.1       riz  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
     79        1.1       riz  */
     80        1.1       riz 
     81        1.1       riz #ifndef _DEV_PCI_IF_MSKVAR_H_
     82        1.1       riz #define _DEV_PCI_IF_MSKVAR_H_
     83        1.1       riz 
     84       1.12  riastrad #include <sys/rndsource.h>
     85        1.1       riz 
     86        1.1       riz struct sk_jpool_entry {
     87        1.1       riz 	int                             slot;
     88        1.1       riz 	LIST_ENTRY(sk_jpool_entry)	jpool_entries;
     89        1.1       riz };
     90        1.1       riz 
     91        1.1       riz struct sk_chain {
     92        1.1       riz 	void			*sk_le;
     93        1.1       riz 	struct mbuf		*sk_mbuf;
     94        1.1       riz 	struct sk_chain		*sk_next;
     95        1.1       riz };
     96        1.1       riz 
     97        1.1       riz /*
     98        1.1       riz  * Number of DMA segments in a TxCB. Note that this is carefully
     99        1.1       riz  * chosen to make the total struct size an even power of two. It's
    100        1.1       riz  * critical that no TxCB be split across a page boundary since
    101        1.1       riz  * no attempt is made to allocate physically contiguous memory.
    102        1.1       riz  *
    103        1.1       riz  */
    104        1.1       riz #define SK_NTXSEG      30
    105        1.1       riz 
    106        1.1       riz struct sk_txmap_entry {
    107        1.1       riz 	bus_dmamap_t			dmamap;
    108        1.1       riz 	SIMPLEQ_ENTRY(sk_txmap_entry)	link;
    109        1.1       riz };
    110        1.1       riz 
    111        1.1       riz struct msk_chain_data {
    112        1.1       riz 	struct sk_chain		sk_tx_chain[MSK_TX_RING_CNT];
    113        1.1       riz 	struct sk_chain		sk_rx_chain[MSK_RX_RING_CNT];
    114        1.1       riz 	struct sk_txmap_entry	*sk_tx_map[MSK_TX_RING_CNT];
    115        1.1       riz 	bus_dmamap_t		sk_rx_map[MSK_RX_RING_CNT];
    116        1.1       riz 	bus_dmamap_t		sk_rx_jumbo_map;
    117  1.12.16.3  pgoyette 	unsigned		sk_tx_prod;
    118  1.12.16.3  pgoyette 	unsigned		sk_tx_cons;
    119  1.12.16.3  pgoyette 	unsigned		sk_tx_cnt;
    120  1.12.16.3  pgoyette 	u_int32_t		sk_tx_hiaddr;
    121  1.12.16.3  pgoyette 	unsigned		sk_rx_prod;
    122  1.12.16.3  pgoyette 	unsigned		sk_rx_cons;
    123  1.12.16.3  pgoyette 	unsigned		sk_rx_cnt;
    124  1.12.16.3  pgoyette 	u_int32_t		sk_rx_hiaddr;
    125        1.1       riz 	/* Stick the jumbo mem management stuff here too. */
    126        1.4  christos 	void *			sk_jslots[MSK_JSLOTS];
    127        1.1       riz 	void			*sk_jumbo_buf;
    128  1.12.16.2  pgoyette 	bus_dma_segment_t	sk_jumbo_seg;
    129  1.12.16.2  pgoyette 	int			sk_jumbo_nseg;
    130        1.1       riz };
    131        1.1       riz 
    132        1.1       riz struct msk_ring_data {
    133        1.1       riz 	struct msk_tx_desc	sk_tx_ring[MSK_TX_RING_CNT];
    134        1.1       riz 	struct msk_rx_desc	sk_rx_ring[MSK_RX_RING_CNT];
    135        1.1       riz };
    136        1.1       riz 
    137        1.1       riz #define MSK_TX_RING_ADDR(sc, i) \
    138        1.1       riz     ((sc)->sk_ring_map->dm_segs[0].ds_addr + \
    139        1.1       riz      offsetof(struct msk_ring_data, sk_tx_ring[(i)]))
    140        1.1       riz 
    141        1.1       riz #define MSK_RX_RING_ADDR(sc, i) \
    142        1.1       riz     ((sc)->sk_ring_map->dm_segs[0].ds_addr + \
    143        1.1       riz      offsetof(struct msk_ring_data, sk_rx_ring[(i)]))
    144        1.1       riz 
    145        1.1       riz #define MSK_CDOFF(x)	offsetof(struct msk_ring_data, x)
    146        1.1       riz #define MSK_CDTXOFF(x)	MSK_CDOFF(sk_tx_ring[(x)])
    147        1.1       riz #define MSK_CDRXOFF(x)	MSK_CDOFF(sk_rx_ring[(x)])
    148        1.1       riz #define MSK_CDSTOFF(x)	((x) * sizeof(struct msk_status_desc))
    149        1.1       riz 
    150        1.1       riz #define MSK_CDTXSYNC(sc, x, n, ops)					\
    151        1.1       riz do {									\
    152        1.1       riz 	int __x, __n;							\
    153        1.1       riz 									\
    154        1.1       riz 	__x = (x);							\
    155        1.1       riz 	__n = (n);							\
    156        1.1       riz 									\
    157        1.1       riz 	/* If it will wrap around, sync to the end of the ring. */	\
    158        1.1       riz 	if ((__x + __n) > MSK_TX_RING_CNT) {				\
    159        1.1       riz 		bus_dmamap_sync((sc)->sk_softc->sc_dmatag,		\
    160        1.1       riz 		    (sc)->sk_ring_map, MSK_CDTXOFF(__x),		\
    161        1.1       riz 		    sizeof(struct msk_tx_desc) * (MSK_TX_RING_CNT - __x), \
    162        1.1       riz 		    (ops));						\
    163        1.1       riz 		__n -= (MSK_TX_RING_CNT - __x);				\
    164        1.1       riz 		__x = 0;						\
    165        1.1       riz 	}								\
    166        1.1       riz 									\
    167        1.1       riz 	/* Now sync whatever is left. */				\
    168        1.1       riz 	bus_dmamap_sync((sc)->sk_softc->sc_dmatag, (sc)->sk_ring_map,	\
    169        1.1       riz 	    MSK_CDTXOFF((__x)), sizeof(struct msk_tx_desc) * __n, (ops)); \
    170        1.1       riz } while (/*CONSTCOND*/0)
    171        1.1       riz 
    172        1.1       riz #define MSK_CDRXSYNC(sc, x, ops)					\
    173        1.1       riz do {									\
    174        1.1       riz 	bus_dmamap_sync((sc)->sk_softc->sc_dmatag, (sc)->sk_ring_map,	\
    175        1.1       riz 	    MSK_CDRXOFF((x)), sizeof(struct msk_rx_desc), (ops));	\
    176        1.1       riz } while (/*CONSTCOND*/0)
    177        1.1       riz 
    178        1.1       riz #define MSK_CDSTSYNC(sc, x, ops)					\
    179        1.1       riz do {									\
    180        1.1       riz 	bus_dmamap_sync((sc)->sc_dmatag, (sc)->sk_status_map,		\
    181        1.1       riz 	    MSK_CDSTOFF((x)), sizeof(struct msk_status_desc), (ops));	\
    182        1.1       riz } while (/*CONSTCOND*/0)
    183        1.1       riz 
    184        1.1       riz #define SK_INC(x, y)	(x) = (x + 1) % y
    185        1.1       riz 
    186        1.1       riz /* Forward decl. */
    187        1.1       riz struct sk_if_softc;
    188        1.1       riz 
    189        1.1       riz /* Softc for the Yukon-II controller. */
    190        1.1       riz struct sk_softc {
    191       1.11   msaitoh 	device_t		sk_dev;
    192        1.1       riz 	bus_space_handle_t	sk_bhandle;	/* bus space handle */
    193        1.1       riz 	bus_space_tag_t		sk_btag;	/* bus space tag */
    194  1.12.16.1  pgoyette 	bus_size_t		sk_bsize;	/* bus space size */
    195        1.1       riz 	void			*sk_intrhand;	/* irq handler handle */
    196  1.12.16.4  pgoyette 	pci_intr_handle_t	*sk_pihp;
    197  1.12.16.1  pgoyette 	pci_chipset_tag_t	sk_pc;
    198  1.12.16.1  pgoyette 	u_int8_t		sk_fibertype;
    199        1.1       riz 	u_int8_t		sk_type;
    200        1.1       riz 	u_int8_t		sk_rev;
    201        1.1       riz 	u_int8_t		sk_macs;	/* # of MACs */
    202        1.1       riz 	const char		*sk_name;
    203        1.1       riz 	u_int32_t		sk_ramsize;	/* amount of RAM on NIC */
    204        1.1       riz 	u_int32_t		sk_intrmask;
    205        1.1       riz 	struct sysctllog	*sk_clog;
    206        1.1       riz 	int			sk_int_mod;
    207        1.1       riz 	int			sk_int_mod_pending;
    208        1.1       riz 	bus_dma_tag_t		sc_dmatag;
    209        1.1       riz 	struct sk_if_softc	*sk_if[2];
    210        1.1       riz 	struct msk_status_desc	*sk_status_ring;
    211        1.1       riz 	bus_dmamap_t		sk_status_map;
    212  1.12.16.1  pgoyette 	bus_dma_segment_t	sk_status_seg;
    213  1.12.16.1  pgoyette 	int			sk_status_nseg;
    214        1.1       riz 	int			sk_status_idx;
    215        1.5  kiyohara 	int			sk_status_own_idx;
    216  1.12.16.2  pgoyette 	u_int8_t		rnd_attached;
    217  1.12.16.2  pgoyette 	krndsource_t		rnd_source;
    218        1.1       riz };
    219        1.1       riz 
    220        1.1       riz /* Softc for each logical interface */
    221        1.1       riz struct sk_if_softc {
    222       1.11   msaitoh 	device_t		sk_dev;
    223        1.1       riz 	struct ethercom		sk_ethercom;	/* interface info */
    224        1.1       riz 	struct mii_data		sk_mii;
    225        1.1       riz 	u_int8_t		sk_enaddr[ETHER_ADDR_LEN]; /* station addr */
    226        1.1       riz 	u_int8_t		sk_port;	/* port # on controller */
    227        1.1       riz 	u_int32_t		sk_rx_ramstart;
    228        1.1       riz 	u_int32_t		sk_rx_ramend;
    229        1.1       riz 	u_int32_t		sk_tx_ramstart;
    230        1.1       riz 	u_int32_t		sk_tx_ramend;
    231  1.12.16.2  pgoyette 	int			sk_pktlen;	/* XXX set but unused for now */
    232        1.1       riz 	int			sk_link;
    233        1.1       riz 	struct callout		sk_tick_ch;
    234  1.12.16.2  pgoyette 	struct callout		sk_tick_rx;
    235        1.1       riz 	struct msk_chain_data	sk_cdata;
    236        1.1       riz 	struct msk_ring_data	*sk_rdata;
    237        1.1       riz 	bus_dmamap_t		sk_ring_map;
    238  1.12.16.1  pgoyette 	bus_dma_segment_t	sk_ring_seg;
    239  1.12.16.1  pgoyette 	int			sk_ring_nseg;
    240        1.1       riz 	int			sk_status_idx;
    241        1.1       riz 	struct sk_softc		*sk_softc;	/* parent controller */
    242        1.1       riz 	int			sk_if_flags;
    243        1.7      cube 	kmutex_t		sk_jpool_mtx;
    244        1.1       riz 	LIST_HEAD(__sk_jfreehead, sk_jpool_entry)	sk_jfree_listhead;
    245        1.1       riz 	LIST_HEAD(__sk_jinusehead, sk_jpool_entry)	sk_jinuse_listhead;
    246        1.1       riz 	SIMPLEQ_HEAD(__sk_txmaphead, sk_txmap_entry)	sk_txmap_head;
    247        1.1       riz };
    248        1.1       riz 
    249        1.1       riz struct skc_attach_args {
    250        1.1       riz 	u_int16_t	skc_port;
    251        1.1       riz 	u_int8_t	skc_type;
    252        1.1       riz 	u_int8_t	skc_rev;
    253        1.1       riz };
    254        1.1       riz 
    255        1.1       riz #endif /* _DEV_PCI_IF_MSKVAR_H_ */
    256