if_nfe.c revision 1.11
1 /* $NetBSD: if_nfe.c,v 1.11 2007/01/01 04:13:25 tsutsui Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.52 2006/03/02 09:04:00 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.11 2007/01/01 04:13:25 tsutsui Exp $"); 25 26 #include "opt_inet.h" 27 #include "bpfilter.h" 28 #include "vlan.h" 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/types.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/queue.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/socket.h> 41 42 #include <machine/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/pci/if_nfereg.h> 74 #include <dev/pci/if_nfevar.h> 75 76 int nfe_match(struct device *, struct cfdata *, void *); 77 void nfe_attach(struct device *, struct device *, void *); 78 void nfe_power(int, void *); 79 void nfe_miibus_statchg(struct device *); 80 int nfe_miibus_readreg(struct device *, int, int); 81 void nfe_miibus_writereg(struct device *, int, int, int); 82 int nfe_intr(void *); 83 int nfe_ioctl(struct ifnet *, u_long, caddr_t); 84 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 85 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 86 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 87 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 88 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 89 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 90 void nfe_rxeof(struct nfe_softc *); 91 void nfe_txeof(struct nfe_softc *); 92 int nfe_encap(struct nfe_softc *, struct mbuf *); 93 void nfe_start(struct ifnet *); 94 void nfe_watchdog(struct ifnet *); 95 int nfe_init(struct ifnet *); 96 void nfe_stop(struct ifnet *, int); 97 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *); 98 void nfe_jfree(struct mbuf *, caddr_t, size_t, void *); 99 int nfe_jpool_alloc(struct nfe_softc *); 100 void nfe_jpool_free(struct nfe_softc *); 101 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 102 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 105 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 int nfe_ifmedia_upd(struct ifnet *); 108 void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 109 void nfe_setmulti(struct nfe_softc *); 110 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 111 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 112 void nfe_tick(void *); 113 114 CFATTACH_DECL(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, NULL, NULL); 115 116 /*#define NFE_NO_JUMBO*/ 117 118 #ifdef NFE_DEBUG 119 int nfedebug = 0; 120 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 121 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 122 #else 123 #define DPRINTF(x) 124 #define DPRINTFN(n,x) 125 #endif 126 127 /* deal with naming differences */ 128 129 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 130 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 134 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 135 136 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 137 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 140 141 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 142 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 145 146 #ifdef _LP64 147 #define __LP64__ 1 148 #endif 149 150 const struct nfe_product { 151 pci_vendor_id_t vendor; 152 pci_product_id_t product; 153 } nfe_devices[] = { 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 155 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 } 177 }; 178 179 int 180 nfe_match(struct device *dev, struct cfdata *match, void *aux) 181 { 182 struct pci_attach_args *pa = aux; 183 const struct nfe_product *np; 184 int i; 185 186 for (i = 0; i < sizeof(nfe_devices) / sizeof(nfe_devices[0]); i++) { 187 np = &nfe_devices[i]; 188 if (PCI_VENDOR(pa->pa_id) == np->vendor && 189 PCI_PRODUCT(pa->pa_id) == np->product) 190 return 1; 191 } 192 return 0; 193 } 194 195 void 196 nfe_attach(struct device *parent, struct device *self, void *aux) 197 { 198 struct nfe_softc *sc = (struct nfe_softc *)self; 199 struct pci_attach_args *pa = aux; 200 pci_chipset_tag_t pc = pa->pa_pc; 201 pci_intr_handle_t ih; 202 const char *intrstr; 203 struct ifnet *ifp; 204 bus_size_t memsize; 205 pcireg_t memtype; 206 char devinfo[256]; 207 208 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 209 aprint_normal(": %s (rev. 0x%02x)\n", 210 devinfo, PCI_REVISION(pa->pa_class)); 211 212 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 213 switch (memtype) { 214 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 215 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 216 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 217 &sc->sc_memh, NULL, &memsize) == 0) 218 break; 219 /* FALLTHROUGH */ 220 default: 221 printf("%s: could not map mem space\n", sc->sc_dev.dv_xname); 222 return; 223 } 224 225 if (pci_intr_map(pa, &ih) != 0) { 226 printf("%s: could not map interrupt\n", sc->sc_dev.dv_xname); 227 return; 228 } 229 230 intrstr = pci_intr_string(pc, ih); 231 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 232 if (sc->sc_ih == NULL) { 233 printf("%s: could not establish interrupt", 234 sc->sc_dev.dv_xname); 235 if (intrstr != NULL) 236 printf(" at %s", intrstr); 237 printf("\n"); 238 return; 239 } 240 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 241 242 sc->sc_dmat = pa->pa_dmat; 243 244 nfe_get_macaddr(sc, sc->sc_enaddr); 245 printf("%s: Ethernet address %s\n", 246 sc->sc_dev.dv_xname, ether_sprintf(sc->sc_enaddr)); 247 248 sc->sc_flags = 0; 249 250 switch (PCI_PRODUCT(pa->pa_id)) { 251 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 252 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 253 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 254 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 255 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 256 break; 257 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 258 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 259 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 260 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 261 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 262 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 263 sc->sc_flags |= NFE_40BIT_ADDR; 264 break; 265 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 266 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 267 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 268 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 269 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 270 break; 271 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 272 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 273 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 274 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 275 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 276 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 277 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 278 NFE_HW_VLAN; 279 break; 280 } 281 282 #ifndef NFE_NO_JUMBO 283 /* enable jumbo frames for adapters that support it */ 284 if (sc->sc_flags & NFE_JUMBO_SUP) 285 sc->sc_flags |= NFE_USE_JUMBO; 286 #endif 287 288 /* 289 * Allocate Tx and Rx rings. 290 */ 291 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 292 printf("%s: could not allocate Tx ring\n", 293 sc->sc_dev.dv_xname); 294 return; 295 } 296 297 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 298 printf("%s: could not allocate Rx ring\n", 299 sc->sc_dev.dv_xname); 300 nfe_free_tx_ring(sc, &sc->txq); 301 return; 302 } 303 304 ifp = &sc->sc_ethercom.ec_if; 305 ifp->if_softc = sc; 306 ifp->if_mtu = ETHERMTU; 307 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 308 ifp->if_ioctl = nfe_ioctl; 309 ifp->if_start = nfe_start; 310 ifp->if_watchdog = nfe_watchdog; 311 ifp->if_init = nfe_init; 312 ifp->if_baudrate = IF_Gbps(1); 313 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 314 IFQ_SET_READY(&ifp->if_snd); 315 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 316 317 #if NVLAN > 0 318 if (sc->sc_flags & NFE_HW_VLAN) 319 sc->sc_ethercom.ec_capabilities |= 320 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 321 #endif 322 #ifdef NFE_CSUM 323 if (sc->sc_flags & NFE_HW_CSUM) { 324 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 325 IFCAP_CSUM_UDPv4; 326 } 327 #endif 328 329 sc->sc_mii.mii_ifp = ifp; 330 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 331 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 332 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 333 334 ifmedia_init(&sc->sc_mii.mii_media, 0, nfe_ifmedia_upd, 335 nfe_ifmedia_sts); 336 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 337 MII_OFFSET_ANY, 0); 338 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 339 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 340 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 341 0, NULL); 342 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 343 } else 344 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 345 346 if_attach(ifp); 347 ether_ifattach(ifp, sc->sc_enaddr); 348 349 callout_init(&sc->sc_tick_ch); 350 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 351 352 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 353 nfe_power, sc); 354 } 355 356 void 357 nfe_power(int why, void *arg) 358 { 359 struct nfe_softc *sc = arg; 360 struct ifnet *ifp; 361 362 if (why == PWR_RESUME) { 363 ifp = &sc->sc_ethercom.ec_if; 364 if (ifp->if_flags & IFF_UP) { 365 ifp->if_flags &= ~IFF_RUNNING; 366 nfe_init(ifp); 367 if (ifp->if_flags & IFF_RUNNING) 368 nfe_start(ifp); 369 } 370 } 371 } 372 373 void 374 nfe_miibus_statchg(struct device *dev) 375 { 376 struct nfe_softc *sc = (struct nfe_softc *)dev; 377 struct mii_data *mii = &sc->sc_mii; 378 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 379 380 phy = NFE_READ(sc, NFE_PHY_IFACE); 381 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 382 383 seed = NFE_READ(sc, NFE_RNDSEED); 384 seed &= ~NFE_SEED_MASK; 385 386 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 387 phy |= NFE_PHY_HDX; /* half-duplex */ 388 misc |= NFE_MISC1_HDX; 389 } 390 391 switch (IFM_SUBTYPE(mii->mii_media_active)) { 392 case IFM_1000_T: /* full-duplex only */ 393 link |= NFE_MEDIA_1000T; 394 seed |= NFE_SEED_1000T; 395 phy |= NFE_PHY_1000T; 396 break; 397 case IFM_100_TX: 398 link |= NFE_MEDIA_100TX; 399 seed |= NFE_SEED_100TX; 400 phy |= NFE_PHY_100TX; 401 break; 402 case IFM_10_T: 403 link |= NFE_MEDIA_10T; 404 seed |= NFE_SEED_10T; 405 break; 406 } 407 408 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 409 410 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 411 NFE_WRITE(sc, NFE_MISC1, misc); 412 NFE_WRITE(sc, NFE_LINKSPEED, link); 413 } 414 415 int 416 nfe_miibus_readreg(struct device *dev, int phy, int reg) 417 { 418 struct nfe_softc *sc = (struct nfe_softc *)dev; 419 uint32_t val; 420 int ntries; 421 422 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 423 424 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 425 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 426 DELAY(100); 427 } 428 429 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 430 431 for (ntries = 0; ntries < 1000; ntries++) { 432 DELAY(100); 433 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 434 break; 435 } 436 if (ntries == 1000) { 437 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 438 sc->sc_dev.dv_xname)); 439 return 0; 440 } 441 442 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 443 DPRINTFN(2, ("%s: could not read PHY\n", 444 sc->sc_dev.dv_xname)); 445 return 0; 446 } 447 448 val = NFE_READ(sc, NFE_PHY_DATA); 449 if (val != 0xffffffff && val != 0) 450 sc->mii_phyaddr = phy; 451 452 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 453 sc->sc_dev.dv_xname, phy, reg, val)); 454 455 return val; 456 } 457 458 void 459 nfe_miibus_writereg(struct device *dev, int phy, int reg, int val) 460 { 461 struct nfe_softc *sc = (struct nfe_softc *)dev; 462 uint32_t ctl; 463 int ntries; 464 465 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 466 467 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 468 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 469 DELAY(100); 470 } 471 472 NFE_WRITE(sc, NFE_PHY_DATA, val); 473 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 474 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 475 476 for (ntries = 0; ntries < 1000; ntries++) { 477 DELAY(100); 478 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 479 break; 480 } 481 #ifdef NFE_DEBUG 482 if (nfedebug >= 2 && ntries == 1000) 483 printf("could not write to PHY\n"); 484 #endif 485 } 486 487 int 488 nfe_intr(void *arg) 489 { 490 struct nfe_softc *sc = arg; 491 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 492 uint32_t r; 493 494 if ((r = NFE_READ(sc, NFE_IRQ_STATUS)) == 0) 495 return 0; /* not for us */ 496 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 497 498 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 499 500 if (r & NFE_IRQ_LINK) { 501 NFE_READ(sc, NFE_PHY_STATUS); 502 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 503 DPRINTF(("%s: link state changed\n", sc->sc_dev.dv_xname)); 504 } 505 506 if (ifp->if_flags & IFF_RUNNING) { 507 /* check Rx ring */ 508 nfe_rxeof(sc); 509 510 /* check Tx ring */ 511 nfe_txeof(sc); 512 } 513 514 return 1; 515 } 516 517 int 518 nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 519 { 520 struct nfe_softc *sc = ifp->if_softc; 521 struct ifreq *ifr = (struct ifreq *)data; 522 struct ifaddr *ifa = (struct ifaddr *)data; 523 int s, error = 0; 524 525 s = splnet(); 526 527 switch (cmd) { 528 case SIOCSIFADDR: 529 ifp->if_flags |= IFF_UP; 530 nfe_init(ifp); 531 switch (ifa->ifa_addr->sa_family) { 532 #ifdef INET 533 case AF_INET: 534 arp_ifinit(ifp, ifa); 535 break; 536 #endif 537 default: 538 break; 539 } 540 break; 541 case SIOCSIFMTU: 542 if (ifr->ifr_mtu < ETHERMIN || 543 ((sc->sc_flags & NFE_USE_JUMBO) && 544 ifr->ifr_mtu > ETHERMTU_JUMBO) || 545 (!(sc->sc_flags & NFE_USE_JUMBO) && 546 ifr->ifr_mtu > ETHERMTU)) 547 error = EINVAL; 548 else if (ifp->if_mtu != ifr->ifr_mtu) 549 ifp->if_mtu = ifr->ifr_mtu; 550 break; 551 case SIOCSIFFLAGS: 552 if (ifp->if_flags & IFF_UP) { 553 /* 554 * If only the PROMISC or ALLMULTI flag changes, then 555 * don't do a full re-init of the chip, just update 556 * the Rx filter. 557 */ 558 if ((ifp->if_flags & IFF_RUNNING) && 559 ((ifp->if_flags ^ sc->sc_if_flags) & 560 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 561 nfe_setmulti(sc); 562 else 563 nfe_init(ifp); 564 } else { 565 if (ifp->if_flags & IFF_RUNNING) 566 nfe_stop(ifp, 1); 567 } 568 sc->sc_if_flags = ifp->if_flags; 569 break; 570 case SIOCADDMULTI: 571 case SIOCDELMULTI: 572 error = (cmd == SIOCADDMULTI) ? 573 ether_addmulti(ifr, &sc->sc_ethercom) : 574 ether_delmulti(ifr, &sc->sc_ethercom); 575 576 if (error == ENETRESET) { 577 if (ifp->if_flags & IFF_RUNNING) 578 nfe_setmulti(sc); 579 error = 0; 580 } 581 break; 582 case SIOCSIFMEDIA: 583 case SIOCGIFMEDIA: 584 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 585 break; 586 default: 587 error = ether_ioctl(ifp, cmd, data); 588 if (error == ENETRESET) { 589 if (ifp->if_flags & IFF_RUNNING) 590 nfe_setmulti(sc); 591 error = 0; 592 } 593 break; 594 595 } 596 597 splx(s); 598 599 return error; 600 } 601 602 void 603 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 604 { 605 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 606 (caddr_t)desc32 - (caddr_t)sc->txq.desc32, 607 sizeof (struct nfe_desc32), ops); 608 } 609 610 void 611 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 612 { 613 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 614 (caddr_t)desc64 - (caddr_t)sc->txq.desc64, 615 sizeof (struct nfe_desc64), ops); 616 } 617 618 void 619 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 620 { 621 if (end > start) { 622 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 623 (caddr_t)&sc->txq.desc32[start] - (caddr_t)sc->txq.desc32, 624 (caddr_t)&sc->txq.desc32[end] - 625 (caddr_t)&sc->txq.desc32[start], ops); 626 return; 627 } 628 /* sync from 'start' to end of ring */ 629 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 630 (caddr_t)&sc->txq.desc32[start] - (caddr_t)sc->txq.desc32, 631 (caddr_t)&sc->txq.desc32[NFE_TX_RING_COUNT] - 632 (caddr_t)&sc->txq.desc32[start], ops); 633 634 /* sync from start of ring to 'end' */ 635 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 636 (caddr_t)&sc->txq.desc32[end] - (caddr_t)sc->txq.desc32, ops); 637 } 638 639 void 640 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 641 { 642 if (end > start) { 643 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 644 (caddr_t)&sc->txq.desc64[start] - (caddr_t)sc->txq.desc64, 645 (caddr_t)&sc->txq.desc64[end] - 646 (caddr_t)&sc->txq.desc64[start], ops); 647 return; 648 } 649 /* sync from 'start' to end of ring */ 650 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 651 (caddr_t)&sc->txq.desc64[start] - (caddr_t)sc->txq.desc64, 652 (caddr_t)&sc->txq.desc64[NFE_TX_RING_COUNT] - 653 (caddr_t)&sc->txq.desc64[start], ops); 654 655 /* sync from start of ring to 'end' */ 656 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 657 (caddr_t)&sc->txq.desc64[end] - (caddr_t)sc->txq.desc64, ops); 658 } 659 660 void 661 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 662 { 663 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 664 (caddr_t)desc32 - (caddr_t)sc->rxq.desc32, 665 sizeof (struct nfe_desc32), ops); 666 } 667 668 void 669 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 670 { 671 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 672 (caddr_t)desc64 - (caddr_t)sc->rxq.desc64, 673 sizeof (struct nfe_desc64), ops); 674 } 675 676 void 677 nfe_rxeof(struct nfe_softc *sc) 678 { 679 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 680 struct nfe_desc32 *desc32; 681 struct nfe_desc64 *desc64; 682 struct nfe_rx_data *data; 683 struct nfe_jbuf *jbuf; 684 struct mbuf *m, *mnew; 685 bus_addr_t physaddr; 686 uint16_t flags; 687 int error, len; 688 689 desc32 = NULL; 690 desc64 = NULL; 691 for (;;) { 692 data = &sc->rxq.data[sc->rxq.cur]; 693 694 if (sc->sc_flags & NFE_40BIT_ADDR) { 695 desc64 = &sc->rxq.desc64[sc->rxq.cur]; 696 nfe_rxdesc64_sync(sc, desc64, BUS_DMASYNC_POSTREAD); 697 698 flags = le16toh(desc64->flags); 699 len = le16toh(desc64->length) & 0x3fff; 700 } else { 701 desc32 = &sc->rxq.desc32[sc->rxq.cur]; 702 nfe_rxdesc32_sync(sc, desc32, BUS_DMASYNC_POSTREAD); 703 704 flags = le16toh(desc32->flags); 705 len = le16toh(desc32->length) & 0x3fff; 706 } 707 708 if (flags & NFE_RX_READY) 709 break; 710 711 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 712 if (!(flags & NFE_RX_VALID_V1)) 713 goto skip; 714 715 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 716 flags &= ~NFE_RX_ERROR; 717 len--; /* fix buffer length */ 718 } 719 } else { 720 if (!(flags & NFE_RX_VALID_V2)) 721 goto skip; 722 723 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 724 flags &= ~NFE_RX_ERROR; 725 len--; /* fix buffer length */ 726 } 727 } 728 729 if (flags & NFE_RX_ERROR) { 730 ifp->if_ierrors++; 731 goto skip; 732 } 733 734 /* 735 * Try to allocate a new mbuf for this ring element and load 736 * it before processing the current mbuf. If the ring element 737 * cannot be loaded, drop the received packet and reuse the 738 * old mbuf. In the unlikely case that the old mbuf can't be 739 * reloaded either, explicitly panic. 740 */ 741 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 742 if (mnew == NULL) { 743 ifp->if_ierrors++; 744 goto skip; 745 } 746 747 if (sc->sc_flags & NFE_USE_JUMBO) { 748 if ((jbuf = nfe_jalloc(sc)) == NULL) { 749 m_freem(mnew); 750 ifp->if_ierrors++; 751 goto skip; 752 } 753 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 754 755 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 756 mtod(data->m, caddr_t) - sc->rxq.jpool, NFE_JBYTES, 757 BUS_DMASYNC_POSTREAD); 758 759 physaddr = jbuf->physaddr; 760 } else { 761 MCLGET(mnew, M_DONTWAIT); 762 if (!(mnew->m_flags & M_EXT)) { 763 m_freem(mnew); 764 ifp->if_ierrors++; 765 goto skip; 766 } 767 768 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 769 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 770 bus_dmamap_unload(sc->sc_dmat, data->map); 771 772 error = bus_dmamap_load(sc->sc_dmat, data->map, 773 mtod(mnew, void *), MCLBYTES, NULL, 774 BUS_DMA_READ | BUS_DMA_NOWAIT); 775 if (error != 0) { 776 m_freem(mnew); 777 778 /* try to reload the old mbuf */ 779 error = bus_dmamap_load(sc->sc_dmat, data->map, 780 mtod(data->m, void *), MCLBYTES, NULL, 781 BUS_DMA_READ | BUS_DMA_NOWAIT); 782 if (error != 0) { 783 /* very unlikely that it will fail.. */ 784 panic("%s: could not load old rx mbuf", 785 sc->sc_dev.dv_xname); 786 } 787 ifp->if_ierrors++; 788 goto skip; 789 } 790 physaddr = data->map->dm_segs[0].ds_addr; 791 } 792 793 /* 794 * New mbuf successfully loaded, update Rx ring and continue 795 * processing. 796 */ 797 m = data->m; 798 data->m = mnew; 799 800 /* finalize mbuf */ 801 m->m_pkthdr.len = m->m_len = len; 802 m->m_pkthdr.rcvif = ifp; 803 804 #ifdef notyet 805 if (sc->sc_flags & NFE_HW_CSUM) { 806 if (flags & NFE_RX_IP_CSUMOK) 807 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 808 if (flags & NFE_RX_UDP_CSUMOK) 809 m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK; 810 if (flags & NFE_RX_TCP_CSUMOK) 811 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK; 812 } 813 #elif defined(NFE_CSUM) 814 if ((sc->sc_flags & NFE_HW_CSUM) && (flags & NFE_RX_CSUMOK)) 815 m->m_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK; 816 #endif 817 818 #if NBPFILTER > 0 819 if (ifp->if_bpf) 820 bpf_mtap(ifp->if_bpf, m); 821 #endif 822 ifp->if_ipackets++; 823 (*ifp->if_input)(ifp, m); 824 825 /* update mapping address in h/w descriptor */ 826 if (sc->sc_flags & NFE_40BIT_ADDR) { 827 #if defined(__LP64__) 828 desc64->physaddr[0] = htole32(physaddr >> 32); 829 #endif 830 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 831 } else { 832 desc32->physaddr = htole32(physaddr); 833 } 834 835 skip: if (sc->sc_flags & NFE_40BIT_ADDR) { 836 desc64->length = htole16(sc->rxq.bufsz); 837 desc64->flags = htole16(NFE_RX_READY); 838 839 nfe_rxdesc64_sync(sc, desc64, BUS_DMASYNC_PREWRITE); 840 } else { 841 desc32->length = htole16(sc->rxq.bufsz); 842 desc32->flags = htole16(NFE_RX_READY); 843 844 nfe_rxdesc32_sync(sc, desc32, BUS_DMASYNC_PREWRITE); 845 } 846 847 sc->rxq.cur = (sc->rxq.cur + 1) % NFE_RX_RING_COUNT; 848 } 849 } 850 851 void 852 nfe_txeof(struct nfe_softc *sc) 853 { 854 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 855 struct nfe_desc32 *desc32; 856 struct nfe_desc64 *desc64; 857 struct nfe_tx_data *data = NULL; 858 uint16_t flags; 859 860 while (sc->txq.next != sc->txq.cur) { 861 if (sc->sc_flags & NFE_40BIT_ADDR) { 862 desc64 = &sc->txq.desc64[sc->txq.next]; 863 nfe_txdesc64_sync(sc, desc64, BUS_DMASYNC_POSTREAD); 864 865 flags = le16toh(desc64->flags); 866 } else { 867 desc32 = &sc->txq.desc32[sc->txq.next]; 868 nfe_txdesc32_sync(sc, desc32, BUS_DMASYNC_POSTREAD); 869 870 flags = le16toh(desc32->flags); 871 } 872 873 if (flags & NFE_TX_VALID) 874 break; 875 876 data = &sc->txq.data[sc->txq.next]; 877 878 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 879 if (!(flags & NFE_TX_LASTFRAG_V1) && data->m == NULL) 880 goto skip; 881 882 if ((flags & NFE_TX_ERROR_V1) != 0) { 883 printf("%s: tx v1 error 0x%04x\n", 884 sc->sc_dev.dv_xname, flags); 885 ifp->if_oerrors++; 886 } else 887 ifp->if_opackets++; 888 } else { 889 if (!(flags & NFE_TX_LASTFRAG_V2) && data->m == NULL) 890 goto skip; 891 892 if ((flags & NFE_TX_ERROR_V2) != 0) { 893 printf("%s: tx v2 error 0x%04x\n", 894 sc->sc_dev.dv_xname, flags); 895 ifp->if_oerrors++; 896 } else 897 ifp->if_opackets++; 898 } 899 900 if (data->m == NULL) { /* should not get there */ 901 printf("%s: last fragment bit w/o associated mbuf!\n", 902 sc->sc_dev.dv_xname); 903 goto skip; 904 } 905 906 /* last fragment of the mbuf chain transmitted */ 907 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 908 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 909 bus_dmamap_unload(sc->sc_dmat, data->active); 910 m_freem(data->m); 911 data->m = NULL; 912 913 ifp->if_timer = 0; 914 915 skip: sc->txq.queued--; 916 sc->txq.next = (sc->txq.next + 1) % NFE_TX_RING_COUNT; 917 } 918 919 if (data != NULL) { /* at least one slot freed */ 920 ifp->if_flags &= ~IFF_OACTIVE; 921 nfe_start(ifp); 922 } 923 } 924 925 int 926 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 927 { 928 struct nfe_desc32 *desc32; 929 struct nfe_desc64 *desc64; 930 struct nfe_tx_data *data; 931 bus_dmamap_t map; 932 uint16_t flags; 933 #if NVLAN > 0 934 struct m_tag *mtag; 935 uint32_t vtag = 0; 936 #endif 937 int error, i, first; 938 939 desc32 = NULL; 940 desc64 = NULL; 941 data = NULL; 942 943 flags = 0; 944 first = sc->txq.cur; 945 946 map = sc->txq.data[first].map; 947 948 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 949 if (error != 0) { 950 printf("%s: could not map mbuf (error %d)\n", 951 sc->sc_dev.dv_xname, error); 952 return error; 953 } 954 955 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 956 bus_dmamap_unload(sc->sc_dmat, map); 957 return ENOBUFS; 958 } 959 960 #if NVLAN > 0 961 /* setup h/w VLAN tagging */ 962 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 963 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 964 #endif 965 #ifdef NFE_CSUM 966 if (m0->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 967 flags |= NFE_TX_IP_CSUM; 968 if (m0->m_pkthdr.csum_flags & (M_TCPV4_CSUM_OUT | M_UDPV4_CSUM_OUT)) 969 flags |= NFE_TX_TCP_CSUM; 970 #endif 971 972 for (i = 0; i < map->dm_nsegs; i++) { 973 data = &sc->txq.data[sc->txq.cur]; 974 975 if (sc->sc_flags & NFE_40BIT_ADDR) { 976 desc64 = &sc->txq.desc64[sc->txq.cur]; 977 #if defined(__LP64__) 978 desc64->physaddr[0] = 979 htole32(map->dm_segs[i].ds_addr >> 32); 980 #endif 981 desc64->physaddr[1] = 982 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 983 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 984 desc64->flags = htole16(flags); 985 #if NVLAN > 0 986 desc64->vtag = htole32(vtag); 987 #endif 988 } else { 989 desc32 = &sc->txq.desc32[sc->txq.cur]; 990 991 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 992 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 993 desc32->flags = htole16(flags); 994 } 995 996 if (map->dm_nsegs > 1) { 997 /* 998 * Checksum flags and vtag belong to the first fragment 999 * only. 1000 */ 1001 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_CSUM); 1002 #if NVLAN > 0 1003 vtag = 0; 1004 #endif 1005 /* 1006 * Setting of the valid bit in the first descriptor is 1007 * deferred until the whole chain is fully setup. 1008 */ 1009 flags |= NFE_TX_VALID; 1010 } 1011 1012 sc->txq.queued++; 1013 sc->txq.cur = (sc->txq.cur + 1) % NFE_TX_RING_COUNT; 1014 } 1015 1016 /* the whole mbuf chain has been setup */ 1017 if (sc->sc_flags & NFE_40BIT_ADDR) { 1018 /* fix last descriptor */ 1019 flags |= NFE_TX_LASTFRAG_V2; 1020 desc64->flags = htole16(flags); 1021 1022 /* finally, set the valid bit in the first descriptor */ 1023 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1024 } else { 1025 /* fix last descriptor */ 1026 if (sc->sc_flags & NFE_JUMBO_SUP) 1027 flags |= NFE_TX_LASTFRAG_V2; 1028 else 1029 flags |= NFE_TX_LASTFRAG_V1; 1030 desc32->flags = htole16(flags); 1031 1032 /* finally, set the valid bit in the first descriptor */ 1033 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1034 } 1035 1036 data->m = m0; 1037 data->active = map; 1038 1039 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1040 BUS_DMASYNC_PREWRITE); 1041 1042 return 0; 1043 } 1044 1045 void 1046 nfe_start(struct ifnet *ifp) 1047 { 1048 struct nfe_softc *sc = ifp->if_softc; 1049 int old = sc->txq.cur; 1050 struct mbuf *m0; 1051 1052 for (;;) { 1053 IFQ_POLL(&ifp->if_snd, m0); 1054 if (m0 == NULL) 1055 break; 1056 1057 if (nfe_encap(sc, m0) != 0) { 1058 ifp->if_flags |= IFF_OACTIVE; 1059 break; 1060 } 1061 1062 /* packet put in h/w queue, remove from s/w queue */ 1063 IFQ_DEQUEUE(&ifp->if_snd, m0); 1064 1065 #if NBPFILTER > 0 1066 if (ifp->if_bpf != NULL) 1067 bpf_mtap(ifp->if_bpf, m0); 1068 #endif 1069 } 1070 if (sc->txq.cur == old) /* nothing sent */ 1071 return; 1072 1073 if (sc->sc_flags & NFE_40BIT_ADDR) 1074 nfe_txdesc64_rsync(sc, old, sc->txq.cur, BUS_DMASYNC_PREWRITE); 1075 else 1076 nfe_txdesc32_rsync(sc, old, sc->txq.cur, BUS_DMASYNC_PREWRITE); 1077 1078 /* kick Tx */ 1079 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1080 1081 /* 1082 * Set a timeout in case the chip goes out to lunch. 1083 */ 1084 ifp->if_timer = 5; 1085 } 1086 1087 void 1088 nfe_watchdog(struct ifnet *ifp) 1089 { 1090 struct nfe_softc *sc = ifp->if_softc; 1091 1092 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1093 1094 ifp->if_flags &= ~IFF_RUNNING; 1095 nfe_init(ifp); 1096 1097 ifp->if_oerrors++; 1098 } 1099 1100 int 1101 nfe_init(struct ifnet *ifp) 1102 { 1103 struct nfe_softc *sc = ifp->if_softc; 1104 uint32_t tmp; 1105 1106 if (ifp->if_flags & IFF_RUNNING) 1107 return 0; 1108 1109 nfe_stop(ifp, 0); 1110 1111 NFE_WRITE(sc, NFE_TX_UNK, 0); 1112 NFE_WRITE(sc, NFE_STATUS, 0); 1113 1114 sc->rxtxctl = NFE_RXTX_BIT2; 1115 if (sc->sc_flags & NFE_40BIT_ADDR) 1116 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1117 else if (sc->sc_flags & NFE_JUMBO_SUP) 1118 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1119 #ifdef NFE_CSUM 1120 if (sc->sc_flags & NFE_HW_CSUM) 1121 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1122 #endif 1123 #if NVLAN > 0 1124 /* 1125 * Although the adapter is capable of stripping VLAN tags from received 1126 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1127 * purpose. This will be done in software by our network stack. 1128 */ 1129 if (sc->sc_flags & NFE_HW_VLAN) 1130 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1131 #endif 1132 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1133 DELAY(10); 1134 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1135 1136 #if NVLAN 1137 if (sc->sc_flags & NFE_HW_VLAN) 1138 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1139 #endif 1140 1141 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1142 1143 /* set MAC address */ 1144 nfe_set_macaddr(sc, sc->sc_enaddr); 1145 1146 /* tell MAC where rings are in memory */ 1147 #ifdef __LP64__ 1148 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1149 #endif 1150 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1151 #ifdef __LP64__ 1152 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1153 #endif 1154 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1155 1156 NFE_WRITE(sc, NFE_RING_SIZE, 1157 (NFE_RX_RING_COUNT - 1) << 16 | 1158 (NFE_TX_RING_COUNT - 1)); 1159 1160 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1161 1162 /* force MAC to wakeup */ 1163 tmp = NFE_READ(sc, NFE_PWR_STATE); 1164 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1165 DELAY(10); 1166 tmp = NFE_READ(sc, NFE_PWR_STATE); 1167 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1168 1169 #if 1 1170 /* configure interrupts coalescing/mitigation */ 1171 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1172 #else 1173 /* no interrupt mitigation: one interrupt per packet */ 1174 NFE_WRITE(sc, NFE_IMTIMER, 970); 1175 #endif 1176 1177 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1178 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1179 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1180 1181 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1182 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1183 1184 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1185 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC); 1186 1187 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1188 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1189 DELAY(10); 1190 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1191 1192 /* set Rx filter */ 1193 nfe_setmulti(sc); 1194 1195 nfe_ifmedia_upd(ifp); 1196 1197 /* enable Rx */ 1198 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1199 1200 /* enable Tx */ 1201 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1202 1203 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1204 1205 /* enable interrupts */ 1206 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1207 1208 callout_schedule(&sc->sc_tick_ch, hz); 1209 1210 ifp->if_flags |= IFF_RUNNING; 1211 ifp->if_flags &= ~IFF_OACTIVE; 1212 1213 return 0; 1214 } 1215 1216 void 1217 nfe_stop(struct ifnet *ifp, int disable) 1218 { 1219 struct nfe_softc *sc = ifp->if_softc; 1220 1221 callout_stop(&sc->sc_tick_ch); 1222 1223 ifp->if_timer = 0; 1224 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1225 1226 mii_down(&sc->sc_mii); 1227 1228 /* abort Tx */ 1229 NFE_WRITE(sc, NFE_TX_CTL, 0); 1230 1231 /* disable Rx */ 1232 NFE_WRITE(sc, NFE_RX_CTL, 0); 1233 1234 /* disable interrupts */ 1235 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1236 1237 /* reset Tx and Rx rings */ 1238 nfe_reset_tx_ring(sc, &sc->txq); 1239 nfe_reset_rx_ring(sc, &sc->rxq); 1240 } 1241 1242 int 1243 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1244 { 1245 struct nfe_desc32 *desc32; 1246 struct nfe_desc64 *desc64; 1247 struct nfe_rx_data *data; 1248 struct nfe_jbuf *jbuf; 1249 void **desc; 1250 bus_addr_t physaddr; 1251 int i, nsegs, error, descsize; 1252 1253 if (sc->sc_flags & NFE_40BIT_ADDR) { 1254 desc = (void **)&ring->desc64; 1255 descsize = sizeof (struct nfe_desc64); 1256 } else { 1257 desc = (void **)&ring->desc32; 1258 descsize = sizeof (struct nfe_desc32); 1259 } 1260 1261 ring->cur = ring->next = 0; 1262 ring->bufsz = MCLBYTES; 1263 1264 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1265 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1266 if (error != 0) { 1267 printf("%s: could not create desc DMA map\n", 1268 sc->sc_dev.dv_xname); 1269 goto fail; 1270 } 1271 1272 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1273 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1274 if (error != 0) { 1275 printf("%s: could not allocate DMA memory\n", 1276 sc->sc_dev.dv_xname); 1277 goto fail; 1278 } 1279 1280 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1281 NFE_RX_RING_COUNT * descsize, (caddr_t *)desc, BUS_DMA_NOWAIT); 1282 if (error != 0) { 1283 printf("%s: could not map desc DMA memory\n", 1284 sc->sc_dev.dv_xname); 1285 goto fail; 1286 } 1287 1288 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1289 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1290 if (error != 0) { 1291 printf("%s: could not load desc DMA map\n", 1292 sc->sc_dev.dv_xname); 1293 goto fail; 1294 } 1295 1296 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1297 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1298 1299 if (sc->sc_flags & NFE_USE_JUMBO) { 1300 ring->bufsz = NFE_JBYTES; 1301 if ((error = nfe_jpool_alloc(sc)) != 0) { 1302 printf("%s: could not allocate jumbo frames\n", 1303 sc->sc_dev.dv_xname); 1304 goto fail; 1305 } 1306 } 1307 1308 /* 1309 * Pre-allocate Rx buffers and populate Rx ring. 1310 */ 1311 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1312 data = &sc->rxq.data[i]; 1313 1314 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1315 if (data->m == NULL) { 1316 printf("%s: could not allocate rx mbuf\n", 1317 sc->sc_dev.dv_xname); 1318 error = ENOMEM; 1319 goto fail; 1320 } 1321 1322 if (sc->sc_flags & NFE_USE_JUMBO) { 1323 if ((jbuf = nfe_jalloc(sc)) == NULL) { 1324 printf("%s: could not allocate jumbo buffer\n", 1325 sc->sc_dev.dv_xname); 1326 goto fail; 1327 } 1328 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1329 sc); 1330 1331 physaddr = jbuf->physaddr; 1332 } else { 1333 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1334 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1335 if (error != 0) { 1336 printf("%s: could not create DMA map\n", 1337 sc->sc_dev.dv_xname); 1338 goto fail; 1339 } 1340 MCLGET(data->m, M_DONTWAIT); 1341 if (!(data->m->m_flags & M_EXT)) { 1342 printf("%s: could not allocate mbuf cluster\n", 1343 sc->sc_dev.dv_xname); 1344 error = ENOMEM; 1345 goto fail; 1346 } 1347 1348 error = bus_dmamap_load(sc->sc_dmat, data->map, 1349 mtod(data->m, void *), MCLBYTES, NULL, 1350 BUS_DMA_READ | BUS_DMA_NOWAIT); 1351 if (error != 0) { 1352 printf("%s: could not load rx buf DMA map", 1353 sc->sc_dev.dv_xname); 1354 goto fail; 1355 } 1356 physaddr = data->map->dm_segs[0].ds_addr; 1357 } 1358 1359 if (sc->sc_flags & NFE_40BIT_ADDR) { 1360 desc64 = &sc->rxq.desc64[i]; 1361 #if defined(__LP64__) 1362 desc64->physaddr[0] = htole32(physaddr >> 32); 1363 #endif 1364 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1365 desc64->length = htole16(sc->rxq.bufsz); 1366 desc64->flags = htole16(NFE_RX_READY); 1367 } else { 1368 desc32 = &sc->rxq.desc32[i]; 1369 desc32->physaddr = htole32(physaddr); 1370 desc32->length = htole16(sc->rxq.bufsz); 1371 desc32->flags = htole16(NFE_RX_READY); 1372 } 1373 } 1374 1375 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1376 BUS_DMASYNC_PREWRITE); 1377 1378 return 0; 1379 1380 fail: nfe_free_rx_ring(sc, ring); 1381 return error; 1382 } 1383 1384 void 1385 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1386 { 1387 int i; 1388 1389 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1390 if (sc->sc_flags & NFE_40BIT_ADDR) { 1391 ring->desc64[i].length = htole16(ring->bufsz); 1392 ring->desc64[i].flags = htole16(NFE_RX_READY); 1393 } else { 1394 ring->desc32[i].length = htole16(ring->bufsz); 1395 ring->desc32[i].flags = htole16(NFE_RX_READY); 1396 } 1397 } 1398 1399 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1400 BUS_DMASYNC_PREWRITE); 1401 1402 ring->cur = ring->next = 0; 1403 } 1404 1405 void 1406 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1407 { 1408 struct nfe_rx_data *data; 1409 void *desc; 1410 int i, descsize; 1411 1412 if (sc->sc_flags & NFE_40BIT_ADDR) { 1413 desc = ring->desc64; 1414 descsize = sizeof (struct nfe_desc64); 1415 } else { 1416 desc = ring->desc32; 1417 descsize = sizeof (struct nfe_desc32); 1418 } 1419 1420 if (desc != NULL) { 1421 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1422 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1423 bus_dmamap_unload(sc->sc_dmat, ring->map); 1424 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)desc, 1425 NFE_RX_RING_COUNT * descsize); 1426 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1427 } 1428 1429 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1430 data = &ring->data[i]; 1431 1432 if (data->map != NULL) { 1433 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1434 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1435 bus_dmamap_unload(sc->sc_dmat, data->map); 1436 bus_dmamap_destroy(sc->sc_dmat, data->map); 1437 } 1438 if (data->m != NULL) 1439 m_freem(data->m); 1440 } 1441 } 1442 1443 struct nfe_jbuf * 1444 nfe_jalloc(struct nfe_softc *sc) 1445 { 1446 struct nfe_jbuf *jbuf; 1447 1448 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1449 if (jbuf == NULL) 1450 return NULL; 1451 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1452 return jbuf; 1453 } 1454 1455 /* 1456 * This is called automatically by the network stack when the mbuf is freed. 1457 * Caution must be taken that the NIC might be reset by the time the mbuf is 1458 * freed. 1459 */ 1460 void 1461 nfe_jfree(struct mbuf *m, caddr_t buf, size_t size, void *arg) 1462 { 1463 struct nfe_softc *sc = arg; 1464 struct nfe_jbuf *jbuf; 1465 int i; 1466 1467 /* find the jbuf from the base pointer */ 1468 i = (buf - sc->rxq.jpool) / NFE_JBYTES; 1469 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1470 printf("%s: request to free a buffer (%p) not managed by us\n", 1471 sc->sc_dev.dv_xname, buf); 1472 return; 1473 } 1474 jbuf = &sc->rxq.jbuf[i]; 1475 1476 /* ..and put it back in the free list */ 1477 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1478 1479 if (m != NULL) 1480 pool_cache_put(&mbpool_cache, m); 1481 } 1482 1483 int 1484 nfe_jpool_alloc(struct nfe_softc *sc) 1485 { 1486 struct nfe_rx_ring *ring = &sc->rxq; 1487 struct nfe_jbuf *jbuf; 1488 bus_addr_t physaddr; 1489 caddr_t buf; 1490 int i, nsegs, error; 1491 1492 /* 1493 * Allocate a big chunk of DMA'able memory. 1494 */ 1495 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1496 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1497 if (error != 0) { 1498 printf("%s: could not create jumbo DMA map\n", 1499 sc->sc_dev.dv_xname); 1500 goto fail; 1501 } 1502 1503 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1504 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1505 if (error != 0) { 1506 printf("%s could not allocate jumbo DMA memory\n", 1507 sc->sc_dev.dv_xname); 1508 goto fail; 1509 } 1510 1511 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1512 &ring->jpool, BUS_DMA_NOWAIT); 1513 if (error != 0) { 1514 printf("%s: could not map jumbo DMA memory\n", 1515 sc->sc_dev.dv_xname); 1516 goto fail; 1517 } 1518 1519 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1520 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1521 if (error != 0) { 1522 printf("%s: could not load jumbo DMA map\n", 1523 sc->sc_dev.dv_xname); 1524 goto fail; 1525 } 1526 1527 /* ..and split it into 9KB chunks */ 1528 SLIST_INIT(&ring->jfreelist); 1529 1530 buf = ring->jpool; 1531 physaddr = ring->jmap->dm_segs[0].ds_addr; 1532 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1533 jbuf = &ring->jbuf[i]; 1534 1535 jbuf->buf = buf; 1536 jbuf->physaddr = physaddr; 1537 1538 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1539 1540 buf += NFE_JBYTES; 1541 physaddr += NFE_JBYTES; 1542 } 1543 1544 return 0; 1545 1546 fail: nfe_jpool_free(sc); 1547 return error; 1548 } 1549 1550 void 1551 nfe_jpool_free(struct nfe_softc *sc) 1552 { 1553 struct nfe_rx_ring *ring = &sc->rxq; 1554 1555 if (ring->jmap != NULL) { 1556 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1557 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1558 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1559 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1560 } 1561 if (ring->jpool != NULL) { 1562 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1563 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1564 } 1565 } 1566 1567 int 1568 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1569 { 1570 int i, nsegs, error; 1571 void **desc; 1572 int descsize; 1573 1574 if (sc->sc_flags & NFE_40BIT_ADDR) { 1575 desc = (void **)&ring->desc64; 1576 descsize = sizeof (struct nfe_desc64); 1577 } else { 1578 desc = (void **)&ring->desc32; 1579 descsize = sizeof (struct nfe_desc32); 1580 } 1581 1582 ring->queued = 0; 1583 ring->cur = ring->next = 0; 1584 1585 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1586 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1587 1588 if (error != 0) { 1589 printf("%s: could not create desc DMA map\n", 1590 sc->sc_dev.dv_xname); 1591 goto fail; 1592 } 1593 1594 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1595 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1596 if (error != 0) { 1597 printf("%s: could not allocate DMA memory\n", 1598 sc->sc_dev.dv_xname); 1599 goto fail; 1600 } 1601 1602 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1603 NFE_TX_RING_COUNT * descsize, (caddr_t *)desc, BUS_DMA_NOWAIT); 1604 if (error != 0) { 1605 printf("%s: could not map desc DMA memory\n", 1606 sc->sc_dev.dv_xname); 1607 goto fail; 1608 } 1609 1610 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1611 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1612 if (error != 0) { 1613 printf("%s: could not load desc DMA map\n", 1614 sc->sc_dev.dv_xname); 1615 goto fail; 1616 } 1617 1618 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1619 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1620 1621 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1622 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1623 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1624 &ring->data[i].map); 1625 if (error != 0) { 1626 printf("%s: could not create DMA map\n", 1627 sc->sc_dev.dv_xname); 1628 goto fail; 1629 } 1630 } 1631 1632 return 0; 1633 1634 fail: nfe_free_tx_ring(sc, ring); 1635 return error; 1636 } 1637 1638 void 1639 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1640 { 1641 struct nfe_tx_data *data; 1642 int i; 1643 1644 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1645 if (sc->sc_flags & NFE_40BIT_ADDR) 1646 ring->desc64[i].flags = 0; 1647 else 1648 ring->desc32[i].flags = 0; 1649 1650 data = &ring->data[i]; 1651 1652 if (data->m != NULL) { 1653 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1654 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1655 bus_dmamap_unload(sc->sc_dmat, data->active); 1656 m_freem(data->m); 1657 data->m = NULL; 1658 } 1659 } 1660 1661 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1662 BUS_DMASYNC_PREWRITE); 1663 1664 ring->queued = 0; 1665 ring->cur = ring->next = 0; 1666 } 1667 1668 void 1669 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1670 { 1671 struct nfe_tx_data *data; 1672 void *desc; 1673 int i, descsize; 1674 1675 if (sc->sc_flags & NFE_40BIT_ADDR) { 1676 desc = ring->desc64; 1677 descsize = sizeof (struct nfe_desc64); 1678 } else { 1679 desc = ring->desc32; 1680 descsize = sizeof (struct nfe_desc32); 1681 } 1682 1683 if (desc != NULL) { 1684 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1685 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1686 bus_dmamap_unload(sc->sc_dmat, ring->map); 1687 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)desc, 1688 NFE_TX_RING_COUNT * descsize); 1689 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1690 } 1691 1692 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1693 data = &ring->data[i]; 1694 1695 if (data->m != NULL) { 1696 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1697 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1698 bus_dmamap_unload(sc->sc_dmat, data->active); 1699 m_freem(data->m); 1700 } 1701 } 1702 1703 /* ..and now actually destroy the DMA mappings */ 1704 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1705 data = &ring->data[i]; 1706 if (data->map == NULL) 1707 continue; 1708 bus_dmamap_destroy(sc->sc_dmat, data->map); 1709 } 1710 } 1711 1712 int 1713 nfe_ifmedia_upd(struct ifnet *ifp) 1714 { 1715 struct nfe_softc *sc = ifp->if_softc; 1716 struct mii_data *mii = &sc->sc_mii; 1717 struct mii_softc *miisc; 1718 1719 if (mii->mii_instance != 0) { 1720 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1721 mii_phy_reset(miisc); 1722 } 1723 return mii_mediachg(mii); 1724 } 1725 1726 void 1727 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1728 { 1729 struct nfe_softc *sc = ifp->if_softc; 1730 struct mii_data *mii = &sc->sc_mii; 1731 1732 mii_pollstat(mii); 1733 ifmr->ifm_status = mii->mii_media_status; 1734 ifmr->ifm_active = mii->mii_media_active; 1735 } 1736 1737 void 1738 nfe_setmulti(struct nfe_softc *sc) 1739 { 1740 struct ethercom *ec = &sc->sc_ethercom; 1741 struct ifnet *ifp = &ec->ec_if; 1742 struct ether_multi *enm; 1743 struct ether_multistep step; 1744 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1745 uint32_t filter = NFE_RXFILTER_MAGIC; 1746 int i; 1747 1748 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1749 bzero(addr, ETHER_ADDR_LEN); 1750 bzero(mask, ETHER_ADDR_LEN); 1751 goto done; 1752 } 1753 1754 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1755 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1756 1757 ETHER_FIRST_MULTI(step, ec, enm); 1758 while (enm != NULL) { 1759 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1760 ifp->if_flags |= IFF_ALLMULTI; 1761 bzero(addr, ETHER_ADDR_LEN); 1762 bzero(mask, ETHER_ADDR_LEN); 1763 goto done; 1764 } 1765 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1766 addr[i] &= enm->enm_addrlo[i]; 1767 mask[i] &= ~enm->enm_addrlo[i]; 1768 } 1769 ETHER_NEXT_MULTI(step, enm); 1770 } 1771 for (i = 0; i < ETHER_ADDR_LEN; i++) 1772 mask[i] |= addr[i]; 1773 1774 done: 1775 addr[0] |= 0x01; /* make sure multicast bit is set */ 1776 1777 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1778 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1779 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1780 addr[5] << 8 | addr[4]); 1781 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1782 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1783 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1784 mask[5] << 8 | mask[4]); 1785 1786 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1787 NFE_WRITE(sc, NFE_RXFILTER, filter); 1788 } 1789 1790 void 1791 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1792 { 1793 uint32_t tmp; 1794 1795 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1796 addr[0] = (tmp >> 8) & 0xff; 1797 addr[1] = (tmp & 0xff); 1798 1799 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1800 addr[2] = (tmp >> 24) & 0xff; 1801 addr[3] = (tmp >> 16) & 0xff; 1802 addr[4] = (tmp >> 8) & 0xff; 1803 addr[5] = (tmp & 0xff); 1804 } 1805 1806 void 1807 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1808 { 1809 NFE_WRITE(sc, NFE_MACADDR_LO, 1810 addr[5] << 8 | addr[4]); 1811 NFE_WRITE(sc, NFE_MACADDR_HI, 1812 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1813 } 1814 1815 void 1816 nfe_tick(void *arg) 1817 { 1818 struct nfe_softc *sc = arg; 1819 int s; 1820 1821 s = splnet(); 1822 mii_tick(&sc->sc_mii); 1823 splx(s); 1824 1825 callout_schedule(&sc->sc_tick_ch, hz); 1826 } 1827
Indexes created Tue Sep 30 07:10:03 GMT 2025