if_nfe.c revision 1.12
1 /* $NetBSD: if_nfe.c,v 1.12 2007/01/05 01:33:57 jmcneill Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.52 2006/03/02 09:04:00 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.12 2007/01/05 01:33:57 jmcneill Exp $"); 25 26 #include "opt_inet.h" 27 #include "bpfilter.h" 28 #include "vlan.h" 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/types.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/queue.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/socket.h> 41 42 #include <machine/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/pci/if_nfereg.h> 74 #include <dev/pci/if_nfevar.h> 75 76 int nfe_match(struct device *, struct cfdata *, void *); 77 void nfe_attach(struct device *, struct device *, void *); 78 void nfe_power(int, void *); 79 void nfe_miibus_statchg(struct device *); 80 int nfe_miibus_readreg(struct device *, int, int); 81 void nfe_miibus_writereg(struct device *, int, int, int); 82 int nfe_intr(void *); 83 int nfe_ioctl(struct ifnet *, u_long, caddr_t); 84 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 85 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 86 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 87 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 88 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 89 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 90 void nfe_rxeof(struct nfe_softc *); 91 void nfe_txeof(struct nfe_softc *); 92 int nfe_encap(struct nfe_softc *, struct mbuf *); 93 void nfe_start(struct ifnet *); 94 void nfe_watchdog(struct ifnet *); 95 int nfe_init(struct ifnet *); 96 void nfe_stop(struct ifnet *, int); 97 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *); 98 void nfe_jfree(struct mbuf *, caddr_t, size_t, void *); 99 int nfe_jpool_alloc(struct nfe_softc *); 100 void nfe_jpool_free(struct nfe_softc *); 101 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 102 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 105 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 int nfe_ifmedia_upd(struct ifnet *); 108 void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 109 void nfe_setmulti(struct nfe_softc *); 110 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 111 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 112 void nfe_tick(void *); 113 114 CFATTACH_DECL(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, NULL, NULL); 115 116 /*#define NFE_NO_JUMBO*/ 117 118 #ifdef NFE_DEBUG 119 int nfedebug = 0; 120 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 121 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 122 #else 123 #define DPRINTF(x) 124 #define DPRINTFN(n,x) 125 #endif 126 127 /* deal with naming differences */ 128 129 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 130 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 134 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 135 136 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 137 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 140 141 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 142 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 145 146 #ifdef _LP64 147 #define __LP64__ 1 148 #endif 149 150 const struct nfe_product { 151 pci_vendor_id_t vendor; 152 pci_product_id_t product; 153 } nfe_devices[] = { 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 155 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 } 177 }; 178 179 int 180 nfe_match(struct device *dev, struct cfdata *match, void *aux) 181 { 182 struct pci_attach_args *pa = aux; 183 const struct nfe_product *np; 184 int i; 185 186 for (i = 0; i < sizeof(nfe_devices) / sizeof(nfe_devices[0]); i++) { 187 np = &nfe_devices[i]; 188 if (PCI_VENDOR(pa->pa_id) == np->vendor && 189 PCI_PRODUCT(pa->pa_id) == np->product) 190 return 1; 191 } 192 return 0; 193 } 194 195 void 196 nfe_attach(struct device *parent, struct device *self, void *aux) 197 { 198 struct nfe_softc *sc = (struct nfe_softc *)self; 199 struct pci_attach_args *pa = aux; 200 pci_chipset_tag_t pc = pa->pa_pc; 201 pci_intr_handle_t ih; 202 const char *intrstr; 203 struct ifnet *ifp; 204 bus_size_t memsize; 205 pcireg_t memtype; 206 char devinfo[256]; 207 208 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 209 aprint_normal(": %s (rev. 0x%02x)\n", 210 devinfo, PCI_REVISION(pa->pa_class)); 211 212 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 213 switch (memtype) { 214 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 215 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 216 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 217 &sc->sc_memh, NULL, &memsize) == 0) 218 break; 219 /* FALLTHROUGH */ 220 default: 221 printf("%s: could not map mem space\n", sc->sc_dev.dv_xname); 222 return; 223 } 224 225 if (pci_intr_map(pa, &ih) != 0) { 226 printf("%s: could not map interrupt\n", sc->sc_dev.dv_xname); 227 return; 228 } 229 230 intrstr = pci_intr_string(pc, ih); 231 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 232 if (sc->sc_ih == NULL) { 233 printf("%s: could not establish interrupt", 234 sc->sc_dev.dv_xname); 235 if (intrstr != NULL) 236 printf(" at %s", intrstr); 237 printf("\n"); 238 return; 239 } 240 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 241 242 sc->sc_dmat = pa->pa_dmat; 243 244 nfe_get_macaddr(sc, sc->sc_enaddr); 245 printf("%s: Ethernet address %s\n", 246 sc->sc_dev.dv_xname, ether_sprintf(sc->sc_enaddr)); 247 248 sc->sc_flags = 0; 249 250 switch (PCI_PRODUCT(pa->pa_id)) { 251 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 252 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 253 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 254 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 255 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 256 break; 257 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 258 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 259 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 260 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 261 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 262 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 263 sc->sc_flags |= NFE_40BIT_ADDR; 264 break; 265 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 266 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 267 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 268 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 269 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 270 break; 271 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 272 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 273 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 274 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 275 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 276 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 277 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 278 NFE_HW_VLAN; 279 break; 280 } 281 282 #ifndef NFE_NO_JUMBO 283 /* enable jumbo frames for adapters that support it */ 284 if (sc->sc_flags & NFE_JUMBO_SUP) 285 sc->sc_flags |= NFE_USE_JUMBO; 286 #endif 287 288 /* 289 * Allocate Tx and Rx rings. 290 */ 291 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 292 printf("%s: could not allocate Tx ring\n", 293 sc->sc_dev.dv_xname); 294 return; 295 } 296 297 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 298 printf("%s: could not allocate Rx ring\n", 299 sc->sc_dev.dv_xname); 300 nfe_free_tx_ring(sc, &sc->txq); 301 return; 302 } 303 304 ifp = &sc->sc_ethercom.ec_if; 305 ifp->if_softc = sc; 306 ifp->if_mtu = ETHERMTU; 307 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 308 ifp->if_ioctl = nfe_ioctl; 309 ifp->if_start = nfe_start; 310 ifp->if_watchdog = nfe_watchdog; 311 ifp->if_init = nfe_init; 312 ifp->if_baudrate = IF_Gbps(1); 313 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 314 IFQ_SET_READY(&ifp->if_snd); 315 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 316 317 #if NVLAN > 0 318 if (sc->sc_flags & NFE_HW_VLAN) 319 sc->sc_ethercom.ec_capabilities |= 320 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 321 #endif 322 #ifdef NFE_CSUM 323 if (sc->sc_flags & NFE_HW_CSUM) { 324 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 325 IFCAP_CSUM_UDPv4; 326 } 327 #endif 328 329 sc->sc_mii.mii_ifp = ifp; 330 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 331 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 332 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 333 334 ifmedia_init(&sc->sc_mii.mii_media, 0, nfe_ifmedia_upd, 335 nfe_ifmedia_sts); 336 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 337 MII_OFFSET_ANY, 0); 338 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 339 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 340 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 341 0, NULL); 342 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 343 } else 344 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 345 346 if_attach(ifp); 347 ether_ifattach(ifp, sc->sc_enaddr); 348 349 callout_init(&sc->sc_tick_ch); 350 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 351 352 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 353 nfe_power, sc); 354 } 355 356 void 357 nfe_power(int why, void *arg) 358 { 359 struct nfe_softc *sc = arg; 360 struct ifnet *ifp; 361 362 if (why == PWR_RESUME) { 363 ifp = &sc->sc_ethercom.ec_if; 364 if (ifp->if_flags & IFF_UP) { 365 ifp->if_flags &= ~IFF_RUNNING; 366 nfe_init(ifp); 367 if (ifp->if_flags & IFF_RUNNING) 368 nfe_start(ifp); 369 } 370 } 371 } 372 373 void 374 nfe_miibus_statchg(struct device *dev) 375 { 376 struct nfe_softc *sc = (struct nfe_softc *)dev; 377 struct mii_data *mii = &sc->sc_mii; 378 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 379 380 phy = NFE_READ(sc, NFE_PHY_IFACE); 381 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 382 383 seed = NFE_READ(sc, NFE_RNDSEED); 384 seed &= ~NFE_SEED_MASK; 385 386 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 387 phy |= NFE_PHY_HDX; /* half-duplex */ 388 misc |= NFE_MISC1_HDX; 389 } 390 391 switch (IFM_SUBTYPE(mii->mii_media_active)) { 392 case IFM_1000_T: /* full-duplex only */ 393 link |= NFE_MEDIA_1000T; 394 seed |= NFE_SEED_1000T; 395 phy |= NFE_PHY_1000T; 396 break; 397 case IFM_100_TX: 398 link |= NFE_MEDIA_100TX; 399 seed |= NFE_SEED_100TX; 400 phy |= NFE_PHY_100TX; 401 break; 402 case IFM_10_T: 403 link |= NFE_MEDIA_10T; 404 seed |= NFE_SEED_10T; 405 break; 406 } 407 408 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 409 410 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 411 NFE_WRITE(sc, NFE_MISC1, misc); 412 NFE_WRITE(sc, NFE_LINKSPEED, link); 413 } 414 415 int 416 nfe_miibus_readreg(struct device *dev, int phy, int reg) 417 { 418 struct nfe_softc *sc = (struct nfe_softc *)dev; 419 uint32_t val; 420 int ntries; 421 422 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 423 424 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 425 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 426 DELAY(100); 427 } 428 429 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 430 431 for (ntries = 0; ntries < 1000; ntries++) { 432 DELAY(100); 433 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 434 break; 435 } 436 if (ntries == 1000) { 437 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 438 sc->sc_dev.dv_xname)); 439 return 0; 440 } 441 442 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 443 DPRINTFN(2, ("%s: could not read PHY\n", 444 sc->sc_dev.dv_xname)); 445 return 0; 446 } 447 448 val = NFE_READ(sc, NFE_PHY_DATA); 449 if (val != 0xffffffff && val != 0) 450 sc->mii_phyaddr = phy; 451 452 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 453 sc->sc_dev.dv_xname, phy, reg, val)); 454 455 return val; 456 } 457 458 void 459 nfe_miibus_writereg(struct device *dev, int phy, int reg, int val) 460 { 461 struct nfe_softc *sc = (struct nfe_softc *)dev; 462 uint32_t ctl; 463 int ntries; 464 465 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 466 467 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 468 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 469 DELAY(100); 470 } 471 472 NFE_WRITE(sc, NFE_PHY_DATA, val); 473 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 474 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 475 476 for (ntries = 0; ntries < 1000; ntries++) { 477 DELAY(100); 478 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 479 break; 480 } 481 #ifdef NFE_DEBUG 482 if (nfedebug >= 2 && ntries == 1000) 483 printf("could not write to PHY\n"); 484 #endif 485 } 486 487 int 488 nfe_intr(void *arg) 489 { 490 struct nfe_softc *sc = arg; 491 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 492 uint32_t r; 493 494 if ((r = NFE_READ(sc, NFE_IRQ_STATUS)) == 0) 495 return 0; /* not for us */ 496 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 497 498 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 499 500 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 501 502 if (r & NFE_IRQ_LINK) { 503 NFE_READ(sc, NFE_PHY_STATUS); 504 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 505 DPRINTF(("%s: link state changed\n", sc->sc_dev.dv_xname)); 506 } 507 508 if (ifp->if_flags & IFF_RUNNING) { 509 /* check Rx ring */ 510 nfe_rxeof(sc); 511 512 /* check Tx ring */ 513 nfe_txeof(sc); 514 } 515 516 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 517 518 if (ifp->if_flags & IFF_RUNNING && 519 !IF_IS_EMPTY(&ifp->if_snd)) 520 nfe_start(ifp); 521 522 return 1; 523 } 524 525 int 526 nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 527 { 528 struct nfe_softc *sc = ifp->if_softc; 529 struct ifreq *ifr = (struct ifreq *)data; 530 struct ifaddr *ifa = (struct ifaddr *)data; 531 int s, error = 0; 532 533 s = splnet(); 534 535 switch (cmd) { 536 case SIOCSIFADDR: 537 ifp->if_flags |= IFF_UP; 538 nfe_init(ifp); 539 switch (ifa->ifa_addr->sa_family) { 540 #ifdef INET 541 case AF_INET: 542 arp_ifinit(ifp, ifa); 543 break; 544 #endif 545 default: 546 break; 547 } 548 break; 549 case SIOCSIFMTU: 550 if (ifr->ifr_mtu < ETHERMIN || 551 ((sc->sc_flags & NFE_USE_JUMBO) && 552 ifr->ifr_mtu > ETHERMTU_JUMBO) || 553 (!(sc->sc_flags & NFE_USE_JUMBO) && 554 ifr->ifr_mtu > ETHERMTU)) 555 error = EINVAL; 556 else if (ifp->if_mtu != ifr->ifr_mtu) 557 ifp->if_mtu = ifr->ifr_mtu; 558 break; 559 case SIOCSIFFLAGS: 560 if (ifp->if_flags & IFF_UP) { 561 /* 562 * If only the PROMISC or ALLMULTI flag changes, then 563 * don't do a full re-init of the chip, just update 564 * the Rx filter. 565 */ 566 if ((ifp->if_flags & IFF_RUNNING) && 567 ((ifp->if_flags ^ sc->sc_if_flags) & 568 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 569 nfe_setmulti(sc); 570 else 571 nfe_init(ifp); 572 } else { 573 if (ifp->if_flags & IFF_RUNNING) 574 nfe_stop(ifp, 1); 575 } 576 sc->sc_if_flags = ifp->if_flags; 577 break; 578 case SIOCADDMULTI: 579 case SIOCDELMULTI: 580 error = (cmd == SIOCADDMULTI) ? 581 ether_addmulti(ifr, &sc->sc_ethercom) : 582 ether_delmulti(ifr, &sc->sc_ethercom); 583 584 if (error == ENETRESET) { 585 if (ifp->if_flags & IFF_RUNNING) 586 nfe_setmulti(sc); 587 error = 0; 588 } 589 break; 590 case SIOCSIFMEDIA: 591 case SIOCGIFMEDIA: 592 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 593 break; 594 default: 595 error = ether_ioctl(ifp, cmd, data); 596 if (error == ENETRESET) { 597 if (ifp->if_flags & IFF_RUNNING) 598 nfe_setmulti(sc); 599 error = 0; 600 } 601 break; 602 603 } 604 605 splx(s); 606 607 return error; 608 } 609 610 void 611 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 612 { 613 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 614 (caddr_t)desc32 - (caddr_t)sc->txq.desc32, 615 sizeof (struct nfe_desc32), ops); 616 } 617 618 void 619 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 620 { 621 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 622 (caddr_t)desc64 - (caddr_t)sc->txq.desc64, 623 sizeof (struct nfe_desc64), ops); 624 } 625 626 void 627 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 628 { 629 if (end > start) { 630 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 631 (caddr_t)&sc->txq.desc32[start] - (caddr_t)sc->txq.desc32, 632 (caddr_t)&sc->txq.desc32[end] - 633 (caddr_t)&sc->txq.desc32[start], ops); 634 return; 635 } 636 /* sync from 'start' to end of ring */ 637 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 638 (caddr_t)&sc->txq.desc32[start] - (caddr_t)sc->txq.desc32, 639 (caddr_t)&sc->txq.desc32[NFE_TX_RING_COUNT] - 640 (caddr_t)&sc->txq.desc32[start], ops); 641 642 /* sync from start of ring to 'end' */ 643 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 644 (caddr_t)&sc->txq.desc32[end] - (caddr_t)sc->txq.desc32, ops); 645 } 646 647 void 648 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 649 { 650 if (end > start) { 651 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 652 (caddr_t)&sc->txq.desc64[start] - (caddr_t)sc->txq.desc64, 653 (caddr_t)&sc->txq.desc64[end] - 654 (caddr_t)&sc->txq.desc64[start], ops); 655 return; 656 } 657 /* sync from 'start' to end of ring */ 658 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 659 (caddr_t)&sc->txq.desc64[start] - (caddr_t)sc->txq.desc64, 660 (caddr_t)&sc->txq.desc64[NFE_TX_RING_COUNT] - 661 (caddr_t)&sc->txq.desc64[start], ops); 662 663 /* sync from start of ring to 'end' */ 664 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 665 (caddr_t)&sc->txq.desc64[end] - (caddr_t)sc->txq.desc64, ops); 666 } 667 668 void 669 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 670 { 671 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 672 (caddr_t)desc32 - (caddr_t)sc->rxq.desc32, 673 sizeof (struct nfe_desc32), ops); 674 } 675 676 void 677 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 678 { 679 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 680 (caddr_t)desc64 - (caddr_t)sc->rxq.desc64, 681 sizeof (struct nfe_desc64), ops); 682 } 683 684 void 685 nfe_rxeof(struct nfe_softc *sc) 686 { 687 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 688 struct nfe_desc32 *desc32; 689 struct nfe_desc64 *desc64; 690 struct nfe_rx_data *data; 691 struct nfe_jbuf *jbuf; 692 struct mbuf *m, *mnew; 693 bus_addr_t physaddr; 694 uint16_t flags; 695 int error, len; 696 697 desc32 = NULL; 698 desc64 = NULL; 699 for (;;) { 700 data = &sc->rxq.data[sc->rxq.cur]; 701 702 if (sc->sc_flags & NFE_40BIT_ADDR) { 703 desc64 = &sc->rxq.desc64[sc->rxq.cur]; 704 nfe_rxdesc64_sync(sc, desc64, BUS_DMASYNC_POSTREAD); 705 706 flags = le16toh(desc64->flags); 707 len = le16toh(desc64->length) & 0x3fff; 708 } else { 709 desc32 = &sc->rxq.desc32[sc->rxq.cur]; 710 nfe_rxdesc32_sync(sc, desc32, BUS_DMASYNC_POSTREAD); 711 712 flags = le16toh(desc32->flags); 713 len = le16toh(desc32->length) & 0x3fff; 714 } 715 716 if (flags & NFE_RX_READY) 717 break; 718 719 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 720 if (!(flags & NFE_RX_VALID_V1)) 721 goto skip; 722 723 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 724 flags &= ~NFE_RX_ERROR; 725 len--; /* fix buffer length */ 726 } 727 } else { 728 if (!(flags & NFE_RX_VALID_V2)) 729 goto skip; 730 731 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 732 flags &= ~NFE_RX_ERROR; 733 len--; /* fix buffer length */ 734 } 735 } 736 737 if (flags & NFE_RX_ERROR) { 738 ifp->if_ierrors++; 739 goto skip; 740 } 741 742 /* 743 * Try to allocate a new mbuf for this ring element and load 744 * it before processing the current mbuf. If the ring element 745 * cannot be loaded, drop the received packet and reuse the 746 * old mbuf. In the unlikely case that the old mbuf can't be 747 * reloaded either, explicitly panic. 748 */ 749 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 750 if (mnew == NULL) { 751 ifp->if_ierrors++; 752 goto skip; 753 } 754 755 if (sc->sc_flags & NFE_USE_JUMBO) { 756 if ((jbuf = nfe_jalloc(sc)) == NULL) { 757 m_freem(mnew); 758 ifp->if_ierrors++; 759 goto skip; 760 } 761 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 762 763 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 764 mtod(data->m, caddr_t) - sc->rxq.jpool, NFE_JBYTES, 765 BUS_DMASYNC_POSTREAD); 766 767 physaddr = jbuf->physaddr; 768 } else { 769 MCLGET(mnew, M_DONTWAIT); 770 if (!(mnew->m_flags & M_EXT)) { 771 m_freem(mnew); 772 ifp->if_ierrors++; 773 goto skip; 774 } 775 776 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 777 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 778 bus_dmamap_unload(sc->sc_dmat, data->map); 779 780 error = bus_dmamap_load(sc->sc_dmat, data->map, 781 mtod(mnew, void *), MCLBYTES, NULL, 782 BUS_DMA_READ | BUS_DMA_NOWAIT); 783 if (error != 0) { 784 m_freem(mnew); 785 786 /* try to reload the old mbuf */ 787 error = bus_dmamap_load(sc->sc_dmat, data->map, 788 mtod(data->m, void *), MCLBYTES, NULL, 789 BUS_DMA_READ | BUS_DMA_NOWAIT); 790 if (error != 0) { 791 /* very unlikely that it will fail.. */ 792 panic("%s: could not load old rx mbuf", 793 sc->sc_dev.dv_xname); 794 } 795 ifp->if_ierrors++; 796 goto skip; 797 } 798 physaddr = data->map->dm_segs[0].ds_addr; 799 } 800 801 /* 802 * New mbuf successfully loaded, update Rx ring and continue 803 * processing. 804 */ 805 m = data->m; 806 data->m = mnew; 807 808 /* finalize mbuf */ 809 m->m_pkthdr.len = m->m_len = len; 810 m->m_pkthdr.rcvif = ifp; 811 812 #ifdef notyet 813 if (sc->sc_flags & NFE_HW_CSUM) { 814 if (flags & NFE_RX_IP_CSUMOK) 815 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 816 if (flags & NFE_RX_UDP_CSUMOK) 817 m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK; 818 if (flags & NFE_RX_TCP_CSUMOK) 819 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK; 820 } 821 #elif defined(NFE_CSUM) 822 if ((sc->sc_flags & NFE_HW_CSUM) && (flags & NFE_RX_CSUMOK)) 823 m->m_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK; 824 #endif 825 826 #if NBPFILTER > 0 827 if (ifp->if_bpf) 828 bpf_mtap(ifp->if_bpf, m); 829 #endif 830 ifp->if_ipackets++; 831 (*ifp->if_input)(ifp, m); 832 833 /* update mapping address in h/w descriptor */ 834 if (sc->sc_flags & NFE_40BIT_ADDR) { 835 #if defined(__LP64__) 836 desc64->physaddr[0] = htole32(physaddr >> 32); 837 #endif 838 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 839 } else { 840 desc32->physaddr = htole32(physaddr); 841 } 842 843 skip: if (sc->sc_flags & NFE_40BIT_ADDR) { 844 desc64->length = htole16(sc->rxq.bufsz); 845 desc64->flags = htole16(NFE_RX_READY); 846 847 nfe_rxdesc64_sync(sc, desc64, BUS_DMASYNC_PREWRITE); 848 } else { 849 desc32->length = htole16(sc->rxq.bufsz); 850 desc32->flags = htole16(NFE_RX_READY); 851 852 nfe_rxdesc32_sync(sc, desc32, BUS_DMASYNC_PREWRITE); 853 } 854 855 sc->rxq.cur = (sc->rxq.cur + 1) % NFE_RX_RING_COUNT; 856 } 857 } 858 859 void 860 nfe_txeof(struct nfe_softc *sc) 861 { 862 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 863 struct nfe_desc32 *desc32; 864 struct nfe_desc64 *desc64; 865 struct nfe_tx_data *data = NULL; 866 uint16_t flags; 867 868 while (sc->txq.next != sc->txq.cur) { 869 if (sc->sc_flags & NFE_40BIT_ADDR) { 870 desc64 = &sc->txq.desc64[sc->txq.next]; 871 nfe_txdesc64_sync(sc, desc64, BUS_DMASYNC_POSTREAD); 872 873 flags = le16toh(desc64->flags); 874 } else { 875 desc32 = &sc->txq.desc32[sc->txq.next]; 876 nfe_txdesc32_sync(sc, desc32, BUS_DMASYNC_POSTREAD); 877 878 flags = le16toh(desc32->flags); 879 } 880 881 if (flags & NFE_TX_VALID) 882 break; 883 884 data = &sc->txq.data[sc->txq.next]; 885 886 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 887 if (!(flags & NFE_TX_LASTFRAG_V1) && data->m == NULL) 888 goto skip; 889 890 if ((flags & NFE_TX_ERROR_V1) != 0) { 891 printf("%s: tx v1 error 0x%04x\n", 892 sc->sc_dev.dv_xname, flags); 893 ifp->if_oerrors++; 894 } else 895 ifp->if_opackets++; 896 } else { 897 if (!(flags & NFE_TX_LASTFRAG_V2) && data->m == NULL) 898 goto skip; 899 900 if ((flags & NFE_TX_ERROR_V2) != 0) { 901 printf("%s: tx v2 error 0x%04x\n", 902 sc->sc_dev.dv_xname, flags); 903 ifp->if_oerrors++; 904 } else 905 ifp->if_opackets++; 906 } 907 908 if (data->m == NULL) { /* should not get there */ 909 printf("%s: last fragment bit w/o associated mbuf!\n", 910 sc->sc_dev.dv_xname); 911 goto skip; 912 } 913 914 /* last fragment of the mbuf chain transmitted */ 915 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 916 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 917 bus_dmamap_unload(sc->sc_dmat, data->active); 918 m_freem(data->m); 919 data->m = NULL; 920 921 ifp->if_timer = 0; 922 923 skip: sc->txq.queued--; 924 sc->txq.next = (sc->txq.next + 1) % NFE_TX_RING_COUNT; 925 } 926 927 if (data != NULL) { /* at least one slot freed */ 928 ifp->if_flags &= ~IFF_OACTIVE; 929 nfe_start(ifp); 930 } 931 } 932 933 int 934 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 935 { 936 struct nfe_desc32 *desc32; 937 struct nfe_desc64 *desc64; 938 struct nfe_tx_data *data; 939 bus_dmamap_t map; 940 uint16_t flags; 941 #if NVLAN > 0 942 struct m_tag *mtag; 943 uint32_t vtag = 0; 944 #endif 945 int error, i, first; 946 947 desc32 = NULL; 948 desc64 = NULL; 949 data = NULL; 950 951 flags = 0; 952 first = sc->txq.cur; 953 954 map = sc->txq.data[first].map; 955 956 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 957 if (error != 0) { 958 printf("%s: could not map mbuf (error %d)\n", 959 sc->sc_dev.dv_xname, error); 960 return error; 961 } 962 963 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 964 bus_dmamap_unload(sc->sc_dmat, map); 965 return ENOBUFS; 966 } 967 968 #if NVLAN > 0 969 /* setup h/w VLAN tagging */ 970 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 971 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 972 #endif 973 #ifdef NFE_CSUM 974 if (m0->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 975 flags |= NFE_TX_IP_CSUM; 976 if (m0->m_pkthdr.csum_flags & (M_TCPV4_CSUM_OUT | M_UDPV4_CSUM_OUT)) 977 flags |= NFE_TX_TCP_CSUM; 978 #endif 979 980 for (i = 0; i < map->dm_nsegs; i++) { 981 data = &sc->txq.data[sc->txq.cur]; 982 983 if (sc->sc_flags & NFE_40BIT_ADDR) { 984 desc64 = &sc->txq.desc64[sc->txq.cur]; 985 #if defined(__LP64__) 986 desc64->physaddr[0] = 987 htole32(map->dm_segs[i].ds_addr >> 32); 988 #endif 989 desc64->physaddr[1] = 990 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 991 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 992 desc64->flags = htole16(flags); 993 #if NVLAN > 0 994 desc64->vtag = htole32(vtag); 995 #endif 996 } else { 997 desc32 = &sc->txq.desc32[sc->txq.cur]; 998 999 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1000 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1001 desc32->flags = htole16(flags); 1002 } 1003 1004 if (map->dm_nsegs > 1) { 1005 /* 1006 * Checksum flags and vtag belong to the first fragment 1007 * only. 1008 */ 1009 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_CSUM); 1010 #if NVLAN > 0 1011 vtag = 0; 1012 #endif 1013 /* 1014 * Setting of the valid bit in the first descriptor is 1015 * deferred until the whole chain is fully setup. 1016 */ 1017 flags |= NFE_TX_VALID; 1018 } 1019 1020 sc->txq.queued++; 1021 sc->txq.cur = (sc->txq.cur + 1) % NFE_TX_RING_COUNT; 1022 } 1023 1024 /* the whole mbuf chain has been setup */ 1025 if (sc->sc_flags & NFE_40BIT_ADDR) { 1026 /* fix last descriptor */ 1027 flags |= NFE_TX_LASTFRAG_V2; 1028 desc64->flags = htole16(flags); 1029 1030 /* finally, set the valid bit in the first descriptor */ 1031 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1032 } else { 1033 /* fix last descriptor */ 1034 if (sc->sc_flags & NFE_JUMBO_SUP) 1035 flags |= NFE_TX_LASTFRAG_V2; 1036 else 1037 flags |= NFE_TX_LASTFRAG_V1; 1038 desc32->flags = htole16(flags); 1039 1040 /* finally, set the valid bit in the first descriptor */ 1041 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1042 } 1043 1044 data->m = m0; 1045 data->active = map; 1046 1047 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1048 BUS_DMASYNC_PREWRITE); 1049 1050 return 0; 1051 } 1052 1053 void 1054 nfe_start(struct ifnet *ifp) 1055 { 1056 struct nfe_softc *sc = ifp->if_softc; 1057 int old = sc->txq.cur; 1058 struct mbuf *m0; 1059 1060 for (;;) { 1061 IFQ_POLL(&ifp->if_snd, m0); 1062 if (m0 == NULL) 1063 break; 1064 1065 if (nfe_encap(sc, m0) != 0) { 1066 ifp->if_flags |= IFF_OACTIVE; 1067 break; 1068 } 1069 1070 /* packet put in h/w queue, remove from s/w queue */ 1071 IFQ_DEQUEUE(&ifp->if_snd, m0); 1072 1073 #if NBPFILTER > 0 1074 if (ifp->if_bpf != NULL) 1075 bpf_mtap(ifp->if_bpf, m0); 1076 #endif 1077 } 1078 if (sc->txq.cur == old) /* nothing sent */ 1079 return; 1080 1081 if (sc->sc_flags & NFE_40BIT_ADDR) 1082 nfe_txdesc64_rsync(sc, old, sc->txq.cur, BUS_DMASYNC_PREWRITE); 1083 else 1084 nfe_txdesc32_rsync(sc, old, sc->txq.cur, BUS_DMASYNC_PREWRITE); 1085 1086 /* kick Tx */ 1087 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1088 1089 /* 1090 * Set a timeout in case the chip goes out to lunch. 1091 */ 1092 ifp->if_timer = 5; 1093 } 1094 1095 void 1096 nfe_watchdog(struct ifnet *ifp) 1097 { 1098 struct nfe_softc *sc = ifp->if_softc; 1099 1100 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1101 1102 ifp->if_flags &= ~IFF_RUNNING; 1103 nfe_init(ifp); 1104 1105 ifp->if_oerrors++; 1106 } 1107 1108 int 1109 nfe_init(struct ifnet *ifp) 1110 { 1111 struct nfe_softc *sc = ifp->if_softc; 1112 uint32_t tmp; 1113 int s; 1114 1115 if (ifp->if_flags & IFF_RUNNING) 1116 return 0; 1117 1118 nfe_stop(ifp, 0); 1119 1120 NFE_WRITE(sc, NFE_TX_UNK, 0); 1121 NFE_WRITE(sc, NFE_STATUS, 0); 1122 1123 sc->rxtxctl = NFE_RXTX_BIT2; 1124 if (sc->sc_flags & NFE_40BIT_ADDR) 1125 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1126 else if (sc->sc_flags & NFE_JUMBO_SUP) 1127 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1128 #ifdef NFE_CSUM 1129 if (sc->sc_flags & NFE_HW_CSUM) 1130 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1131 #endif 1132 #if NVLAN > 0 1133 /* 1134 * Although the adapter is capable of stripping VLAN tags from received 1135 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1136 * purpose. This will be done in software by our network stack. 1137 */ 1138 if (sc->sc_flags & NFE_HW_VLAN) 1139 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1140 #endif 1141 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1142 DELAY(10); 1143 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1144 1145 #if NVLAN 1146 if (sc->sc_flags & NFE_HW_VLAN) 1147 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1148 #endif 1149 1150 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1151 1152 /* set MAC address */ 1153 nfe_set_macaddr(sc, sc->sc_enaddr); 1154 1155 /* tell MAC where rings are in memory */ 1156 #ifdef __LP64__ 1157 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1158 #endif 1159 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1160 #ifdef __LP64__ 1161 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1162 #endif 1163 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1164 1165 NFE_WRITE(sc, NFE_RING_SIZE, 1166 (NFE_RX_RING_COUNT - 1) << 16 | 1167 (NFE_TX_RING_COUNT - 1)); 1168 1169 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1170 1171 /* force MAC to wakeup */ 1172 tmp = NFE_READ(sc, NFE_PWR_STATE); 1173 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1174 DELAY(10); 1175 tmp = NFE_READ(sc, NFE_PWR_STATE); 1176 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1177 1178 s = splnet(); 1179 nfe_intr(sc); /* XXX clear IRQ status registers */ 1180 splx(s); 1181 1182 #if 1 1183 /* configure interrupts coalescing/mitigation */ 1184 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1185 #else 1186 /* no interrupt mitigation: one interrupt per packet */ 1187 NFE_WRITE(sc, NFE_IMTIMER, 970); 1188 #endif 1189 1190 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1191 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1192 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1193 1194 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1195 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1196 1197 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1198 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC); 1199 1200 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1201 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1202 DELAY(10); 1203 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1204 1205 /* set Rx filter */ 1206 nfe_setmulti(sc); 1207 1208 nfe_ifmedia_upd(ifp); 1209 1210 nfe_tick(sc); 1211 1212 /* enable Rx */ 1213 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1214 1215 /* enable Tx */ 1216 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1217 1218 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1219 1220 /* enable interrupts */ 1221 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1222 1223 callout_schedule(&sc->sc_tick_ch, hz); 1224 1225 ifp->if_flags |= IFF_RUNNING; 1226 ifp->if_flags &= ~IFF_OACTIVE; 1227 1228 return 0; 1229 } 1230 1231 void 1232 nfe_stop(struct ifnet *ifp, int disable) 1233 { 1234 struct nfe_softc *sc = ifp->if_softc; 1235 1236 callout_stop(&sc->sc_tick_ch); 1237 1238 ifp->if_timer = 0; 1239 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1240 1241 mii_down(&sc->sc_mii); 1242 1243 /* abort Tx */ 1244 NFE_WRITE(sc, NFE_TX_CTL, 0); 1245 1246 /* disable Rx */ 1247 NFE_WRITE(sc, NFE_RX_CTL, 0); 1248 1249 /* disable interrupts */ 1250 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1251 1252 /* reset Tx and Rx rings */ 1253 nfe_reset_tx_ring(sc, &sc->txq); 1254 nfe_reset_rx_ring(sc, &sc->rxq); 1255 } 1256 1257 int 1258 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1259 { 1260 struct nfe_desc32 *desc32; 1261 struct nfe_desc64 *desc64; 1262 struct nfe_rx_data *data; 1263 struct nfe_jbuf *jbuf; 1264 void **desc; 1265 bus_addr_t physaddr; 1266 int i, nsegs, error, descsize; 1267 1268 if (sc->sc_flags & NFE_40BIT_ADDR) { 1269 desc = (void **)&ring->desc64; 1270 descsize = sizeof (struct nfe_desc64); 1271 } else { 1272 desc = (void **)&ring->desc32; 1273 descsize = sizeof (struct nfe_desc32); 1274 } 1275 1276 ring->cur = ring->next = 0; 1277 ring->bufsz = MCLBYTES; 1278 1279 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1280 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1281 if (error != 0) { 1282 printf("%s: could not create desc DMA map\n", 1283 sc->sc_dev.dv_xname); 1284 goto fail; 1285 } 1286 1287 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1288 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1289 if (error != 0) { 1290 printf("%s: could not allocate DMA memory\n", 1291 sc->sc_dev.dv_xname); 1292 goto fail; 1293 } 1294 1295 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1296 NFE_RX_RING_COUNT * descsize, (caddr_t *)desc, BUS_DMA_NOWAIT); 1297 if (error != 0) { 1298 printf("%s: could not map desc DMA memory\n", 1299 sc->sc_dev.dv_xname); 1300 goto fail; 1301 } 1302 1303 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1304 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1305 if (error != 0) { 1306 printf("%s: could not load desc DMA map\n", 1307 sc->sc_dev.dv_xname); 1308 goto fail; 1309 } 1310 1311 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1312 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1313 1314 if (sc->sc_flags & NFE_USE_JUMBO) { 1315 ring->bufsz = NFE_JBYTES; 1316 if ((error = nfe_jpool_alloc(sc)) != 0) { 1317 printf("%s: could not allocate jumbo frames\n", 1318 sc->sc_dev.dv_xname); 1319 goto fail; 1320 } 1321 } 1322 1323 /* 1324 * Pre-allocate Rx buffers and populate Rx ring. 1325 */ 1326 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1327 data = &sc->rxq.data[i]; 1328 1329 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1330 if (data->m == NULL) { 1331 printf("%s: could not allocate rx mbuf\n", 1332 sc->sc_dev.dv_xname); 1333 error = ENOMEM; 1334 goto fail; 1335 } 1336 1337 if (sc->sc_flags & NFE_USE_JUMBO) { 1338 if ((jbuf = nfe_jalloc(sc)) == NULL) { 1339 printf("%s: could not allocate jumbo buffer\n", 1340 sc->sc_dev.dv_xname); 1341 goto fail; 1342 } 1343 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1344 sc); 1345 1346 physaddr = jbuf->physaddr; 1347 } else { 1348 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1349 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1350 if (error != 0) { 1351 printf("%s: could not create DMA map\n", 1352 sc->sc_dev.dv_xname); 1353 goto fail; 1354 } 1355 MCLGET(data->m, M_DONTWAIT); 1356 if (!(data->m->m_flags & M_EXT)) { 1357 printf("%s: could not allocate mbuf cluster\n", 1358 sc->sc_dev.dv_xname); 1359 error = ENOMEM; 1360 goto fail; 1361 } 1362 1363 error = bus_dmamap_load(sc->sc_dmat, data->map, 1364 mtod(data->m, void *), MCLBYTES, NULL, 1365 BUS_DMA_READ | BUS_DMA_NOWAIT); 1366 if (error != 0) { 1367 printf("%s: could not load rx buf DMA map", 1368 sc->sc_dev.dv_xname); 1369 goto fail; 1370 } 1371 physaddr = data->map->dm_segs[0].ds_addr; 1372 } 1373 1374 if (sc->sc_flags & NFE_40BIT_ADDR) { 1375 desc64 = &sc->rxq.desc64[i]; 1376 #if defined(__LP64__) 1377 desc64->physaddr[0] = htole32(physaddr >> 32); 1378 #endif 1379 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1380 desc64->length = htole16(sc->rxq.bufsz); 1381 desc64->flags = htole16(NFE_RX_READY); 1382 } else { 1383 desc32 = &sc->rxq.desc32[i]; 1384 desc32->physaddr = htole32(physaddr); 1385 desc32->length = htole16(sc->rxq.bufsz); 1386 desc32->flags = htole16(NFE_RX_READY); 1387 } 1388 } 1389 1390 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1391 BUS_DMASYNC_PREWRITE); 1392 1393 return 0; 1394 1395 fail: nfe_free_rx_ring(sc, ring); 1396 return error; 1397 } 1398 1399 void 1400 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1401 { 1402 int i; 1403 1404 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1405 if (sc->sc_flags & NFE_40BIT_ADDR) { 1406 ring->desc64[i].length = htole16(ring->bufsz); 1407 ring->desc64[i].flags = htole16(NFE_RX_READY); 1408 } else { 1409 ring->desc32[i].length = htole16(ring->bufsz); 1410 ring->desc32[i].flags = htole16(NFE_RX_READY); 1411 } 1412 } 1413 1414 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1415 BUS_DMASYNC_PREWRITE); 1416 1417 ring->cur = ring->next = 0; 1418 } 1419 1420 void 1421 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1422 { 1423 struct nfe_rx_data *data; 1424 void *desc; 1425 int i, descsize; 1426 1427 if (sc->sc_flags & NFE_40BIT_ADDR) { 1428 desc = ring->desc64; 1429 descsize = sizeof (struct nfe_desc64); 1430 } else { 1431 desc = ring->desc32; 1432 descsize = sizeof (struct nfe_desc32); 1433 } 1434 1435 if (desc != NULL) { 1436 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1437 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1438 bus_dmamap_unload(sc->sc_dmat, ring->map); 1439 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)desc, 1440 NFE_RX_RING_COUNT * descsize); 1441 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1442 } 1443 1444 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1445 data = &ring->data[i]; 1446 1447 if (data->map != NULL) { 1448 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1449 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1450 bus_dmamap_unload(sc->sc_dmat, data->map); 1451 bus_dmamap_destroy(sc->sc_dmat, data->map); 1452 } 1453 if (data->m != NULL) 1454 m_freem(data->m); 1455 } 1456 } 1457 1458 struct nfe_jbuf * 1459 nfe_jalloc(struct nfe_softc *sc) 1460 { 1461 struct nfe_jbuf *jbuf; 1462 1463 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1464 if (jbuf == NULL) 1465 return NULL; 1466 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1467 return jbuf; 1468 } 1469 1470 /* 1471 * This is called automatically by the network stack when the mbuf is freed. 1472 * Caution must be taken that the NIC might be reset by the time the mbuf is 1473 * freed. 1474 */ 1475 void 1476 nfe_jfree(struct mbuf *m, caddr_t buf, size_t size, void *arg) 1477 { 1478 struct nfe_softc *sc = arg; 1479 struct nfe_jbuf *jbuf; 1480 int i; 1481 1482 /* find the jbuf from the base pointer */ 1483 i = (buf - sc->rxq.jpool) / NFE_JBYTES; 1484 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1485 printf("%s: request to free a buffer (%p) not managed by us\n", 1486 sc->sc_dev.dv_xname, buf); 1487 return; 1488 } 1489 jbuf = &sc->rxq.jbuf[i]; 1490 1491 /* ..and put it back in the free list */ 1492 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1493 1494 if (m != NULL) 1495 pool_cache_put(&mbpool_cache, m); 1496 } 1497 1498 int 1499 nfe_jpool_alloc(struct nfe_softc *sc) 1500 { 1501 struct nfe_rx_ring *ring = &sc->rxq; 1502 struct nfe_jbuf *jbuf; 1503 bus_addr_t physaddr; 1504 caddr_t buf; 1505 int i, nsegs, error; 1506 1507 /* 1508 * Allocate a big chunk of DMA'able memory. 1509 */ 1510 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1511 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1512 if (error != 0) { 1513 printf("%s: could not create jumbo DMA map\n", 1514 sc->sc_dev.dv_xname); 1515 goto fail; 1516 } 1517 1518 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1519 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1520 if (error != 0) { 1521 printf("%s could not allocate jumbo DMA memory\n", 1522 sc->sc_dev.dv_xname); 1523 goto fail; 1524 } 1525 1526 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1527 &ring->jpool, BUS_DMA_NOWAIT); 1528 if (error != 0) { 1529 printf("%s: could not map jumbo DMA memory\n", 1530 sc->sc_dev.dv_xname); 1531 goto fail; 1532 } 1533 1534 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1535 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1536 if (error != 0) { 1537 printf("%s: could not load jumbo DMA map\n", 1538 sc->sc_dev.dv_xname); 1539 goto fail; 1540 } 1541 1542 /* ..and split it into 9KB chunks */ 1543 SLIST_INIT(&ring->jfreelist); 1544 1545 buf = ring->jpool; 1546 physaddr = ring->jmap->dm_segs[0].ds_addr; 1547 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1548 jbuf = &ring->jbuf[i]; 1549 1550 jbuf->buf = buf; 1551 jbuf->physaddr = physaddr; 1552 1553 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1554 1555 buf += NFE_JBYTES; 1556 physaddr += NFE_JBYTES; 1557 } 1558 1559 return 0; 1560 1561 fail: nfe_jpool_free(sc); 1562 return error; 1563 } 1564 1565 void 1566 nfe_jpool_free(struct nfe_softc *sc) 1567 { 1568 struct nfe_rx_ring *ring = &sc->rxq; 1569 1570 if (ring->jmap != NULL) { 1571 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1572 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1573 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1574 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1575 } 1576 if (ring->jpool != NULL) { 1577 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1578 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1579 } 1580 } 1581 1582 int 1583 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1584 { 1585 int i, nsegs, error; 1586 void **desc; 1587 int descsize; 1588 1589 if (sc->sc_flags & NFE_40BIT_ADDR) { 1590 desc = (void **)&ring->desc64; 1591 descsize = sizeof (struct nfe_desc64); 1592 } else { 1593 desc = (void **)&ring->desc32; 1594 descsize = sizeof (struct nfe_desc32); 1595 } 1596 1597 ring->queued = 0; 1598 ring->cur = ring->next = 0; 1599 1600 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1601 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1602 1603 if (error != 0) { 1604 printf("%s: could not create desc DMA map\n", 1605 sc->sc_dev.dv_xname); 1606 goto fail; 1607 } 1608 1609 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1610 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1611 if (error != 0) { 1612 printf("%s: could not allocate DMA memory\n", 1613 sc->sc_dev.dv_xname); 1614 goto fail; 1615 } 1616 1617 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1618 NFE_TX_RING_COUNT * descsize, (caddr_t *)desc, BUS_DMA_NOWAIT); 1619 if (error != 0) { 1620 printf("%s: could not map desc DMA memory\n", 1621 sc->sc_dev.dv_xname); 1622 goto fail; 1623 } 1624 1625 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1626 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1627 if (error != 0) { 1628 printf("%s: could not load desc DMA map\n", 1629 sc->sc_dev.dv_xname); 1630 goto fail; 1631 } 1632 1633 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1634 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1635 1636 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1637 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1638 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1639 &ring->data[i].map); 1640 if (error != 0) { 1641 printf("%s: could not create DMA map\n", 1642 sc->sc_dev.dv_xname); 1643 goto fail; 1644 } 1645 } 1646 1647 return 0; 1648 1649 fail: nfe_free_tx_ring(sc, ring); 1650 return error; 1651 } 1652 1653 void 1654 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1655 { 1656 struct nfe_tx_data *data; 1657 int i; 1658 1659 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1660 if (sc->sc_flags & NFE_40BIT_ADDR) 1661 ring->desc64[i].flags = 0; 1662 else 1663 ring->desc32[i].flags = 0; 1664 1665 data = &ring->data[i]; 1666 1667 if (data->m != NULL) { 1668 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1669 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1670 bus_dmamap_unload(sc->sc_dmat, data->active); 1671 m_freem(data->m); 1672 data->m = NULL; 1673 } 1674 } 1675 1676 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1677 BUS_DMASYNC_PREWRITE); 1678 1679 ring->queued = 0; 1680 ring->cur = ring->next = 0; 1681 } 1682 1683 void 1684 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1685 { 1686 struct nfe_tx_data *data; 1687 void *desc; 1688 int i, descsize; 1689 1690 if (sc->sc_flags & NFE_40BIT_ADDR) { 1691 desc = ring->desc64; 1692 descsize = sizeof (struct nfe_desc64); 1693 } else { 1694 desc = ring->desc32; 1695 descsize = sizeof (struct nfe_desc32); 1696 } 1697 1698 if (desc != NULL) { 1699 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1700 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1701 bus_dmamap_unload(sc->sc_dmat, ring->map); 1702 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)desc, 1703 NFE_TX_RING_COUNT * descsize); 1704 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1705 } 1706 1707 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1708 data = &ring->data[i]; 1709 1710 if (data->m != NULL) { 1711 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1712 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1713 bus_dmamap_unload(sc->sc_dmat, data->active); 1714 m_freem(data->m); 1715 } 1716 } 1717 1718 /* ..and now actually destroy the DMA mappings */ 1719 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1720 data = &ring->data[i]; 1721 if (data->map == NULL) 1722 continue; 1723 bus_dmamap_destroy(sc->sc_dmat, data->map); 1724 } 1725 } 1726 1727 int 1728 nfe_ifmedia_upd(struct ifnet *ifp) 1729 { 1730 struct nfe_softc *sc = ifp->if_softc; 1731 struct mii_data *mii = &sc->sc_mii; 1732 struct mii_softc *miisc; 1733 1734 if (mii->mii_instance != 0) { 1735 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1736 mii_phy_reset(miisc); 1737 } 1738 return mii_mediachg(mii); 1739 } 1740 1741 void 1742 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1743 { 1744 struct nfe_softc *sc = ifp->if_softc; 1745 struct mii_data *mii = &sc->sc_mii; 1746 1747 mii_pollstat(mii); 1748 ifmr->ifm_status = mii->mii_media_status; 1749 ifmr->ifm_active = mii->mii_media_active; 1750 } 1751 1752 void 1753 nfe_setmulti(struct nfe_softc *sc) 1754 { 1755 struct ethercom *ec = &sc->sc_ethercom; 1756 struct ifnet *ifp = &ec->ec_if; 1757 struct ether_multi *enm; 1758 struct ether_multistep step; 1759 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1760 uint32_t filter = NFE_RXFILTER_MAGIC; 1761 int i; 1762 1763 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1764 bzero(addr, ETHER_ADDR_LEN); 1765 bzero(mask, ETHER_ADDR_LEN); 1766 goto done; 1767 } 1768 1769 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1770 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1771 1772 ETHER_FIRST_MULTI(step, ec, enm); 1773 while (enm != NULL) { 1774 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1775 ifp->if_flags |= IFF_ALLMULTI; 1776 bzero(addr, ETHER_ADDR_LEN); 1777 bzero(mask, ETHER_ADDR_LEN); 1778 goto done; 1779 } 1780 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1781 addr[i] &= enm->enm_addrlo[i]; 1782 mask[i] &= ~enm->enm_addrlo[i]; 1783 } 1784 ETHER_NEXT_MULTI(step, enm); 1785 } 1786 for (i = 0; i < ETHER_ADDR_LEN; i++) 1787 mask[i] |= addr[i]; 1788 1789 done: 1790 addr[0] |= 0x01; /* make sure multicast bit is set */ 1791 1792 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1793 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1794 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1795 addr[5] << 8 | addr[4]); 1796 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1797 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1798 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1799 mask[5] << 8 | mask[4]); 1800 1801 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1802 NFE_WRITE(sc, NFE_RXFILTER, filter); 1803 } 1804 1805 void 1806 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1807 { 1808 uint32_t tmp; 1809 1810 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1811 addr[0] = (tmp >> 8) & 0xff; 1812 addr[1] = (tmp & 0xff); 1813 1814 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1815 addr[2] = (tmp >> 24) & 0xff; 1816 addr[3] = (tmp >> 16) & 0xff; 1817 addr[4] = (tmp >> 8) & 0xff; 1818 addr[5] = (tmp & 0xff); 1819 } 1820 1821 void 1822 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1823 { 1824 NFE_WRITE(sc, NFE_MACADDR_LO, 1825 addr[5] << 8 | addr[4]); 1826 NFE_WRITE(sc, NFE_MACADDR_HI, 1827 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1828 } 1829 1830 void 1831 nfe_tick(void *arg) 1832 { 1833 struct nfe_softc *sc = arg; 1834 int s; 1835 1836 s = splnet(); 1837 mii_tick(&sc->sc_mii); 1838 splx(s); 1839 1840 callout_schedule(&sc->sc_tick_ch, hz); 1841 } 1842
Indexes created Tue Sep 30 07:10:03 GMT 2025