if_nfe.c revision 1.16
1 /* $NetBSD: if_nfe.c,v 1.16 2007/07/09 21:00:54 ad Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.52 2006/03/02 09:04:00 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.16 2007/07/09 21:00:54 ad Exp $"); 25 26 #include "opt_inet.h" 27 #include "bpfilter.h" 28 #include "vlan.h" 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/types.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/queue.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/socket.h> 41 42 #include <machine/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/pci/if_nfereg.h> 74 #include <dev/pci/if_nfevar.h> 75 76 int nfe_match(struct device *, struct cfdata *, void *); 77 void nfe_attach(struct device *, struct device *, void *); 78 void nfe_power(int, void *); 79 void nfe_miibus_statchg(struct device *); 80 int nfe_miibus_readreg(struct device *, int, int); 81 void nfe_miibus_writereg(struct device *, int, int, int); 82 int nfe_intr(void *); 83 int nfe_ioctl(struct ifnet *, u_long, void *); 84 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 85 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 86 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 87 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 88 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 89 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 90 void nfe_rxeof(struct nfe_softc *); 91 void nfe_txeof(struct nfe_softc *); 92 int nfe_encap(struct nfe_softc *, struct mbuf *); 93 void nfe_start(struct ifnet *); 94 void nfe_watchdog(struct ifnet *); 95 int nfe_init(struct ifnet *); 96 void nfe_stop(struct ifnet *, int); 97 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *); 98 void nfe_jfree(struct mbuf *, void *, size_t, void *); 99 int nfe_jpool_alloc(struct nfe_softc *); 100 void nfe_jpool_free(struct nfe_softc *); 101 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 102 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 105 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 int nfe_ifmedia_upd(struct ifnet *); 108 void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 109 void nfe_setmulti(struct nfe_softc *); 110 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 111 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 112 void nfe_tick(void *); 113 114 CFATTACH_DECL(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, NULL, NULL); 115 116 /*#define NFE_NO_JUMBO*/ 117 118 #ifdef NFE_DEBUG 119 int nfedebug = 0; 120 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 121 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 122 #else 123 #define DPRINTF(x) 124 #define DPRINTFN(n,x) 125 #endif 126 127 /* deal with naming differences */ 128 129 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 130 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 134 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 135 136 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 137 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 140 141 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 142 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 145 146 #ifdef _LP64 147 #define __LP64__ 1 148 #endif 149 150 const struct nfe_product { 151 pci_vendor_id_t vendor; 152 pci_product_id_t product; 153 } nfe_devices[] = { 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 155 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 } 177 }; 178 179 int 180 nfe_match(struct device *dev, struct cfdata *match, void *aux) 181 { 182 struct pci_attach_args *pa = aux; 183 const struct nfe_product *np; 184 int i; 185 186 for (i = 0; i < sizeof(nfe_devices) / sizeof(nfe_devices[0]); i++) { 187 np = &nfe_devices[i]; 188 if (PCI_VENDOR(pa->pa_id) == np->vendor && 189 PCI_PRODUCT(pa->pa_id) == np->product) 190 return 1; 191 } 192 return 0; 193 } 194 195 void 196 nfe_attach(struct device *parent, struct device *self, void *aux) 197 { 198 struct nfe_softc *sc = (struct nfe_softc *)self; 199 struct pci_attach_args *pa = aux; 200 pci_chipset_tag_t pc = pa->pa_pc; 201 pci_intr_handle_t ih; 202 const char *intrstr; 203 struct ifnet *ifp; 204 bus_size_t memsize; 205 pcireg_t memtype; 206 char devinfo[256]; 207 208 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 209 aprint_normal(": %s (rev. 0x%02x)\n", 210 devinfo, PCI_REVISION(pa->pa_class)); 211 212 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 213 switch (memtype) { 214 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 215 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 216 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 217 &sc->sc_memh, NULL, &memsize) == 0) 218 break; 219 /* FALLTHROUGH */ 220 default: 221 printf("%s: could not map mem space\n", sc->sc_dev.dv_xname); 222 return; 223 } 224 225 if (pci_intr_map(pa, &ih) != 0) { 226 printf("%s: could not map interrupt\n", sc->sc_dev.dv_xname); 227 return; 228 } 229 230 intrstr = pci_intr_string(pc, ih); 231 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 232 if (sc->sc_ih == NULL) { 233 printf("%s: could not establish interrupt", 234 sc->sc_dev.dv_xname); 235 if (intrstr != NULL) 236 printf(" at %s", intrstr); 237 printf("\n"); 238 return; 239 } 240 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 241 242 sc->sc_dmat = pa->pa_dmat; 243 244 nfe_get_macaddr(sc, sc->sc_enaddr); 245 printf("%s: Ethernet address %s\n", 246 sc->sc_dev.dv_xname, ether_sprintf(sc->sc_enaddr)); 247 248 sc->sc_flags = 0; 249 250 switch (PCI_PRODUCT(pa->pa_id)) { 251 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 252 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 253 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 254 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 255 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 256 break; 257 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 258 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 259 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 260 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 261 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 262 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 263 sc->sc_flags |= NFE_40BIT_ADDR; 264 break; 265 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 266 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 267 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 268 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 269 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 270 break; 271 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 272 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 273 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 274 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 275 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 276 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 277 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 278 NFE_HW_VLAN; 279 break; 280 } 281 282 #ifndef NFE_NO_JUMBO 283 /* enable jumbo frames for adapters that support it */ 284 if (sc->sc_flags & NFE_JUMBO_SUP) 285 sc->sc_flags |= NFE_USE_JUMBO; 286 #endif 287 288 /* 289 * Allocate Tx and Rx rings. 290 */ 291 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 292 printf("%s: could not allocate Tx ring\n", 293 sc->sc_dev.dv_xname); 294 return; 295 } 296 297 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 298 printf("%s: could not allocate Rx ring\n", 299 sc->sc_dev.dv_xname); 300 nfe_free_tx_ring(sc, &sc->txq); 301 return; 302 } 303 304 ifp = &sc->sc_ethercom.ec_if; 305 ifp->if_softc = sc; 306 ifp->if_mtu = ETHERMTU; 307 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 308 ifp->if_ioctl = nfe_ioctl; 309 ifp->if_start = nfe_start; 310 ifp->if_watchdog = nfe_watchdog; 311 ifp->if_init = nfe_init; 312 ifp->if_baudrate = IF_Gbps(1); 313 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 314 IFQ_SET_READY(&ifp->if_snd); 315 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 316 317 #if NVLAN > 0 318 if (sc->sc_flags & NFE_HW_VLAN) 319 sc->sc_ethercom.ec_capabilities |= 320 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 321 #endif 322 if (sc->sc_flags & NFE_HW_CSUM) { 323 ifp->if_capabilities |= 324 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 325 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 326 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 327 } 328 329 sc->sc_mii.mii_ifp = ifp; 330 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 331 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 332 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 333 334 ifmedia_init(&sc->sc_mii.mii_media, 0, nfe_ifmedia_upd, 335 nfe_ifmedia_sts); 336 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 337 MII_OFFSET_ANY, 0); 338 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 339 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 340 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 341 0, NULL); 342 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 343 } else 344 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 345 346 if_attach(ifp); 347 ether_ifattach(ifp, sc->sc_enaddr); 348 349 callout_init(&sc->sc_tick_ch, 0); 350 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 351 352 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 353 nfe_power, sc); 354 } 355 356 void 357 nfe_power(int why, void *arg) 358 { 359 struct nfe_softc *sc = arg; 360 struct ifnet *ifp; 361 362 if (why == PWR_RESUME) { 363 ifp = &sc->sc_ethercom.ec_if; 364 if (ifp->if_flags & IFF_UP) { 365 ifp->if_flags &= ~IFF_RUNNING; 366 nfe_init(ifp); 367 if (ifp->if_flags & IFF_RUNNING) 368 nfe_start(ifp); 369 } 370 } 371 } 372 373 void 374 nfe_miibus_statchg(struct device *dev) 375 { 376 struct nfe_softc *sc = (struct nfe_softc *)dev; 377 struct mii_data *mii = &sc->sc_mii; 378 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 379 380 phy = NFE_READ(sc, NFE_PHY_IFACE); 381 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 382 383 seed = NFE_READ(sc, NFE_RNDSEED); 384 seed &= ~NFE_SEED_MASK; 385 386 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 387 phy |= NFE_PHY_HDX; /* half-duplex */ 388 misc |= NFE_MISC1_HDX; 389 } 390 391 switch (IFM_SUBTYPE(mii->mii_media_active)) { 392 case IFM_1000_T: /* full-duplex only */ 393 link |= NFE_MEDIA_1000T; 394 seed |= NFE_SEED_1000T; 395 phy |= NFE_PHY_1000T; 396 break; 397 case IFM_100_TX: 398 link |= NFE_MEDIA_100TX; 399 seed |= NFE_SEED_100TX; 400 phy |= NFE_PHY_100TX; 401 break; 402 case IFM_10_T: 403 link |= NFE_MEDIA_10T; 404 seed |= NFE_SEED_10T; 405 break; 406 } 407 408 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 409 410 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 411 NFE_WRITE(sc, NFE_MISC1, misc); 412 NFE_WRITE(sc, NFE_LINKSPEED, link); 413 } 414 415 int 416 nfe_miibus_readreg(struct device *dev, int phy, int reg) 417 { 418 struct nfe_softc *sc = (struct nfe_softc *)dev; 419 uint32_t val; 420 int ntries; 421 422 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 423 424 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 425 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 426 DELAY(100); 427 } 428 429 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 430 431 for (ntries = 0; ntries < 1000; ntries++) { 432 DELAY(100); 433 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 434 break; 435 } 436 if (ntries == 1000) { 437 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 438 sc->sc_dev.dv_xname)); 439 return 0; 440 } 441 442 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 443 DPRINTFN(2, ("%s: could not read PHY\n", 444 sc->sc_dev.dv_xname)); 445 return 0; 446 } 447 448 val = NFE_READ(sc, NFE_PHY_DATA); 449 if (val != 0xffffffff && val != 0) 450 sc->mii_phyaddr = phy; 451 452 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 453 sc->sc_dev.dv_xname, phy, reg, val)); 454 455 return val; 456 } 457 458 void 459 nfe_miibus_writereg(struct device *dev, int phy, int reg, int val) 460 { 461 struct nfe_softc *sc = (struct nfe_softc *)dev; 462 uint32_t ctl; 463 int ntries; 464 465 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 466 467 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 468 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 469 DELAY(100); 470 } 471 472 NFE_WRITE(sc, NFE_PHY_DATA, val); 473 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 474 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 475 476 for (ntries = 0; ntries < 1000; ntries++) { 477 DELAY(100); 478 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 479 break; 480 } 481 #ifdef NFE_DEBUG 482 if (nfedebug >= 2 && ntries == 1000) 483 printf("could not write to PHY\n"); 484 #endif 485 } 486 487 int 488 nfe_intr(void *arg) 489 { 490 struct nfe_softc *sc = arg; 491 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 492 uint32_t r; 493 int handled; 494 495 if ((ifp->if_flags & IFF_UP) == 0) 496 return 0; 497 498 handled = 0; 499 500 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 501 502 for (;;) { 503 r = NFE_READ(sc, NFE_IRQ_STATUS); 504 if ((r & NFE_IRQ_WANTED) == 0) 505 break; 506 507 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 508 handled = 1; 509 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 510 511 if ((r & (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX)) 512 != 0) { 513 /* check Rx ring */ 514 nfe_rxeof(sc); 515 } 516 517 if ((r & (NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE)) 518 != 0) { 519 /* check Tx ring */ 520 nfe_txeof(sc); 521 } 522 523 if ((r & NFE_IRQ_LINK) != 0) { 524 NFE_READ(sc, NFE_PHY_STATUS); 525 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 526 DPRINTF(("%s: link state changed\n", 527 sc->sc_dev.dv_xname)); 528 } 529 } 530 531 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 532 533 if (handled && !IF_IS_EMPTY(&ifp->if_snd)) 534 nfe_start(ifp); 535 536 return handled; 537 } 538 539 int 540 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 541 { 542 struct nfe_softc *sc = ifp->if_softc; 543 struct ifreq *ifr = (struct ifreq *)data; 544 struct ifaddr *ifa = (struct ifaddr *)data; 545 int s, error = 0; 546 547 s = splnet(); 548 549 switch (cmd) { 550 case SIOCSIFADDR: 551 ifp->if_flags |= IFF_UP; 552 nfe_init(ifp); 553 switch (ifa->ifa_addr->sa_family) { 554 #ifdef INET 555 case AF_INET: 556 arp_ifinit(ifp, ifa); 557 break; 558 #endif 559 default: 560 break; 561 } 562 break; 563 case SIOCSIFMTU: 564 if (ifr->ifr_mtu < ETHERMIN || 565 ((sc->sc_flags & NFE_USE_JUMBO) && 566 ifr->ifr_mtu > ETHERMTU_JUMBO) || 567 (!(sc->sc_flags & NFE_USE_JUMBO) && 568 ifr->ifr_mtu > ETHERMTU)) 569 error = EINVAL; 570 else if (ifp->if_mtu != ifr->ifr_mtu) 571 ifp->if_mtu = ifr->ifr_mtu; 572 break; 573 case SIOCSIFFLAGS: 574 if (ifp->if_flags & IFF_UP) { 575 /* 576 * If only the PROMISC or ALLMULTI flag changes, then 577 * don't do a full re-init of the chip, just update 578 * the Rx filter. 579 */ 580 if ((ifp->if_flags & IFF_RUNNING) && 581 ((ifp->if_flags ^ sc->sc_if_flags) & 582 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 583 nfe_setmulti(sc); 584 else 585 nfe_init(ifp); 586 } else { 587 if (ifp->if_flags & IFF_RUNNING) 588 nfe_stop(ifp, 1); 589 } 590 sc->sc_if_flags = ifp->if_flags; 591 break; 592 case SIOCADDMULTI: 593 case SIOCDELMULTI: 594 error = (cmd == SIOCADDMULTI) ? 595 ether_addmulti(ifr, &sc->sc_ethercom) : 596 ether_delmulti(ifr, &sc->sc_ethercom); 597 598 if (error == ENETRESET) { 599 if (ifp->if_flags & IFF_RUNNING) 600 nfe_setmulti(sc); 601 error = 0; 602 } 603 break; 604 case SIOCSIFMEDIA: 605 case SIOCGIFMEDIA: 606 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 607 break; 608 default: 609 error = ether_ioctl(ifp, cmd, data); 610 if (error == ENETRESET) { 611 if (ifp->if_flags & IFF_RUNNING) 612 nfe_setmulti(sc); 613 error = 0; 614 } 615 break; 616 617 } 618 619 splx(s); 620 621 return error; 622 } 623 624 void 625 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 626 { 627 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 628 (char *)desc32 - (char *)sc->txq.desc32, 629 sizeof (struct nfe_desc32), ops); 630 } 631 632 void 633 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 634 { 635 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 636 (char *)desc64 - (char *)sc->txq.desc64, 637 sizeof (struct nfe_desc64), ops); 638 } 639 640 void 641 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 642 { 643 if (end > start) { 644 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 645 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 646 (char *)&sc->txq.desc32[end] - 647 (char *)&sc->txq.desc32[start], ops); 648 return; 649 } 650 /* sync from 'start' to end of ring */ 651 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 652 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 653 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 654 (char *)&sc->txq.desc32[start], ops); 655 656 /* sync from start of ring to 'end' */ 657 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 658 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 659 } 660 661 void 662 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 663 { 664 if (end > start) { 665 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 666 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 667 (char *)&sc->txq.desc64[end] - 668 (char *)&sc->txq.desc64[start], ops); 669 return; 670 } 671 /* sync from 'start' to end of ring */ 672 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 673 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 674 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 675 (char *)&sc->txq.desc64[start], ops); 676 677 /* sync from start of ring to 'end' */ 678 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 679 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 680 } 681 682 void 683 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 684 { 685 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 686 (char *)desc32 - (char *)sc->rxq.desc32, 687 sizeof (struct nfe_desc32), ops); 688 } 689 690 void 691 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 692 { 693 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 694 (char *)desc64 - (char *)sc->rxq.desc64, 695 sizeof (struct nfe_desc64), ops); 696 } 697 698 void 699 nfe_rxeof(struct nfe_softc *sc) 700 { 701 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 702 struct nfe_desc32 *desc32; 703 struct nfe_desc64 *desc64; 704 struct nfe_rx_data *data; 705 struct nfe_jbuf *jbuf; 706 struct mbuf *m, *mnew; 707 bus_addr_t physaddr; 708 uint16_t flags; 709 int error, len, i; 710 711 desc32 = NULL; 712 desc64 = NULL; 713 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 714 data = &sc->rxq.data[i]; 715 716 if (sc->sc_flags & NFE_40BIT_ADDR) { 717 desc64 = &sc->rxq.desc64[i]; 718 nfe_rxdesc64_sync(sc, desc64, 719 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 720 721 flags = le16toh(desc64->flags); 722 len = le16toh(desc64->length) & 0x3fff; 723 } else { 724 desc32 = &sc->rxq.desc32[i]; 725 nfe_rxdesc32_sync(sc, desc32, 726 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 727 728 flags = le16toh(desc32->flags); 729 len = le16toh(desc32->length) & 0x3fff; 730 } 731 732 if ((flags & NFE_RX_READY) != 0) 733 break; 734 735 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 736 if ((flags & NFE_RX_VALID_V1) == 0) 737 goto skip; 738 739 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 740 flags &= ~NFE_RX_ERROR; 741 len--; /* fix buffer length */ 742 } 743 } else { 744 if ((flags & NFE_RX_VALID_V2) == 0) 745 goto skip; 746 747 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 748 flags &= ~NFE_RX_ERROR; 749 len--; /* fix buffer length */ 750 } 751 } 752 753 if (flags & NFE_RX_ERROR) { 754 ifp->if_ierrors++; 755 goto skip; 756 } 757 758 /* 759 * Try to allocate a new mbuf for this ring element and load 760 * it before processing the current mbuf. If the ring element 761 * cannot be loaded, drop the received packet and reuse the 762 * old mbuf. In the unlikely case that the old mbuf can't be 763 * reloaded either, explicitly panic. 764 */ 765 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 766 if (mnew == NULL) { 767 ifp->if_ierrors++; 768 goto skip; 769 } 770 771 if (sc->sc_flags & NFE_USE_JUMBO) { 772 if ((jbuf = nfe_jalloc(sc)) == NULL) { 773 m_freem(mnew); 774 ifp->if_ierrors++; 775 goto skip; 776 } 777 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 778 779 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 780 mtod(data->m, char *) - (char *)sc->rxq.jpool, 781 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 782 783 physaddr = jbuf->physaddr; 784 } else { 785 MCLGET(mnew, M_DONTWAIT); 786 if ((mnew->m_flags & M_EXT) == 0) { 787 m_freem(mnew); 788 ifp->if_ierrors++; 789 goto skip; 790 } 791 792 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 793 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 794 bus_dmamap_unload(sc->sc_dmat, data->map); 795 796 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, 797 mnew, BUS_DMA_READ | BUS_DMA_NOWAIT); 798 if (error != 0) { 799 m_freem(mnew); 800 801 /* try to reload the old mbuf */ 802 error = bus_dmamap_load_mbuf(sc->sc_dmat, 803 data->map, data->m, 804 BUS_DMA_READ | BUS_DMA_NOWAIT); 805 if (error != 0) { 806 /* very unlikely that it will fail.. */ 807 panic("%s: could not load old rx mbuf", 808 sc->sc_dev.dv_xname); 809 } 810 ifp->if_ierrors++; 811 goto skip; 812 } 813 physaddr = data->map->dm_segs[0].ds_addr; 814 } 815 816 /* 817 * New mbuf successfully loaded, update Rx ring and continue 818 * processing. 819 */ 820 m = data->m; 821 data->m = mnew; 822 823 /* finalize mbuf */ 824 m->m_pkthdr.len = m->m_len = len; 825 m->m_pkthdr.rcvif = ifp; 826 827 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 828 /* 829 * XXX 830 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 831 */ 832 if (flags & NFE_RX_IP_CSUMOK) { 833 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 834 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 835 sc->sc_dev.dv_xname)); 836 } 837 /* 838 * XXX 839 * no way to check M_CSUM_TCP_UDP_BAD or 840 * other protocols? 841 */ 842 if (flags & NFE_RX_UDP_CSUMOK) { 843 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 844 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 845 sc->sc_dev.dv_xname)); 846 } else if (flags & NFE_RX_TCP_CSUMOK) { 847 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 848 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 849 sc->sc_dev.dv_xname)); 850 } 851 } 852 853 #if NBPFILTER > 0 854 if (ifp->if_bpf) 855 bpf_mtap(ifp->if_bpf, m); 856 #endif 857 ifp->if_ipackets++; 858 (*ifp->if_input)(ifp, m); 859 860 /* update mapping address in h/w descriptor */ 861 if (sc->sc_flags & NFE_40BIT_ADDR) { 862 #if defined(__LP64__) 863 desc64->physaddr[0] = htole32(physaddr >> 32); 864 #endif 865 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 866 } else { 867 desc32->physaddr = htole32(physaddr); 868 } 869 870 skip: 871 if (sc->sc_flags & NFE_40BIT_ADDR) { 872 desc64->length = htole16(sc->rxq.bufsz); 873 desc64->flags = htole16(NFE_RX_READY); 874 875 nfe_rxdesc64_sync(sc, desc64, 876 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 877 } else { 878 desc32->length = htole16(sc->rxq.bufsz); 879 desc32->flags = htole16(NFE_RX_READY); 880 881 nfe_rxdesc32_sync(sc, desc32, 882 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 883 } 884 } 885 /* update current RX pointer */ 886 sc->rxq.cur = i; 887 } 888 889 void 890 nfe_txeof(struct nfe_softc *sc) 891 { 892 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 893 struct nfe_desc32 *desc32; 894 struct nfe_desc64 *desc64; 895 struct nfe_tx_data *data = NULL; 896 int i; 897 uint16_t flags; 898 899 for (i = sc->txq.next; 900 sc->txq.queued > 0; 901 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 902 if (sc->sc_flags & NFE_40BIT_ADDR) { 903 desc64 = &sc->txq.desc64[i]; 904 nfe_txdesc64_sync(sc, desc64, 905 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 906 907 flags = le16toh(desc64->flags); 908 } else { 909 desc32 = &sc->txq.desc32[i]; 910 nfe_txdesc32_sync(sc, desc32, 911 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 912 913 flags = le16toh(desc32->flags); 914 } 915 916 if ((flags & NFE_TX_VALID) != 0) 917 break; 918 919 data = &sc->txq.data[i]; 920 921 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 922 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 923 data->m == NULL) 924 continue; 925 926 if ((flags & NFE_TX_ERROR_V1) != 0) { 927 printf("%s: tx v1 error 0x%04x\n", 928 sc->sc_dev.dv_xname, flags); 929 ifp->if_oerrors++; 930 } else 931 ifp->if_opackets++; 932 } else { 933 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 934 data->m == NULL) 935 continue; 936 937 if ((flags & NFE_TX_ERROR_V2) != 0) { 938 printf("%s: tx v2 error 0x%04x\n", 939 sc->sc_dev.dv_xname, flags); 940 ifp->if_oerrors++; 941 } else 942 ifp->if_opackets++; 943 } 944 945 if (data->m == NULL) { /* should not get there */ 946 printf("%s: last fragment bit w/o associated mbuf!\n", 947 sc->sc_dev.dv_xname); 948 continue; 949 } 950 951 /* last fragment of the mbuf chain transmitted */ 952 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 953 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 954 bus_dmamap_unload(sc->sc_dmat, data->active); 955 m_freem(data->m); 956 data->m = NULL; 957 } 958 959 sc->txq.next = i; 960 961 if (sc->txq.queued < NFE_TX_RING_COUNT) { 962 /* at least one slot freed */ 963 ifp->if_flags &= ~IFF_OACTIVE; 964 } 965 966 if (sc->txq.queued == 0) { 967 /* all queued packets are sent */ 968 ifp->if_timer = 0; 969 } 970 } 971 972 int 973 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 974 { 975 struct nfe_desc32 *desc32; 976 struct nfe_desc64 *desc64; 977 struct nfe_tx_data *data; 978 bus_dmamap_t map; 979 uint16_t flags, csumflags; 980 #if NVLAN > 0 981 struct m_tag *mtag; 982 uint32_t vtag = 0; 983 #endif 984 int error, i, first; 985 986 desc32 = NULL; 987 desc64 = NULL; 988 data = NULL; 989 990 flags = 0; 991 csumflags = 0; 992 first = sc->txq.cur; 993 994 map = sc->txq.data[first].map; 995 996 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 997 if (error != 0) { 998 printf("%s: could not map mbuf (error %d)\n", 999 sc->sc_dev.dv_xname, error); 1000 return error; 1001 } 1002 1003 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1004 bus_dmamap_unload(sc->sc_dmat, map); 1005 return ENOBUFS; 1006 } 1007 1008 #if NVLAN > 0 1009 /* setup h/w VLAN tagging */ 1010 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1011 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1012 #endif 1013 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1014 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1015 csumflags |= NFE_TX_IP_CSUM; 1016 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1017 csumflags |= NFE_TX_TCP_UDP_CSUM; 1018 } 1019 1020 for (i = 0; i < map->dm_nsegs; i++) { 1021 data = &sc->txq.data[sc->txq.cur]; 1022 1023 if (sc->sc_flags & NFE_40BIT_ADDR) { 1024 desc64 = &sc->txq.desc64[sc->txq.cur]; 1025 #if defined(__LP64__) 1026 desc64->physaddr[0] = 1027 htole32(map->dm_segs[i].ds_addr >> 32); 1028 #endif 1029 desc64->physaddr[1] = 1030 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1031 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1032 desc64->flags = htole16(flags); 1033 desc64->vtag = 0; 1034 } else { 1035 desc32 = &sc->txq.desc32[sc->txq.cur]; 1036 1037 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1038 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1039 desc32->flags = htole16(flags); 1040 } 1041 1042 /* 1043 * Setting of the valid bit in the first descriptor is 1044 * deferred until the whole chain is fully setup. 1045 */ 1046 flags |= NFE_TX_VALID; 1047 1048 sc->txq.queued++; 1049 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1050 } 1051 1052 /* the whole mbuf chain has been setup */ 1053 if (sc->sc_flags & NFE_40BIT_ADDR) { 1054 /* fix last descriptor */ 1055 flags |= NFE_TX_LASTFRAG_V2; 1056 desc64->flags = htole16(flags); 1057 1058 /* Checksum flags and vtag belong to the first fragment only. */ 1059 #if NVLAN > 0 1060 sc->txq.desc64[first].vtag = htole32(vtag); 1061 #endif 1062 sc->txq.desc64[first].flags |= htole16(csumflags); 1063 1064 /* finally, set the valid bit in the first descriptor */ 1065 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1066 } else { 1067 /* fix last descriptor */ 1068 if (sc->sc_flags & NFE_JUMBO_SUP) 1069 flags |= NFE_TX_LASTFRAG_V2; 1070 else 1071 flags |= NFE_TX_LASTFRAG_V1; 1072 desc32->flags = htole16(flags); 1073 1074 /* Checksum flags belong to the first fragment only. */ 1075 sc->txq.desc32[first].flags |= htole16(csumflags); 1076 1077 /* finally, set the valid bit in the first descriptor */ 1078 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1079 } 1080 1081 data->m = m0; 1082 data->active = map; 1083 1084 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1085 BUS_DMASYNC_PREWRITE); 1086 1087 return 0; 1088 } 1089 1090 void 1091 nfe_start(struct ifnet *ifp) 1092 { 1093 struct nfe_softc *sc = ifp->if_softc; 1094 int old = sc->txq.queued; 1095 struct mbuf *m0; 1096 1097 for (;;) { 1098 IFQ_POLL(&ifp->if_snd, m0); 1099 if (m0 == NULL) 1100 break; 1101 1102 if (nfe_encap(sc, m0) != 0) { 1103 ifp->if_flags |= IFF_OACTIVE; 1104 break; 1105 } 1106 1107 /* packet put in h/w queue, remove from s/w queue */ 1108 IFQ_DEQUEUE(&ifp->if_snd, m0); 1109 1110 #if NBPFILTER > 0 1111 if (ifp->if_bpf != NULL) 1112 bpf_mtap(ifp->if_bpf, m0); 1113 #endif 1114 } 1115 1116 if (sc->txq.queued != old) { 1117 /* packets are queued */ 1118 if (sc->sc_flags & NFE_40BIT_ADDR) 1119 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1120 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1121 else 1122 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1123 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1124 /* kick Tx */ 1125 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1126 1127 /* 1128 * Set a timeout in case the chip goes out to lunch. 1129 */ 1130 ifp->if_timer = 5; 1131 } 1132 } 1133 1134 void 1135 nfe_watchdog(struct ifnet *ifp) 1136 { 1137 struct nfe_softc *sc = ifp->if_softc; 1138 1139 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1140 1141 ifp->if_flags &= ~IFF_RUNNING; 1142 nfe_init(ifp); 1143 1144 ifp->if_oerrors++; 1145 } 1146 1147 int 1148 nfe_init(struct ifnet *ifp) 1149 { 1150 struct nfe_softc *sc = ifp->if_softc; 1151 uint32_t tmp; 1152 int s; 1153 1154 if (ifp->if_flags & IFF_RUNNING) 1155 return 0; 1156 1157 nfe_stop(ifp, 0); 1158 1159 NFE_WRITE(sc, NFE_TX_UNK, 0); 1160 NFE_WRITE(sc, NFE_STATUS, 0); 1161 1162 sc->rxtxctl = NFE_RXTX_BIT2; 1163 if (sc->sc_flags & NFE_40BIT_ADDR) 1164 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1165 else if (sc->sc_flags & NFE_JUMBO_SUP) 1166 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1167 if (sc->sc_flags & NFE_HW_CSUM) 1168 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1169 #if NVLAN > 0 1170 /* 1171 * Although the adapter is capable of stripping VLAN tags from received 1172 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1173 * purpose. This will be done in software by our network stack. 1174 */ 1175 if (sc->sc_flags & NFE_HW_VLAN) 1176 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1177 #endif 1178 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1179 DELAY(10); 1180 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1181 1182 #if NVLAN 1183 if (sc->sc_flags & NFE_HW_VLAN) 1184 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1185 #endif 1186 1187 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1188 1189 /* set MAC address */ 1190 nfe_set_macaddr(sc, sc->sc_enaddr); 1191 1192 /* tell MAC where rings are in memory */ 1193 #ifdef __LP64__ 1194 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1195 #endif 1196 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1197 #ifdef __LP64__ 1198 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1199 #endif 1200 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1201 1202 NFE_WRITE(sc, NFE_RING_SIZE, 1203 (NFE_RX_RING_COUNT - 1) << 16 | 1204 (NFE_TX_RING_COUNT - 1)); 1205 1206 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1207 1208 /* force MAC to wakeup */ 1209 tmp = NFE_READ(sc, NFE_PWR_STATE); 1210 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1211 DELAY(10); 1212 tmp = NFE_READ(sc, NFE_PWR_STATE); 1213 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1214 1215 s = splnet(); 1216 nfe_intr(sc); /* XXX clear IRQ status registers */ 1217 splx(s); 1218 1219 #if 1 1220 /* configure interrupts coalescing/mitigation */ 1221 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1222 #else 1223 /* no interrupt mitigation: one interrupt per packet */ 1224 NFE_WRITE(sc, NFE_IMTIMER, 970); 1225 #endif 1226 1227 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1228 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1229 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1230 1231 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1232 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1233 1234 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1235 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC); 1236 1237 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1238 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1239 DELAY(10); 1240 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1241 1242 /* set Rx filter */ 1243 nfe_setmulti(sc); 1244 1245 nfe_ifmedia_upd(ifp); 1246 1247 nfe_tick(sc); 1248 1249 /* enable Rx */ 1250 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1251 1252 /* enable Tx */ 1253 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1254 1255 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1256 1257 /* enable interrupts */ 1258 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1259 1260 callout_schedule(&sc->sc_tick_ch, hz); 1261 1262 ifp->if_flags |= IFF_RUNNING; 1263 ifp->if_flags &= ~IFF_OACTIVE; 1264 1265 return 0; 1266 } 1267 1268 void 1269 nfe_stop(struct ifnet *ifp, int disable) 1270 { 1271 struct nfe_softc *sc = ifp->if_softc; 1272 1273 callout_stop(&sc->sc_tick_ch); 1274 1275 ifp->if_timer = 0; 1276 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1277 1278 mii_down(&sc->sc_mii); 1279 1280 /* abort Tx */ 1281 NFE_WRITE(sc, NFE_TX_CTL, 0); 1282 1283 /* disable Rx */ 1284 NFE_WRITE(sc, NFE_RX_CTL, 0); 1285 1286 /* disable interrupts */ 1287 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1288 1289 /* reset Tx and Rx rings */ 1290 nfe_reset_tx_ring(sc, &sc->txq); 1291 nfe_reset_rx_ring(sc, &sc->rxq); 1292 } 1293 1294 int 1295 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1296 { 1297 struct nfe_desc32 *desc32; 1298 struct nfe_desc64 *desc64; 1299 struct nfe_rx_data *data; 1300 struct nfe_jbuf *jbuf; 1301 void **desc; 1302 bus_addr_t physaddr; 1303 int i, nsegs, error, descsize; 1304 1305 if (sc->sc_flags & NFE_40BIT_ADDR) { 1306 desc = (void **)&ring->desc64; 1307 descsize = sizeof (struct nfe_desc64); 1308 } else { 1309 desc = (void **)&ring->desc32; 1310 descsize = sizeof (struct nfe_desc32); 1311 } 1312 1313 ring->cur = ring->next = 0; 1314 ring->bufsz = MCLBYTES; 1315 1316 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1317 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1318 if (error != 0) { 1319 printf("%s: could not create desc DMA map\n", 1320 sc->sc_dev.dv_xname); 1321 goto fail; 1322 } 1323 1324 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1325 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1326 if (error != 0) { 1327 printf("%s: could not allocate DMA memory\n", 1328 sc->sc_dev.dv_xname); 1329 goto fail; 1330 } 1331 1332 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1333 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1334 if (error != 0) { 1335 printf("%s: could not map desc DMA memory\n", 1336 sc->sc_dev.dv_xname); 1337 goto fail; 1338 } 1339 1340 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1341 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1342 if (error != 0) { 1343 printf("%s: could not load desc DMA map\n", 1344 sc->sc_dev.dv_xname); 1345 goto fail; 1346 } 1347 1348 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1349 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1350 1351 if (sc->sc_flags & NFE_USE_JUMBO) { 1352 ring->bufsz = NFE_JBYTES; 1353 if ((error = nfe_jpool_alloc(sc)) != 0) { 1354 printf("%s: could not allocate jumbo frames\n", 1355 sc->sc_dev.dv_xname); 1356 goto fail; 1357 } 1358 } 1359 1360 /* 1361 * Pre-allocate Rx buffers and populate Rx ring. 1362 */ 1363 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1364 data = &sc->rxq.data[i]; 1365 1366 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1367 if (data->m == NULL) { 1368 printf("%s: could not allocate rx mbuf\n", 1369 sc->sc_dev.dv_xname); 1370 error = ENOMEM; 1371 goto fail; 1372 } 1373 1374 if (sc->sc_flags & NFE_USE_JUMBO) { 1375 if ((jbuf = nfe_jalloc(sc)) == NULL) { 1376 printf("%s: could not allocate jumbo buffer\n", 1377 sc->sc_dev.dv_xname); 1378 goto fail; 1379 } 1380 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1381 sc); 1382 1383 physaddr = jbuf->physaddr; 1384 } else { 1385 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1386 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1387 if (error != 0) { 1388 printf("%s: could not create DMA map\n", 1389 sc->sc_dev.dv_xname); 1390 goto fail; 1391 } 1392 MCLGET(data->m, M_DONTWAIT); 1393 if (!(data->m->m_flags & M_EXT)) { 1394 printf("%s: could not allocate mbuf cluster\n", 1395 sc->sc_dev.dv_xname); 1396 error = ENOMEM; 1397 goto fail; 1398 } 1399 1400 error = bus_dmamap_load(sc->sc_dmat, data->map, 1401 mtod(data->m, void *), MCLBYTES, NULL, 1402 BUS_DMA_READ | BUS_DMA_NOWAIT); 1403 if (error != 0) { 1404 printf("%s: could not load rx buf DMA map", 1405 sc->sc_dev.dv_xname); 1406 goto fail; 1407 } 1408 physaddr = data->map->dm_segs[0].ds_addr; 1409 } 1410 1411 if (sc->sc_flags & NFE_40BIT_ADDR) { 1412 desc64 = &sc->rxq.desc64[i]; 1413 #if defined(__LP64__) 1414 desc64->physaddr[0] = htole32(physaddr >> 32); 1415 #endif 1416 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1417 desc64->length = htole16(sc->rxq.bufsz); 1418 desc64->flags = htole16(NFE_RX_READY); 1419 } else { 1420 desc32 = &sc->rxq.desc32[i]; 1421 desc32->physaddr = htole32(physaddr); 1422 desc32->length = htole16(sc->rxq.bufsz); 1423 desc32->flags = htole16(NFE_RX_READY); 1424 } 1425 } 1426 1427 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1428 BUS_DMASYNC_PREWRITE); 1429 1430 return 0; 1431 1432 fail: nfe_free_rx_ring(sc, ring); 1433 return error; 1434 } 1435 1436 void 1437 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1438 { 1439 int i; 1440 1441 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1442 if (sc->sc_flags & NFE_40BIT_ADDR) { 1443 ring->desc64[i].length = htole16(ring->bufsz); 1444 ring->desc64[i].flags = htole16(NFE_RX_READY); 1445 } else { 1446 ring->desc32[i].length = htole16(ring->bufsz); 1447 ring->desc32[i].flags = htole16(NFE_RX_READY); 1448 } 1449 } 1450 1451 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1452 BUS_DMASYNC_PREWRITE); 1453 1454 ring->cur = ring->next = 0; 1455 } 1456 1457 void 1458 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1459 { 1460 struct nfe_rx_data *data; 1461 void *desc; 1462 int i, descsize; 1463 1464 if (sc->sc_flags & NFE_40BIT_ADDR) { 1465 desc = ring->desc64; 1466 descsize = sizeof (struct nfe_desc64); 1467 } else { 1468 desc = ring->desc32; 1469 descsize = sizeof (struct nfe_desc32); 1470 } 1471 1472 if (desc != NULL) { 1473 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1474 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1475 bus_dmamap_unload(sc->sc_dmat, ring->map); 1476 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1477 NFE_RX_RING_COUNT * descsize); 1478 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1479 } 1480 1481 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1482 data = &ring->data[i]; 1483 1484 if (data->map != NULL) { 1485 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1486 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1487 bus_dmamap_unload(sc->sc_dmat, data->map); 1488 bus_dmamap_destroy(sc->sc_dmat, data->map); 1489 } 1490 if (data->m != NULL) 1491 m_freem(data->m); 1492 } 1493 } 1494 1495 struct nfe_jbuf * 1496 nfe_jalloc(struct nfe_softc *sc) 1497 { 1498 struct nfe_jbuf *jbuf; 1499 1500 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1501 if (jbuf == NULL) 1502 return NULL; 1503 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1504 return jbuf; 1505 } 1506 1507 /* 1508 * This is called automatically by the network stack when the mbuf is freed. 1509 * Caution must be taken that the NIC might be reset by the time the mbuf is 1510 * freed. 1511 */ 1512 void 1513 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1514 { 1515 struct nfe_softc *sc = arg; 1516 struct nfe_jbuf *jbuf; 1517 int i; 1518 1519 /* find the jbuf from the base pointer */ 1520 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1521 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1522 printf("%s: request to free a buffer (%p) not managed by us\n", 1523 sc->sc_dev.dv_xname, buf); 1524 return; 1525 } 1526 jbuf = &sc->rxq.jbuf[i]; 1527 1528 /* ..and put it back in the free list */ 1529 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1530 1531 if (m != NULL) 1532 pool_cache_put(&mbpool_cache, m); 1533 } 1534 1535 int 1536 nfe_jpool_alloc(struct nfe_softc *sc) 1537 { 1538 struct nfe_rx_ring *ring = &sc->rxq; 1539 struct nfe_jbuf *jbuf; 1540 bus_addr_t physaddr; 1541 char *buf; 1542 int i, nsegs, error; 1543 1544 /* 1545 * Allocate a big chunk of DMA'able memory. 1546 */ 1547 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1548 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1549 if (error != 0) { 1550 printf("%s: could not create jumbo DMA map\n", 1551 sc->sc_dev.dv_xname); 1552 goto fail; 1553 } 1554 1555 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1556 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1557 if (error != 0) { 1558 printf("%s could not allocate jumbo DMA memory\n", 1559 sc->sc_dev.dv_xname); 1560 goto fail; 1561 } 1562 1563 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1564 &ring->jpool, BUS_DMA_NOWAIT); 1565 if (error != 0) { 1566 printf("%s: could not map jumbo DMA memory\n", 1567 sc->sc_dev.dv_xname); 1568 goto fail; 1569 } 1570 1571 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1572 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1573 if (error != 0) { 1574 printf("%s: could not load jumbo DMA map\n", 1575 sc->sc_dev.dv_xname); 1576 goto fail; 1577 } 1578 1579 /* ..and split it into 9KB chunks */ 1580 SLIST_INIT(&ring->jfreelist); 1581 1582 buf = ring->jpool; 1583 physaddr = ring->jmap->dm_segs[0].ds_addr; 1584 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1585 jbuf = &ring->jbuf[i]; 1586 1587 jbuf->buf = buf; 1588 jbuf->physaddr = physaddr; 1589 1590 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1591 1592 buf += NFE_JBYTES; 1593 physaddr += NFE_JBYTES; 1594 } 1595 1596 return 0; 1597 1598 fail: nfe_jpool_free(sc); 1599 return error; 1600 } 1601 1602 void 1603 nfe_jpool_free(struct nfe_softc *sc) 1604 { 1605 struct nfe_rx_ring *ring = &sc->rxq; 1606 1607 if (ring->jmap != NULL) { 1608 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1609 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1610 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1611 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1612 } 1613 if (ring->jpool != NULL) { 1614 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1615 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1616 } 1617 } 1618 1619 int 1620 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1621 { 1622 int i, nsegs, error; 1623 void **desc; 1624 int descsize; 1625 1626 if (sc->sc_flags & NFE_40BIT_ADDR) { 1627 desc = (void **)&ring->desc64; 1628 descsize = sizeof (struct nfe_desc64); 1629 } else { 1630 desc = (void **)&ring->desc32; 1631 descsize = sizeof (struct nfe_desc32); 1632 } 1633 1634 ring->queued = 0; 1635 ring->cur = ring->next = 0; 1636 1637 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1638 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1639 1640 if (error != 0) { 1641 printf("%s: could not create desc DMA map\n", 1642 sc->sc_dev.dv_xname); 1643 goto fail; 1644 } 1645 1646 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1647 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1648 if (error != 0) { 1649 printf("%s: could not allocate DMA memory\n", 1650 sc->sc_dev.dv_xname); 1651 goto fail; 1652 } 1653 1654 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1655 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1656 if (error != 0) { 1657 printf("%s: could not map desc DMA memory\n", 1658 sc->sc_dev.dv_xname); 1659 goto fail; 1660 } 1661 1662 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1663 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1664 if (error != 0) { 1665 printf("%s: could not load desc DMA map\n", 1666 sc->sc_dev.dv_xname); 1667 goto fail; 1668 } 1669 1670 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1671 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1672 1673 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1674 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1675 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1676 &ring->data[i].map); 1677 if (error != 0) { 1678 printf("%s: could not create DMA map\n", 1679 sc->sc_dev.dv_xname); 1680 goto fail; 1681 } 1682 } 1683 1684 return 0; 1685 1686 fail: nfe_free_tx_ring(sc, ring); 1687 return error; 1688 } 1689 1690 void 1691 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1692 { 1693 struct nfe_tx_data *data; 1694 int i; 1695 1696 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1697 if (sc->sc_flags & NFE_40BIT_ADDR) 1698 ring->desc64[i].flags = 0; 1699 else 1700 ring->desc32[i].flags = 0; 1701 1702 data = &ring->data[i]; 1703 1704 if (data->m != NULL) { 1705 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1706 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1707 bus_dmamap_unload(sc->sc_dmat, data->active); 1708 m_freem(data->m); 1709 data->m = NULL; 1710 } 1711 } 1712 1713 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1714 BUS_DMASYNC_PREWRITE); 1715 1716 ring->queued = 0; 1717 ring->cur = ring->next = 0; 1718 } 1719 1720 void 1721 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1722 { 1723 struct nfe_tx_data *data; 1724 void *desc; 1725 int i, descsize; 1726 1727 if (sc->sc_flags & NFE_40BIT_ADDR) { 1728 desc = ring->desc64; 1729 descsize = sizeof (struct nfe_desc64); 1730 } else { 1731 desc = ring->desc32; 1732 descsize = sizeof (struct nfe_desc32); 1733 } 1734 1735 if (desc != NULL) { 1736 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1737 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1738 bus_dmamap_unload(sc->sc_dmat, ring->map); 1739 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1740 NFE_TX_RING_COUNT * descsize); 1741 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1742 } 1743 1744 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1745 data = &ring->data[i]; 1746 1747 if (data->m != NULL) { 1748 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1749 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1750 bus_dmamap_unload(sc->sc_dmat, data->active); 1751 m_freem(data->m); 1752 } 1753 } 1754 1755 /* ..and now actually destroy the DMA mappings */ 1756 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1757 data = &ring->data[i]; 1758 if (data->map == NULL) 1759 continue; 1760 bus_dmamap_destroy(sc->sc_dmat, data->map); 1761 } 1762 } 1763 1764 int 1765 nfe_ifmedia_upd(struct ifnet *ifp) 1766 { 1767 struct nfe_softc *sc = ifp->if_softc; 1768 struct mii_data *mii = &sc->sc_mii; 1769 struct mii_softc *miisc; 1770 1771 if (mii->mii_instance != 0) { 1772 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1773 mii_phy_reset(miisc); 1774 } 1775 return mii_mediachg(mii); 1776 } 1777 1778 void 1779 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1780 { 1781 struct nfe_softc *sc = ifp->if_softc; 1782 struct mii_data *mii = &sc->sc_mii; 1783 1784 mii_pollstat(mii); 1785 ifmr->ifm_status = mii->mii_media_status; 1786 ifmr->ifm_active = mii->mii_media_active; 1787 } 1788 1789 void 1790 nfe_setmulti(struct nfe_softc *sc) 1791 { 1792 struct ethercom *ec = &sc->sc_ethercom; 1793 struct ifnet *ifp = &ec->ec_if; 1794 struct ether_multi *enm; 1795 struct ether_multistep step; 1796 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1797 uint32_t filter = NFE_RXFILTER_MAGIC; 1798 int i; 1799 1800 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1801 bzero(addr, ETHER_ADDR_LEN); 1802 bzero(mask, ETHER_ADDR_LEN); 1803 goto done; 1804 } 1805 1806 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1807 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1808 1809 ETHER_FIRST_MULTI(step, ec, enm); 1810 while (enm != NULL) { 1811 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1812 ifp->if_flags |= IFF_ALLMULTI; 1813 bzero(addr, ETHER_ADDR_LEN); 1814 bzero(mask, ETHER_ADDR_LEN); 1815 goto done; 1816 } 1817 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1818 addr[i] &= enm->enm_addrlo[i]; 1819 mask[i] &= ~enm->enm_addrlo[i]; 1820 } 1821 ETHER_NEXT_MULTI(step, enm); 1822 } 1823 for (i = 0; i < ETHER_ADDR_LEN; i++) 1824 mask[i] |= addr[i]; 1825 1826 done: 1827 addr[0] |= 0x01; /* make sure multicast bit is set */ 1828 1829 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1830 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1831 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1832 addr[5] << 8 | addr[4]); 1833 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1834 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1835 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1836 mask[5] << 8 | mask[4]); 1837 1838 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1839 NFE_WRITE(sc, NFE_RXFILTER, filter); 1840 } 1841 1842 void 1843 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1844 { 1845 uint32_t tmp; 1846 1847 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1848 addr[0] = (tmp >> 8) & 0xff; 1849 addr[1] = (tmp & 0xff); 1850 1851 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1852 addr[2] = (tmp >> 24) & 0xff; 1853 addr[3] = (tmp >> 16) & 0xff; 1854 addr[4] = (tmp >> 8) & 0xff; 1855 addr[5] = (tmp & 0xff); 1856 } 1857 1858 void 1859 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1860 { 1861 NFE_WRITE(sc, NFE_MACADDR_LO, 1862 addr[5] << 8 | addr[4]); 1863 NFE_WRITE(sc, NFE_MACADDR_HI, 1864 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1865 } 1866 1867 void 1868 nfe_tick(void *arg) 1869 { 1870 struct nfe_softc *sc = arg; 1871 int s; 1872 1873 s = splnet(); 1874 mii_tick(&sc->sc_mii); 1875 splx(s); 1876 1877 callout_schedule(&sc->sc_tick_ch, hz); 1878 } 1879
Indexes created Tue Sep 30 07:10:03 GMT 2025