if_nfe.c revision 1.16.6.3
1 /* $NetBSD: if_nfe.c,v 1.16.6.3 2007/10/05 00:40:12 joerg Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.52 2006/03/02 09:04:00 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.16.6.3 2007/10/05 00:40:12 joerg Exp $"); 25 26 #include "opt_inet.h" 27 #include "bpfilter.h" 28 #include "vlan.h" 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/types.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/queue.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/socket.h> 41 42 #include <machine/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/pci/if_nfereg.h> 74 #include <dev/pci/if_nfevar.h> 75 76 int nfe_match(struct device *, struct cfdata *, void *); 77 void nfe_attach(struct device *, struct device *, void *); 78 void nfe_power(int, void *); 79 void nfe_miibus_statchg(struct device *); 80 int nfe_miibus_readreg(struct device *, int, int); 81 void nfe_miibus_writereg(struct device *, int, int, int); 82 int nfe_intr(void *); 83 int nfe_ioctl(struct ifnet *, u_long, void *); 84 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 85 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 86 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 87 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 88 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 89 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 90 void nfe_rxeof(struct nfe_softc *); 91 void nfe_txeof(struct nfe_softc *); 92 int nfe_encap(struct nfe_softc *, struct mbuf *); 93 void nfe_start(struct ifnet *); 94 void nfe_watchdog(struct ifnet *); 95 int nfe_init(struct ifnet *); 96 void nfe_stop(struct ifnet *, int); 97 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 98 void nfe_jfree(struct mbuf *, void *, size_t, void *); 99 int nfe_jpool_alloc(struct nfe_softc *); 100 void nfe_jpool_free(struct nfe_softc *); 101 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 102 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 105 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 int nfe_ifmedia_upd(struct ifnet *); 108 void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 109 void nfe_setmulti(struct nfe_softc *); 110 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 111 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 112 void nfe_tick(void *); 113 114 CFATTACH_DECL(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, NULL, NULL); 115 116 /*#define NFE_NO_JUMBO*/ 117 118 #ifdef NFE_DEBUG 119 int nfedebug = 0; 120 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 121 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 122 #else 123 #define DPRINTF(x) 124 #define DPRINTFN(n,x) 125 #endif 126 127 /* deal with naming differences */ 128 129 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 130 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 134 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 135 136 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 137 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 140 141 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 142 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 145 146 #ifdef _LP64 147 #define __LP64__ 1 148 #endif 149 150 const struct nfe_product { 151 pci_vendor_id_t vendor; 152 pci_product_id_t product; 153 } nfe_devices[] = { 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 155 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 } 177 }; 178 179 int 180 nfe_match(struct device *dev, struct cfdata *match, void *aux) 181 { 182 struct pci_attach_args *pa = aux; 183 const struct nfe_product *np; 184 int i; 185 186 for (i = 0; i < sizeof(nfe_devices) / sizeof(nfe_devices[0]); i++) { 187 np = &nfe_devices[i]; 188 if (PCI_VENDOR(pa->pa_id) == np->vendor && 189 PCI_PRODUCT(pa->pa_id) == np->product) 190 return 1; 191 } 192 return 0; 193 } 194 195 void 196 nfe_attach(struct device *parent, struct device *self, void *aux) 197 { 198 struct nfe_softc *sc = (struct nfe_softc *)self; 199 struct pci_attach_args *pa = aux; 200 pci_chipset_tag_t pc = pa->pa_pc; 201 pci_intr_handle_t ih; 202 const char *intrstr; 203 struct ifnet *ifp; 204 bus_size_t memsize; 205 pcireg_t memtype; 206 char devinfo[256]; 207 pnp_status_t pnp_status; 208 209 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 210 aprint_normal(": %s (rev. 0x%02x)\n", 211 devinfo, PCI_REVISION(pa->pa_class)); 212 213 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 214 switch (memtype) { 215 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 216 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 217 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 218 &sc->sc_memh, NULL, &memsize) == 0) 219 break; 220 /* FALLTHROUGH */ 221 default: 222 printf("%s: could not map mem space\n", sc->sc_dev.dv_xname); 223 return; 224 } 225 226 if (pci_intr_map(pa, &ih) != 0) { 227 printf("%s: could not map interrupt\n", sc->sc_dev.dv_xname); 228 return; 229 } 230 231 intrstr = pci_intr_string(pc, ih); 232 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 233 if (sc->sc_ih == NULL) { 234 printf("%s: could not establish interrupt", 235 sc->sc_dev.dv_xname); 236 if (intrstr != NULL) 237 printf(" at %s", intrstr); 238 printf("\n"); 239 return; 240 } 241 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 242 243 sc->sc_dmat = pa->pa_dmat; 244 245 nfe_get_macaddr(sc, sc->sc_enaddr); 246 printf("%s: Ethernet address %s\n", 247 sc->sc_dev.dv_xname, ether_sprintf(sc->sc_enaddr)); 248 249 sc->sc_flags = 0; 250 251 switch (PCI_PRODUCT(pa->pa_id)) { 252 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 253 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 254 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 255 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 256 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 257 break; 258 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 259 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 260 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 261 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 262 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 263 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 264 sc->sc_flags |= NFE_40BIT_ADDR; 265 break; 266 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 267 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 268 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 269 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 270 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 271 break; 272 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 273 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 274 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 275 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 276 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 277 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 278 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 279 NFE_HW_VLAN; 280 break; 281 } 282 283 #ifndef NFE_NO_JUMBO 284 /* enable jumbo frames for adapters that support it */ 285 if (sc->sc_flags & NFE_JUMBO_SUP) 286 sc->sc_flags |= NFE_USE_JUMBO; 287 #endif 288 289 /* 290 * Allocate Tx and Rx rings. 291 */ 292 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 293 printf("%s: could not allocate Tx ring\n", 294 sc->sc_dev.dv_xname); 295 return; 296 } 297 298 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 299 printf("%s: could not allocate Rx ring\n", 300 sc->sc_dev.dv_xname); 301 nfe_free_tx_ring(sc, &sc->txq); 302 return; 303 } 304 305 ifp = &sc->sc_ethercom.ec_if; 306 ifp->if_softc = sc; 307 ifp->if_mtu = ETHERMTU; 308 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 309 ifp->if_ioctl = nfe_ioctl; 310 ifp->if_start = nfe_start; 311 ifp->if_stop = nfe_stop; 312 ifp->if_watchdog = nfe_watchdog; 313 ifp->if_init = nfe_init; 314 ifp->if_baudrate = IF_Gbps(1); 315 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 316 IFQ_SET_READY(&ifp->if_snd); 317 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 318 319 #if NVLAN > 0 320 if (sc->sc_flags & NFE_HW_VLAN) 321 sc->sc_ethercom.ec_capabilities |= 322 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 323 #endif 324 if (sc->sc_flags & NFE_HW_CSUM) { 325 ifp->if_capabilities |= 326 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 327 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 328 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 329 } 330 331 sc->sc_mii.mii_ifp = ifp; 332 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 333 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 334 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 335 336 ifmedia_init(&sc->sc_mii.mii_media, 0, nfe_ifmedia_upd, 337 nfe_ifmedia_sts); 338 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 339 MII_OFFSET_ANY, 0); 340 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 341 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 342 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 343 0, NULL); 344 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 345 } else 346 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 347 348 if_attach(ifp); 349 ether_ifattach(ifp, sc->sc_enaddr); 350 351 callout_init(&sc->sc_tick_ch, 0); 352 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 353 354 pnp_status = pci_net_generic_power_register(self, 355 pa->pa_pc, pa->pa_tag, ifp, NULL, NULL); 356 if (pnp_status != PNP_STATUS_SUCCESS) { 357 aprint_error_dev(self, "couldn't establish power handler\n"); 358 } 359 } 360 361 void 362 nfe_miibus_statchg(struct device *dev) 363 { 364 struct nfe_softc *sc = (struct nfe_softc *)dev; 365 struct mii_data *mii = &sc->sc_mii; 366 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 367 368 phy = NFE_READ(sc, NFE_PHY_IFACE); 369 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 370 371 seed = NFE_READ(sc, NFE_RNDSEED); 372 seed &= ~NFE_SEED_MASK; 373 374 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 375 phy |= NFE_PHY_HDX; /* half-duplex */ 376 misc |= NFE_MISC1_HDX; 377 } 378 379 switch (IFM_SUBTYPE(mii->mii_media_active)) { 380 case IFM_1000_T: /* full-duplex only */ 381 link |= NFE_MEDIA_1000T; 382 seed |= NFE_SEED_1000T; 383 phy |= NFE_PHY_1000T; 384 break; 385 case IFM_100_TX: 386 link |= NFE_MEDIA_100TX; 387 seed |= NFE_SEED_100TX; 388 phy |= NFE_PHY_100TX; 389 break; 390 case IFM_10_T: 391 link |= NFE_MEDIA_10T; 392 seed |= NFE_SEED_10T; 393 break; 394 } 395 396 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 397 398 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 399 NFE_WRITE(sc, NFE_MISC1, misc); 400 NFE_WRITE(sc, NFE_LINKSPEED, link); 401 } 402 403 int 404 nfe_miibus_readreg(struct device *dev, int phy, int reg) 405 { 406 struct nfe_softc *sc = (struct nfe_softc *)dev; 407 uint32_t val; 408 int ntries; 409 410 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 411 412 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 413 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 414 DELAY(100); 415 } 416 417 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 418 419 for (ntries = 0; ntries < 1000; ntries++) { 420 DELAY(100); 421 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 422 break; 423 } 424 if (ntries == 1000) { 425 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 426 sc->sc_dev.dv_xname)); 427 return 0; 428 } 429 430 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 431 DPRINTFN(2, ("%s: could not read PHY\n", 432 sc->sc_dev.dv_xname)); 433 return 0; 434 } 435 436 val = NFE_READ(sc, NFE_PHY_DATA); 437 if (val != 0xffffffff && val != 0) 438 sc->mii_phyaddr = phy; 439 440 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 441 sc->sc_dev.dv_xname, phy, reg, val)); 442 443 return val; 444 } 445 446 void 447 nfe_miibus_writereg(struct device *dev, int phy, int reg, int val) 448 { 449 struct nfe_softc *sc = (struct nfe_softc *)dev; 450 uint32_t ctl; 451 int ntries; 452 453 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 454 455 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 456 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 457 DELAY(100); 458 } 459 460 NFE_WRITE(sc, NFE_PHY_DATA, val); 461 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 462 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 463 464 for (ntries = 0; ntries < 1000; ntries++) { 465 DELAY(100); 466 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 467 break; 468 } 469 #ifdef NFE_DEBUG 470 if (nfedebug >= 2 && ntries == 1000) 471 printf("could not write to PHY\n"); 472 #endif 473 } 474 475 int 476 nfe_intr(void *arg) 477 { 478 struct nfe_softc *sc = arg; 479 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 480 uint32_t r; 481 int handled; 482 483 if ((ifp->if_flags & IFF_UP) == 0) 484 return 0; 485 486 handled = 0; 487 488 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 489 490 for (;;) { 491 r = NFE_READ(sc, NFE_IRQ_STATUS); 492 if ((r & NFE_IRQ_WANTED) == 0) 493 break; 494 495 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 496 handled = 1; 497 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 498 499 if ((r & (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX)) 500 != 0) { 501 /* check Rx ring */ 502 nfe_rxeof(sc); 503 } 504 505 if ((r & (NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE)) 506 != 0) { 507 /* check Tx ring */ 508 nfe_txeof(sc); 509 } 510 511 if ((r & NFE_IRQ_LINK) != 0) { 512 NFE_READ(sc, NFE_PHY_STATUS); 513 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 514 DPRINTF(("%s: link state changed\n", 515 sc->sc_dev.dv_xname)); 516 } 517 } 518 519 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 520 521 if (handled && !IF_IS_EMPTY(&ifp->if_snd)) 522 nfe_start(ifp); 523 524 return handled; 525 } 526 527 int 528 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 529 { 530 struct nfe_softc *sc = ifp->if_softc; 531 struct ifreq *ifr = (struct ifreq *)data; 532 struct ifaddr *ifa = (struct ifaddr *)data; 533 int s, error = 0; 534 535 s = splnet(); 536 537 switch (cmd) { 538 case SIOCSIFADDR: 539 ifp->if_flags |= IFF_UP; 540 nfe_init(ifp); 541 switch (ifa->ifa_addr->sa_family) { 542 #ifdef INET 543 case AF_INET: 544 arp_ifinit(ifp, ifa); 545 break; 546 #endif 547 default: 548 break; 549 } 550 break; 551 case SIOCSIFMTU: 552 if (ifr->ifr_mtu < ETHERMIN || 553 ((sc->sc_flags & NFE_USE_JUMBO) && 554 ifr->ifr_mtu > ETHERMTU_JUMBO) || 555 (!(sc->sc_flags & NFE_USE_JUMBO) && 556 ifr->ifr_mtu > ETHERMTU)) 557 error = EINVAL; 558 else if (ifp->if_mtu != ifr->ifr_mtu) 559 ifp->if_mtu = ifr->ifr_mtu; 560 break; 561 case SIOCSIFFLAGS: 562 if (ifp->if_flags & IFF_UP) { 563 /* 564 * If only the PROMISC or ALLMULTI flag changes, then 565 * don't do a full re-init of the chip, just update 566 * the Rx filter. 567 */ 568 if ((ifp->if_flags & IFF_RUNNING) && 569 ((ifp->if_flags ^ sc->sc_if_flags) & 570 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 571 nfe_setmulti(sc); 572 else 573 nfe_init(ifp); 574 } else { 575 if (ifp->if_flags & IFF_RUNNING) 576 nfe_stop(ifp, 1); 577 } 578 sc->sc_if_flags = ifp->if_flags; 579 break; 580 case SIOCADDMULTI: 581 case SIOCDELMULTI: 582 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 583 if (ifp->if_flags & IFF_RUNNING) 584 nfe_setmulti(sc); 585 error = 0; 586 } 587 break; 588 case SIOCSIFMEDIA: 589 case SIOCGIFMEDIA: 590 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 591 break; 592 default: 593 error = ether_ioctl(ifp, cmd, data); 594 if (error == ENETRESET) { 595 if (ifp->if_flags & IFF_RUNNING) 596 nfe_setmulti(sc); 597 error = 0; 598 } 599 break; 600 601 } 602 603 splx(s); 604 605 return error; 606 } 607 608 void 609 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 610 { 611 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 612 (char *)desc32 - (char *)sc->txq.desc32, 613 sizeof (struct nfe_desc32), ops); 614 } 615 616 void 617 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 618 { 619 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 620 (char *)desc64 - (char *)sc->txq.desc64, 621 sizeof (struct nfe_desc64), ops); 622 } 623 624 void 625 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 626 { 627 if (end > start) { 628 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 629 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 630 (char *)&sc->txq.desc32[end] - 631 (char *)&sc->txq.desc32[start], ops); 632 return; 633 } 634 /* sync from 'start' to end of ring */ 635 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 636 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 637 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 638 (char *)&sc->txq.desc32[start], ops); 639 640 /* sync from start of ring to 'end' */ 641 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 642 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 643 } 644 645 void 646 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 647 { 648 if (end > start) { 649 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 650 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 651 (char *)&sc->txq.desc64[end] - 652 (char *)&sc->txq.desc64[start], ops); 653 return; 654 } 655 /* sync from 'start' to end of ring */ 656 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 657 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 658 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 659 (char *)&sc->txq.desc64[start], ops); 660 661 /* sync from start of ring to 'end' */ 662 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 663 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 664 } 665 666 void 667 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 668 { 669 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 670 (char *)desc32 - (char *)sc->rxq.desc32, 671 sizeof (struct nfe_desc32), ops); 672 } 673 674 void 675 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 676 { 677 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 678 (char *)desc64 - (char *)sc->rxq.desc64, 679 sizeof (struct nfe_desc64), ops); 680 } 681 682 void 683 nfe_rxeof(struct nfe_softc *sc) 684 { 685 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 686 struct nfe_desc32 *desc32; 687 struct nfe_desc64 *desc64; 688 struct nfe_rx_data *data; 689 struct nfe_jbuf *jbuf; 690 struct mbuf *m, *mnew; 691 bus_addr_t physaddr; 692 uint16_t flags; 693 int error, len, i; 694 695 desc32 = NULL; 696 desc64 = NULL; 697 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 698 data = &sc->rxq.data[i]; 699 700 if (sc->sc_flags & NFE_40BIT_ADDR) { 701 desc64 = &sc->rxq.desc64[i]; 702 nfe_rxdesc64_sync(sc, desc64, 703 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 704 705 flags = le16toh(desc64->flags); 706 len = le16toh(desc64->length) & 0x3fff; 707 } else { 708 desc32 = &sc->rxq.desc32[i]; 709 nfe_rxdesc32_sync(sc, desc32, 710 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 711 712 flags = le16toh(desc32->flags); 713 len = le16toh(desc32->length) & 0x3fff; 714 } 715 716 if ((flags & NFE_RX_READY) != 0) 717 break; 718 719 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 720 if ((flags & NFE_RX_VALID_V1) == 0) 721 goto skip; 722 723 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 724 flags &= ~NFE_RX_ERROR; 725 len--; /* fix buffer length */ 726 } 727 } else { 728 if ((flags & NFE_RX_VALID_V2) == 0) 729 goto skip; 730 731 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 732 flags &= ~NFE_RX_ERROR; 733 len--; /* fix buffer length */ 734 } 735 } 736 737 if (flags & NFE_RX_ERROR) { 738 ifp->if_ierrors++; 739 goto skip; 740 } 741 742 /* 743 * Try to allocate a new mbuf for this ring element and load 744 * it before processing the current mbuf. If the ring element 745 * cannot be loaded, drop the received packet and reuse the 746 * old mbuf. In the unlikely case that the old mbuf can't be 747 * reloaded either, explicitly panic. 748 */ 749 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 750 if (mnew == NULL) { 751 ifp->if_ierrors++; 752 goto skip; 753 } 754 755 if (sc->sc_flags & NFE_USE_JUMBO) { 756 physaddr = 757 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 758 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 759 if (len > MCLBYTES) { 760 m_freem(mnew); 761 ifp->if_ierrors++; 762 goto skip1; 763 } 764 MCLGET(mnew, M_DONTWAIT); 765 if ((mnew->m_flags & M_EXT) == 0) { 766 m_freem(mnew); 767 ifp->if_ierrors++; 768 goto skip1; 769 } 770 771 memcpy(mtod(mnew, void *), 772 mtod(data->m, const void *), len); 773 m = mnew; 774 goto mbufcopied; 775 } else { 776 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 777 778 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 779 mtod(data->m, char *) - (char *)sc->rxq.jpool, 780 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 781 782 physaddr = jbuf->physaddr; 783 } 784 } else { 785 MCLGET(mnew, M_DONTWAIT); 786 if ((mnew->m_flags & M_EXT) == 0) { 787 m_freem(mnew); 788 ifp->if_ierrors++; 789 goto skip; 790 } 791 792 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 793 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 794 bus_dmamap_unload(sc->sc_dmat, data->map); 795 796 error = bus_dmamap_load(sc->sc_dmat, data->map, 797 mtod(mnew, void *), MCLBYTES, NULL, 798 BUS_DMA_READ | BUS_DMA_NOWAIT); 799 if (error != 0) { 800 m_freem(mnew); 801 802 /* try to reload the old mbuf */ 803 error = bus_dmamap_load(sc->sc_dmat, data->map, 804 mtod(data->m, void *), MCLBYTES, NULL, 805 BUS_DMA_READ | BUS_DMA_NOWAIT); 806 if (error != 0) { 807 /* very unlikely that it will fail.. */ 808 panic("%s: could not load old rx mbuf", 809 sc->sc_dev.dv_xname); 810 } 811 ifp->if_ierrors++; 812 goto skip; 813 } 814 physaddr = data->map->dm_segs[0].ds_addr; 815 } 816 817 /* 818 * New mbuf successfully loaded, update Rx ring and continue 819 * processing. 820 */ 821 m = data->m; 822 data->m = mnew; 823 824 mbufcopied: 825 /* finalize mbuf */ 826 m->m_pkthdr.len = m->m_len = len; 827 m->m_pkthdr.rcvif = ifp; 828 829 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 830 /* 831 * XXX 832 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 833 */ 834 if (flags & NFE_RX_IP_CSUMOK) { 835 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 836 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 837 sc->sc_dev.dv_xname)); 838 } 839 /* 840 * XXX 841 * no way to check M_CSUM_TCP_UDP_BAD or 842 * other protocols? 843 */ 844 if (flags & NFE_RX_UDP_CSUMOK) { 845 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 846 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 847 sc->sc_dev.dv_xname)); 848 } else if (flags & NFE_RX_TCP_CSUMOK) { 849 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 850 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 851 sc->sc_dev.dv_xname)); 852 } 853 } 854 855 #if NBPFILTER > 0 856 if (ifp->if_bpf) 857 bpf_mtap(ifp->if_bpf, m); 858 #endif 859 ifp->if_ipackets++; 860 (*ifp->if_input)(ifp, m); 861 862 skip1: 863 /* update mapping address in h/w descriptor */ 864 if (sc->sc_flags & NFE_40BIT_ADDR) { 865 #if defined(__LP64__) 866 desc64->physaddr[0] = htole32(physaddr >> 32); 867 #endif 868 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 869 } else { 870 desc32->physaddr = htole32(physaddr); 871 } 872 873 skip: 874 if (sc->sc_flags & NFE_40BIT_ADDR) { 875 desc64->length = htole16(sc->rxq.bufsz); 876 desc64->flags = htole16(NFE_RX_READY); 877 878 nfe_rxdesc64_sync(sc, desc64, 879 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 880 } else { 881 desc32->length = htole16(sc->rxq.bufsz); 882 desc32->flags = htole16(NFE_RX_READY); 883 884 nfe_rxdesc32_sync(sc, desc32, 885 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 886 } 887 } 888 /* update current RX pointer */ 889 sc->rxq.cur = i; 890 } 891 892 void 893 nfe_txeof(struct nfe_softc *sc) 894 { 895 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 896 struct nfe_desc32 *desc32; 897 struct nfe_desc64 *desc64; 898 struct nfe_tx_data *data = NULL; 899 int i; 900 uint16_t flags; 901 902 for (i = sc->txq.next; 903 sc->txq.queued > 0; 904 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 905 if (sc->sc_flags & NFE_40BIT_ADDR) { 906 desc64 = &sc->txq.desc64[i]; 907 nfe_txdesc64_sync(sc, desc64, 908 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 909 910 flags = le16toh(desc64->flags); 911 } else { 912 desc32 = &sc->txq.desc32[i]; 913 nfe_txdesc32_sync(sc, desc32, 914 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 915 916 flags = le16toh(desc32->flags); 917 } 918 919 if ((flags & NFE_TX_VALID) != 0) 920 break; 921 922 data = &sc->txq.data[i]; 923 924 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 925 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 926 data->m == NULL) 927 continue; 928 929 if ((flags & NFE_TX_ERROR_V1) != 0) { 930 printf("%s: tx v1 error 0x%04x\n", 931 sc->sc_dev.dv_xname, flags); 932 ifp->if_oerrors++; 933 } else 934 ifp->if_opackets++; 935 } else { 936 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 937 data->m == NULL) 938 continue; 939 940 if ((flags & NFE_TX_ERROR_V2) != 0) { 941 printf("%s: tx v2 error 0x%04x\n", 942 sc->sc_dev.dv_xname, flags); 943 ifp->if_oerrors++; 944 } else 945 ifp->if_opackets++; 946 } 947 948 if (data->m == NULL) { /* should not get there */ 949 printf("%s: last fragment bit w/o associated mbuf!\n", 950 sc->sc_dev.dv_xname); 951 continue; 952 } 953 954 /* last fragment of the mbuf chain transmitted */ 955 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 956 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 957 bus_dmamap_unload(sc->sc_dmat, data->active); 958 m_freem(data->m); 959 data->m = NULL; 960 } 961 962 sc->txq.next = i; 963 964 if (sc->txq.queued < NFE_TX_RING_COUNT) { 965 /* at least one slot freed */ 966 ifp->if_flags &= ~IFF_OACTIVE; 967 } 968 969 if (sc->txq.queued == 0) { 970 /* all queued packets are sent */ 971 ifp->if_timer = 0; 972 } 973 } 974 975 int 976 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 977 { 978 struct nfe_desc32 *desc32; 979 struct nfe_desc64 *desc64; 980 struct nfe_tx_data *data; 981 bus_dmamap_t map; 982 uint16_t flags, csumflags; 983 #if NVLAN > 0 984 struct m_tag *mtag; 985 uint32_t vtag = 0; 986 #endif 987 int error, i, first; 988 989 desc32 = NULL; 990 desc64 = NULL; 991 data = NULL; 992 993 flags = 0; 994 csumflags = 0; 995 first = sc->txq.cur; 996 997 map = sc->txq.data[first].map; 998 999 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1000 if (error != 0) { 1001 printf("%s: could not map mbuf (error %d)\n", 1002 sc->sc_dev.dv_xname, error); 1003 return error; 1004 } 1005 1006 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1007 bus_dmamap_unload(sc->sc_dmat, map); 1008 return ENOBUFS; 1009 } 1010 1011 #if NVLAN > 0 1012 /* setup h/w VLAN tagging */ 1013 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1014 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1015 #endif 1016 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1017 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1018 csumflags |= NFE_TX_IP_CSUM; 1019 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1020 csumflags |= NFE_TX_TCP_UDP_CSUM; 1021 } 1022 1023 for (i = 0; i < map->dm_nsegs; i++) { 1024 data = &sc->txq.data[sc->txq.cur]; 1025 1026 if (sc->sc_flags & NFE_40BIT_ADDR) { 1027 desc64 = &sc->txq.desc64[sc->txq.cur]; 1028 #if defined(__LP64__) 1029 desc64->physaddr[0] = 1030 htole32(map->dm_segs[i].ds_addr >> 32); 1031 #endif 1032 desc64->physaddr[1] = 1033 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1034 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1035 desc64->flags = htole16(flags); 1036 desc64->vtag = 0; 1037 } else { 1038 desc32 = &sc->txq.desc32[sc->txq.cur]; 1039 1040 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1041 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1042 desc32->flags = htole16(flags); 1043 } 1044 1045 /* 1046 * Setting of the valid bit in the first descriptor is 1047 * deferred until the whole chain is fully setup. 1048 */ 1049 flags |= NFE_TX_VALID; 1050 1051 sc->txq.queued++; 1052 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1053 } 1054 1055 /* the whole mbuf chain has been setup */ 1056 if (sc->sc_flags & NFE_40BIT_ADDR) { 1057 /* fix last descriptor */ 1058 flags |= NFE_TX_LASTFRAG_V2; 1059 desc64->flags = htole16(flags); 1060 1061 /* Checksum flags and vtag belong to the first fragment only. */ 1062 #if NVLAN > 0 1063 sc->txq.desc64[first].vtag = htole32(vtag); 1064 #endif 1065 sc->txq.desc64[first].flags |= htole16(csumflags); 1066 1067 /* finally, set the valid bit in the first descriptor */ 1068 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1069 } else { 1070 /* fix last descriptor */ 1071 if (sc->sc_flags & NFE_JUMBO_SUP) 1072 flags |= NFE_TX_LASTFRAG_V2; 1073 else 1074 flags |= NFE_TX_LASTFRAG_V1; 1075 desc32->flags = htole16(flags); 1076 1077 /* Checksum flags belong to the first fragment only. */ 1078 sc->txq.desc32[first].flags |= htole16(csumflags); 1079 1080 /* finally, set the valid bit in the first descriptor */ 1081 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1082 } 1083 1084 data->m = m0; 1085 data->active = map; 1086 1087 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1088 BUS_DMASYNC_PREWRITE); 1089 1090 return 0; 1091 } 1092 1093 void 1094 nfe_start(struct ifnet *ifp) 1095 { 1096 struct nfe_softc *sc = ifp->if_softc; 1097 int old = sc->txq.queued; 1098 struct mbuf *m0; 1099 1100 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 1101 return; 1102 1103 for (;;) { 1104 IFQ_POLL(&ifp->if_snd, m0); 1105 if (m0 == NULL) 1106 break; 1107 1108 if (nfe_encap(sc, m0) != 0) { 1109 ifp->if_flags |= IFF_OACTIVE; 1110 break; 1111 } 1112 1113 /* packet put in h/w queue, remove from s/w queue */ 1114 IFQ_DEQUEUE(&ifp->if_snd, m0); 1115 1116 #if NBPFILTER > 0 1117 if (ifp->if_bpf != NULL) 1118 bpf_mtap(ifp->if_bpf, m0); 1119 #endif 1120 } 1121 1122 if (sc->txq.queued != old) { 1123 /* packets are queued */ 1124 if (sc->sc_flags & NFE_40BIT_ADDR) 1125 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1126 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1127 else 1128 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1129 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1130 /* kick Tx */ 1131 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1132 1133 /* 1134 * Set a timeout in case the chip goes out to lunch. 1135 */ 1136 ifp->if_timer = 5; 1137 } 1138 } 1139 1140 void 1141 nfe_watchdog(struct ifnet *ifp) 1142 { 1143 struct nfe_softc *sc = ifp->if_softc; 1144 1145 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1146 1147 ifp->if_flags &= ~IFF_RUNNING; 1148 nfe_init(ifp); 1149 1150 ifp->if_oerrors++; 1151 } 1152 1153 int 1154 nfe_init(struct ifnet *ifp) 1155 { 1156 struct nfe_softc *sc = ifp->if_softc; 1157 uint32_t tmp; 1158 int s; 1159 1160 if (ifp->if_flags & IFF_RUNNING) 1161 return 0; 1162 1163 nfe_stop(ifp, 0); 1164 1165 NFE_WRITE(sc, NFE_TX_UNK, 0); 1166 NFE_WRITE(sc, NFE_STATUS, 0); 1167 1168 sc->rxtxctl = NFE_RXTX_BIT2; 1169 if (sc->sc_flags & NFE_40BIT_ADDR) 1170 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1171 else if (sc->sc_flags & NFE_JUMBO_SUP) 1172 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1173 if (sc->sc_flags & NFE_HW_CSUM) 1174 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1175 #if NVLAN > 0 1176 /* 1177 * Although the adapter is capable of stripping VLAN tags from received 1178 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1179 * purpose. This will be done in software by our network stack. 1180 */ 1181 if (sc->sc_flags & NFE_HW_VLAN) 1182 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1183 #endif 1184 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1185 DELAY(10); 1186 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1187 1188 #if NVLAN 1189 if (sc->sc_flags & NFE_HW_VLAN) 1190 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1191 #endif 1192 1193 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1194 1195 /* set MAC address */ 1196 nfe_set_macaddr(sc, sc->sc_enaddr); 1197 1198 /* tell MAC where rings are in memory */ 1199 #ifdef __LP64__ 1200 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1201 #endif 1202 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1203 #ifdef __LP64__ 1204 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1205 #endif 1206 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1207 1208 NFE_WRITE(sc, NFE_RING_SIZE, 1209 (NFE_RX_RING_COUNT - 1) << 16 | 1210 (NFE_TX_RING_COUNT - 1)); 1211 1212 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1213 1214 /* force MAC to wakeup */ 1215 tmp = NFE_READ(sc, NFE_PWR_STATE); 1216 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1217 DELAY(10); 1218 tmp = NFE_READ(sc, NFE_PWR_STATE); 1219 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1220 1221 s = splnet(); 1222 nfe_intr(sc); /* XXX clear IRQ status registers */ 1223 splx(s); 1224 1225 #if 1 1226 /* configure interrupts coalescing/mitigation */ 1227 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1228 #else 1229 /* no interrupt mitigation: one interrupt per packet */ 1230 NFE_WRITE(sc, NFE_IMTIMER, 970); 1231 #endif 1232 1233 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1234 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1235 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1236 1237 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1238 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1239 1240 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1241 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC); 1242 1243 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1244 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1245 DELAY(10); 1246 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1247 1248 /* set Rx filter */ 1249 nfe_setmulti(sc); 1250 1251 nfe_ifmedia_upd(ifp); 1252 1253 nfe_tick(sc); 1254 1255 /* enable Rx */ 1256 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1257 1258 /* enable Tx */ 1259 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1260 1261 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1262 1263 /* enable interrupts */ 1264 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1265 1266 callout_schedule(&sc->sc_tick_ch, hz); 1267 1268 ifp->if_flags |= IFF_RUNNING; 1269 ifp->if_flags &= ~IFF_OACTIVE; 1270 1271 return 0; 1272 } 1273 1274 void 1275 nfe_stop(struct ifnet *ifp, int disable) 1276 { 1277 struct nfe_softc *sc = ifp->if_softc; 1278 1279 callout_stop(&sc->sc_tick_ch); 1280 1281 ifp->if_timer = 0; 1282 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1283 1284 mii_down(&sc->sc_mii); 1285 1286 /* abort Tx */ 1287 NFE_WRITE(sc, NFE_TX_CTL, 0); 1288 1289 /* disable Rx */ 1290 NFE_WRITE(sc, NFE_RX_CTL, 0); 1291 1292 /* disable interrupts */ 1293 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1294 1295 /* reset Tx and Rx rings */ 1296 nfe_reset_tx_ring(sc, &sc->txq); 1297 nfe_reset_rx_ring(sc, &sc->rxq); 1298 } 1299 1300 int 1301 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1302 { 1303 struct nfe_desc32 *desc32; 1304 struct nfe_desc64 *desc64; 1305 struct nfe_rx_data *data; 1306 struct nfe_jbuf *jbuf; 1307 void **desc; 1308 bus_addr_t physaddr; 1309 int i, nsegs, error, descsize; 1310 1311 if (sc->sc_flags & NFE_40BIT_ADDR) { 1312 desc = (void **)&ring->desc64; 1313 descsize = sizeof (struct nfe_desc64); 1314 } else { 1315 desc = (void **)&ring->desc32; 1316 descsize = sizeof (struct nfe_desc32); 1317 } 1318 1319 ring->cur = ring->next = 0; 1320 ring->bufsz = MCLBYTES; 1321 1322 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1323 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1324 if (error != 0) { 1325 printf("%s: could not create desc DMA map\n", 1326 sc->sc_dev.dv_xname); 1327 goto fail; 1328 } 1329 1330 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1331 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1332 if (error != 0) { 1333 printf("%s: could not allocate DMA memory\n", 1334 sc->sc_dev.dv_xname); 1335 goto fail; 1336 } 1337 1338 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1339 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1340 if (error != 0) { 1341 printf("%s: could not map desc DMA memory\n", 1342 sc->sc_dev.dv_xname); 1343 goto fail; 1344 } 1345 1346 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1347 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1348 if (error != 0) { 1349 printf("%s: could not load desc DMA map\n", 1350 sc->sc_dev.dv_xname); 1351 goto fail; 1352 } 1353 1354 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1355 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1356 1357 if (sc->sc_flags & NFE_USE_JUMBO) { 1358 ring->bufsz = NFE_JBYTES; 1359 if ((error = nfe_jpool_alloc(sc)) != 0) { 1360 printf("%s: could not allocate jumbo frames\n", 1361 sc->sc_dev.dv_xname); 1362 goto fail; 1363 } 1364 } 1365 1366 /* 1367 * Pre-allocate Rx buffers and populate Rx ring. 1368 */ 1369 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1370 data = &sc->rxq.data[i]; 1371 1372 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1373 if (data->m == NULL) { 1374 printf("%s: could not allocate rx mbuf\n", 1375 sc->sc_dev.dv_xname); 1376 error = ENOMEM; 1377 goto fail; 1378 } 1379 1380 if (sc->sc_flags & NFE_USE_JUMBO) { 1381 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1382 printf("%s: could not allocate jumbo buffer\n", 1383 sc->sc_dev.dv_xname); 1384 goto fail; 1385 } 1386 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1387 sc); 1388 1389 physaddr = jbuf->physaddr; 1390 } else { 1391 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1392 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1393 if (error != 0) { 1394 printf("%s: could not create DMA map\n", 1395 sc->sc_dev.dv_xname); 1396 goto fail; 1397 } 1398 MCLGET(data->m, M_DONTWAIT); 1399 if (!(data->m->m_flags & M_EXT)) { 1400 printf("%s: could not allocate mbuf cluster\n", 1401 sc->sc_dev.dv_xname); 1402 error = ENOMEM; 1403 goto fail; 1404 } 1405 1406 error = bus_dmamap_load(sc->sc_dmat, data->map, 1407 mtod(data->m, void *), MCLBYTES, NULL, 1408 BUS_DMA_READ | BUS_DMA_NOWAIT); 1409 if (error != 0) { 1410 printf("%s: could not load rx buf DMA map", 1411 sc->sc_dev.dv_xname); 1412 goto fail; 1413 } 1414 physaddr = data->map->dm_segs[0].ds_addr; 1415 } 1416 1417 if (sc->sc_flags & NFE_40BIT_ADDR) { 1418 desc64 = &sc->rxq.desc64[i]; 1419 #if defined(__LP64__) 1420 desc64->physaddr[0] = htole32(physaddr >> 32); 1421 #endif 1422 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1423 desc64->length = htole16(sc->rxq.bufsz); 1424 desc64->flags = htole16(NFE_RX_READY); 1425 } else { 1426 desc32 = &sc->rxq.desc32[i]; 1427 desc32->physaddr = htole32(physaddr); 1428 desc32->length = htole16(sc->rxq.bufsz); 1429 desc32->flags = htole16(NFE_RX_READY); 1430 } 1431 } 1432 1433 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1434 BUS_DMASYNC_PREWRITE); 1435 1436 return 0; 1437 1438 fail: nfe_free_rx_ring(sc, ring); 1439 return error; 1440 } 1441 1442 void 1443 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1444 { 1445 int i; 1446 1447 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1448 if (sc->sc_flags & NFE_40BIT_ADDR) { 1449 ring->desc64[i].length = htole16(ring->bufsz); 1450 ring->desc64[i].flags = htole16(NFE_RX_READY); 1451 } else { 1452 ring->desc32[i].length = htole16(ring->bufsz); 1453 ring->desc32[i].flags = htole16(NFE_RX_READY); 1454 } 1455 } 1456 1457 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1458 BUS_DMASYNC_PREWRITE); 1459 1460 ring->cur = ring->next = 0; 1461 } 1462 1463 void 1464 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1465 { 1466 struct nfe_rx_data *data; 1467 void *desc; 1468 int i, descsize; 1469 1470 if (sc->sc_flags & NFE_40BIT_ADDR) { 1471 desc = ring->desc64; 1472 descsize = sizeof (struct nfe_desc64); 1473 } else { 1474 desc = ring->desc32; 1475 descsize = sizeof (struct nfe_desc32); 1476 } 1477 1478 if (desc != NULL) { 1479 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1480 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1481 bus_dmamap_unload(sc->sc_dmat, ring->map); 1482 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1483 NFE_RX_RING_COUNT * descsize); 1484 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1485 } 1486 1487 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1488 data = &ring->data[i]; 1489 1490 if (data->map != NULL) { 1491 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1492 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1493 bus_dmamap_unload(sc->sc_dmat, data->map); 1494 bus_dmamap_destroy(sc->sc_dmat, data->map); 1495 } 1496 if (data->m != NULL) 1497 m_freem(data->m); 1498 } 1499 } 1500 1501 struct nfe_jbuf * 1502 nfe_jalloc(struct nfe_softc *sc, int i) 1503 { 1504 struct nfe_jbuf *jbuf; 1505 1506 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1507 if (jbuf == NULL) 1508 return NULL; 1509 sc->rxq.jbufmap[i] = 1510 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1511 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1512 return jbuf; 1513 } 1514 1515 /* 1516 * This is called automatically by the network stack when the mbuf is freed. 1517 * Caution must be taken that the NIC might be reset by the time the mbuf is 1518 * freed. 1519 */ 1520 void 1521 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1522 { 1523 struct nfe_softc *sc = arg; 1524 struct nfe_jbuf *jbuf; 1525 int i; 1526 1527 /* find the jbuf from the base pointer */ 1528 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1529 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1530 printf("%s: request to free a buffer (%p) not managed by us\n", 1531 sc->sc_dev.dv_xname, buf); 1532 return; 1533 } 1534 jbuf = &sc->rxq.jbuf[i]; 1535 1536 /* ..and put it back in the free list */ 1537 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1538 1539 if (m != NULL) 1540 pool_cache_put(&mbpool_cache, m); 1541 } 1542 1543 int 1544 nfe_jpool_alloc(struct nfe_softc *sc) 1545 { 1546 struct nfe_rx_ring *ring = &sc->rxq; 1547 struct nfe_jbuf *jbuf; 1548 bus_addr_t physaddr; 1549 char *buf; 1550 int i, nsegs, error; 1551 1552 /* 1553 * Allocate a big chunk of DMA'able memory. 1554 */ 1555 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1556 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1557 if (error != 0) { 1558 printf("%s: could not create jumbo DMA map\n", 1559 sc->sc_dev.dv_xname); 1560 goto fail; 1561 } 1562 1563 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1564 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1565 if (error != 0) { 1566 printf("%s could not allocate jumbo DMA memory\n", 1567 sc->sc_dev.dv_xname); 1568 goto fail; 1569 } 1570 1571 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1572 &ring->jpool, BUS_DMA_NOWAIT); 1573 if (error != 0) { 1574 printf("%s: could not map jumbo DMA memory\n", 1575 sc->sc_dev.dv_xname); 1576 goto fail; 1577 } 1578 1579 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1580 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1581 if (error != 0) { 1582 printf("%s: could not load jumbo DMA map\n", 1583 sc->sc_dev.dv_xname); 1584 goto fail; 1585 } 1586 1587 /* ..and split it into 9KB chunks */ 1588 SLIST_INIT(&ring->jfreelist); 1589 1590 buf = ring->jpool; 1591 physaddr = ring->jmap->dm_segs[0].ds_addr; 1592 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1593 jbuf = &ring->jbuf[i]; 1594 1595 jbuf->buf = buf; 1596 jbuf->physaddr = physaddr; 1597 1598 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1599 1600 buf += NFE_JBYTES; 1601 physaddr += NFE_JBYTES; 1602 } 1603 1604 return 0; 1605 1606 fail: nfe_jpool_free(sc); 1607 return error; 1608 } 1609 1610 void 1611 nfe_jpool_free(struct nfe_softc *sc) 1612 { 1613 struct nfe_rx_ring *ring = &sc->rxq; 1614 1615 if (ring->jmap != NULL) { 1616 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1617 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1618 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1619 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1620 } 1621 if (ring->jpool != NULL) { 1622 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1623 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1624 } 1625 } 1626 1627 int 1628 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1629 { 1630 int i, nsegs, error; 1631 void **desc; 1632 int descsize; 1633 1634 if (sc->sc_flags & NFE_40BIT_ADDR) { 1635 desc = (void **)&ring->desc64; 1636 descsize = sizeof (struct nfe_desc64); 1637 } else { 1638 desc = (void **)&ring->desc32; 1639 descsize = sizeof (struct nfe_desc32); 1640 } 1641 1642 ring->queued = 0; 1643 ring->cur = ring->next = 0; 1644 1645 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1646 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1647 1648 if (error != 0) { 1649 printf("%s: could not create desc DMA map\n", 1650 sc->sc_dev.dv_xname); 1651 goto fail; 1652 } 1653 1654 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1655 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1656 if (error != 0) { 1657 printf("%s: could not allocate DMA memory\n", 1658 sc->sc_dev.dv_xname); 1659 goto fail; 1660 } 1661 1662 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1663 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1664 if (error != 0) { 1665 printf("%s: could not map desc DMA memory\n", 1666 sc->sc_dev.dv_xname); 1667 goto fail; 1668 } 1669 1670 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1671 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1672 if (error != 0) { 1673 printf("%s: could not load desc DMA map\n", 1674 sc->sc_dev.dv_xname); 1675 goto fail; 1676 } 1677 1678 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1679 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1680 1681 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1682 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1683 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1684 &ring->data[i].map); 1685 if (error != 0) { 1686 printf("%s: could not create DMA map\n", 1687 sc->sc_dev.dv_xname); 1688 goto fail; 1689 } 1690 } 1691 1692 return 0; 1693 1694 fail: nfe_free_tx_ring(sc, ring); 1695 return error; 1696 } 1697 1698 void 1699 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1700 { 1701 struct nfe_tx_data *data; 1702 int i; 1703 1704 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1705 if (sc->sc_flags & NFE_40BIT_ADDR) 1706 ring->desc64[i].flags = 0; 1707 else 1708 ring->desc32[i].flags = 0; 1709 1710 data = &ring->data[i]; 1711 1712 if (data->m != NULL) { 1713 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1714 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1715 bus_dmamap_unload(sc->sc_dmat, data->active); 1716 m_freem(data->m); 1717 data->m = NULL; 1718 } 1719 } 1720 1721 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1722 BUS_DMASYNC_PREWRITE); 1723 1724 ring->queued = 0; 1725 ring->cur = ring->next = 0; 1726 } 1727 1728 void 1729 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1730 { 1731 struct nfe_tx_data *data; 1732 void *desc; 1733 int i, descsize; 1734 1735 if (sc->sc_flags & NFE_40BIT_ADDR) { 1736 desc = ring->desc64; 1737 descsize = sizeof (struct nfe_desc64); 1738 } else { 1739 desc = ring->desc32; 1740 descsize = sizeof (struct nfe_desc32); 1741 } 1742 1743 if (desc != NULL) { 1744 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1745 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1746 bus_dmamap_unload(sc->sc_dmat, ring->map); 1747 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1748 NFE_TX_RING_COUNT * descsize); 1749 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1750 } 1751 1752 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1753 data = &ring->data[i]; 1754 1755 if (data->m != NULL) { 1756 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1757 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1758 bus_dmamap_unload(sc->sc_dmat, data->active); 1759 m_freem(data->m); 1760 } 1761 } 1762 1763 /* ..and now actually destroy the DMA mappings */ 1764 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1765 data = &ring->data[i]; 1766 if (data->map == NULL) 1767 continue; 1768 bus_dmamap_destroy(sc->sc_dmat, data->map); 1769 } 1770 } 1771 1772 int 1773 nfe_ifmedia_upd(struct ifnet *ifp) 1774 { 1775 struct nfe_softc *sc = ifp->if_softc; 1776 struct mii_data *mii = &sc->sc_mii; 1777 struct mii_softc *miisc; 1778 1779 if (mii->mii_instance != 0) { 1780 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1781 mii_phy_reset(miisc); 1782 } 1783 return mii_mediachg(mii); 1784 } 1785 1786 void 1787 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1788 { 1789 struct nfe_softc *sc = ifp->if_softc; 1790 struct mii_data *mii = &sc->sc_mii; 1791 1792 mii_pollstat(mii); 1793 ifmr->ifm_status = mii->mii_media_status; 1794 ifmr->ifm_active = mii->mii_media_active; 1795 } 1796 1797 void 1798 nfe_setmulti(struct nfe_softc *sc) 1799 { 1800 struct ethercom *ec = &sc->sc_ethercom; 1801 struct ifnet *ifp = &ec->ec_if; 1802 struct ether_multi *enm; 1803 struct ether_multistep step; 1804 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1805 uint32_t filter = NFE_RXFILTER_MAGIC; 1806 int i; 1807 1808 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1809 bzero(addr, ETHER_ADDR_LEN); 1810 bzero(mask, ETHER_ADDR_LEN); 1811 goto done; 1812 } 1813 1814 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1815 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1816 1817 ETHER_FIRST_MULTI(step, ec, enm); 1818 while (enm != NULL) { 1819 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1820 ifp->if_flags |= IFF_ALLMULTI; 1821 bzero(addr, ETHER_ADDR_LEN); 1822 bzero(mask, ETHER_ADDR_LEN); 1823 goto done; 1824 } 1825 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1826 addr[i] &= enm->enm_addrlo[i]; 1827 mask[i] &= ~enm->enm_addrlo[i]; 1828 } 1829 ETHER_NEXT_MULTI(step, enm); 1830 } 1831 for (i = 0; i < ETHER_ADDR_LEN; i++) 1832 mask[i] |= addr[i]; 1833 1834 done: 1835 addr[0] |= 0x01; /* make sure multicast bit is set */ 1836 1837 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1838 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1839 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1840 addr[5] << 8 | addr[4]); 1841 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1842 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1843 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1844 mask[5] << 8 | mask[4]); 1845 1846 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1847 NFE_WRITE(sc, NFE_RXFILTER, filter); 1848 } 1849 1850 void 1851 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1852 { 1853 uint32_t tmp; 1854 1855 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1856 addr[0] = (tmp >> 8) & 0xff; 1857 addr[1] = (tmp & 0xff); 1858 1859 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1860 addr[2] = (tmp >> 24) & 0xff; 1861 addr[3] = (tmp >> 16) & 0xff; 1862 addr[4] = (tmp >> 8) & 0xff; 1863 addr[5] = (tmp & 0xff); 1864 } 1865 1866 void 1867 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1868 { 1869 NFE_WRITE(sc, NFE_MACADDR_LO, 1870 addr[5] << 8 | addr[4]); 1871 NFE_WRITE(sc, NFE_MACADDR_HI, 1872 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1873 } 1874 1875 void 1876 nfe_tick(void *arg) 1877 { 1878 struct nfe_softc *sc = arg; 1879 int s; 1880 1881 s = splnet(); 1882 mii_tick(&sc->sc_mii); 1883 splx(s); 1884 1885 callout_schedule(&sc->sc_tick_ch, hz); 1886 } 1887
Indexes created Mon Oct 13 14:09:54 GMT 2025