if_nfe.c revision 1.16.6.6
1 /* $NetBSD: if_nfe.c,v 1.16.6.6 2007/11/11 16:47:41 joerg Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.52 2006/03/02 09:04:00 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.16.6.6 2007/11/11 16:47:41 joerg Exp $"); 25 26 #include "opt_inet.h" 27 #include "bpfilter.h" 28 #include "vlan.h" 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/types.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/queue.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/socket.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/pci/if_nfereg.h> 74 #include <dev/pci/if_nfevar.h> 75 76 int nfe_match(struct device *, struct cfdata *, void *); 77 void nfe_attach(struct device *, struct device *, void *); 78 void nfe_power(int, void *); 79 void nfe_miibus_statchg(struct device *); 80 int nfe_miibus_readreg(struct device *, int, int); 81 void nfe_miibus_writereg(struct device *, int, int, int); 82 int nfe_intr(void *); 83 int nfe_ioctl(struct ifnet *, u_long, void *); 84 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 85 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 86 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 87 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 88 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 89 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 90 void nfe_rxeof(struct nfe_softc *); 91 void nfe_txeof(struct nfe_softc *); 92 int nfe_encap(struct nfe_softc *, struct mbuf *); 93 void nfe_start(struct ifnet *); 94 void nfe_watchdog(struct ifnet *); 95 int nfe_init(struct ifnet *); 96 void nfe_stop(struct ifnet *, int); 97 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 98 void nfe_jfree(struct mbuf *, void *, size_t, void *); 99 int nfe_jpool_alloc(struct nfe_softc *); 100 void nfe_jpool_free(struct nfe_softc *); 101 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 102 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 105 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 int nfe_ifmedia_upd(struct ifnet *); 108 void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 109 void nfe_setmulti(struct nfe_softc *); 110 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 111 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 112 void nfe_tick(void *); 113 114 CFATTACH_DECL(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, NULL, NULL); 115 116 /*#define NFE_NO_JUMBO*/ 117 118 #ifdef NFE_DEBUG 119 int nfedebug = 0; 120 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 121 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 122 #else 123 #define DPRINTF(x) 124 #define DPRINTFN(n,x) 125 #endif 126 127 /* deal with naming differences */ 128 129 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 130 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 134 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 135 136 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 137 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 140 141 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 142 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 145 146 #ifdef _LP64 147 #define __LP64__ 1 148 #endif 149 150 const struct nfe_product { 151 pci_vendor_id_t vendor; 152 pci_product_id_t product; 153 } nfe_devices[] = { 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 155 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 } 177 }; 178 179 int 180 nfe_match(struct device *dev, struct cfdata *match, void *aux) 181 { 182 struct pci_attach_args *pa = aux; 183 const struct nfe_product *np; 184 int i; 185 186 for (i = 0; i < sizeof(nfe_devices) / sizeof(nfe_devices[0]); i++) { 187 np = &nfe_devices[i]; 188 if (PCI_VENDOR(pa->pa_id) == np->vendor && 189 PCI_PRODUCT(pa->pa_id) == np->product) 190 return 1; 191 } 192 return 0; 193 } 194 195 void 196 nfe_attach(struct device *parent, struct device *self, void *aux) 197 { 198 struct nfe_softc *sc = (struct nfe_softc *)self; 199 struct pci_attach_args *pa = aux; 200 pci_chipset_tag_t pc = pa->pa_pc; 201 pci_intr_handle_t ih; 202 const char *intrstr; 203 struct ifnet *ifp; 204 bus_size_t memsize; 205 pcireg_t memtype; 206 char devinfo[256]; 207 208 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 209 aprint_normal(": %s (rev. 0x%02x)\n", 210 devinfo, PCI_REVISION(pa->pa_class)); 211 212 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 213 switch (memtype) { 214 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 215 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 216 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 217 &sc->sc_memh, NULL, &memsize) == 0) 218 break; 219 /* FALLTHROUGH */ 220 default: 221 printf("%s: could not map mem space\n", sc->sc_dev.dv_xname); 222 return; 223 } 224 225 if (pci_intr_map(pa, &ih) != 0) { 226 printf("%s: could not map interrupt\n", sc->sc_dev.dv_xname); 227 return; 228 } 229 230 intrstr = pci_intr_string(pc, ih); 231 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 232 if (sc->sc_ih == NULL) { 233 printf("%s: could not establish interrupt", 234 sc->sc_dev.dv_xname); 235 if (intrstr != NULL) 236 printf(" at %s", intrstr); 237 printf("\n"); 238 return; 239 } 240 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 241 242 sc->sc_dmat = pa->pa_dmat; 243 244 nfe_get_macaddr(sc, sc->sc_enaddr); 245 printf("%s: Ethernet address %s\n", 246 sc->sc_dev.dv_xname, ether_sprintf(sc->sc_enaddr)); 247 248 sc->sc_flags = 0; 249 250 switch (PCI_PRODUCT(pa->pa_id)) { 251 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 252 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 253 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 254 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 255 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 256 break; 257 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 258 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 259 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 260 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 261 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 262 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 263 sc->sc_flags |= NFE_40BIT_ADDR; 264 break; 265 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 266 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 267 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 268 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 269 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 270 break; 271 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 272 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 273 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 274 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 275 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 276 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 277 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 278 NFE_HW_VLAN; 279 break; 280 } 281 282 #ifndef NFE_NO_JUMBO 283 /* enable jumbo frames for adapters that support it */ 284 if (sc->sc_flags & NFE_JUMBO_SUP) 285 sc->sc_flags |= NFE_USE_JUMBO; 286 #endif 287 288 /* 289 * Allocate Tx and Rx rings. 290 */ 291 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 292 printf("%s: could not allocate Tx ring\n", 293 sc->sc_dev.dv_xname); 294 return; 295 } 296 297 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 298 printf("%s: could not allocate Rx ring\n", 299 sc->sc_dev.dv_xname); 300 nfe_free_tx_ring(sc, &sc->txq); 301 return; 302 } 303 304 ifp = &sc->sc_ethercom.ec_if; 305 ifp->if_softc = sc; 306 ifp->if_mtu = ETHERMTU; 307 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 308 ifp->if_ioctl = nfe_ioctl; 309 ifp->if_start = nfe_start; 310 ifp->if_stop = nfe_stop; 311 ifp->if_watchdog = nfe_watchdog; 312 ifp->if_init = nfe_init; 313 ifp->if_baudrate = IF_Gbps(1); 314 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 315 IFQ_SET_READY(&ifp->if_snd); 316 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 317 318 #if NVLAN > 0 319 if (sc->sc_flags & NFE_HW_VLAN) 320 sc->sc_ethercom.ec_capabilities |= 321 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 322 #endif 323 if (sc->sc_flags & NFE_HW_CSUM) { 324 ifp->if_capabilities |= 325 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 326 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 327 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 328 } 329 330 sc->sc_mii.mii_ifp = ifp; 331 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 332 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 333 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 334 335 ifmedia_init(&sc->sc_mii.mii_media, 0, nfe_ifmedia_upd, 336 nfe_ifmedia_sts); 337 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 338 MII_OFFSET_ANY, 0); 339 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 340 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 341 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 342 0, NULL); 343 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 344 } else 345 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 346 347 if_attach(ifp); 348 ether_ifattach(ifp, sc->sc_enaddr); 349 350 callout_init(&sc->sc_tick_ch, 0); 351 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 352 353 if (!pnp_device_register(self, NULL, NULL)) 354 aprint_error_dev(self, "couldn't establish power handler\n"); 355 else 356 pnp_class_network_register(self, ifp); 357 } 358 359 void 360 nfe_miibus_statchg(struct device *dev) 361 { 362 struct nfe_softc *sc = (struct nfe_softc *)dev; 363 struct mii_data *mii = &sc->sc_mii; 364 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 365 366 phy = NFE_READ(sc, NFE_PHY_IFACE); 367 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 368 369 seed = NFE_READ(sc, NFE_RNDSEED); 370 seed &= ~NFE_SEED_MASK; 371 372 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 373 phy |= NFE_PHY_HDX; /* half-duplex */ 374 misc |= NFE_MISC1_HDX; 375 } 376 377 switch (IFM_SUBTYPE(mii->mii_media_active)) { 378 case IFM_1000_T: /* full-duplex only */ 379 link |= NFE_MEDIA_1000T; 380 seed |= NFE_SEED_1000T; 381 phy |= NFE_PHY_1000T; 382 break; 383 case IFM_100_TX: 384 link |= NFE_MEDIA_100TX; 385 seed |= NFE_SEED_100TX; 386 phy |= NFE_PHY_100TX; 387 break; 388 case IFM_10_T: 389 link |= NFE_MEDIA_10T; 390 seed |= NFE_SEED_10T; 391 break; 392 } 393 394 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 395 396 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 397 NFE_WRITE(sc, NFE_MISC1, misc); 398 NFE_WRITE(sc, NFE_LINKSPEED, link); 399 } 400 401 int 402 nfe_miibus_readreg(struct device *dev, int phy, int reg) 403 { 404 struct nfe_softc *sc = (struct nfe_softc *)dev; 405 uint32_t val; 406 int ntries; 407 408 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 409 410 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 411 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 412 DELAY(100); 413 } 414 415 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 416 417 for (ntries = 0; ntries < 1000; ntries++) { 418 DELAY(100); 419 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 420 break; 421 } 422 if (ntries == 1000) { 423 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 424 sc->sc_dev.dv_xname)); 425 return 0; 426 } 427 428 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 429 DPRINTFN(2, ("%s: could not read PHY\n", 430 sc->sc_dev.dv_xname)); 431 return 0; 432 } 433 434 val = NFE_READ(sc, NFE_PHY_DATA); 435 if (val != 0xffffffff && val != 0) 436 sc->mii_phyaddr = phy; 437 438 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 439 sc->sc_dev.dv_xname, phy, reg, val)); 440 441 return val; 442 } 443 444 void 445 nfe_miibus_writereg(struct device *dev, int phy, int reg, int val) 446 { 447 struct nfe_softc *sc = (struct nfe_softc *)dev; 448 uint32_t ctl; 449 int ntries; 450 451 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 452 453 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 454 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 455 DELAY(100); 456 } 457 458 NFE_WRITE(sc, NFE_PHY_DATA, val); 459 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 460 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 461 462 for (ntries = 0; ntries < 1000; ntries++) { 463 DELAY(100); 464 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 465 break; 466 } 467 #ifdef NFE_DEBUG 468 if (nfedebug >= 2 && ntries == 1000) 469 printf("could not write to PHY\n"); 470 #endif 471 } 472 473 int 474 nfe_intr(void *arg) 475 { 476 struct nfe_softc *sc = arg; 477 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 478 uint32_t r; 479 int handled; 480 481 if ((ifp->if_flags & IFF_UP) == 0) 482 return 0; 483 484 handled = 0; 485 486 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 487 488 for (;;) { 489 r = NFE_READ(sc, NFE_IRQ_STATUS); 490 if ((r & NFE_IRQ_WANTED) == 0) 491 break; 492 493 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 494 handled = 1; 495 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 496 497 if ((r & (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX)) 498 != 0) { 499 /* check Rx ring */ 500 nfe_rxeof(sc); 501 } 502 503 if ((r & (NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE)) 504 != 0) { 505 /* check Tx ring */ 506 nfe_txeof(sc); 507 } 508 509 if ((r & NFE_IRQ_LINK) != 0) { 510 NFE_READ(sc, NFE_PHY_STATUS); 511 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 512 DPRINTF(("%s: link state changed\n", 513 sc->sc_dev.dv_xname)); 514 } 515 } 516 517 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 518 519 if (handled && !IF_IS_EMPTY(&ifp->if_snd)) 520 nfe_start(ifp); 521 522 return handled; 523 } 524 525 int 526 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 527 { 528 struct nfe_softc *sc = ifp->if_softc; 529 struct ifreq *ifr = (struct ifreq *)data; 530 struct ifaddr *ifa = (struct ifaddr *)data; 531 int s, error = 0; 532 533 s = splnet(); 534 535 switch (cmd) { 536 case SIOCSIFADDR: 537 ifp->if_flags |= IFF_UP; 538 nfe_init(ifp); 539 switch (ifa->ifa_addr->sa_family) { 540 #ifdef INET 541 case AF_INET: 542 arp_ifinit(ifp, ifa); 543 break; 544 #endif 545 default: 546 break; 547 } 548 break; 549 case SIOCSIFMTU: 550 if (ifr->ifr_mtu < ETHERMIN || 551 ((sc->sc_flags & NFE_USE_JUMBO) && 552 ifr->ifr_mtu > ETHERMTU_JUMBO) || 553 (!(sc->sc_flags & NFE_USE_JUMBO) && 554 ifr->ifr_mtu > ETHERMTU)) 555 error = EINVAL; 556 else if (ifp->if_mtu != ifr->ifr_mtu) 557 ifp->if_mtu = ifr->ifr_mtu; 558 break; 559 case SIOCSIFFLAGS: 560 if (ifp->if_flags & IFF_UP) { 561 /* 562 * If only the PROMISC or ALLMULTI flag changes, then 563 * don't do a full re-init of the chip, just update 564 * the Rx filter. 565 */ 566 if ((ifp->if_flags & IFF_RUNNING) && 567 ((ifp->if_flags ^ sc->sc_if_flags) & 568 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 569 nfe_setmulti(sc); 570 else 571 nfe_init(ifp); 572 } else { 573 if (ifp->if_flags & IFF_RUNNING) 574 nfe_stop(ifp, 1); 575 } 576 sc->sc_if_flags = ifp->if_flags; 577 break; 578 case SIOCADDMULTI: 579 case SIOCDELMULTI: 580 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 581 if (ifp->if_flags & IFF_RUNNING) 582 nfe_setmulti(sc); 583 error = 0; 584 } 585 break; 586 case SIOCSIFMEDIA: 587 case SIOCGIFMEDIA: 588 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 589 break; 590 default: 591 error = ether_ioctl(ifp, cmd, data); 592 if (error == ENETRESET) { 593 if (ifp->if_flags & IFF_RUNNING) 594 nfe_setmulti(sc); 595 error = 0; 596 } 597 break; 598 599 } 600 601 splx(s); 602 603 return error; 604 } 605 606 void 607 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 608 { 609 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 610 (char *)desc32 - (char *)sc->txq.desc32, 611 sizeof (struct nfe_desc32), ops); 612 } 613 614 void 615 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 616 { 617 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 618 (char *)desc64 - (char *)sc->txq.desc64, 619 sizeof (struct nfe_desc64), ops); 620 } 621 622 void 623 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 624 { 625 if (end > start) { 626 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 627 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 628 (char *)&sc->txq.desc32[end] - 629 (char *)&sc->txq.desc32[start], ops); 630 return; 631 } 632 /* sync from 'start' to end of ring */ 633 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 634 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 635 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 636 (char *)&sc->txq.desc32[start], ops); 637 638 /* sync from start of ring to 'end' */ 639 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 640 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 641 } 642 643 void 644 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 645 { 646 if (end > start) { 647 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 648 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 649 (char *)&sc->txq.desc64[end] - 650 (char *)&sc->txq.desc64[start], ops); 651 return; 652 } 653 /* sync from 'start' to end of ring */ 654 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 655 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 656 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 657 (char *)&sc->txq.desc64[start], ops); 658 659 /* sync from start of ring to 'end' */ 660 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 661 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 662 } 663 664 void 665 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 666 { 667 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 668 (char *)desc32 - (char *)sc->rxq.desc32, 669 sizeof (struct nfe_desc32), ops); 670 } 671 672 void 673 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 674 { 675 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 676 (char *)desc64 - (char *)sc->rxq.desc64, 677 sizeof (struct nfe_desc64), ops); 678 } 679 680 void 681 nfe_rxeof(struct nfe_softc *sc) 682 { 683 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 684 struct nfe_desc32 *desc32; 685 struct nfe_desc64 *desc64; 686 struct nfe_rx_data *data; 687 struct nfe_jbuf *jbuf; 688 struct mbuf *m, *mnew; 689 bus_addr_t physaddr; 690 uint16_t flags; 691 int error, len, i; 692 693 desc32 = NULL; 694 desc64 = NULL; 695 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 696 data = &sc->rxq.data[i]; 697 698 if (sc->sc_flags & NFE_40BIT_ADDR) { 699 desc64 = &sc->rxq.desc64[i]; 700 nfe_rxdesc64_sync(sc, desc64, 701 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 702 703 flags = le16toh(desc64->flags); 704 len = le16toh(desc64->length) & 0x3fff; 705 } else { 706 desc32 = &sc->rxq.desc32[i]; 707 nfe_rxdesc32_sync(sc, desc32, 708 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 709 710 flags = le16toh(desc32->flags); 711 len = le16toh(desc32->length) & 0x3fff; 712 } 713 714 if ((flags & NFE_RX_READY) != 0) 715 break; 716 717 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 718 if ((flags & NFE_RX_VALID_V1) == 0) 719 goto skip; 720 721 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 722 flags &= ~NFE_RX_ERROR; 723 len--; /* fix buffer length */ 724 } 725 } else { 726 if ((flags & NFE_RX_VALID_V2) == 0) 727 goto skip; 728 729 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 730 flags &= ~NFE_RX_ERROR; 731 len--; /* fix buffer length */ 732 } 733 } 734 735 if (flags & NFE_RX_ERROR) { 736 ifp->if_ierrors++; 737 goto skip; 738 } 739 740 /* 741 * Try to allocate a new mbuf for this ring element and load 742 * it before processing the current mbuf. If the ring element 743 * cannot be loaded, drop the received packet and reuse the 744 * old mbuf. In the unlikely case that the old mbuf can't be 745 * reloaded either, explicitly panic. 746 */ 747 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 748 if (mnew == NULL) { 749 ifp->if_ierrors++; 750 goto skip; 751 } 752 753 if (sc->sc_flags & NFE_USE_JUMBO) { 754 physaddr = 755 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 756 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 757 if (len > MCLBYTES) { 758 m_freem(mnew); 759 ifp->if_ierrors++; 760 goto skip1; 761 } 762 MCLGET(mnew, M_DONTWAIT); 763 if ((mnew->m_flags & M_EXT) == 0) { 764 m_freem(mnew); 765 ifp->if_ierrors++; 766 goto skip1; 767 } 768 769 memcpy(mtod(mnew, void *), 770 mtod(data->m, const void *), len); 771 m = mnew; 772 goto mbufcopied; 773 } else { 774 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 775 776 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 777 mtod(data->m, char *) - (char *)sc->rxq.jpool, 778 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 779 780 physaddr = jbuf->physaddr; 781 } 782 } else { 783 MCLGET(mnew, M_DONTWAIT); 784 if ((mnew->m_flags & M_EXT) == 0) { 785 m_freem(mnew); 786 ifp->if_ierrors++; 787 goto skip; 788 } 789 790 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 791 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 792 bus_dmamap_unload(sc->sc_dmat, data->map); 793 794 error = bus_dmamap_load(sc->sc_dmat, data->map, 795 mtod(mnew, void *), MCLBYTES, NULL, 796 BUS_DMA_READ | BUS_DMA_NOWAIT); 797 if (error != 0) { 798 m_freem(mnew); 799 800 /* try to reload the old mbuf */ 801 error = bus_dmamap_load(sc->sc_dmat, data->map, 802 mtod(data->m, void *), MCLBYTES, NULL, 803 BUS_DMA_READ | BUS_DMA_NOWAIT); 804 if (error != 0) { 805 /* very unlikely that it will fail.. */ 806 panic("%s: could not load old rx mbuf", 807 sc->sc_dev.dv_xname); 808 } 809 ifp->if_ierrors++; 810 goto skip; 811 } 812 physaddr = data->map->dm_segs[0].ds_addr; 813 } 814 815 /* 816 * New mbuf successfully loaded, update Rx ring and continue 817 * processing. 818 */ 819 m = data->m; 820 data->m = mnew; 821 822 mbufcopied: 823 /* finalize mbuf */ 824 m->m_pkthdr.len = m->m_len = len; 825 m->m_pkthdr.rcvif = ifp; 826 827 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 828 /* 829 * XXX 830 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 831 */ 832 if (flags & NFE_RX_IP_CSUMOK) { 833 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 834 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 835 sc->sc_dev.dv_xname)); 836 } 837 /* 838 * XXX 839 * no way to check M_CSUM_TCP_UDP_BAD or 840 * other protocols? 841 */ 842 if (flags & NFE_RX_UDP_CSUMOK) { 843 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 844 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 845 sc->sc_dev.dv_xname)); 846 } else if (flags & NFE_RX_TCP_CSUMOK) { 847 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 848 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 849 sc->sc_dev.dv_xname)); 850 } 851 } 852 853 #if NBPFILTER > 0 854 if (ifp->if_bpf) 855 bpf_mtap(ifp->if_bpf, m); 856 #endif 857 ifp->if_ipackets++; 858 (*ifp->if_input)(ifp, m); 859 860 skip1: 861 /* update mapping address in h/w descriptor */ 862 if (sc->sc_flags & NFE_40BIT_ADDR) { 863 #if defined(__LP64__) 864 desc64->physaddr[0] = htole32(physaddr >> 32); 865 #endif 866 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 867 } else { 868 desc32->physaddr = htole32(physaddr); 869 } 870 871 skip: 872 if (sc->sc_flags & NFE_40BIT_ADDR) { 873 desc64->length = htole16(sc->rxq.bufsz); 874 desc64->flags = htole16(NFE_RX_READY); 875 876 nfe_rxdesc64_sync(sc, desc64, 877 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 878 } else { 879 desc32->length = htole16(sc->rxq.bufsz); 880 desc32->flags = htole16(NFE_RX_READY); 881 882 nfe_rxdesc32_sync(sc, desc32, 883 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 884 } 885 } 886 /* update current RX pointer */ 887 sc->rxq.cur = i; 888 } 889 890 void 891 nfe_txeof(struct nfe_softc *sc) 892 { 893 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 894 struct nfe_desc32 *desc32; 895 struct nfe_desc64 *desc64; 896 struct nfe_tx_data *data = NULL; 897 int i; 898 uint16_t flags; 899 900 for (i = sc->txq.next; 901 sc->txq.queued > 0; 902 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 903 if (sc->sc_flags & NFE_40BIT_ADDR) { 904 desc64 = &sc->txq.desc64[i]; 905 nfe_txdesc64_sync(sc, desc64, 906 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 907 908 flags = le16toh(desc64->flags); 909 } else { 910 desc32 = &sc->txq.desc32[i]; 911 nfe_txdesc32_sync(sc, desc32, 912 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 913 914 flags = le16toh(desc32->flags); 915 } 916 917 if ((flags & NFE_TX_VALID) != 0) 918 break; 919 920 data = &sc->txq.data[i]; 921 922 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 923 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 924 data->m == NULL) 925 continue; 926 927 if ((flags & NFE_TX_ERROR_V1) != 0) { 928 printf("%s: tx v1 error 0x%04x\n", 929 sc->sc_dev.dv_xname, flags); 930 ifp->if_oerrors++; 931 } else 932 ifp->if_opackets++; 933 } else { 934 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 935 data->m == NULL) 936 continue; 937 938 if ((flags & NFE_TX_ERROR_V2) != 0) { 939 printf("%s: tx v2 error 0x%04x\n", 940 sc->sc_dev.dv_xname, flags); 941 ifp->if_oerrors++; 942 } else 943 ifp->if_opackets++; 944 } 945 946 if (data->m == NULL) { /* should not get there */ 947 printf("%s: last fragment bit w/o associated mbuf!\n", 948 sc->sc_dev.dv_xname); 949 continue; 950 } 951 952 /* last fragment of the mbuf chain transmitted */ 953 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 954 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 955 bus_dmamap_unload(sc->sc_dmat, data->active); 956 m_freem(data->m); 957 data->m = NULL; 958 } 959 960 sc->txq.next = i; 961 962 if (sc->txq.queued < NFE_TX_RING_COUNT) { 963 /* at least one slot freed */ 964 ifp->if_flags &= ~IFF_OACTIVE; 965 } 966 967 if (sc->txq.queued == 0) { 968 /* all queued packets are sent */ 969 ifp->if_timer = 0; 970 } 971 } 972 973 int 974 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 975 { 976 struct nfe_desc32 *desc32; 977 struct nfe_desc64 *desc64; 978 struct nfe_tx_data *data; 979 bus_dmamap_t map; 980 uint16_t flags, csumflags; 981 #if NVLAN > 0 982 struct m_tag *mtag; 983 uint32_t vtag = 0; 984 #endif 985 int error, i, first; 986 987 desc32 = NULL; 988 desc64 = NULL; 989 data = NULL; 990 991 flags = 0; 992 csumflags = 0; 993 first = sc->txq.cur; 994 995 map = sc->txq.data[first].map; 996 997 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 998 if (error != 0) { 999 printf("%s: could not map mbuf (error %d)\n", 1000 sc->sc_dev.dv_xname, error); 1001 return error; 1002 } 1003 1004 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1005 bus_dmamap_unload(sc->sc_dmat, map); 1006 return ENOBUFS; 1007 } 1008 1009 #if NVLAN > 0 1010 /* setup h/w VLAN tagging */ 1011 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1012 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1013 #endif 1014 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1015 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1016 csumflags |= NFE_TX_IP_CSUM; 1017 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1018 csumflags |= NFE_TX_TCP_UDP_CSUM; 1019 } 1020 1021 for (i = 0; i < map->dm_nsegs; i++) { 1022 data = &sc->txq.data[sc->txq.cur]; 1023 1024 if (sc->sc_flags & NFE_40BIT_ADDR) { 1025 desc64 = &sc->txq.desc64[sc->txq.cur]; 1026 #if defined(__LP64__) 1027 desc64->physaddr[0] = 1028 htole32(map->dm_segs[i].ds_addr >> 32); 1029 #endif 1030 desc64->physaddr[1] = 1031 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1032 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1033 desc64->flags = htole16(flags); 1034 desc64->vtag = 0; 1035 } else { 1036 desc32 = &sc->txq.desc32[sc->txq.cur]; 1037 1038 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1039 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1040 desc32->flags = htole16(flags); 1041 } 1042 1043 /* 1044 * Setting of the valid bit in the first descriptor is 1045 * deferred until the whole chain is fully setup. 1046 */ 1047 flags |= NFE_TX_VALID; 1048 1049 sc->txq.queued++; 1050 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1051 } 1052 1053 /* the whole mbuf chain has been setup */ 1054 if (sc->sc_flags & NFE_40BIT_ADDR) { 1055 /* fix last descriptor */ 1056 flags |= NFE_TX_LASTFRAG_V2; 1057 desc64->flags = htole16(flags); 1058 1059 /* Checksum flags and vtag belong to the first fragment only. */ 1060 #if NVLAN > 0 1061 sc->txq.desc64[first].vtag = htole32(vtag); 1062 #endif 1063 sc->txq.desc64[first].flags |= htole16(csumflags); 1064 1065 /* finally, set the valid bit in the first descriptor */ 1066 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1067 } else { 1068 /* fix last descriptor */ 1069 if (sc->sc_flags & NFE_JUMBO_SUP) 1070 flags |= NFE_TX_LASTFRAG_V2; 1071 else 1072 flags |= NFE_TX_LASTFRAG_V1; 1073 desc32->flags = htole16(flags); 1074 1075 /* Checksum flags belong to the first fragment only. */ 1076 sc->txq.desc32[first].flags |= htole16(csumflags); 1077 1078 /* finally, set the valid bit in the first descriptor */ 1079 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1080 } 1081 1082 data->m = m0; 1083 data->active = map; 1084 1085 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1086 BUS_DMASYNC_PREWRITE); 1087 1088 return 0; 1089 } 1090 1091 void 1092 nfe_start(struct ifnet *ifp) 1093 { 1094 struct nfe_softc *sc = ifp->if_softc; 1095 int old = sc->txq.queued; 1096 struct mbuf *m0; 1097 1098 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 1099 return; 1100 1101 for (;;) { 1102 IFQ_POLL(&ifp->if_snd, m0); 1103 if (m0 == NULL) 1104 break; 1105 1106 if (nfe_encap(sc, m0) != 0) { 1107 ifp->if_flags |= IFF_OACTIVE; 1108 break; 1109 } 1110 1111 /* packet put in h/w queue, remove from s/w queue */ 1112 IFQ_DEQUEUE(&ifp->if_snd, m0); 1113 1114 #if NBPFILTER > 0 1115 if (ifp->if_bpf != NULL) 1116 bpf_mtap(ifp->if_bpf, m0); 1117 #endif 1118 } 1119 1120 if (sc->txq.queued != old) { 1121 /* packets are queued */ 1122 if (sc->sc_flags & NFE_40BIT_ADDR) 1123 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1124 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1125 else 1126 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1127 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1128 /* kick Tx */ 1129 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1130 1131 /* 1132 * Set a timeout in case the chip goes out to lunch. 1133 */ 1134 ifp->if_timer = 5; 1135 } 1136 } 1137 1138 void 1139 nfe_watchdog(struct ifnet *ifp) 1140 { 1141 struct nfe_softc *sc = ifp->if_softc; 1142 1143 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1144 1145 ifp->if_flags &= ~IFF_RUNNING; 1146 nfe_init(ifp); 1147 1148 ifp->if_oerrors++; 1149 } 1150 1151 int 1152 nfe_init(struct ifnet *ifp) 1153 { 1154 struct nfe_softc *sc = ifp->if_softc; 1155 uint32_t tmp; 1156 int s; 1157 1158 if (ifp->if_flags & IFF_RUNNING) 1159 return 0; 1160 1161 nfe_stop(ifp, 0); 1162 1163 NFE_WRITE(sc, NFE_TX_UNK, 0); 1164 NFE_WRITE(sc, NFE_STATUS, 0); 1165 1166 sc->rxtxctl = NFE_RXTX_BIT2; 1167 if (sc->sc_flags & NFE_40BIT_ADDR) 1168 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1169 else if (sc->sc_flags & NFE_JUMBO_SUP) 1170 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1171 if (sc->sc_flags & NFE_HW_CSUM) 1172 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1173 #if NVLAN > 0 1174 /* 1175 * Although the adapter is capable of stripping VLAN tags from received 1176 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1177 * purpose. This will be done in software by our network stack. 1178 */ 1179 if (sc->sc_flags & NFE_HW_VLAN) 1180 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1181 #endif 1182 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1183 DELAY(10); 1184 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1185 1186 #if NVLAN 1187 if (sc->sc_flags & NFE_HW_VLAN) 1188 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1189 #endif 1190 1191 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1192 1193 /* set MAC address */ 1194 nfe_set_macaddr(sc, sc->sc_enaddr); 1195 1196 /* tell MAC where rings are in memory */ 1197 #ifdef __LP64__ 1198 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1199 #endif 1200 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1201 #ifdef __LP64__ 1202 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1203 #endif 1204 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1205 1206 NFE_WRITE(sc, NFE_RING_SIZE, 1207 (NFE_RX_RING_COUNT - 1) << 16 | 1208 (NFE_TX_RING_COUNT - 1)); 1209 1210 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1211 1212 /* force MAC to wakeup */ 1213 tmp = NFE_READ(sc, NFE_PWR_STATE); 1214 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1215 DELAY(10); 1216 tmp = NFE_READ(sc, NFE_PWR_STATE); 1217 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1218 1219 s = splnet(); 1220 nfe_intr(sc); /* XXX clear IRQ status registers */ 1221 splx(s); 1222 1223 #if 1 1224 /* configure interrupts coalescing/mitigation */ 1225 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1226 #else 1227 /* no interrupt mitigation: one interrupt per packet */ 1228 NFE_WRITE(sc, NFE_IMTIMER, 970); 1229 #endif 1230 1231 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1232 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1233 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1234 1235 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1236 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1237 1238 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1239 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC); 1240 1241 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1242 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1243 DELAY(10); 1244 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1245 1246 /* set Rx filter */ 1247 nfe_setmulti(sc); 1248 1249 nfe_ifmedia_upd(ifp); 1250 1251 nfe_tick(sc); 1252 1253 /* enable Rx */ 1254 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1255 1256 /* enable Tx */ 1257 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1258 1259 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1260 1261 /* enable interrupts */ 1262 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1263 1264 callout_schedule(&sc->sc_tick_ch, hz); 1265 1266 ifp->if_flags |= IFF_RUNNING; 1267 ifp->if_flags &= ~IFF_OACTIVE; 1268 1269 return 0; 1270 } 1271 1272 void 1273 nfe_stop(struct ifnet *ifp, int disable) 1274 { 1275 struct nfe_softc *sc = ifp->if_softc; 1276 1277 callout_stop(&sc->sc_tick_ch); 1278 1279 ifp->if_timer = 0; 1280 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1281 1282 mii_down(&sc->sc_mii); 1283 1284 /* abort Tx */ 1285 NFE_WRITE(sc, NFE_TX_CTL, 0); 1286 1287 /* disable Rx */ 1288 NFE_WRITE(sc, NFE_RX_CTL, 0); 1289 1290 /* disable interrupts */ 1291 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1292 1293 /* reset Tx and Rx rings */ 1294 nfe_reset_tx_ring(sc, &sc->txq); 1295 nfe_reset_rx_ring(sc, &sc->rxq); 1296 } 1297 1298 int 1299 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1300 { 1301 struct nfe_desc32 *desc32; 1302 struct nfe_desc64 *desc64; 1303 struct nfe_rx_data *data; 1304 struct nfe_jbuf *jbuf; 1305 void **desc; 1306 bus_addr_t physaddr; 1307 int i, nsegs, error, descsize; 1308 1309 if (sc->sc_flags & NFE_40BIT_ADDR) { 1310 desc = (void **)&ring->desc64; 1311 descsize = sizeof (struct nfe_desc64); 1312 } else { 1313 desc = (void **)&ring->desc32; 1314 descsize = sizeof (struct nfe_desc32); 1315 } 1316 1317 ring->cur = ring->next = 0; 1318 ring->bufsz = MCLBYTES; 1319 1320 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1321 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1322 if (error != 0) { 1323 printf("%s: could not create desc DMA map\n", 1324 sc->sc_dev.dv_xname); 1325 goto fail; 1326 } 1327 1328 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1329 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1330 if (error != 0) { 1331 printf("%s: could not allocate DMA memory\n", 1332 sc->sc_dev.dv_xname); 1333 goto fail; 1334 } 1335 1336 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1337 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1338 if (error != 0) { 1339 printf("%s: could not map desc DMA memory\n", 1340 sc->sc_dev.dv_xname); 1341 goto fail; 1342 } 1343 1344 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1345 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1346 if (error != 0) { 1347 printf("%s: could not load desc DMA map\n", 1348 sc->sc_dev.dv_xname); 1349 goto fail; 1350 } 1351 1352 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1353 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1354 1355 if (sc->sc_flags & NFE_USE_JUMBO) { 1356 ring->bufsz = NFE_JBYTES; 1357 if ((error = nfe_jpool_alloc(sc)) != 0) { 1358 printf("%s: could not allocate jumbo frames\n", 1359 sc->sc_dev.dv_xname); 1360 goto fail; 1361 } 1362 } 1363 1364 /* 1365 * Pre-allocate Rx buffers and populate Rx ring. 1366 */ 1367 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1368 data = &sc->rxq.data[i]; 1369 1370 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1371 if (data->m == NULL) { 1372 printf("%s: could not allocate rx mbuf\n", 1373 sc->sc_dev.dv_xname); 1374 error = ENOMEM; 1375 goto fail; 1376 } 1377 1378 if (sc->sc_flags & NFE_USE_JUMBO) { 1379 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1380 printf("%s: could not allocate jumbo buffer\n", 1381 sc->sc_dev.dv_xname); 1382 goto fail; 1383 } 1384 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1385 sc); 1386 1387 physaddr = jbuf->physaddr; 1388 } else { 1389 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1390 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1391 if (error != 0) { 1392 printf("%s: could not create DMA map\n", 1393 sc->sc_dev.dv_xname); 1394 goto fail; 1395 } 1396 MCLGET(data->m, M_DONTWAIT); 1397 if (!(data->m->m_flags & M_EXT)) { 1398 printf("%s: could not allocate mbuf cluster\n", 1399 sc->sc_dev.dv_xname); 1400 error = ENOMEM; 1401 goto fail; 1402 } 1403 1404 error = bus_dmamap_load(sc->sc_dmat, data->map, 1405 mtod(data->m, void *), MCLBYTES, NULL, 1406 BUS_DMA_READ | BUS_DMA_NOWAIT); 1407 if (error != 0) { 1408 printf("%s: could not load rx buf DMA map", 1409 sc->sc_dev.dv_xname); 1410 goto fail; 1411 } 1412 physaddr = data->map->dm_segs[0].ds_addr; 1413 } 1414 1415 if (sc->sc_flags & NFE_40BIT_ADDR) { 1416 desc64 = &sc->rxq.desc64[i]; 1417 #if defined(__LP64__) 1418 desc64->physaddr[0] = htole32(physaddr >> 32); 1419 #endif 1420 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1421 desc64->length = htole16(sc->rxq.bufsz); 1422 desc64->flags = htole16(NFE_RX_READY); 1423 } else { 1424 desc32 = &sc->rxq.desc32[i]; 1425 desc32->physaddr = htole32(physaddr); 1426 desc32->length = htole16(sc->rxq.bufsz); 1427 desc32->flags = htole16(NFE_RX_READY); 1428 } 1429 } 1430 1431 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1432 BUS_DMASYNC_PREWRITE); 1433 1434 return 0; 1435 1436 fail: nfe_free_rx_ring(sc, ring); 1437 return error; 1438 } 1439 1440 void 1441 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1442 { 1443 int i; 1444 1445 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1446 if (sc->sc_flags & NFE_40BIT_ADDR) { 1447 ring->desc64[i].length = htole16(ring->bufsz); 1448 ring->desc64[i].flags = htole16(NFE_RX_READY); 1449 } else { 1450 ring->desc32[i].length = htole16(ring->bufsz); 1451 ring->desc32[i].flags = htole16(NFE_RX_READY); 1452 } 1453 } 1454 1455 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1456 BUS_DMASYNC_PREWRITE); 1457 1458 ring->cur = ring->next = 0; 1459 } 1460 1461 void 1462 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1463 { 1464 struct nfe_rx_data *data; 1465 void *desc; 1466 int i, descsize; 1467 1468 if (sc->sc_flags & NFE_40BIT_ADDR) { 1469 desc = ring->desc64; 1470 descsize = sizeof (struct nfe_desc64); 1471 } else { 1472 desc = ring->desc32; 1473 descsize = sizeof (struct nfe_desc32); 1474 } 1475 1476 if (desc != NULL) { 1477 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1478 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1479 bus_dmamap_unload(sc->sc_dmat, ring->map); 1480 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1481 NFE_RX_RING_COUNT * descsize); 1482 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1483 } 1484 1485 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1486 data = &ring->data[i]; 1487 1488 if (data->map != NULL) { 1489 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1490 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1491 bus_dmamap_unload(sc->sc_dmat, data->map); 1492 bus_dmamap_destroy(sc->sc_dmat, data->map); 1493 } 1494 if (data->m != NULL) 1495 m_freem(data->m); 1496 } 1497 } 1498 1499 struct nfe_jbuf * 1500 nfe_jalloc(struct nfe_softc *sc, int i) 1501 { 1502 struct nfe_jbuf *jbuf; 1503 1504 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1505 if (jbuf == NULL) 1506 return NULL; 1507 sc->rxq.jbufmap[i] = 1508 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1509 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1510 return jbuf; 1511 } 1512 1513 /* 1514 * This is called automatically by the network stack when the mbuf is freed. 1515 * Caution must be taken that the NIC might be reset by the time the mbuf is 1516 * freed. 1517 */ 1518 void 1519 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1520 { 1521 struct nfe_softc *sc = arg; 1522 struct nfe_jbuf *jbuf; 1523 int i; 1524 1525 /* find the jbuf from the base pointer */ 1526 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1527 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1528 printf("%s: request to free a buffer (%p) not managed by us\n", 1529 sc->sc_dev.dv_xname, buf); 1530 return; 1531 } 1532 jbuf = &sc->rxq.jbuf[i]; 1533 1534 /* ..and put it back in the free list */ 1535 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1536 1537 if (m != NULL) 1538 pool_cache_put(mb_cache, m); 1539 } 1540 1541 int 1542 nfe_jpool_alloc(struct nfe_softc *sc) 1543 { 1544 struct nfe_rx_ring *ring = &sc->rxq; 1545 struct nfe_jbuf *jbuf; 1546 bus_addr_t physaddr; 1547 char *buf; 1548 int i, nsegs, error; 1549 1550 /* 1551 * Allocate a big chunk of DMA'able memory. 1552 */ 1553 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1554 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1555 if (error != 0) { 1556 printf("%s: could not create jumbo DMA map\n", 1557 sc->sc_dev.dv_xname); 1558 goto fail; 1559 } 1560 1561 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1562 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1563 if (error != 0) { 1564 printf("%s could not allocate jumbo DMA memory\n", 1565 sc->sc_dev.dv_xname); 1566 goto fail; 1567 } 1568 1569 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1570 &ring->jpool, BUS_DMA_NOWAIT); 1571 if (error != 0) { 1572 printf("%s: could not map jumbo DMA memory\n", 1573 sc->sc_dev.dv_xname); 1574 goto fail; 1575 } 1576 1577 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1578 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1579 if (error != 0) { 1580 printf("%s: could not load jumbo DMA map\n", 1581 sc->sc_dev.dv_xname); 1582 goto fail; 1583 } 1584 1585 /* ..and split it into 9KB chunks */ 1586 SLIST_INIT(&ring->jfreelist); 1587 1588 buf = ring->jpool; 1589 physaddr = ring->jmap->dm_segs[0].ds_addr; 1590 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1591 jbuf = &ring->jbuf[i]; 1592 1593 jbuf->buf = buf; 1594 jbuf->physaddr = physaddr; 1595 1596 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1597 1598 buf += NFE_JBYTES; 1599 physaddr += NFE_JBYTES; 1600 } 1601 1602 return 0; 1603 1604 fail: nfe_jpool_free(sc); 1605 return error; 1606 } 1607 1608 void 1609 nfe_jpool_free(struct nfe_softc *sc) 1610 { 1611 struct nfe_rx_ring *ring = &sc->rxq; 1612 1613 if (ring->jmap != NULL) { 1614 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1615 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1616 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1617 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1618 } 1619 if (ring->jpool != NULL) { 1620 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1621 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1622 } 1623 } 1624 1625 int 1626 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1627 { 1628 int i, nsegs, error; 1629 void **desc; 1630 int descsize; 1631 1632 if (sc->sc_flags & NFE_40BIT_ADDR) { 1633 desc = (void **)&ring->desc64; 1634 descsize = sizeof (struct nfe_desc64); 1635 } else { 1636 desc = (void **)&ring->desc32; 1637 descsize = sizeof (struct nfe_desc32); 1638 } 1639 1640 ring->queued = 0; 1641 ring->cur = ring->next = 0; 1642 1643 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1644 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1645 1646 if (error != 0) { 1647 printf("%s: could not create desc DMA map\n", 1648 sc->sc_dev.dv_xname); 1649 goto fail; 1650 } 1651 1652 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1653 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1654 if (error != 0) { 1655 printf("%s: could not allocate DMA memory\n", 1656 sc->sc_dev.dv_xname); 1657 goto fail; 1658 } 1659 1660 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1661 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1662 if (error != 0) { 1663 printf("%s: could not map desc DMA memory\n", 1664 sc->sc_dev.dv_xname); 1665 goto fail; 1666 } 1667 1668 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1669 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1670 if (error != 0) { 1671 printf("%s: could not load desc DMA map\n", 1672 sc->sc_dev.dv_xname); 1673 goto fail; 1674 } 1675 1676 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1677 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1678 1679 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1680 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1681 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1682 &ring->data[i].map); 1683 if (error != 0) { 1684 printf("%s: could not create DMA map\n", 1685 sc->sc_dev.dv_xname); 1686 goto fail; 1687 } 1688 } 1689 1690 return 0; 1691 1692 fail: nfe_free_tx_ring(sc, ring); 1693 return error; 1694 } 1695 1696 void 1697 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1698 { 1699 struct nfe_tx_data *data; 1700 int i; 1701 1702 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1703 if (sc->sc_flags & NFE_40BIT_ADDR) 1704 ring->desc64[i].flags = 0; 1705 else 1706 ring->desc32[i].flags = 0; 1707 1708 data = &ring->data[i]; 1709 1710 if (data->m != NULL) { 1711 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1712 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1713 bus_dmamap_unload(sc->sc_dmat, data->active); 1714 m_freem(data->m); 1715 data->m = NULL; 1716 } 1717 } 1718 1719 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1720 BUS_DMASYNC_PREWRITE); 1721 1722 ring->queued = 0; 1723 ring->cur = ring->next = 0; 1724 } 1725 1726 void 1727 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1728 { 1729 struct nfe_tx_data *data; 1730 void *desc; 1731 int i, descsize; 1732 1733 if (sc->sc_flags & NFE_40BIT_ADDR) { 1734 desc = ring->desc64; 1735 descsize = sizeof (struct nfe_desc64); 1736 } else { 1737 desc = ring->desc32; 1738 descsize = sizeof (struct nfe_desc32); 1739 } 1740 1741 if (desc != NULL) { 1742 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1743 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1744 bus_dmamap_unload(sc->sc_dmat, ring->map); 1745 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1746 NFE_TX_RING_COUNT * descsize); 1747 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1748 } 1749 1750 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1751 data = &ring->data[i]; 1752 1753 if (data->m != NULL) { 1754 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1755 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1756 bus_dmamap_unload(sc->sc_dmat, data->active); 1757 m_freem(data->m); 1758 } 1759 } 1760 1761 /* ..and now actually destroy the DMA mappings */ 1762 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1763 data = &ring->data[i]; 1764 if (data->map == NULL) 1765 continue; 1766 bus_dmamap_destroy(sc->sc_dmat, data->map); 1767 } 1768 } 1769 1770 int 1771 nfe_ifmedia_upd(struct ifnet *ifp) 1772 { 1773 struct nfe_softc *sc = ifp->if_softc; 1774 struct mii_data *mii = &sc->sc_mii; 1775 struct mii_softc *miisc; 1776 1777 if (mii->mii_instance != 0) { 1778 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1779 mii_phy_reset(miisc); 1780 } 1781 return mii_mediachg(mii); 1782 } 1783 1784 void 1785 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1786 { 1787 struct nfe_softc *sc = ifp->if_softc; 1788 struct mii_data *mii = &sc->sc_mii; 1789 1790 mii_pollstat(mii); 1791 ifmr->ifm_status = mii->mii_media_status; 1792 ifmr->ifm_active = mii->mii_media_active; 1793 } 1794 1795 void 1796 nfe_setmulti(struct nfe_softc *sc) 1797 { 1798 struct ethercom *ec = &sc->sc_ethercom; 1799 struct ifnet *ifp = &ec->ec_if; 1800 struct ether_multi *enm; 1801 struct ether_multistep step; 1802 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1803 uint32_t filter = NFE_RXFILTER_MAGIC; 1804 int i; 1805 1806 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1807 bzero(addr, ETHER_ADDR_LEN); 1808 bzero(mask, ETHER_ADDR_LEN); 1809 goto done; 1810 } 1811 1812 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1813 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1814 1815 ETHER_FIRST_MULTI(step, ec, enm); 1816 while (enm != NULL) { 1817 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1818 ifp->if_flags |= IFF_ALLMULTI; 1819 bzero(addr, ETHER_ADDR_LEN); 1820 bzero(mask, ETHER_ADDR_LEN); 1821 goto done; 1822 } 1823 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1824 addr[i] &= enm->enm_addrlo[i]; 1825 mask[i] &= ~enm->enm_addrlo[i]; 1826 } 1827 ETHER_NEXT_MULTI(step, enm); 1828 } 1829 for (i = 0; i < ETHER_ADDR_LEN; i++) 1830 mask[i] |= addr[i]; 1831 1832 done: 1833 addr[0] |= 0x01; /* make sure multicast bit is set */ 1834 1835 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1836 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1837 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1838 addr[5] << 8 | addr[4]); 1839 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1840 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1841 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1842 mask[5] << 8 | mask[4]); 1843 1844 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1845 NFE_WRITE(sc, NFE_RXFILTER, filter); 1846 } 1847 1848 void 1849 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1850 { 1851 uint32_t tmp; 1852 1853 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1854 addr[0] = (tmp >> 8) & 0xff; 1855 addr[1] = (tmp & 0xff); 1856 1857 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1858 addr[2] = (tmp >> 24) & 0xff; 1859 addr[3] = (tmp >> 16) & 0xff; 1860 addr[4] = (tmp >> 8) & 0xff; 1861 addr[5] = (tmp & 0xff); 1862 } 1863 1864 void 1865 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1866 { 1867 NFE_WRITE(sc, NFE_MACADDR_LO, 1868 addr[5] << 8 | addr[4]); 1869 NFE_WRITE(sc, NFE_MACADDR_HI, 1870 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1871 } 1872 1873 void 1874 nfe_tick(void *arg) 1875 { 1876 struct nfe_softc *sc = arg; 1877 int s; 1878 1879 s = splnet(); 1880 mii_tick(&sc->sc_mii); 1881 splx(s); 1882 1883 callout_schedule(&sc->sc_tick_ch, hz); 1884 } 1885
Indexes created Mon Oct 13 14:09:54 GMT 2025