if_nfe.c revision 1.17
1 /* $NetBSD: if_nfe.c,v 1.17 2007/09/01 07:32:30 dyoung Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.52 2006/03/02 09:04:00 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.17 2007/09/01 07:32:30 dyoung Exp $"); 25 26 #include "opt_inet.h" 27 #include "bpfilter.h" 28 #include "vlan.h" 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/types.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/queue.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/socket.h> 41 42 #include <machine/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/pci/if_nfereg.h> 74 #include <dev/pci/if_nfevar.h> 75 76 int nfe_match(struct device *, struct cfdata *, void *); 77 void nfe_attach(struct device *, struct device *, void *); 78 void nfe_power(int, void *); 79 void nfe_miibus_statchg(struct device *); 80 int nfe_miibus_readreg(struct device *, int, int); 81 void nfe_miibus_writereg(struct device *, int, int, int); 82 int nfe_intr(void *); 83 int nfe_ioctl(struct ifnet *, u_long, void *); 84 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 85 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 86 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 87 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 88 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 89 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 90 void nfe_rxeof(struct nfe_softc *); 91 void nfe_txeof(struct nfe_softc *); 92 int nfe_encap(struct nfe_softc *, struct mbuf *); 93 void nfe_start(struct ifnet *); 94 void nfe_watchdog(struct ifnet *); 95 int nfe_init(struct ifnet *); 96 void nfe_stop(struct ifnet *, int); 97 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *); 98 void nfe_jfree(struct mbuf *, void *, size_t, void *); 99 int nfe_jpool_alloc(struct nfe_softc *); 100 void nfe_jpool_free(struct nfe_softc *); 101 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 102 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 105 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 int nfe_ifmedia_upd(struct ifnet *); 108 void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 109 void nfe_setmulti(struct nfe_softc *); 110 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 111 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 112 void nfe_tick(void *); 113 114 CFATTACH_DECL(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, NULL, NULL); 115 116 /*#define NFE_NO_JUMBO*/ 117 118 #ifdef NFE_DEBUG 119 int nfedebug = 0; 120 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 121 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 122 #else 123 #define DPRINTF(x) 124 #define DPRINTFN(n,x) 125 #endif 126 127 /* deal with naming differences */ 128 129 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 130 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 134 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 135 136 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 137 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 140 141 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 142 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 145 146 #ifdef _LP64 147 #define __LP64__ 1 148 #endif 149 150 const struct nfe_product { 151 pci_vendor_id_t vendor; 152 pci_product_id_t product; 153 } nfe_devices[] = { 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 155 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 } 177 }; 178 179 int 180 nfe_match(struct device *dev, struct cfdata *match, void *aux) 181 { 182 struct pci_attach_args *pa = aux; 183 const struct nfe_product *np; 184 int i; 185 186 for (i = 0; i < sizeof(nfe_devices) / sizeof(nfe_devices[0]); i++) { 187 np = &nfe_devices[i]; 188 if (PCI_VENDOR(pa->pa_id) == np->vendor && 189 PCI_PRODUCT(pa->pa_id) == np->product) 190 return 1; 191 } 192 return 0; 193 } 194 195 void 196 nfe_attach(struct device *parent, struct device *self, void *aux) 197 { 198 struct nfe_softc *sc = (struct nfe_softc *)self; 199 struct pci_attach_args *pa = aux; 200 pci_chipset_tag_t pc = pa->pa_pc; 201 pci_intr_handle_t ih; 202 const char *intrstr; 203 struct ifnet *ifp; 204 bus_size_t memsize; 205 pcireg_t memtype; 206 char devinfo[256]; 207 208 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 209 aprint_normal(": %s (rev. 0x%02x)\n", 210 devinfo, PCI_REVISION(pa->pa_class)); 211 212 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 213 switch (memtype) { 214 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 215 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 216 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 217 &sc->sc_memh, NULL, &memsize) == 0) 218 break; 219 /* FALLTHROUGH */ 220 default: 221 printf("%s: could not map mem space\n", sc->sc_dev.dv_xname); 222 return; 223 } 224 225 if (pci_intr_map(pa, &ih) != 0) { 226 printf("%s: could not map interrupt\n", sc->sc_dev.dv_xname); 227 return; 228 } 229 230 intrstr = pci_intr_string(pc, ih); 231 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 232 if (sc->sc_ih == NULL) { 233 printf("%s: could not establish interrupt", 234 sc->sc_dev.dv_xname); 235 if (intrstr != NULL) 236 printf(" at %s", intrstr); 237 printf("\n"); 238 return; 239 } 240 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 241 242 sc->sc_dmat = pa->pa_dmat; 243 244 nfe_get_macaddr(sc, sc->sc_enaddr); 245 printf("%s: Ethernet address %s\n", 246 sc->sc_dev.dv_xname, ether_sprintf(sc->sc_enaddr)); 247 248 sc->sc_flags = 0; 249 250 switch (PCI_PRODUCT(pa->pa_id)) { 251 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 252 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 253 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 254 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 255 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 256 break; 257 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 258 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 259 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 260 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 261 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 262 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 263 sc->sc_flags |= NFE_40BIT_ADDR; 264 break; 265 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 266 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 267 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 268 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 269 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 270 break; 271 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 272 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 273 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 274 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 275 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 276 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 277 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 278 NFE_HW_VLAN; 279 break; 280 } 281 282 #ifndef NFE_NO_JUMBO 283 /* enable jumbo frames for adapters that support it */ 284 if (sc->sc_flags & NFE_JUMBO_SUP) 285 sc->sc_flags |= NFE_USE_JUMBO; 286 #endif 287 288 /* 289 * Allocate Tx and Rx rings. 290 */ 291 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 292 printf("%s: could not allocate Tx ring\n", 293 sc->sc_dev.dv_xname); 294 return; 295 } 296 297 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 298 printf("%s: could not allocate Rx ring\n", 299 sc->sc_dev.dv_xname); 300 nfe_free_tx_ring(sc, &sc->txq); 301 return; 302 } 303 304 ifp = &sc->sc_ethercom.ec_if; 305 ifp->if_softc = sc; 306 ifp->if_mtu = ETHERMTU; 307 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 308 ifp->if_ioctl = nfe_ioctl; 309 ifp->if_start = nfe_start; 310 ifp->if_watchdog = nfe_watchdog; 311 ifp->if_init = nfe_init; 312 ifp->if_baudrate = IF_Gbps(1); 313 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 314 IFQ_SET_READY(&ifp->if_snd); 315 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 316 317 #if NVLAN > 0 318 if (sc->sc_flags & NFE_HW_VLAN) 319 sc->sc_ethercom.ec_capabilities |= 320 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 321 #endif 322 if (sc->sc_flags & NFE_HW_CSUM) { 323 ifp->if_capabilities |= 324 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 325 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 326 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 327 } 328 329 sc->sc_mii.mii_ifp = ifp; 330 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 331 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 332 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 333 334 ifmedia_init(&sc->sc_mii.mii_media, 0, nfe_ifmedia_upd, 335 nfe_ifmedia_sts); 336 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 337 MII_OFFSET_ANY, 0); 338 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 339 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 340 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 341 0, NULL); 342 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 343 } else 344 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 345 346 if_attach(ifp); 347 ether_ifattach(ifp, sc->sc_enaddr); 348 349 callout_init(&sc->sc_tick_ch, 0); 350 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 351 352 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 353 nfe_power, sc); 354 } 355 356 void 357 nfe_power(int why, void *arg) 358 { 359 struct nfe_softc *sc = arg; 360 struct ifnet *ifp; 361 362 if (why == PWR_RESUME) { 363 ifp = &sc->sc_ethercom.ec_if; 364 if (ifp->if_flags & IFF_UP) { 365 ifp->if_flags &= ~IFF_RUNNING; 366 nfe_init(ifp); 367 if (ifp->if_flags & IFF_RUNNING) 368 nfe_start(ifp); 369 } 370 } 371 } 372 373 void 374 nfe_miibus_statchg(struct device *dev) 375 { 376 struct nfe_softc *sc = (struct nfe_softc *)dev; 377 struct mii_data *mii = &sc->sc_mii; 378 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 379 380 phy = NFE_READ(sc, NFE_PHY_IFACE); 381 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 382 383 seed = NFE_READ(sc, NFE_RNDSEED); 384 seed &= ~NFE_SEED_MASK; 385 386 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 387 phy |= NFE_PHY_HDX; /* half-duplex */ 388 misc |= NFE_MISC1_HDX; 389 } 390 391 switch (IFM_SUBTYPE(mii->mii_media_active)) { 392 case IFM_1000_T: /* full-duplex only */ 393 link |= NFE_MEDIA_1000T; 394 seed |= NFE_SEED_1000T; 395 phy |= NFE_PHY_1000T; 396 break; 397 case IFM_100_TX: 398 link |= NFE_MEDIA_100TX; 399 seed |= NFE_SEED_100TX; 400 phy |= NFE_PHY_100TX; 401 break; 402 case IFM_10_T: 403 link |= NFE_MEDIA_10T; 404 seed |= NFE_SEED_10T; 405 break; 406 } 407 408 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 409 410 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 411 NFE_WRITE(sc, NFE_MISC1, misc); 412 NFE_WRITE(sc, NFE_LINKSPEED, link); 413 } 414 415 int 416 nfe_miibus_readreg(struct device *dev, int phy, int reg) 417 { 418 struct nfe_softc *sc = (struct nfe_softc *)dev; 419 uint32_t val; 420 int ntries; 421 422 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 423 424 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 425 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 426 DELAY(100); 427 } 428 429 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 430 431 for (ntries = 0; ntries < 1000; ntries++) { 432 DELAY(100); 433 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 434 break; 435 } 436 if (ntries == 1000) { 437 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 438 sc->sc_dev.dv_xname)); 439 return 0; 440 } 441 442 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 443 DPRINTFN(2, ("%s: could not read PHY\n", 444 sc->sc_dev.dv_xname)); 445 return 0; 446 } 447 448 val = NFE_READ(sc, NFE_PHY_DATA); 449 if (val != 0xffffffff && val != 0) 450 sc->mii_phyaddr = phy; 451 452 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 453 sc->sc_dev.dv_xname, phy, reg, val)); 454 455 return val; 456 } 457 458 void 459 nfe_miibus_writereg(struct device *dev, int phy, int reg, int val) 460 { 461 struct nfe_softc *sc = (struct nfe_softc *)dev; 462 uint32_t ctl; 463 int ntries; 464 465 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 466 467 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 468 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 469 DELAY(100); 470 } 471 472 NFE_WRITE(sc, NFE_PHY_DATA, val); 473 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 474 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 475 476 for (ntries = 0; ntries < 1000; ntries++) { 477 DELAY(100); 478 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 479 break; 480 } 481 #ifdef NFE_DEBUG 482 if (nfedebug >= 2 && ntries == 1000) 483 printf("could not write to PHY\n"); 484 #endif 485 } 486 487 int 488 nfe_intr(void *arg) 489 { 490 struct nfe_softc *sc = arg; 491 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 492 uint32_t r; 493 int handled; 494 495 if ((ifp->if_flags & IFF_UP) == 0) 496 return 0; 497 498 handled = 0; 499 500 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 501 502 for (;;) { 503 r = NFE_READ(sc, NFE_IRQ_STATUS); 504 if ((r & NFE_IRQ_WANTED) == 0) 505 break; 506 507 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 508 handled = 1; 509 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 510 511 if ((r & (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX)) 512 != 0) { 513 /* check Rx ring */ 514 nfe_rxeof(sc); 515 } 516 517 if ((r & (NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE)) 518 != 0) { 519 /* check Tx ring */ 520 nfe_txeof(sc); 521 } 522 523 if ((r & NFE_IRQ_LINK) != 0) { 524 NFE_READ(sc, NFE_PHY_STATUS); 525 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 526 DPRINTF(("%s: link state changed\n", 527 sc->sc_dev.dv_xname)); 528 } 529 } 530 531 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 532 533 if (handled && !IF_IS_EMPTY(&ifp->if_snd)) 534 nfe_start(ifp); 535 536 return handled; 537 } 538 539 int 540 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 541 { 542 struct nfe_softc *sc = ifp->if_softc; 543 struct ifreq *ifr = (struct ifreq *)data; 544 struct ifaddr *ifa = (struct ifaddr *)data; 545 int s, error = 0; 546 547 s = splnet(); 548 549 switch (cmd) { 550 case SIOCSIFADDR: 551 ifp->if_flags |= IFF_UP; 552 nfe_init(ifp); 553 switch (ifa->ifa_addr->sa_family) { 554 #ifdef INET 555 case AF_INET: 556 arp_ifinit(ifp, ifa); 557 break; 558 #endif 559 default: 560 break; 561 } 562 break; 563 case SIOCSIFMTU: 564 if (ifr->ifr_mtu < ETHERMIN || 565 ((sc->sc_flags & NFE_USE_JUMBO) && 566 ifr->ifr_mtu > ETHERMTU_JUMBO) || 567 (!(sc->sc_flags & NFE_USE_JUMBO) && 568 ifr->ifr_mtu > ETHERMTU)) 569 error = EINVAL; 570 else if (ifp->if_mtu != ifr->ifr_mtu) 571 ifp->if_mtu = ifr->ifr_mtu; 572 break; 573 case SIOCSIFFLAGS: 574 if (ifp->if_flags & IFF_UP) { 575 /* 576 * If only the PROMISC or ALLMULTI flag changes, then 577 * don't do a full re-init of the chip, just update 578 * the Rx filter. 579 */ 580 if ((ifp->if_flags & IFF_RUNNING) && 581 ((ifp->if_flags ^ sc->sc_if_flags) & 582 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 583 nfe_setmulti(sc); 584 else 585 nfe_init(ifp); 586 } else { 587 if (ifp->if_flags & IFF_RUNNING) 588 nfe_stop(ifp, 1); 589 } 590 sc->sc_if_flags = ifp->if_flags; 591 break; 592 case SIOCADDMULTI: 593 case SIOCDELMULTI: 594 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 595 if (ifp->if_flags & IFF_RUNNING) 596 nfe_setmulti(sc); 597 error = 0; 598 } 599 break; 600 case SIOCSIFMEDIA: 601 case SIOCGIFMEDIA: 602 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 603 break; 604 default: 605 error = ether_ioctl(ifp, cmd, data); 606 if (error == ENETRESET) { 607 if (ifp->if_flags & IFF_RUNNING) 608 nfe_setmulti(sc); 609 error = 0; 610 } 611 break; 612 613 } 614 615 splx(s); 616 617 return error; 618 } 619 620 void 621 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 622 { 623 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 624 (char *)desc32 - (char *)sc->txq.desc32, 625 sizeof (struct nfe_desc32), ops); 626 } 627 628 void 629 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 630 { 631 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 632 (char *)desc64 - (char *)sc->txq.desc64, 633 sizeof (struct nfe_desc64), ops); 634 } 635 636 void 637 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 638 { 639 if (end > start) { 640 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 641 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 642 (char *)&sc->txq.desc32[end] - 643 (char *)&sc->txq.desc32[start], ops); 644 return; 645 } 646 /* sync from 'start' to end of ring */ 647 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 648 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 649 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 650 (char *)&sc->txq.desc32[start], ops); 651 652 /* sync from start of ring to 'end' */ 653 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 654 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 655 } 656 657 void 658 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 659 { 660 if (end > start) { 661 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 662 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 663 (char *)&sc->txq.desc64[end] - 664 (char *)&sc->txq.desc64[start], ops); 665 return; 666 } 667 /* sync from 'start' to end of ring */ 668 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 669 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 670 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 671 (char *)&sc->txq.desc64[start], ops); 672 673 /* sync from start of ring to 'end' */ 674 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 675 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 676 } 677 678 void 679 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 680 { 681 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 682 (char *)desc32 - (char *)sc->rxq.desc32, 683 sizeof (struct nfe_desc32), ops); 684 } 685 686 void 687 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 688 { 689 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 690 (char *)desc64 - (char *)sc->rxq.desc64, 691 sizeof (struct nfe_desc64), ops); 692 } 693 694 void 695 nfe_rxeof(struct nfe_softc *sc) 696 { 697 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 698 struct nfe_desc32 *desc32; 699 struct nfe_desc64 *desc64; 700 struct nfe_rx_data *data; 701 struct nfe_jbuf *jbuf; 702 struct mbuf *m, *mnew; 703 bus_addr_t physaddr; 704 uint16_t flags; 705 int error, len, i; 706 707 desc32 = NULL; 708 desc64 = NULL; 709 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 710 data = &sc->rxq.data[i]; 711 712 if (sc->sc_flags & NFE_40BIT_ADDR) { 713 desc64 = &sc->rxq.desc64[i]; 714 nfe_rxdesc64_sync(sc, desc64, 715 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 716 717 flags = le16toh(desc64->flags); 718 len = le16toh(desc64->length) & 0x3fff; 719 } else { 720 desc32 = &sc->rxq.desc32[i]; 721 nfe_rxdesc32_sync(sc, desc32, 722 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 723 724 flags = le16toh(desc32->flags); 725 len = le16toh(desc32->length) & 0x3fff; 726 } 727 728 if ((flags & NFE_RX_READY) != 0) 729 break; 730 731 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 732 if ((flags & NFE_RX_VALID_V1) == 0) 733 goto skip; 734 735 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 736 flags &= ~NFE_RX_ERROR; 737 len--; /* fix buffer length */ 738 } 739 } else { 740 if ((flags & NFE_RX_VALID_V2) == 0) 741 goto skip; 742 743 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 744 flags &= ~NFE_RX_ERROR; 745 len--; /* fix buffer length */ 746 } 747 } 748 749 if (flags & NFE_RX_ERROR) { 750 ifp->if_ierrors++; 751 goto skip; 752 } 753 754 /* 755 * Try to allocate a new mbuf for this ring element and load 756 * it before processing the current mbuf. If the ring element 757 * cannot be loaded, drop the received packet and reuse the 758 * old mbuf. In the unlikely case that the old mbuf can't be 759 * reloaded either, explicitly panic. 760 */ 761 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 762 if (mnew == NULL) { 763 ifp->if_ierrors++; 764 goto skip; 765 } 766 767 if (sc->sc_flags & NFE_USE_JUMBO) { 768 if ((jbuf = nfe_jalloc(sc)) == NULL) { 769 m_freem(mnew); 770 ifp->if_ierrors++; 771 goto skip; 772 } 773 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 774 775 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 776 mtod(data->m, char *) - (char *)sc->rxq.jpool, 777 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 778 779 physaddr = jbuf->physaddr; 780 } else { 781 MCLGET(mnew, M_DONTWAIT); 782 if ((mnew->m_flags & M_EXT) == 0) { 783 m_freem(mnew); 784 ifp->if_ierrors++; 785 goto skip; 786 } 787 788 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 789 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 790 bus_dmamap_unload(sc->sc_dmat, data->map); 791 792 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, 793 mnew, BUS_DMA_READ | BUS_DMA_NOWAIT); 794 if (error != 0) { 795 m_freem(mnew); 796 797 /* try to reload the old mbuf */ 798 error = bus_dmamap_load_mbuf(sc->sc_dmat, 799 data->map, data->m, 800 BUS_DMA_READ | BUS_DMA_NOWAIT); 801 if (error != 0) { 802 /* very unlikely that it will fail.. */ 803 panic("%s: could not load old rx mbuf", 804 sc->sc_dev.dv_xname); 805 } 806 ifp->if_ierrors++; 807 goto skip; 808 } 809 physaddr = data->map->dm_segs[0].ds_addr; 810 } 811 812 /* 813 * New mbuf successfully loaded, update Rx ring and continue 814 * processing. 815 */ 816 m = data->m; 817 data->m = mnew; 818 819 /* finalize mbuf */ 820 m->m_pkthdr.len = m->m_len = len; 821 m->m_pkthdr.rcvif = ifp; 822 823 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 824 /* 825 * XXX 826 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 827 */ 828 if (flags & NFE_RX_IP_CSUMOK) { 829 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 830 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 831 sc->sc_dev.dv_xname)); 832 } 833 /* 834 * XXX 835 * no way to check M_CSUM_TCP_UDP_BAD or 836 * other protocols? 837 */ 838 if (flags & NFE_RX_UDP_CSUMOK) { 839 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 840 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 841 sc->sc_dev.dv_xname)); 842 } else if (flags & NFE_RX_TCP_CSUMOK) { 843 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 844 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 845 sc->sc_dev.dv_xname)); 846 } 847 } 848 849 #if NBPFILTER > 0 850 if (ifp->if_bpf) 851 bpf_mtap(ifp->if_bpf, m); 852 #endif 853 ifp->if_ipackets++; 854 (*ifp->if_input)(ifp, m); 855 856 /* update mapping address in h/w descriptor */ 857 if (sc->sc_flags & NFE_40BIT_ADDR) { 858 #if defined(__LP64__) 859 desc64->physaddr[0] = htole32(physaddr >> 32); 860 #endif 861 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 862 } else { 863 desc32->physaddr = htole32(physaddr); 864 } 865 866 skip: 867 if (sc->sc_flags & NFE_40BIT_ADDR) { 868 desc64->length = htole16(sc->rxq.bufsz); 869 desc64->flags = htole16(NFE_RX_READY); 870 871 nfe_rxdesc64_sync(sc, desc64, 872 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 873 } else { 874 desc32->length = htole16(sc->rxq.bufsz); 875 desc32->flags = htole16(NFE_RX_READY); 876 877 nfe_rxdesc32_sync(sc, desc32, 878 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 879 } 880 } 881 /* update current RX pointer */ 882 sc->rxq.cur = i; 883 } 884 885 void 886 nfe_txeof(struct nfe_softc *sc) 887 { 888 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 889 struct nfe_desc32 *desc32; 890 struct nfe_desc64 *desc64; 891 struct nfe_tx_data *data = NULL; 892 int i; 893 uint16_t flags; 894 895 for (i = sc->txq.next; 896 sc->txq.queued > 0; 897 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 898 if (sc->sc_flags & NFE_40BIT_ADDR) { 899 desc64 = &sc->txq.desc64[i]; 900 nfe_txdesc64_sync(sc, desc64, 901 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 902 903 flags = le16toh(desc64->flags); 904 } else { 905 desc32 = &sc->txq.desc32[i]; 906 nfe_txdesc32_sync(sc, desc32, 907 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 908 909 flags = le16toh(desc32->flags); 910 } 911 912 if ((flags & NFE_TX_VALID) != 0) 913 break; 914 915 data = &sc->txq.data[i]; 916 917 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 918 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 919 data->m == NULL) 920 continue; 921 922 if ((flags & NFE_TX_ERROR_V1) != 0) { 923 printf("%s: tx v1 error 0x%04x\n", 924 sc->sc_dev.dv_xname, flags); 925 ifp->if_oerrors++; 926 } else 927 ifp->if_opackets++; 928 } else { 929 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 930 data->m == NULL) 931 continue; 932 933 if ((flags & NFE_TX_ERROR_V2) != 0) { 934 printf("%s: tx v2 error 0x%04x\n", 935 sc->sc_dev.dv_xname, flags); 936 ifp->if_oerrors++; 937 } else 938 ifp->if_opackets++; 939 } 940 941 if (data->m == NULL) { /* should not get there */ 942 printf("%s: last fragment bit w/o associated mbuf!\n", 943 sc->sc_dev.dv_xname); 944 continue; 945 } 946 947 /* last fragment of the mbuf chain transmitted */ 948 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 949 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 950 bus_dmamap_unload(sc->sc_dmat, data->active); 951 m_freem(data->m); 952 data->m = NULL; 953 } 954 955 sc->txq.next = i; 956 957 if (sc->txq.queued < NFE_TX_RING_COUNT) { 958 /* at least one slot freed */ 959 ifp->if_flags &= ~IFF_OACTIVE; 960 } 961 962 if (sc->txq.queued == 0) { 963 /* all queued packets are sent */ 964 ifp->if_timer = 0; 965 } 966 } 967 968 int 969 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 970 { 971 struct nfe_desc32 *desc32; 972 struct nfe_desc64 *desc64; 973 struct nfe_tx_data *data; 974 bus_dmamap_t map; 975 uint16_t flags, csumflags; 976 #if NVLAN > 0 977 struct m_tag *mtag; 978 uint32_t vtag = 0; 979 #endif 980 int error, i, first; 981 982 desc32 = NULL; 983 desc64 = NULL; 984 data = NULL; 985 986 flags = 0; 987 csumflags = 0; 988 first = sc->txq.cur; 989 990 map = sc->txq.data[first].map; 991 992 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 993 if (error != 0) { 994 printf("%s: could not map mbuf (error %d)\n", 995 sc->sc_dev.dv_xname, error); 996 return error; 997 } 998 999 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1000 bus_dmamap_unload(sc->sc_dmat, map); 1001 return ENOBUFS; 1002 } 1003 1004 #if NVLAN > 0 1005 /* setup h/w VLAN tagging */ 1006 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1007 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1008 #endif 1009 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1010 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1011 csumflags |= NFE_TX_IP_CSUM; 1012 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1013 csumflags |= NFE_TX_TCP_UDP_CSUM; 1014 } 1015 1016 for (i = 0; i < map->dm_nsegs; i++) { 1017 data = &sc->txq.data[sc->txq.cur]; 1018 1019 if (sc->sc_flags & NFE_40BIT_ADDR) { 1020 desc64 = &sc->txq.desc64[sc->txq.cur]; 1021 #if defined(__LP64__) 1022 desc64->physaddr[0] = 1023 htole32(map->dm_segs[i].ds_addr >> 32); 1024 #endif 1025 desc64->physaddr[1] = 1026 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1027 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1028 desc64->flags = htole16(flags); 1029 desc64->vtag = 0; 1030 } else { 1031 desc32 = &sc->txq.desc32[sc->txq.cur]; 1032 1033 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1034 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1035 desc32->flags = htole16(flags); 1036 } 1037 1038 /* 1039 * Setting of the valid bit in the first descriptor is 1040 * deferred until the whole chain is fully setup. 1041 */ 1042 flags |= NFE_TX_VALID; 1043 1044 sc->txq.queued++; 1045 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1046 } 1047 1048 /* the whole mbuf chain has been setup */ 1049 if (sc->sc_flags & NFE_40BIT_ADDR) { 1050 /* fix last descriptor */ 1051 flags |= NFE_TX_LASTFRAG_V2; 1052 desc64->flags = htole16(flags); 1053 1054 /* Checksum flags and vtag belong to the first fragment only. */ 1055 #if NVLAN > 0 1056 sc->txq.desc64[first].vtag = htole32(vtag); 1057 #endif 1058 sc->txq.desc64[first].flags |= htole16(csumflags); 1059 1060 /* finally, set the valid bit in the first descriptor */ 1061 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1062 } else { 1063 /* fix last descriptor */ 1064 if (sc->sc_flags & NFE_JUMBO_SUP) 1065 flags |= NFE_TX_LASTFRAG_V2; 1066 else 1067 flags |= NFE_TX_LASTFRAG_V1; 1068 desc32->flags = htole16(flags); 1069 1070 /* Checksum flags belong to the first fragment only. */ 1071 sc->txq.desc32[first].flags |= htole16(csumflags); 1072 1073 /* finally, set the valid bit in the first descriptor */ 1074 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1075 } 1076 1077 data->m = m0; 1078 data->active = map; 1079 1080 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1081 BUS_DMASYNC_PREWRITE); 1082 1083 return 0; 1084 } 1085 1086 void 1087 nfe_start(struct ifnet *ifp) 1088 { 1089 struct nfe_softc *sc = ifp->if_softc; 1090 int old = sc->txq.queued; 1091 struct mbuf *m0; 1092 1093 for (;;) { 1094 IFQ_POLL(&ifp->if_snd, m0); 1095 if (m0 == NULL) 1096 break; 1097 1098 if (nfe_encap(sc, m0) != 0) { 1099 ifp->if_flags |= IFF_OACTIVE; 1100 break; 1101 } 1102 1103 /* packet put in h/w queue, remove from s/w queue */ 1104 IFQ_DEQUEUE(&ifp->if_snd, m0); 1105 1106 #if NBPFILTER > 0 1107 if (ifp->if_bpf != NULL) 1108 bpf_mtap(ifp->if_bpf, m0); 1109 #endif 1110 } 1111 1112 if (sc->txq.queued != old) { 1113 /* packets are queued */ 1114 if (sc->sc_flags & NFE_40BIT_ADDR) 1115 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1116 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1117 else 1118 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1119 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1120 /* kick Tx */ 1121 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1122 1123 /* 1124 * Set a timeout in case the chip goes out to lunch. 1125 */ 1126 ifp->if_timer = 5; 1127 } 1128 } 1129 1130 void 1131 nfe_watchdog(struct ifnet *ifp) 1132 { 1133 struct nfe_softc *sc = ifp->if_softc; 1134 1135 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1136 1137 ifp->if_flags &= ~IFF_RUNNING; 1138 nfe_init(ifp); 1139 1140 ifp->if_oerrors++; 1141 } 1142 1143 int 1144 nfe_init(struct ifnet *ifp) 1145 { 1146 struct nfe_softc *sc = ifp->if_softc; 1147 uint32_t tmp; 1148 int s; 1149 1150 if (ifp->if_flags & IFF_RUNNING) 1151 return 0; 1152 1153 nfe_stop(ifp, 0); 1154 1155 NFE_WRITE(sc, NFE_TX_UNK, 0); 1156 NFE_WRITE(sc, NFE_STATUS, 0); 1157 1158 sc->rxtxctl = NFE_RXTX_BIT2; 1159 if (sc->sc_flags & NFE_40BIT_ADDR) 1160 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1161 else if (sc->sc_flags & NFE_JUMBO_SUP) 1162 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1163 if (sc->sc_flags & NFE_HW_CSUM) 1164 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1165 #if NVLAN > 0 1166 /* 1167 * Although the adapter is capable of stripping VLAN tags from received 1168 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1169 * purpose. This will be done in software by our network stack. 1170 */ 1171 if (sc->sc_flags & NFE_HW_VLAN) 1172 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1173 #endif 1174 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1175 DELAY(10); 1176 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1177 1178 #if NVLAN 1179 if (sc->sc_flags & NFE_HW_VLAN) 1180 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1181 #endif 1182 1183 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1184 1185 /* set MAC address */ 1186 nfe_set_macaddr(sc, sc->sc_enaddr); 1187 1188 /* tell MAC where rings are in memory */ 1189 #ifdef __LP64__ 1190 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1191 #endif 1192 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1193 #ifdef __LP64__ 1194 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1195 #endif 1196 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1197 1198 NFE_WRITE(sc, NFE_RING_SIZE, 1199 (NFE_RX_RING_COUNT - 1) << 16 | 1200 (NFE_TX_RING_COUNT - 1)); 1201 1202 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1203 1204 /* force MAC to wakeup */ 1205 tmp = NFE_READ(sc, NFE_PWR_STATE); 1206 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1207 DELAY(10); 1208 tmp = NFE_READ(sc, NFE_PWR_STATE); 1209 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1210 1211 s = splnet(); 1212 nfe_intr(sc); /* XXX clear IRQ status registers */ 1213 splx(s); 1214 1215 #if 1 1216 /* configure interrupts coalescing/mitigation */ 1217 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1218 #else 1219 /* no interrupt mitigation: one interrupt per packet */ 1220 NFE_WRITE(sc, NFE_IMTIMER, 970); 1221 #endif 1222 1223 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1224 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1225 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1226 1227 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1228 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1229 1230 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1231 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC); 1232 1233 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1234 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1235 DELAY(10); 1236 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1237 1238 /* set Rx filter */ 1239 nfe_setmulti(sc); 1240 1241 nfe_ifmedia_upd(ifp); 1242 1243 nfe_tick(sc); 1244 1245 /* enable Rx */ 1246 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1247 1248 /* enable Tx */ 1249 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1250 1251 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1252 1253 /* enable interrupts */ 1254 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1255 1256 callout_schedule(&sc->sc_tick_ch, hz); 1257 1258 ifp->if_flags |= IFF_RUNNING; 1259 ifp->if_flags &= ~IFF_OACTIVE; 1260 1261 return 0; 1262 } 1263 1264 void 1265 nfe_stop(struct ifnet *ifp, int disable) 1266 { 1267 struct nfe_softc *sc = ifp->if_softc; 1268 1269 callout_stop(&sc->sc_tick_ch); 1270 1271 ifp->if_timer = 0; 1272 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1273 1274 mii_down(&sc->sc_mii); 1275 1276 /* abort Tx */ 1277 NFE_WRITE(sc, NFE_TX_CTL, 0); 1278 1279 /* disable Rx */ 1280 NFE_WRITE(sc, NFE_RX_CTL, 0); 1281 1282 /* disable interrupts */ 1283 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1284 1285 /* reset Tx and Rx rings */ 1286 nfe_reset_tx_ring(sc, &sc->txq); 1287 nfe_reset_rx_ring(sc, &sc->rxq); 1288 } 1289 1290 int 1291 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1292 { 1293 struct nfe_desc32 *desc32; 1294 struct nfe_desc64 *desc64; 1295 struct nfe_rx_data *data; 1296 struct nfe_jbuf *jbuf; 1297 void **desc; 1298 bus_addr_t physaddr; 1299 int i, nsegs, error, descsize; 1300 1301 if (sc->sc_flags & NFE_40BIT_ADDR) { 1302 desc = (void **)&ring->desc64; 1303 descsize = sizeof (struct nfe_desc64); 1304 } else { 1305 desc = (void **)&ring->desc32; 1306 descsize = sizeof (struct nfe_desc32); 1307 } 1308 1309 ring->cur = ring->next = 0; 1310 ring->bufsz = MCLBYTES; 1311 1312 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1313 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1314 if (error != 0) { 1315 printf("%s: could not create desc DMA map\n", 1316 sc->sc_dev.dv_xname); 1317 goto fail; 1318 } 1319 1320 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1321 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1322 if (error != 0) { 1323 printf("%s: could not allocate DMA memory\n", 1324 sc->sc_dev.dv_xname); 1325 goto fail; 1326 } 1327 1328 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1329 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1330 if (error != 0) { 1331 printf("%s: could not map desc DMA memory\n", 1332 sc->sc_dev.dv_xname); 1333 goto fail; 1334 } 1335 1336 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1337 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1338 if (error != 0) { 1339 printf("%s: could not load desc DMA map\n", 1340 sc->sc_dev.dv_xname); 1341 goto fail; 1342 } 1343 1344 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1345 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1346 1347 if (sc->sc_flags & NFE_USE_JUMBO) { 1348 ring->bufsz = NFE_JBYTES; 1349 if ((error = nfe_jpool_alloc(sc)) != 0) { 1350 printf("%s: could not allocate jumbo frames\n", 1351 sc->sc_dev.dv_xname); 1352 goto fail; 1353 } 1354 } 1355 1356 /* 1357 * Pre-allocate Rx buffers and populate Rx ring. 1358 */ 1359 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1360 data = &sc->rxq.data[i]; 1361 1362 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1363 if (data->m == NULL) { 1364 printf("%s: could not allocate rx mbuf\n", 1365 sc->sc_dev.dv_xname); 1366 error = ENOMEM; 1367 goto fail; 1368 } 1369 1370 if (sc->sc_flags & NFE_USE_JUMBO) { 1371 if ((jbuf = nfe_jalloc(sc)) == NULL) { 1372 printf("%s: could not allocate jumbo buffer\n", 1373 sc->sc_dev.dv_xname); 1374 goto fail; 1375 } 1376 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1377 sc); 1378 1379 physaddr = jbuf->physaddr; 1380 } else { 1381 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1382 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1383 if (error != 0) { 1384 printf("%s: could not create DMA map\n", 1385 sc->sc_dev.dv_xname); 1386 goto fail; 1387 } 1388 MCLGET(data->m, M_DONTWAIT); 1389 if (!(data->m->m_flags & M_EXT)) { 1390 printf("%s: could not allocate mbuf cluster\n", 1391 sc->sc_dev.dv_xname); 1392 error = ENOMEM; 1393 goto fail; 1394 } 1395 1396 error = bus_dmamap_load(sc->sc_dmat, data->map, 1397 mtod(data->m, void *), MCLBYTES, NULL, 1398 BUS_DMA_READ | BUS_DMA_NOWAIT); 1399 if (error != 0) { 1400 printf("%s: could not load rx buf DMA map", 1401 sc->sc_dev.dv_xname); 1402 goto fail; 1403 } 1404 physaddr = data->map->dm_segs[0].ds_addr; 1405 } 1406 1407 if (sc->sc_flags & NFE_40BIT_ADDR) { 1408 desc64 = &sc->rxq.desc64[i]; 1409 #if defined(__LP64__) 1410 desc64->physaddr[0] = htole32(physaddr >> 32); 1411 #endif 1412 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1413 desc64->length = htole16(sc->rxq.bufsz); 1414 desc64->flags = htole16(NFE_RX_READY); 1415 } else { 1416 desc32 = &sc->rxq.desc32[i]; 1417 desc32->physaddr = htole32(physaddr); 1418 desc32->length = htole16(sc->rxq.bufsz); 1419 desc32->flags = htole16(NFE_RX_READY); 1420 } 1421 } 1422 1423 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1424 BUS_DMASYNC_PREWRITE); 1425 1426 return 0; 1427 1428 fail: nfe_free_rx_ring(sc, ring); 1429 return error; 1430 } 1431 1432 void 1433 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1434 { 1435 int i; 1436 1437 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1438 if (sc->sc_flags & NFE_40BIT_ADDR) { 1439 ring->desc64[i].length = htole16(ring->bufsz); 1440 ring->desc64[i].flags = htole16(NFE_RX_READY); 1441 } else { 1442 ring->desc32[i].length = htole16(ring->bufsz); 1443 ring->desc32[i].flags = htole16(NFE_RX_READY); 1444 } 1445 } 1446 1447 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1448 BUS_DMASYNC_PREWRITE); 1449 1450 ring->cur = ring->next = 0; 1451 } 1452 1453 void 1454 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1455 { 1456 struct nfe_rx_data *data; 1457 void *desc; 1458 int i, descsize; 1459 1460 if (sc->sc_flags & NFE_40BIT_ADDR) { 1461 desc = ring->desc64; 1462 descsize = sizeof (struct nfe_desc64); 1463 } else { 1464 desc = ring->desc32; 1465 descsize = sizeof (struct nfe_desc32); 1466 } 1467 1468 if (desc != NULL) { 1469 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1470 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1471 bus_dmamap_unload(sc->sc_dmat, ring->map); 1472 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1473 NFE_RX_RING_COUNT * descsize); 1474 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1475 } 1476 1477 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1478 data = &ring->data[i]; 1479 1480 if (data->map != NULL) { 1481 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1482 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1483 bus_dmamap_unload(sc->sc_dmat, data->map); 1484 bus_dmamap_destroy(sc->sc_dmat, data->map); 1485 } 1486 if (data->m != NULL) 1487 m_freem(data->m); 1488 } 1489 } 1490 1491 struct nfe_jbuf * 1492 nfe_jalloc(struct nfe_softc *sc) 1493 { 1494 struct nfe_jbuf *jbuf; 1495 1496 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1497 if (jbuf == NULL) 1498 return NULL; 1499 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1500 return jbuf; 1501 } 1502 1503 /* 1504 * This is called automatically by the network stack when the mbuf is freed. 1505 * Caution must be taken that the NIC might be reset by the time the mbuf is 1506 * freed. 1507 */ 1508 void 1509 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1510 { 1511 struct nfe_softc *sc = arg; 1512 struct nfe_jbuf *jbuf; 1513 int i; 1514 1515 /* find the jbuf from the base pointer */ 1516 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1517 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1518 printf("%s: request to free a buffer (%p) not managed by us\n", 1519 sc->sc_dev.dv_xname, buf); 1520 return; 1521 } 1522 jbuf = &sc->rxq.jbuf[i]; 1523 1524 /* ..and put it back in the free list */ 1525 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1526 1527 if (m != NULL) 1528 pool_cache_put(&mbpool_cache, m); 1529 } 1530 1531 int 1532 nfe_jpool_alloc(struct nfe_softc *sc) 1533 { 1534 struct nfe_rx_ring *ring = &sc->rxq; 1535 struct nfe_jbuf *jbuf; 1536 bus_addr_t physaddr; 1537 char *buf; 1538 int i, nsegs, error; 1539 1540 /* 1541 * Allocate a big chunk of DMA'able memory. 1542 */ 1543 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1544 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1545 if (error != 0) { 1546 printf("%s: could not create jumbo DMA map\n", 1547 sc->sc_dev.dv_xname); 1548 goto fail; 1549 } 1550 1551 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1552 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1553 if (error != 0) { 1554 printf("%s could not allocate jumbo DMA memory\n", 1555 sc->sc_dev.dv_xname); 1556 goto fail; 1557 } 1558 1559 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1560 &ring->jpool, BUS_DMA_NOWAIT); 1561 if (error != 0) { 1562 printf("%s: could not map jumbo DMA memory\n", 1563 sc->sc_dev.dv_xname); 1564 goto fail; 1565 } 1566 1567 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1568 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1569 if (error != 0) { 1570 printf("%s: could not load jumbo DMA map\n", 1571 sc->sc_dev.dv_xname); 1572 goto fail; 1573 } 1574 1575 /* ..and split it into 9KB chunks */ 1576 SLIST_INIT(&ring->jfreelist); 1577 1578 buf = ring->jpool; 1579 physaddr = ring->jmap->dm_segs[0].ds_addr; 1580 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1581 jbuf = &ring->jbuf[i]; 1582 1583 jbuf->buf = buf; 1584 jbuf->physaddr = physaddr; 1585 1586 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1587 1588 buf += NFE_JBYTES; 1589 physaddr += NFE_JBYTES; 1590 } 1591 1592 return 0; 1593 1594 fail: nfe_jpool_free(sc); 1595 return error; 1596 } 1597 1598 void 1599 nfe_jpool_free(struct nfe_softc *sc) 1600 { 1601 struct nfe_rx_ring *ring = &sc->rxq; 1602 1603 if (ring->jmap != NULL) { 1604 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1605 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1606 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1607 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1608 } 1609 if (ring->jpool != NULL) { 1610 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1611 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1612 } 1613 } 1614 1615 int 1616 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1617 { 1618 int i, nsegs, error; 1619 void **desc; 1620 int descsize; 1621 1622 if (sc->sc_flags & NFE_40BIT_ADDR) { 1623 desc = (void **)&ring->desc64; 1624 descsize = sizeof (struct nfe_desc64); 1625 } else { 1626 desc = (void **)&ring->desc32; 1627 descsize = sizeof (struct nfe_desc32); 1628 } 1629 1630 ring->queued = 0; 1631 ring->cur = ring->next = 0; 1632 1633 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1634 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1635 1636 if (error != 0) { 1637 printf("%s: could not create desc DMA map\n", 1638 sc->sc_dev.dv_xname); 1639 goto fail; 1640 } 1641 1642 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1643 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1644 if (error != 0) { 1645 printf("%s: could not allocate DMA memory\n", 1646 sc->sc_dev.dv_xname); 1647 goto fail; 1648 } 1649 1650 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1651 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1652 if (error != 0) { 1653 printf("%s: could not map desc DMA memory\n", 1654 sc->sc_dev.dv_xname); 1655 goto fail; 1656 } 1657 1658 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1659 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1660 if (error != 0) { 1661 printf("%s: could not load desc DMA map\n", 1662 sc->sc_dev.dv_xname); 1663 goto fail; 1664 } 1665 1666 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1667 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1668 1669 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1670 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1671 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1672 &ring->data[i].map); 1673 if (error != 0) { 1674 printf("%s: could not create DMA map\n", 1675 sc->sc_dev.dv_xname); 1676 goto fail; 1677 } 1678 } 1679 1680 return 0; 1681 1682 fail: nfe_free_tx_ring(sc, ring); 1683 return error; 1684 } 1685 1686 void 1687 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1688 { 1689 struct nfe_tx_data *data; 1690 int i; 1691 1692 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1693 if (sc->sc_flags & NFE_40BIT_ADDR) 1694 ring->desc64[i].flags = 0; 1695 else 1696 ring->desc32[i].flags = 0; 1697 1698 data = &ring->data[i]; 1699 1700 if (data->m != NULL) { 1701 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1702 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1703 bus_dmamap_unload(sc->sc_dmat, data->active); 1704 m_freem(data->m); 1705 data->m = NULL; 1706 } 1707 } 1708 1709 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1710 BUS_DMASYNC_PREWRITE); 1711 1712 ring->queued = 0; 1713 ring->cur = ring->next = 0; 1714 } 1715 1716 void 1717 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1718 { 1719 struct nfe_tx_data *data; 1720 void *desc; 1721 int i, descsize; 1722 1723 if (sc->sc_flags & NFE_40BIT_ADDR) { 1724 desc = ring->desc64; 1725 descsize = sizeof (struct nfe_desc64); 1726 } else { 1727 desc = ring->desc32; 1728 descsize = sizeof (struct nfe_desc32); 1729 } 1730 1731 if (desc != NULL) { 1732 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1733 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1734 bus_dmamap_unload(sc->sc_dmat, ring->map); 1735 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1736 NFE_TX_RING_COUNT * descsize); 1737 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1738 } 1739 1740 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1741 data = &ring->data[i]; 1742 1743 if (data->m != NULL) { 1744 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1745 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1746 bus_dmamap_unload(sc->sc_dmat, data->active); 1747 m_freem(data->m); 1748 } 1749 } 1750 1751 /* ..and now actually destroy the DMA mappings */ 1752 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1753 data = &ring->data[i]; 1754 if (data->map == NULL) 1755 continue; 1756 bus_dmamap_destroy(sc->sc_dmat, data->map); 1757 } 1758 } 1759 1760 int 1761 nfe_ifmedia_upd(struct ifnet *ifp) 1762 { 1763 struct nfe_softc *sc = ifp->if_softc; 1764 struct mii_data *mii = &sc->sc_mii; 1765 struct mii_softc *miisc; 1766 1767 if (mii->mii_instance != 0) { 1768 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1769 mii_phy_reset(miisc); 1770 } 1771 return mii_mediachg(mii); 1772 } 1773 1774 void 1775 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1776 { 1777 struct nfe_softc *sc = ifp->if_softc; 1778 struct mii_data *mii = &sc->sc_mii; 1779 1780 mii_pollstat(mii); 1781 ifmr->ifm_status = mii->mii_media_status; 1782 ifmr->ifm_active = mii->mii_media_active; 1783 } 1784 1785 void 1786 nfe_setmulti(struct nfe_softc *sc) 1787 { 1788 struct ethercom *ec = &sc->sc_ethercom; 1789 struct ifnet *ifp = &ec->ec_if; 1790 struct ether_multi *enm; 1791 struct ether_multistep step; 1792 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1793 uint32_t filter = NFE_RXFILTER_MAGIC; 1794 int i; 1795 1796 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1797 bzero(addr, ETHER_ADDR_LEN); 1798 bzero(mask, ETHER_ADDR_LEN); 1799 goto done; 1800 } 1801 1802 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1803 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1804 1805 ETHER_FIRST_MULTI(step, ec, enm); 1806 while (enm != NULL) { 1807 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1808 ifp->if_flags |= IFF_ALLMULTI; 1809 bzero(addr, ETHER_ADDR_LEN); 1810 bzero(mask, ETHER_ADDR_LEN); 1811 goto done; 1812 } 1813 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1814 addr[i] &= enm->enm_addrlo[i]; 1815 mask[i] &= ~enm->enm_addrlo[i]; 1816 } 1817 ETHER_NEXT_MULTI(step, enm); 1818 } 1819 for (i = 0; i < ETHER_ADDR_LEN; i++) 1820 mask[i] |= addr[i]; 1821 1822 done: 1823 addr[0] |= 0x01; /* make sure multicast bit is set */ 1824 1825 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1826 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1827 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1828 addr[5] << 8 | addr[4]); 1829 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1830 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1831 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1832 mask[5] << 8 | mask[4]); 1833 1834 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1835 NFE_WRITE(sc, NFE_RXFILTER, filter); 1836 } 1837 1838 void 1839 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1840 { 1841 uint32_t tmp; 1842 1843 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1844 addr[0] = (tmp >> 8) & 0xff; 1845 addr[1] = (tmp & 0xff); 1846 1847 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1848 addr[2] = (tmp >> 24) & 0xff; 1849 addr[3] = (tmp >> 16) & 0xff; 1850 addr[4] = (tmp >> 8) & 0xff; 1851 addr[5] = (tmp & 0xff); 1852 } 1853 1854 void 1855 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1856 { 1857 NFE_WRITE(sc, NFE_MACADDR_LO, 1858 addr[5] << 8 | addr[4]); 1859 NFE_WRITE(sc, NFE_MACADDR_HI, 1860 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1861 } 1862 1863 void 1864 nfe_tick(void *arg) 1865 { 1866 struct nfe_softc *sc = arg; 1867 int s; 1868 1869 s = splnet(); 1870 mii_tick(&sc->sc_mii); 1871 splx(s); 1872 1873 callout_schedule(&sc->sc_tick_ch, hz); 1874 } 1875
Indexes created Tue Sep 30 07:10:03 GMT 2025