if_nfe.c revision 1.20
1 /* $NetBSD: if_nfe.c,v 1.20 2007/10/19 12:00:47 ad Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.52 2006/03/02 09:04:00 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.20 2007/10/19 12:00:47 ad Exp $"); 25 26 #include "opt_inet.h" 27 #include "bpfilter.h" 28 #include "vlan.h" 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/types.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/queue.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/socket.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/pci/if_nfereg.h> 74 #include <dev/pci/if_nfevar.h> 75 76 int nfe_match(struct device *, struct cfdata *, void *); 77 void nfe_attach(struct device *, struct device *, void *); 78 void nfe_power(int, void *); 79 void nfe_miibus_statchg(struct device *); 80 int nfe_miibus_readreg(struct device *, int, int); 81 void nfe_miibus_writereg(struct device *, int, int, int); 82 int nfe_intr(void *); 83 int nfe_ioctl(struct ifnet *, u_long, void *); 84 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 85 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 86 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 87 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 88 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 89 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 90 void nfe_rxeof(struct nfe_softc *); 91 void nfe_txeof(struct nfe_softc *); 92 int nfe_encap(struct nfe_softc *, struct mbuf *); 93 void nfe_start(struct ifnet *); 94 void nfe_watchdog(struct ifnet *); 95 int nfe_init(struct ifnet *); 96 void nfe_stop(struct ifnet *, int); 97 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 98 void nfe_jfree(struct mbuf *, void *, size_t, void *); 99 int nfe_jpool_alloc(struct nfe_softc *); 100 void nfe_jpool_free(struct nfe_softc *); 101 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 102 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 105 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 int nfe_ifmedia_upd(struct ifnet *); 108 void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 109 void nfe_setmulti(struct nfe_softc *); 110 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 111 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 112 void nfe_tick(void *); 113 114 CFATTACH_DECL(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, NULL, NULL); 115 116 /*#define NFE_NO_JUMBO*/ 117 118 #ifdef NFE_DEBUG 119 int nfedebug = 0; 120 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 121 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 122 #else 123 #define DPRINTF(x) 124 #define DPRINTFN(n,x) 125 #endif 126 127 /* deal with naming differences */ 128 129 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 130 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 134 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 135 136 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 137 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 140 141 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 142 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 145 146 #ifdef _LP64 147 #define __LP64__ 1 148 #endif 149 150 const struct nfe_product { 151 pci_vendor_id_t vendor; 152 pci_product_id_t product; 153 } nfe_devices[] = { 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 155 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 } 177 }; 178 179 int 180 nfe_match(struct device *dev, struct cfdata *match, void *aux) 181 { 182 struct pci_attach_args *pa = aux; 183 const struct nfe_product *np; 184 int i; 185 186 for (i = 0; i < sizeof(nfe_devices) / sizeof(nfe_devices[0]); i++) { 187 np = &nfe_devices[i]; 188 if (PCI_VENDOR(pa->pa_id) == np->vendor && 189 PCI_PRODUCT(pa->pa_id) == np->product) 190 return 1; 191 } 192 return 0; 193 } 194 195 void 196 nfe_attach(struct device *parent, struct device *self, void *aux) 197 { 198 struct nfe_softc *sc = (struct nfe_softc *)self; 199 struct pci_attach_args *pa = aux; 200 pci_chipset_tag_t pc = pa->pa_pc; 201 pci_intr_handle_t ih; 202 const char *intrstr; 203 struct ifnet *ifp; 204 bus_size_t memsize; 205 pcireg_t memtype; 206 char devinfo[256]; 207 208 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 209 aprint_normal(": %s (rev. 0x%02x)\n", 210 devinfo, PCI_REVISION(pa->pa_class)); 211 212 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 213 switch (memtype) { 214 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 215 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 216 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 217 &sc->sc_memh, NULL, &memsize) == 0) 218 break; 219 /* FALLTHROUGH */ 220 default: 221 printf("%s: could not map mem space\n", sc->sc_dev.dv_xname); 222 return; 223 } 224 225 if (pci_intr_map(pa, &ih) != 0) { 226 printf("%s: could not map interrupt\n", sc->sc_dev.dv_xname); 227 return; 228 } 229 230 intrstr = pci_intr_string(pc, ih); 231 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 232 if (sc->sc_ih == NULL) { 233 printf("%s: could not establish interrupt", 234 sc->sc_dev.dv_xname); 235 if (intrstr != NULL) 236 printf(" at %s", intrstr); 237 printf("\n"); 238 return; 239 } 240 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 241 242 sc->sc_dmat = pa->pa_dmat; 243 244 nfe_get_macaddr(sc, sc->sc_enaddr); 245 printf("%s: Ethernet address %s\n", 246 sc->sc_dev.dv_xname, ether_sprintf(sc->sc_enaddr)); 247 248 sc->sc_flags = 0; 249 250 switch (PCI_PRODUCT(pa->pa_id)) { 251 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 252 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 253 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 254 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 255 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 256 break; 257 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 258 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 259 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 260 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 261 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 262 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 263 sc->sc_flags |= NFE_40BIT_ADDR; 264 break; 265 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 266 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 267 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 268 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 269 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 270 break; 271 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 272 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 273 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 274 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 275 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 276 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 277 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 278 NFE_HW_VLAN; 279 break; 280 } 281 282 #ifndef NFE_NO_JUMBO 283 /* enable jumbo frames for adapters that support it */ 284 if (sc->sc_flags & NFE_JUMBO_SUP) 285 sc->sc_flags |= NFE_USE_JUMBO; 286 #endif 287 288 /* 289 * Allocate Tx and Rx rings. 290 */ 291 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 292 printf("%s: could not allocate Tx ring\n", 293 sc->sc_dev.dv_xname); 294 return; 295 } 296 297 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 298 printf("%s: could not allocate Rx ring\n", 299 sc->sc_dev.dv_xname); 300 nfe_free_tx_ring(sc, &sc->txq); 301 return; 302 } 303 304 ifp = &sc->sc_ethercom.ec_if; 305 ifp->if_softc = sc; 306 ifp->if_mtu = ETHERMTU; 307 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 308 ifp->if_ioctl = nfe_ioctl; 309 ifp->if_start = nfe_start; 310 ifp->if_watchdog = nfe_watchdog; 311 ifp->if_init = nfe_init; 312 ifp->if_baudrate = IF_Gbps(1); 313 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 314 IFQ_SET_READY(&ifp->if_snd); 315 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 316 317 #if NVLAN > 0 318 if (sc->sc_flags & NFE_HW_VLAN) 319 sc->sc_ethercom.ec_capabilities |= 320 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 321 #endif 322 if (sc->sc_flags & NFE_HW_CSUM) { 323 ifp->if_capabilities |= 324 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 325 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 326 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 327 } 328 329 sc->sc_mii.mii_ifp = ifp; 330 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 331 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 332 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 333 334 ifmedia_init(&sc->sc_mii.mii_media, 0, nfe_ifmedia_upd, 335 nfe_ifmedia_sts); 336 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 337 MII_OFFSET_ANY, 0); 338 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 339 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 340 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 341 0, NULL); 342 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 343 } else 344 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 345 346 if_attach(ifp); 347 ether_ifattach(ifp, sc->sc_enaddr); 348 349 callout_init(&sc->sc_tick_ch, 0); 350 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 351 352 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 353 nfe_power, sc); 354 } 355 356 void 357 nfe_power(int why, void *arg) 358 { 359 struct nfe_softc *sc = arg; 360 struct ifnet *ifp; 361 362 if (why == PWR_RESUME) { 363 ifp = &sc->sc_ethercom.ec_if; 364 if (ifp->if_flags & IFF_UP) { 365 ifp->if_flags &= ~IFF_RUNNING; 366 nfe_init(ifp); 367 if (ifp->if_flags & IFF_RUNNING) 368 nfe_start(ifp); 369 } 370 } 371 } 372 373 void 374 nfe_miibus_statchg(struct device *dev) 375 { 376 struct nfe_softc *sc = (struct nfe_softc *)dev; 377 struct mii_data *mii = &sc->sc_mii; 378 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 379 380 phy = NFE_READ(sc, NFE_PHY_IFACE); 381 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 382 383 seed = NFE_READ(sc, NFE_RNDSEED); 384 seed &= ~NFE_SEED_MASK; 385 386 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 387 phy |= NFE_PHY_HDX; /* half-duplex */ 388 misc |= NFE_MISC1_HDX; 389 } 390 391 switch (IFM_SUBTYPE(mii->mii_media_active)) { 392 case IFM_1000_T: /* full-duplex only */ 393 link |= NFE_MEDIA_1000T; 394 seed |= NFE_SEED_1000T; 395 phy |= NFE_PHY_1000T; 396 break; 397 case IFM_100_TX: 398 link |= NFE_MEDIA_100TX; 399 seed |= NFE_SEED_100TX; 400 phy |= NFE_PHY_100TX; 401 break; 402 case IFM_10_T: 403 link |= NFE_MEDIA_10T; 404 seed |= NFE_SEED_10T; 405 break; 406 } 407 408 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 409 410 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 411 NFE_WRITE(sc, NFE_MISC1, misc); 412 NFE_WRITE(sc, NFE_LINKSPEED, link); 413 } 414 415 int 416 nfe_miibus_readreg(struct device *dev, int phy, int reg) 417 { 418 struct nfe_softc *sc = (struct nfe_softc *)dev; 419 uint32_t val; 420 int ntries; 421 422 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 423 424 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 425 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 426 DELAY(100); 427 } 428 429 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 430 431 for (ntries = 0; ntries < 1000; ntries++) { 432 DELAY(100); 433 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 434 break; 435 } 436 if (ntries == 1000) { 437 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 438 sc->sc_dev.dv_xname)); 439 return 0; 440 } 441 442 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 443 DPRINTFN(2, ("%s: could not read PHY\n", 444 sc->sc_dev.dv_xname)); 445 return 0; 446 } 447 448 val = NFE_READ(sc, NFE_PHY_DATA); 449 if (val != 0xffffffff && val != 0) 450 sc->mii_phyaddr = phy; 451 452 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 453 sc->sc_dev.dv_xname, phy, reg, val)); 454 455 return val; 456 } 457 458 void 459 nfe_miibus_writereg(struct device *dev, int phy, int reg, int val) 460 { 461 struct nfe_softc *sc = (struct nfe_softc *)dev; 462 uint32_t ctl; 463 int ntries; 464 465 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 466 467 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 468 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 469 DELAY(100); 470 } 471 472 NFE_WRITE(sc, NFE_PHY_DATA, val); 473 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 474 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 475 476 for (ntries = 0; ntries < 1000; ntries++) { 477 DELAY(100); 478 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 479 break; 480 } 481 #ifdef NFE_DEBUG 482 if (nfedebug >= 2 && ntries == 1000) 483 printf("could not write to PHY\n"); 484 #endif 485 } 486 487 int 488 nfe_intr(void *arg) 489 { 490 struct nfe_softc *sc = arg; 491 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 492 uint32_t r; 493 int handled; 494 495 if ((ifp->if_flags & IFF_UP) == 0) 496 return 0; 497 498 handled = 0; 499 500 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 501 502 for (;;) { 503 r = NFE_READ(sc, NFE_IRQ_STATUS); 504 if ((r & NFE_IRQ_WANTED) == 0) 505 break; 506 507 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 508 handled = 1; 509 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 510 511 if ((r & (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX)) 512 != 0) { 513 /* check Rx ring */ 514 nfe_rxeof(sc); 515 } 516 517 if ((r & (NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE)) 518 != 0) { 519 /* check Tx ring */ 520 nfe_txeof(sc); 521 } 522 523 if ((r & NFE_IRQ_LINK) != 0) { 524 NFE_READ(sc, NFE_PHY_STATUS); 525 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 526 DPRINTF(("%s: link state changed\n", 527 sc->sc_dev.dv_xname)); 528 } 529 } 530 531 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 532 533 if (handled && !IF_IS_EMPTY(&ifp->if_snd)) 534 nfe_start(ifp); 535 536 return handled; 537 } 538 539 int 540 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 541 { 542 struct nfe_softc *sc = ifp->if_softc; 543 struct ifreq *ifr = (struct ifreq *)data; 544 struct ifaddr *ifa = (struct ifaddr *)data; 545 int s, error = 0; 546 547 s = splnet(); 548 549 switch (cmd) { 550 case SIOCSIFADDR: 551 ifp->if_flags |= IFF_UP; 552 nfe_init(ifp); 553 switch (ifa->ifa_addr->sa_family) { 554 #ifdef INET 555 case AF_INET: 556 arp_ifinit(ifp, ifa); 557 break; 558 #endif 559 default: 560 break; 561 } 562 break; 563 case SIOCSIFMTU: 564 if (ifr->ifr_mtu < ETHERMIN || 565 ((sc->sc_flags & NFE_USE_JUMBO) && 566 ifr->ifr_mtu > ETHERMTU_JUMBO) || 567 (!(sc->sc_flags & NFE_USE_JUMBO) && 568 ifr->ifr_mtu > ETHERMTU)) 569 error = EINVAL; 570 else if (ifp->if_mtu != ifr->ifr_mtu) 571 ifp->if_mtu = ifr->ifr_mtu; 572 break; 573 case SIOCSIFFLAGS: 574 if (ifp->if_flags & IFF_UP) { 575 /* 576 * If only the PROMISC or ALLMULTI flag changes, then 577 * don't do a full re-init of the chip, just update 578 * the Rx filter. 579 */ 580 if ((ifp->if_flags & IFF_RUNNING) && 581 ((ifp->if_flags ^ sc->sc_if_flags) & 582 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 583 nfe_setmulti(sc); 584 else 585 nfe_init(ifp); 586 } else { 587 if (ifp->if_flags & IFF_RUNNING) 588 nfe_stop(ifp, 1); 589 } 590 sc->sc_if_flags = ifp->if_flags; 591 break; 592 case SIOCADDMULTI: 593 case SIOCDELMULTI: 594 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 595 if (ifp->if_flags & IFF_RUNNING) 596 nfe_setmulti(sc); 597 error = 0; 598 } 599 break; 600 case SIOCSIFMEDIA: 601 case SIOCGIFMEDIA: 602 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 603 break; 604 default: 605 error = ether_ioctl(ifp, cmd, data); 606 if (error == ENETRESET) { 607 if (ifp->if_flags & IFF_RUNNING) 608 nfe_setmulti(sc); 609 error = 0; 610 } 611 break; 612 613 } 614 615 splx(s); 616 617 return error; 618 } 619 620 void 621 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 622 { 623 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 624 (char *)desc32 - (char *)sc->txq.desc32, 625 sizeof (struct nfe_desc32), ops); 626 } 627 628 void 629 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 630 { 631 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 632 (char *)desc64 - (char *)sc->txq.desc64, 633 sizeof (struct nfe_desc64), ops); 634 } 635 636 void 637 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 638 { 639 if (end > start) { 640 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 641 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 642 (char *)&sc->txq.desc32[end] - 643 (char *)&sc->txq.desc32[start], ops); 644 return; 645 } 646 /* sync from 'start' to end of ring */ 647 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 648 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 649 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 650 (char *)&sc->txq.desc32[start], ops); 651 652 /* sync from start of ring to 'end' */ 653 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 654 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 655 } 656 657 void 658 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 659 { 660 if (end > start) { 661 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 662 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 663 (char *)&sc->txq.desc64[end] - 664 (char *)&sc->txq.desc64[start], ops); 665 return; 666 } 667 /* sync from 'start' to end of ring */ 668 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 669 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 670 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 671 (char *)&sc->txq.desc64[start], ops); 672 673 /* sync from start of ring to 'end' */ 674 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 675 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 676 } 677 678 void 679 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 680 { 681 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 682 (char *)desc32 - (char *)sc->rxq.desc32, 683 sizeof (struct nfe_desc32), ops); 684 } 685 686 void 687 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 688 { 689 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 690 (char *)desc64 - (char *)sc->rxq.desc64, 691 sizeof (struct nfe_desc64), ops); 692 } 693 694 void 695 nfe_rxeof(struct nfe_softc *sc) 696 { 697 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 698 struct nfe_desc32 *desc32; 699 struct nfe_desc64 *desc64; 700 struct nfe_rx_data *data; 701 struct nfe_jbuf *jbuf; 702 struct mbuf *m, *mnew; 703 bus_addr_t physaddr; 704 uint16_t flags; 705 int error, len, i; 706 707 desc32 = NULL; 708 desc64 = NULL; 709 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 710 data = &sc->rxq.data[i]; 711 712 if (sc->sc_flags & NFE_40BIT_ADDR) { 713 desc64 = &sc->rxq.desc64[i]; 714 nfe_rxdesc64_sync(sc, desc64, 715 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 716 717 flags = le16toh(desc64->flags); 718 len = le16toh(desc64->length) & 0x3fff; 719 } else { 720 desc32 = &sc->rxq.desc32[i]; 721 nfe_rxdesc32_sync(sc, desc32, 722 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 723 724 flags = le16toh(desc32->flags); 725 len = le16toh(desc32->length) & 0x3fff; 726 } 727 728 if ((flags & NFE_RX_READY) != 0) 729 break; 730 731 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 732 if ((flags & NFE_RX_VALID_V1) == 0) 733 goto skip; 734 735 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 736 flags &= ~NFE_RX_ERROR; 737 len--; /* fix buffer length */ 738 } 739 } else { 740 if ((flags & NFE_RX_VALID_V2) == 0) 741 goto skip; 742 743 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 744 flags &= ~NFE_RX_ERROR; 745 len--; /* fix buffer length */ 746 } 747 } 748 749 if (flags & NFE_RX_ERROR) { 750 ifp->if_ierrors++; 751 goto skip; 752 } 753 754 /* 755 * Try to allocate a new mbuf for this ring element and load 756 * it before processing the current mbuf. If the ring element 757 * cannot be loaded, drop the received packet and reuse the 758 * old mbuf. In the unlikely case that the old mbuf can't be 759 * reloaded either, explicitly panic. 760 */ 761 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 762 if (mnew == NULL) { 763 ifp->if_ierrors++; 764 goto skip; 765 } 766 767 if (sc->sc_flags & NFE_USE_JUMBO) { 768 physaddr = 769 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 770 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 771 if (len > MCLBYTES) { 772 m_freem(mnew); 773 ifp->if_ierrors++; 774 goto skip1; 775 } 776 MCLGET(mnew, M_DONTWAIT); 777 if ((mnew->m_flags & M_EXT) == 0) { 778 m_freem(mnew); 779 ifp->if_ierrors++; 780 goto skip1; 781 } 782 783 memcpy(mtod(mnew, void *), 784 mtod(data->m, const void *), len); 785 m = mnew; 786 goto mbufcopied; 787 } else { 788 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 789 790 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 791 mtod(data->m, char *) - (char *)sc->rxq.jpool, 792 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 793 794 physaddr = jbuf->physaddr; 795 } 796 } else { 797 MCLGET(mnew, M_DONTWAIT); 798 if ((mnew->m_flags & M_EXT) == 0) { 799 m_freem(mnew); 800 ifp->if_ierrors++; 801 goto skip; 802 } 803 804 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 805 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 806 bus_dmamap_unload(sc->sc_dmat, data->map); 807 808 error = bus_dmamap_load(sc->sc_dmat, data->map, 809 mtod(mnew, void *), MCLBYTES, NULL, 810 BUS_DMA_READ | BUS_DMA_NOWAIT); 811 if (error != 0) { 812 m_freem(mnew); 813 814 /* try to reload the old mbuf */ 815 error = bus_dmamap_load(sc->sc_dmat, data->map, 816 mtod(data->m, void *), MCLBYTES, NULL, 817 BUS_DMA_READ | BUS_DMA_NOWAIT); 818 if (error != 0) { 819 /* very unlikely that it will fail.. */ 820 panic("%s: could not load old rx mbuf", 821 sc->sc_dev.dv_xname); 822 } 823 ifp->if_ierrors++; 824 goto skip; 825 } 826 physaddr = data->map->dm_segs[0].ds_addr; 827 } 828 829 /* 830 * New mbuf successfully loaded, update Rx ring and continue 831 * processing. 832 */ 833 m = data->m; 834 data->m = mnew; 835 836 mbufcopied: 837 /* finalize mbuf */ 838 m->m_pkthdr.len = m->m_len = len; 839 m->m_pkthdr.rcvif = ifp; 840 841 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 842 /* 843 * XXX 844 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 845 */ 846 if (flags & NFE_RX_IP_CSUMOK) { 847 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 848 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 849 sc->sc_dev.dv_xname)); 850 } 851 /* 852 * XXX 853 * no way to check M_CSUM_TCP_UDP_BAD or 854 * other protocols? 855 */ 856 if (flags & NFE_RX_UDP_CSUMOK) { 857 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 858 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 859 sc->sc_dev.dv_xname)); 860 } else if (flags & NFE_RX_TCP_CSUMOK) { 861 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 862 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 863 sc->sc_dev.dv_xname)); 864 } 865 } 866 867 #if NBPFILTER > 0 868 if (ifp->if_bpf) 869 bpf_mtap(ifp->if_bpf, m); 870 #endif 871 ifp->if_ipackets++; 872 (*ifp->if_input)(ifp, m); 873 874 skip1: 875 /* update mapping address in h/w descriptor */ 876 if (sc->sc_flags & NFE_40BIT_ADDR) { 877 #if defined(__LP64__) 878 desc64->physaddr[0] = htole32(physaddr >> 32); 879 #endif 880 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 881 } else { 882 desc32->physaddr = htole32(physaddr); 883 } 884 885 skip: 886 if (sc->sc_flags & NFE_40BIT_ADDR) { 887 desc64->length = htole16(sc->rxq.bufsz); 888 desc64->flags = htole16(NFE_RX_READY); 889 890 nfe_rxdesc64_sync(sc, desc64, 891 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 892 } else { 893 desc32->length = htole16(sc->rxq.bufsz); 894 desc32->flags = htole16(NFE_RX_READY); 895 896 nfe_rxdesc32_sync(sc, desc32, 897 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 898 } 899 } 900 /* update current RX pointer */ 901 sc->rxq.cur = i; 902 } 903 904 void 905 nfe_txeof(struct nfe_softc *sc) 906 { 907 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 908 struct nfe_desc32 *desc32; 909 struct nfe_desc64 *desc64; 910 struct nfe_tx_data *data = NULL; 911 int i; 912 uint16_t flags; 913 914 for (i = sc->txq.next; 915 sc->txq.queued > 0; 916 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 917 if (sc->sc_flags & NFE_40BIT_ADDR) { 918 desc64 = &sc->txq.desc64[i]; 919 nfe_txdesc64_sync(sc, desc64, 920 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 921 922 flags = le16toh(desc64->flags); 923 } else { 924 desc32 = &sc->txq.desc32[i]; 925 nfe_txdesc32_sync(sc, desc32, 926 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 927 928 flags = le16toh(desc32->flags); 929 } 930 931 if ((flags & NFE_TX_VALID) != 0) 932 break; 933 934 data = &sc->txq.data[i]; 935 936 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 937 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 938 data->m == NULL) 939 continue; 940 941 if ((flags & NFE_TX_ERROR_V1) != 0) { 942 printf("%s: tx v1 error 0x%04x\n", 943 sc->sc_dev.dv_xname, flags); 944 ifp->if_oerrors++; 945 } else 946 ifp->if_opackets++; 947 } else { 948 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 949 data->m == NULL) 950 continue; 951 952 if ((flags & NFE_TX_ERROR_V2) != 0) { 953 printf("%s: tx v2 error 0x%04x\n", 954 sc->sc_dev.dv_xname, flags); 955 ifp->if_oerrors++; 956 } else 957 ifp->if_opackets++; 958 } 959 960 if (data->m == NULL) { /* should not get there */ 961 printf("%s: last fragment bit w/o associated mbuf!\n", 962 sc->sc_dev.dv_xname); 963 continue; 964 } 965 966 /* last fragment of the mbuf chain transmitted */ 967 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 968 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 969 bus_dmamap_unload(sc->sc_dmat, data->active); 970 m_freem(data->m); 971 data->m = NULL; 972 } 973 974 sc->txq.next = i; 975 976 if (sc->txq.queued < NFE_TX_RING_COUNT) { 977 /* at least one slot freed */ 978 ifp->if_flags &= ~IFF_OACTIVE; 979 } 980 981 if (sc->txq.queued == 0) { 982 /* all queued packets are sent */ 983 ifp->if_timer = 0; 984 } 985 } 986 987 int 988 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 989 { 990 struct nfe_desc32 *desc32; 991 struct nfe_desc64 *desc64; 992 struct nfe_tx_data *data; 993 bus_dmamap_t map; 994 uint16_t flags, csumflags; 995 #if NVLAN > 0 996 struct m_tag *mtag; 997 uint32_t vtag = 0; 998 #endif 999 int error, i, first; 1000 1001 desc32 = NULL; 1002 desc64 = NULL; 1003 data = NULL; 1004 1005 flags = 0; 1006 csumflags = 0; 1007 first = sc->txq.cur; 1008 1009 map = sc->txq.data[first].map; 1010 1011 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1012 if (error != 0) { 1013 printf("%s: could not map mbuf (error %d)\n", 1014 sc->sc_dev.dv_xname, error); 1015 return error; 1016 } 1017 1018 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1019 bus_dmamap_unload(sc->sc_dmat, map); 1020 return ENOBUFS; 1021 } 1022 1023 #if NVLAN > 0 1024 /* setup h/w VLAN tagging */ 1025 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1026 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1027 #endif 1028 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1029 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1030 csumflags |= NFE_TX_IP_CSUM; 1031 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1032 csumflags |= NFE_TX_TCP_UDP_CSUM; 1033 } 1034 1035 for (i = 0; i < map->dm_nsegs; i++) { 1036 data = &sc->txq.data[sc->txq.cur]; 1037 1038 if (sc->sc_flags & NFE_40BIT_ADDR) { 1039 desc64 = &sc->txq.desc64[sc->txq.cur]; 1040 #if defined(__LP64__) 1041 desc64->physaddr[0] = 1042 htole32(map->dm_segs[i].ds_addr >> 32); 1043 #endif 1044 desc64->physaddr[1] = 1045 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1046 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1047 desc64->flags = htole16(flags); 1048 desc64->vtag = 0; 1049 } else { 1050 desc32 = &sc->txq.desc32[sc->txq.cur]; 1051 1052 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1053 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1054 desc32->flags = htole16(flags); 1055 } 1056 1057 /* 1058 * Setting of the valid bit in the first descriptor is 1059 * deferred until the whole chain is fully setup. 1060 */ 1061 flags |= NFE_TX_VALID; 1062 1063 sc->txq.queued++; 1064 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1065 } 1066 1067 /* the whole mbuf chain has been setup */ 1068 if (sc->sc_flags & NFE_40BIT_ADDR) { 1069 /* fix last descriptor */ 1070 flags |= NFE_TX_LASTFRAG_V2; 1071 desc64->flags = htole16(flags); 1072 1073 /* Checksum flags and vtag belong to the first fragment only. */ 1074 #if NVLAN > 0 1075 sc->txq.desc64[first].vtag = htole32(vtag); 1076 #endif 1077 sc->txq.desc64[first].flags |= htole16(csumflags); 1078 1079 /* finally, set the valid bit in the first descriptor */ 1080 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1081 } else { 1082 /* fix last descriptor */ 1083 if (sc->sc_flags & NFE_JUMBO_SUP) 1084 flags |= NFE_TX_LASTFRAG_V2; 1085 else 1086 flags |= NFE_TX_LASTFRAG_V1; 1087 desc32->flags = htole16(flags); 1088 1089 /* Checksum flags belong to the first fragment only. */ 1090 sc->txq.desc32[first].flags |= htole16(csumflags); 1091 1092 /* finally, set the valid bit in the first descriptor */ 1093 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1094 } 1095 1096 data->m = m0; 1097 data->active = map; 1098 1099 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1100 BUS_DMASYNC_PREWRITE); 1101 1102 return 0; 1103 } 1104 1105 void 1106 nfe_start(struct ifnet *ifp) 1107 { 1108 struct nfe_softc *sc = ifp->if_softc; 1109 int old = sc->txq.queued; 1110 struct mbuf *m0; 1111 1112 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 1113 return; 1114 1115 for (;;) { 1116 IFQ_POLL(&ifp->if_snd, m0); 1117 if (m0 == NULL) 1118 break; 1119 1120 if (nfe_encap(sc, m0) != 0) { 1121 ifp->if_flags |= IFF_OACTIVE; 1122 break; 1123 } 1124 1125 /* packet put in h/w queue, remove from s/w queue */ 1126 IFQ_DEQUEUE(&ifp->if_snd, m0); 1127 1128 #if NBPFILTER > 0 1129 if (ifp->if_bpf != NULL) 1130 bpf_mtap(ifp->if_bpf, m0); 1131 #endif 1132 } 1133 1134 if (sc->txq.queued != old) { 1135 /* packets are queued */ 1136 if (sc->sc_flags & NFE_40BIT_ADDR) 1137 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1138 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1139 else 1140 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1141 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1142 /* kick Tx */ 1143 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1144 1145 /* 1146 * Set a timeout in case the chip goes out to lunch. 1147 */ 1148 ifp->if_timer = 5; 1149 } 1150 } 1151 1152 void 1153 nfe_watchdog(struct ifnet *ifp) 1154 { 1155 struct nfe_softc *sc = ifp->if_softc; 1156 1157 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1158 1159 ifp->if_flags &= ~IFF_RUNNING; 1160 nfe_init(ifp); 1161 1162 ifp->if_oerrors++; 1163 } 1164 1165 int 1166 nfe_init(struct ifnet *ifp) 1167 { 1168 struct nfe_softc *sc = ifp->if_softc; 1169 uint32_t tmp; 1170 int s; 1171 1172 if (ifp->if_flags & IFF_RUNNING) 1173 return 0; 1174 1175 nfe_stop(ifp, 0); 1176 1177 NFE_WRITE(sc, NFE_TX_UNK, 0); 1178 NFE_WRITE(sc, NFE_STATUS, 0); 1179 1180 sc->rxtxctl = NFE_RXTX_BIT2; 1181 if (sc->sc_flags & NFE_40BIT_ADDR) 1182 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1183 else if (sc->sc_flags & NFE_JUMBO_SUP) 1184 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1185 if (sc->sc_flags & NFE_HW_CSUM) 1186 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1187 #if NVLAN > 0 1188 /* 1189 * Although the adapter is capable of stripping VLAN tags from received 1190 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1191 * purpose. This will be done in software by our network stack. 1192 */ 1193 if (sc->sc_flags & NFE_HW_VLAN) 1194 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1195 #endif 1196 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1197 DELAY(10); 1198 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1199 1200 #if NVLAN 1201 if (sc->sc_flags & NFE_HW_VLAN) 1202 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1203 #endif 1204 1205 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1206 1207 /* set MAC address */ 1208 nfe_set_macaddr(sc, sc->sc_enaddr); 1209 1210 /* tell MAC where rings are in memory */ 1211 #ifdef __LP64__ 1212 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1213 #endif 1214 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1215 #ifdef __LP64__ 1216 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1217 #endif 1218 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1219 1220 NFE_WRITE(sc, NFE_RING_SIZE, 1221 (NFE_RX_RING_COUNT - 1) << 16 | 1222 (NFE_TX_RING_COUNT - 1)); 1223 1224 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1225 1226 /* force MAC to wakeup */ 1227 tmp = NFE_READ(sc, NFE_PWR_STATE); 1228 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1229 DELAY(10); 1230 tmp = NFE_READ(sc, NFE_PWR_STATE); 1231 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1232 1233 s = splnet(); 1234 nfe_intr(sc); /* XXX clear IRQ status registers */ 1235 splx(s); 1236 1237 #if 1 1238 /* configure interrupts coalescing/mitigation */ 1239 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1240 #else 1241 /* no interrupt mitigation: one interrupt per packet */ 1242 NFE_WRITE(sc, NFE_IMTIMER, 970); 1243 #endif 1244 1245 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1246 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1247 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1248 1249 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1250 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1251 1252 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1253 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC); 1254 1255 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1256 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1257 DELAY(10); 1258 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1259 1260 /* set Rx filter */ 1261 nfe_setmulti(sc); 1262 1263 nfe_ifmedia_upd(ifp); 1264 1265 nfe_tick(sc); 1266 1267 /* enable Rx */ 1268 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1269 1270 /* enable Tx */ 1271 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1272 1273 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1274 1275 /* enable interrupts */ 1276 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1277 1278 callout_schedule(&sc->sc_tick_ch, hz); 1279 1280 ifp->if_flags |= IFF_RUNNING; 1281 ifp->if_flags &= ~IFF_OACTIVE; 1282 1283 return 0; 1284 } 1285 1286 void 1287 nfe_stop(struct ifnet *ifp, int disable) 1288 { 1289 struct nfe_softc *sc = ifp->if_softc; 1290 1291 callout_stop(&sc->sc_tick_ch); 1292 1293 ifp->if_timer = 0; 1294 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1295 1296 mii_down(&sc->sc_mii); 1297 1298 /* abort Tx */ 1299 NFE_WRITE(sc, NFE_TX_CTL, 0); 1300 1301 /* disable Rx */ 1302 NFE_WRITE(sc, NFE_RX_CTL, 0); 1303 1304 /* disable interrupts */ 1305 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1306 1307 /* reset Tx and Rx rings */ 1308 nfe_reset_tx_ring(sc, &sc->txq); 1309 nfe_reset_rx_ring(sc, &sc->rxq); 1310 } 1311 1312 int 1313 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1314 { 1315 struct nfe_desc32 *desc32; 1316 struct nfe_desc64 *desc64; 1317 struct nfe_rx_data *data; 1318 struct nfe_jbuf *jbuf; 1319 void **desc; 1320 bus_addr_t physaddr; 1321 int i, nsegs, error, descsize; 1322 1323 if (sc->sc_flags & NFE_40BIT_ADDR) { 1324 desc = (void **)&ring->desc64; 1325 descsize = sizeof (struct nfe_desc64); 1326 } else { 1327 desc = (void **)&ring->desc32; 1328 descsize = sizeof (struct nfe_desc32); 1329 } 1330 1331 ring->cur = ring->next = 0; 1332 ring->bufsz = MCLBYTES; 1333 1334 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1335 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1336 if (error != 0) { 1337 printf("%s: could not create desc DMA map\n", 1338 sc->sc_dev.dv_xname); 1339 goto fail; 1340 } 1341 1342 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1343 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1344 if (error != 0) { 1345 printf("%s: could not allocate DMA memory\n", 1346 sc->sc_dev.dv_xname); 1347 goto fail; 1348 } 1349 1350 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1351 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1352 if (error != 0) { 1353 printf("%s: could not map desc DMA memory\n", 1354 sc->sc_dev.dv_xname); 1355 goto fail; 1356 } 1357 1358 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1359 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1360 if (error != 0) { 1361 printf("%s: could not load desc DMA map\n", 1362 sc->sc_dev.dv_xname); 1363 goto fail; 1364 } 1365 1366 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1367 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1368 1369 if (sc->sc_flags & NFE_USE_JUMBO) { 1370 ring->bufsz = NFE_JBYTES; 1371 if ((error = nfe_jpool_alloc(sc)) != 0) { 1372 printf("%s: could not allocate jumbo frames\n", 1373 sc->sc_dev.dv_xname); 1374 goto fail; 1375 } 1376 } 1377 1378 /* 1379 * Pre-allocate Rx buffers and populate Rx ring. 1380 */ 1381 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1382 data = &sc->rxq.data[i]; 1383 1384 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1385 if (data->m == NULL) { 1386 printf("%s: could not allocate rx mbuf\n", 1387 sc->sc_dev.dv_xname); 1388 error = ENOMEM; 1389 goto fail; 1390 } 1391 1392 if (sc->sc_flags & NFE_USE_JUMBO) { 1393 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1394 printf("%s: could not allocate jumbo buffer\n", 1395 sc->sc_dev.dv_xname); 1396 goto fail; 1397 } 1398 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1399 sc); 1400 1401 physaddr = jbuf->physaddr; 1402 } else { 1403 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1404 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1405 if (error != 0) { 1406 printf("%s: could not create DMA map\n", 1407 sc->sc_dev.dv_xname); 1408 goto fail; 1409 } 1410 MCLGET(data->m, M_DONTWAIT); 1411 if (!(data->m->m_flags & M_EXT)) { 1412 printf("%s: could not allocate mbuf cluster\n", 1413 sc->sc_dev.dv_xname); 1414 error = ENOMEM; 1415 goto fail; 1416 } 1417 1418 error = bus_dmamap_load(sc->sc_dmat, data->map, 1419 mtod(data->m, void *), MCLBYTES, NULL, 1420 BUS_DMA_READ | BUS_DMA_NOWAIT); 1421 if (error != 0) { 1422 printf("%s: could not load rx buf DMA map", 1423 sc->sc_dev.dv_xname); 1424 goto fail; 1425 } 1426 physaddr = data->map->dm_segs[0].ds_addr; 1427 } 1428 1429 if (sc->sc_flags & NFE_40BIT_ADDR) { 1430 desc64 = &sc->rxq.desc64[i]; 1431 #if defined(__LP64__) 1432 desc64->physaddr[0] = htole32(physaddr >> 32); 1433 #endif 1434 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1435 desc64->length = htole16(sc->rxq.bufsz); 1436 desc64->flags = htole16(NFE_RX_READY); 1437 } else { 1438 desc32 = &sc->rxq.desc32[i]; 1439 desc32->physaddr = htole32(physaddr); 1440 desc32->length = htole16(sc->rxq.bufsz); 1441 desc32->flags = htole16(NFE_RX_READY); 1442 } 1443 } 1444 1445 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1446 BUS_DMASYNC_PREWRITE); 1447 1448 return 0; 1449 1450 fail: nfe_free_rx_ring(sc, ring); 1451 return error; 1452 } 1453 1454 void 1455 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1456 { 1457 int i; 1458 1459 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1460 if (sc->sc_flags & NFE_40BIT_ADDR) { 1461 ring->desc64[i].length = htole16(ring->bufsz); 1462 ring->desc64[i].flags = htole16(NFE_RX_READY); 1463 } else { 1464 ring->desc32[i].length = htole16(ring->bufsz); 1465 ring->desc32[i].flags = htole16(NFE_RX_READY); 1466 } 1467 } 1468 1469 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1470 BUS_DMASYNC_PREWRITE); 1471 1472 ring->cur = ring->next = 0; 1473 } 1474 1475 void 1476 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1477 { 1478 struct nfe_rx_data *data; 1479 void *desc; 1480 int i, descsize; 1481 1482 if (sc->sc_flags & NFE_40BIT_ADDR) { 1483 desc = ring->desc64; 1484 descsize = sizeof (struct nfe_desc64); 1485 } else { 1486 desc = ring->desc32; 1487 descsize = sizeof (struct nfe_desc32); 1488 } 1489 1490 if (desc != NULL) { 1491 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1492 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1493 bus_dmamap_unload(sc->sc_dmat, ring->map); 1494 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1495 NFE_RX_RING_COUNT * descsize); 1496 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1497 } 1498 1499 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1500 data = &ring->data[i]; 1501 1502 if (data->map != NULL) { 1503 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1504 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1505 bus_dmamap_unload(sc->sc_dmat, data->map); 1506 bus_dmamap_destroy(sc->sc_dmat, data->map); 1507 } 1508 if (data->m != NULL) 1509 m_freem(data->m); 1510 } 1511 } 1512 1513 struct nfe_jbuf * 1514 nfe_jalloc(struct nfe_softc *sc, int i) 1515 { 1516 struct nfe_jbuf *jbuf; 1517 1518 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1519 if (jbuf == NULL) 1520 return NULL; 1521 sc->rxq.jbufmap[i] = 1522 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1523 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1524 return jbuf; 1525 } 1526 1527 /* 1528 * This is called automatically by the network stack when the mbuf is freed. 1529 * Caution must be taken that the NIC might be reset by the time the mbuf is 1530 * freed. 1531 */ 1532 void 1533 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1534 { 1535 struct nfe_softc *sc = arg; 1536 struct nfe_jbuf *jbuf; 1537 int i; 1538 1539 /* find the jbuf from the base pointer */ 1540 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1541 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1542 printf("%s: request to free a buffer (%p) not managed by us\n", 1543 sc->sc_dev.dv_xname, buf); 1544 return; 1545 } 1546 jbuf = &sc->rxq.jbuf[i]; 1547 1548 /* ..and put it back in the free list */ 1549 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1550 1551 if (m != NULL) 1552 pool_cache_put(&mbpool_cache, m); 1553 } 1554 1555 int 1556 nfe_jpool_alloc(struct nfe_softc *sc) 1557 { 1558 struct nfe_rx_ring *ring = &sc->rxq; 1559 struct nfe_jbuf *jbuf; 1560 bus_addr_t physaddr; 1561 char *buf; 1562 int i, nsegs, error; 1563 1564 /* 1565 * Allocate a big chunk of DMA'able memory. 1566 */ 1567 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1568 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1569 if (error != 0) { 1570 printf("%s: could not create jumbo DMA map\n", 1571 sc->sc_dev.dv_xname); 1572 goto fail; 1573 } 1574 1575 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1576 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1577 if (error != 0) { 1578 printf("%s could not allocate jumbo DMA memory\n", 1579 sc->sc_dev.dv_xname); 1580 goto fail; 1581 } 1582 1583 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1584 &ring->jpool, BUS_DMA_NOWAIT); 1585 if (error != 0) { 1586 printf("%s: could not map jumbo DMA memory\n", 1587 sc->sc_dev.dv_xname); 1588 goto fail; 1589 } 1590 1591 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1592 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1593 if (error != 0) { 1594 printf("%s: could not load jumbo DMA map\n", 1595 sc->sc_dev.dv_xname); 1596 goto fail; 1597 } 1598 1599 /* ..and split it into 9KB chunks */ 1600 SLIST_INIT(&ring->jfreelist); 1601 1602 buf = ring->jpool; 1603 physaddr = ring->jmap->dm_segs[0].ds_addr; 1604 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1605 jbuf = &ring->jbuf[i]; 1606 1607 jbuf->buf = buf; 1608 jbuf->physaddr = physaddr; 1609 1610 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1611 1612 buf += NFE_JBYTES; 1613 physaddr += NFE_JBYTES; 1614 } 1615 1616 return 0; 1617 1618 fail: nfe_jpool_free(sc); 1619 return error; 1620 } 1621 1622 void 1623 nfe_jpool_free(struct nfe_softc *sc) 1624 { 1625 struct nfe_rx_ring *ring = &sc->rxq; 1626 1627 if (ring->jmap != NULL) { 1628 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1629 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1630 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1631 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1632 } 1633 if (ring->jpool != NULL) { 1634 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1635 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1636 } 1637 } 1638 1639 int 1640 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1641 { 1642 int i, nsegs, error; 1643 void **desc; 1644 int descsize; 1645 1646 if (sc->sc_flags & NFE_40BIT_ADDR) { 1647 desc = (void **)&ring->desc64; 1648 descsize = sizeof (struct nfe_desc64); 1649 } else { 1650 desc = (void **)&ring->desc32; 1651 descsize = sizeof (struct nfe_desc32); 1652 } 1653 1654 ring->queued = 0; 1655 ring->cur = ring->next = 0; 1656 1657 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1658 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1659 1660 if (error != 0) { 1661 printf("%s: could not create desc DMA map\n", 1662 sc->sc_dev.dv_xname); 1663 goto fail; 1664 } 1665 1666 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1667 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1668 if (error != 0) { 1669 printf("%s: could not allocate DMA memory\n", 1670 sc->sc_dev.dv_xname); 1671 goto fail; 1672 } 1673 1674 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1675 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1676 if (error != 0) { 1677 printf("%s: could not map desc DMA memory\n", 1678 sc->sc_dev.dv_xname); 1679 goto fail; 1680 } 1681 1682 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1683 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1684 if (error != 0) { 1685 printf("%s: could not load desc DMA map\n", 1686 sc->sc_dev.dv_xname); 1687 goto fail; 1688 } 1689 1690 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1691 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1692 1693 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1694 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1695 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1696 &ring->data[i].map); 1697 if (error != 0) { 1698 printf("%s: could not create DMA map\n", 1699 sc->sc_dev.dv_xname); 1700 goto fail; 1701 } 1702 } 1703 1704 return 0; 1705 1706 fail: nfe_free_tx_ring(sc, ring); 1707 return error; 1708 } 1709 1710 void 1711 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1712 { 1713 struct nfe_tx_data *data; 1714 int i; 1715 1716 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1717 if (sc->sc_flags & NFE_40BIT_ADDR) 1718 ring->desc64[i].flags = 0; 1719 else 1720 ring->desc32[i].flags = 0; 1721 1722 data = &ring->data[i]; 1723 1724 if (data->m != NULL) { 1725 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1726 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1727 bus_dmamap_unload(sc->sc_dmat, data->active); 1728 m_freem(data->m); 1729 data->m = NULL; 1730 } 1731 } 1732 1733 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1734 BUS_DMASYNC_PREWRITE); 1735 1736 ring->queued = 0; 1737 ring->cur = ring->next = 0; 1738 } 1739 1740 void 1741 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1742 { 1743 struct nfe_tx_data *data; 1744 void *desc; 1745 int i, descsize; 1746 1747 if (sc->sc_flags & NFE_40BIT_ADDR) { 1748 desc = ring->desc64; 1749 descsize = sizeof (struct nfe_desc64); 1750 } else { 1751 desc = ring->desc32; 1752 descsize = sizeof (struct nfe_desc32); 1753 } 1754 1755 if (desc != NULL) { 1756 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1757 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1758 bus_dmamap_unload(sc->sc_dmat, ring->map); 1759 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1760 NFE_TX_RING_COUNT * descsize); 1761 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1762 } 1763 1764 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1765 data = &ring->data[i]; 1766 1767 if (data->m != NULL) { 1768 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1769 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1770 bus_dmamap_unload(sc->sc_dmat, data->active); 1771 m_freem(data->m); 1772 } 1773 } 1774 1775 /* ..and now actually destroy the DMA mappings */ 1776 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1777 data = &ring->data[i]; 1778 if (data->map == NULL) 1779 continue; 1780 bus_dmamap_destroy(sc->sc_dmat, data->map); 1781 } 1782 } 1783 1784 int 1785 nfe_ifmedia_upd(struct ifnet *ifp) 1786 { 1787 struct nfe_softc *sc = ifp->if_softc; 1788 struct mii_data *mii = &sc->sc_mii; 1789 struct mii_softc *miisc; 1790 1791 if (mii->mii_instance != 0) { 1792 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1793 mii_phy_reset(miisc); 1794 } 1795 return mii_mediachg(mii); 1796 } 1797 1798 void 1799 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1800 { 1801 struct nfe_softc *sc = ifp->if_softc; 1802 struct mii_data *mii = &sc->sc_mii; 1803 1804 mii_pollstat(mii); 1805 ifmr->ifm_status = mii->mii_media_status; 1806 ifmr->ifm_active = mii->mii_media_active; 1807 } 1808 1809 void 1810 nfe_setmulti(struct nfe_softc *sc) 1811 { 1812 struct ethercom *ec = &sc->sc_ethercom; 1813 struct ifnet *ifp = &ec->ec_if; 1814 struct ether_multi *enm; 1815 struct ether_multistep step; 1816 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1817 uint32_t filter = NFE_RXFILTER_MAGIC; 1818 int i; 1819 1820 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1821 bzero(addr, ETHER_ADDR_LEN); 1822 bzero(mask, ETHER_ADDR_LEN); 1823 goto done; 1824 } 1825 1826 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1827 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1828 1829 ETHER_FIRST_MULTI(step, ec, enm); 1830 while (enm != NULL) { 1831 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1832 ifp->if_flags |= IFF_ALLMULTI; 1833 bzero(addr, ETHER_ADDR_LEN); 1834 bzero(mask, ETHER_ADDR_LEN); 1835 goto done; 1836 } 1837 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1838 addr[i] &= enm->enm_addrlo[i]; 1839 mask[i] &= ~enm->enm_addrlo[i]; 1840 } 1841 ETHER_NEXT_MULTI(step, enm); 1842 } 1843 for (i = 0; i < ETHER_ADDR_LEN; i++) 1844 mask[i] |= addr[i]; 1845 1846 done: 1847 addr[0] |= 0x01; /* make sure multicast bit is set */ 1848 1849 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1850 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1851 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1852 addr[5] << 8 | addr[4]); 1853 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1854 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1855 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1856 mask[5] << 8 | mask[4]); 1857 1858 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1859 NFE_WRITE(sc, NFE_RXFILTER, filter); 1860 } 1861 1862 void 1863 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1864 { 1865 uint32_t tmp; 1866 1867 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1868 addr[0] = (tmp >> 8) & 0xff; 1869 addr[1] = (tmp & 0xff); 1870 1871 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1872 addr[2] = (tmp >> 24) & 0xff; 1873 addr[3] = (tmp >> 16) & 0xff; 1874 addr[4] = (tmp >> 8) & 0xff; 1875 addr[5] = (tmp & 0xff); 1876 } 1877 1878 void 1879 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1880 { 1881 NFE_WRITE(sc, NFE_MACADDR_LO, 1882 addr[5] << 8 | addr[4]); 1883 NFE_WRITE(sc, NFE_MACADDR_HI, 1884 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1885 } 1886 1887 void 1888 nfe_tick(void *arg) 1889 { 1890 struct nfe_softc *sc = arg; 1891 int s; 1892 1893 s = splnet(); 1894 mii_tick(&sc->sc_mii); 1895 splx(s); 1896 1897 callout_schedule(&sc->sc_tick_ch, hz); 1898 } 1899
Indexes created Tue Sep 30 07:10:03 GMT 2025