if_nfe.c revision 1.22
1 /* $NetBSD: if_nfe.c,v 1.22 2007/11/14 12:40:54 xtraeme Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.52 2006/03/02 09:04:00 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.22 2007/11/14 12:40:54 xtraeme Exp $"); 25 26 #include "opt_inet.h" 27 #include "bpfilter.h" 28 #include "vlan.h" 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/types.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/queue.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/socket.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/pci/if_nfereg.h> 74 #include <dev/pci/if_nfevar.h> 75 76 int nfe_match(struct device *, struct cfdata *, void *); 77 void nfe_attach(struct device *, struct device *, void *); 78 void nfe_power(int, void *); 79 void nfe_miibus_statchg(struct device *); 80 int nfe_miibus_readreg(struct device *, int, int); 81 void nfe_miibus_writereg(struct device *, int, int, int); 82 int nfe_intr(void *); 83 int nfe_ioctl(struct ifnet *, u_long, void *); 84 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 85 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 86 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 87 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 88 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 89 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 90 void nfe_rxeof(struct nfe_softc *); 91 void nfe_txeof(struct nfe_softc *); 92 int nfe_encap(struct nfe_softc *, struct mbuf *); 93 void nfe_start(struct ifnet *); 94 void nfe_watchdog(struct ifnet *); 95 int nfe_init(struct ifnet *); 96 void nfe_stop(struct ifnet *, int); 97 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 98 void nfe_jfree(struct mbuf *, void *, size_t, void *); 99 int nfe_jpool_alloc(struct nfe_softc *); 100 void nfe_jpool_free(struct nfe_softc *); 101 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 102 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 105 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 int nfe_ifmedia_upd(struct ifnet *); 108 void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 109 void nfe_setmulti(struct nfe_softc *); 110 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 111 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 112 void nfe_tick(void *); 113 114 CFATTACH_DECL(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, NULL, NULL); 115 116 /*#define NFE_NO_JUMBO*/ 117 118 #ifdef NFE_DEBUG 119 int nfedebug = 0; 120 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 121 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 122 #else 123 #define DPRINTF(x) 124 #define DPRINTFN(n,x) 125 #endif 126 127 /* deal with naming differences */ 128 129 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 130 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 134 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 135 136 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 137 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 140 141 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 142 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 145 146 #ifdef _LP64 147 #define __LP64__ 1 148 #endif 149 150 const struct nfe_product { 151 pci_vendor_id_t vendor; 152 pci_product_id_t product; 153 } nfe_devices[] = { 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 155 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 183 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 184 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 } 185 }; 186 187 int 188 nfe_match(struct device *dev, struct cfdata *match, void *aux) 189 { 190 struct pci_attach_args *pa = aux; 191 const struct nfe_product *np; 192 int i; 193 194 for (i = 0; i < sizeof(nfe_devices) / sizeof(nfe_devices[0]); i++) { 195 np = &nfe_devices[i]; 196 if (PCI_VENDOR(pa->pa_id) == np->vendor && 197 PCI_PRODUCT(pa->pa_id) == np->product) 198 return 1; 199 } 200 return 0; 201 } 202 203 void 204 nfe_attach(struct device *parent, struct device *self, void *aux) 205 { 206 struct nfe_softc *sc = (struct nfe_softc *)self; 207 struct pci_attach_args *pa = aux; 208 pci_chipset_tag_t pc = pa->pa_pc; 209 pci_intr_handle_t ih; 210 const char *intrstr; 211 struct ifnet *ifp; 212 bus_size_t memsize; 213 pcireg_t memtype; 214 char devinfo[256]; 215 216 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 217 aprint_normal(": %s (rev. 0x%02x)\n", 218 devinfo, PCI_REVISION(pa->pa_class)); 219 220 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 221 switch (memtype) { 222 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 223 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 224 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 225 &sc->sc_memh, NULL, &memsize) == 0) 226 break; 227 /* FALLTHROUGH */ 228 default: 229 printf("%s: could not map mem space\n", sc->sc_dev.dv_xname); 230 return; 231 } 232 233 if (pci_intr_map(pa, &ih) != 0) { 234 printf("%s: could not map interrupt\n", sc->sc_dev.dv_xname); 235 return; 236 } 237 238 intrstr = pci_intr_string(pc, ih); 239 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 240 if (sc->sc_ih == NULL) { 241 printf("%s: could not establish interrupt", 242 sc->sc_dev.dv_xname); 243 if (intrstr != NULL) 244 printf(" at %s", intrstr); 245 printf("\n"); 246 return; 247 } 248 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 249 250 sc->sc_dmat = pa->pa_dmat; 251 252 nfe_get_macaddr(sc, sc->sc_enaddr); 253 printf("%s: Ethernet address %s\n", 254 sc->sc_dev.dv_xname, ether_sprintf(sc->sc_enaddr)); 255 256 sc->sc_flags = 0; 257 258 switch (PCI_PRODUCT(pa->pa_id)) { 259 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 260 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 261 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 262 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 263 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 264 break; 265 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 266 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 267 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 268 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 269 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 270 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 271 sc->sc_flags |= NFE_40BIT_ADDR; 272 break; 273 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 274 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 275 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 276 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 277 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 278 break; 279 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 280 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 281 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 282 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 283 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 284 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 285 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 286 NFE_HW_VLAN; 287 break; 288 } 289 290 #ifndef NFE_NO_JUMBO 291 /* enable jumbo frames for adapters that support it */ 292 if (sc->sc_flags & NFE_JUMBO_SUP) 293 sc->sc_flags |= NFE_USE_JUMBO; 294 #endif 295 296 /* 297 * Allocate Tx and Rx rings. 298 */ 299 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 300 printf("%s: could not allocate Tx ring\n", 301 sc->sc_dev.dv_xname); 302 return; 303 } 304 305 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 306 printf("%s: could not allocate Rx ring\n", 307 sc->sc_dev.dv_xname); 308 nfe_free_tx_ring(sc, &sc->txq); 309 return; 310 } 311 312 ifp = &sc->sc_ethercom.ec_if; 313 ifp->if_softc = sc; 314 ifp->if_mtu = ETHERMTU; 315 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 316 ifp->if_ioctl = nfe_ioctl; 317 ifp->if_start = nfe_start; 318 ifp->if_watchdog = nfe_watchdog; 319 ifp->if_init = nfe_init; 320 ifp->if_baudrate = IF_Gbps(1); 321 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 322 IFQ_SET_READY(&ifp->if_snd); 323 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 324 325 #if NVLAN > 0 326 if (sc->sc_flags & NFE_HW_VLAN) 327 sc->sc_ethercom.ec_capabilities |= 328 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 329 #endif 330 if (sc->sc_flags & NFE_HW_CSUM) { 331 ifp->if_capabilities |= 332 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 333 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 334 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 335 } 336 337 sc->sc_mii.mii_ifp = ifp; 338 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 339 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 340 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 341 342 ifmedia_init(&sc->sc_mii.mii_media, 0, nfe_ifmedia_upd, 343 nfe_ifmedia_sts); 344 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 345 MII_OFFSET_ANY, 0); 346 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 347 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 348 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 349 0, NULL); 350 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 351 } else 352 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 353 354 if_attach(ifp); 355 ether_ifattach(ifp, sc->sc_enaddr); 356 357 callout_init(&sc->sc_tick_ch, 0); 358 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 359 360 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 361 nfe_power, sc); 362 } 363 364 void 365 nfe_power(int why, void *arg) 366 { 367 struct nfe_softc *sc = arg; 368 struct ifnet *ifp; 369 370 if (why == PWR_RESUME) { 371 ifp = &sc->sc_ethercom.ec_if; 372 if (ifp->if_flags & IFF_UP) { 373 ifp->if_flags &= ~IFF_RUNNING; 374 nfe_init(ifp); 375 if (ifp->if_flags & IFF_RUNNING) 376 nfe_start(ifp); 377 } 378 } 379 } 380 381 void 382 nfe_miibus_statchg(struct device *dev) 383 { 384 struct nfe_softc *sc = (struct nfe_softc *)dev; 385 struct mii_data *mii = &sc->sc_mii; 386 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 387 388 phy = NFE_READ(sc, NFE_PHY_IFACE); 389 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 390 391 seed = NFE_READ(sc, NFE_RNDSEED); 392 seed &= ~NFE_SEED_MASK; 393 394 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 395 phy |= NFE_PHY_HDX; /* half-duplex */ 396 misc |= NFE_MISC1_HDX; 397 } 398 399 switch (IFM_SUBTYPE(mii->mii_media_active)) { 400 case IFM_1000_T: /* full-duplex only */ 401 link |= NFE_MEDIA_1000T; 402 seed |= NFE_SEED_1000T; 403 phy |= NFE_PHY_1000T; 404 break; 405 case IFM_100_TX: 406 link |= NFE_MEDIA_100TX; 407 seed |= NFE_SEED_100TX; 408 phy |= NFE_PHY_100TX; 409 break; 410 case IFM_10_T: 411 link |= NFE_MEDIA_10T; 412 seed |= NFE_SEED_10T; 413 break; 414 } 415 416 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 417 418 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 419 NFE_WRITE(sc, NFE_MISC1, misc); 420 NFE_WRITE(sc, NFE_LINKSPEED, link); 421 } 422 423 int 424 nfe_miibus_readreg(struct device *dev, int phy, int reg) 425 { 426 struct nfe_softc *sc = (struct nfe_softc *)dev; 427 uint32_t val; 428 int ntries; 429 430 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 431 432 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 433 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 434 DELAY(100); 435 } 436 437 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 438 439 for (ntries = 0; ntries < 1000; ntries++) { 440 DELAY(100); 441 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 442 break; 443 } 444 if (ntries == 1000) { 445 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 446 sc->sc_dev.dv_xname)); 447 return 0; 448 } 449 450 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 451 DPRINTFN(2, ("%s: could not read PHY\n", 452 sc->sc_dev.dv_xname)); 453 return 0; 454 } 455 456 val = NFE_READ(sc, NFE_PHY_DATA); 457 if (val != 0xffffffff && val != 0) 458 sc->mii_phyaddr = phy; 459 460 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 461 sc->sc_dev.dv_xname, phy, reg, val)); 462 463 return val; 464 } 465 466 void 467 nfe_miibus_writereg(struct device *dev, int phy, int reg, int val) 468 { 469 struct nfe_softc *sc = (struct nfe_softc *)dev; 470 uint32_t ctl; 471 int ntries; 472 473 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 474 475 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 476 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 477 DELAY(100); 478 } 479 480 NFE_WRITE(sc, NFE_PHY_DATA, val); 481 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 482 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 483 484 for (ntries = 0; ntries < 1000; ntries++) { 485 DELAY(100); 486 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 487 break; 488 } 489 #ifdef NFE_DEBUG 490 if (nfedebug >= 2 && ntries == 1000) 491 printf("could not write to PHY\n"); 492 #endif 493 } 494 495 int 496 nfe_intr(void *arg) 497 { 498 struct nfe_softc *sc = arg; 499 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 500 uint32_t r; 501 int handled; 502 503 if ((ifp->if_flags & IFF_UP) == 0) 504 return 0; 505 506 handled = 0; 507 508 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 509 510 for (;;) { 511 r = NFE_READ(sc, NFE_IRQ_STATUS); 512 if ((r & NFE_IRQ_WANTED) == 0) 513 break; 514 515 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 516 handled = 1; 517 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 518 519 if ((r & (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX)) 520 != 0) { 521 /* check Rx ring */ 522 nfe_rxeof(sc); 523 } 524 525 if ((r & (NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE)) 526 != 0) { 527 /* check Tx ring */ 528 nfe_txeof(sc); 529 } 530 531 if ((r & NFE_IRQ_LINK) != 0) { 532 NFE_READ(sc, NFE_PHY_STATUS); 533 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 534 DPRINTF(("%s: link state changed\n", 535 sc->sc_dev.dv_xname)); 536 } 537 } 538 539 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 540 541 if (handled && !IF_IS_EMPTY(&ifp->if_snd)) 542 nfe_start(ifp); 543 544 return handled; 545 } 546 547 int 548 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 549 { 550 struct nfe_softc *sc = ifp->if_softc; 551 struct ifreq *ifr = (struct ifreq *)data; 552 struct ifaddr *ifa = (struct ifaddr *)data; 553 int s, error = 0; 554 555 s = splnet(); 556 557 switch (cmd) { 558 case SIOCSIFADDR: 559 ifp->if_flags |= IFF_UP; 560 nfe_init(ifp); 561 switch (ifa->ifa_addr->sa_family) { 562 #ifdef INET 563 case AF_INET: 564 arp_ifinit(ifp, ifa); 565 break; 566 #endif 567 default: 568 break; 569 } 570 break; 571 case SIOCSIFMTU: 572 if (ifr->ifr_mtu < ETHERMIN || 573 ((sc->sc_flags & NFE_USE_JUMBO) && 574 ifr->ifr_mtu > ETHERMTU_JUMBO) || 575 (!(sc->sc_flags & NFE_USE_JUMBO) && 576 ifr->ifr_mtu > ETHERMTU)) 577 error = EINVAL; 578 else if (ifp->if_mtu != ifr->ifr_mtu) 579 ifp->if_mtu = ifr->ifr_mtu; 580 break; 581 case SIOCSIFFLAGS: 582 if (ifp->if_flags & IFF_UP) { 583 /* 584 * If only the PROMISC or ALLMULTI flag changes, then 585 * don't do a full re-init of the chip, just update 586 * the Rx filter. 587 */ 588 if ((ifp->if_flags & IFF_RUNNING) && 589 ((ifp->if_flags ^ sc->sc_if_flags) & 590 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 591 nfe_setmulti(sc); 592 else 593 nfe_init(ifp); 594 } else { 595 if (ifp->if_flags & IFF_RUNNING) 596 nfe_stop(ifp, 1); 597 } 598 sc->sc_if_flags = ifp->if_flags; 599 break; 600 case SIOCADDMULTI: 601 case SIOCDELMULTI: 602 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 603 if (ifp->if_flags & IFF_RUNNING) 604 nfe_setmulti(sc); 605 error = 0; 606 } 607 break; 608 case SIOCSIFMEDIA: 609 case SIOCGIFMEDIA: 610 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 611 break; 612 default: 613 error = ether_ioctl(ifp, cmd, data); 614 if (error == ENETRESET) { 615 if (ifp->if_flags & IFF_RUNNING) 616 nfe_setmulti(sc); 617 error = 0; 618 } 619 break; 620 621 } 622 623 splx(s); 624 625 return error; 626 } 627 628 void 629 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 630 { 631 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 632 (char *)desc32 - (char *)sc->txq.desc32, 633 sizeof (struct nfe_desc32), ops); 634 } 635 636 void 637 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 638 { 639 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 640 (char *)desc64 - (char *)sc->txq.desc64, 641 sizeof (struct nfe_desc64), ops); 642 } 643 644 void 645 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 646 { 647 if (end > start) { 648 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 649 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 650 (char *)&sc->txq.desc32[end] - 651 (char *)&sc->txq.desc32[start], ops); 652 return; 653 } 654 /* sync from 'start' to end of ring */ 655 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 656 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 657 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 658 (char *)&sc->txq.desc32[start], ops); 659 660 /* sync from start of ring to 'end' */ 661 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 662 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 663 } 664 665 void 666 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 667 { 668 if (end > start) { 669 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 670 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 671 (char *)&sc->txq.desc64[end] - 672 (char *)&sc->txq.desc64[start], ops); 673 return; 674 } 675 /* sync from 'start' to end of ring */ 676 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 677 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 678 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 679 (char *)&sc->txq.desc64[start], ops); 680 681 /* sync from start of ring to 'end' */ 682 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 683 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 684 } 685 686 void 687 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 688 { 689 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 690 (char *)desc32 - (char *)sc->rxq.desc32, 691 sizeof (struct nfe_desc32), ops); 692 } 693 694 void 695 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 696 { 697 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 698 (char *)desc64 - (char *)sc->rxq.desc64, 699 sizeof (struct nfe_desc64), ops); 700 } 701 702 void 703 nfe_rxeof(struct nfe_softc *sc) 704 { 705 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 706 struct nfe_desc32 *desc32; 707 struct nfe_desc64 *desc64; 708 struct nfe_rx_data *data; 709 struct nfe_jbuf *jbuf; 710 struct mbuf *m, *mnew; 711 bus_addr_t physaddr; 712 uint16_t flags; 713 int error, len, i; 714 715 desc32 = NULL; 716 desc64 = NULL; 717 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 718 data = &sc->rxq.data[i]; 719 720 if (sc->sc_flags & NFE_40BIT_ADDR) { 721 desc64 = &sc->rxq.desc64[i]; 722 nfe_rxdesc64_sync(sc, desc64, 723 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 724 725 flags = le16toh(desc64->flags); 726 len = le16toh(desc64->length) & 0x3fff; 727 } else { 728 desc32 = &sc->rxq.desc32[i]; 729 nfe_rxdesc32_sync(sc, desc32, 730 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 731 732 flags = le16toh(desc32->flags); 733 len = le16toh(desc32->length) & 0x3fff; 734 } 735 736 if ((flags & NFE_RX_READY) != 0) 737 break; 738 739 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 740 if ((flags & NFE_RX_VALID_V1) == 0) 741 goto skip; 742 743 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 744 flags &= ~NFE_RX_ERROR; 745 len--; /* fix buffer length */ 746 } 747 } else { 748 if ((flags & NFE_RX_VALID_V2) == 0) 749 goto skip; 750 751 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 752 flags &= ~NFE_RX_ERROR; 753 len--; /* fix buffer length */ 754 } 755 } 756 757 if (flags & NFE_RX_ERROR) { 758 ifp->if_ierrors++; 759 goto skip; 760 } 761 762 /* 763 * Try to allocate a new mbuf for this ring element and load 764 * it before processing the current mbuf. If the ring element 765 * cannot be loaded, drop the received packet and reuse the 766 * old mbuf. In the unlikely case that the old mbuf can't be 767 * reloaded either, explicitly panic. 768 */ 769 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 770 if (mnew == NULL) { 771 ifp->if_ierrors++; 772 goto skip; 773 } 774 775 if (sc->sc_flags & NFE_USE_JUMBO) { 776 physaddr = 777 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 778 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 779 if (len > MCLBYTES) { 780 m_freem(mnew); 781 ifp->if_ierrors++; 782 goto skip1; 783 } 784 MCLGET(mnew, M_DONTWAIT); 785 if ((mnew->m_flags & M_EXT) == 0) { 786 m_freem(mnew); 787 ifp->if_ierrors++; 788 goto skip1; 789 } 790 791 memcpy(mtod(mnew, void *), 792 mtod(data->m, const void *), len); 793 m = mnew; 794 goto mbufcopied; 795 } else { 796 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 797 798 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 799 mtod(data->m, char *) - (char *)sc->rxq.jpool, 800 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 801 802 physaddr = jbuf->physaddr; 803 } 804 } else { 805 MCLGET(mnew, M_DONTWAIT); 806 if ((mnew->m_flags & M_EXT) == 0) { 807 m_freem(mnew); 808 ifp->if_ierrors++; 809 goto skip; 810 } 811 812 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 813 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 814 bus_dmamap_unload(sc->sc_dmat, data->map); 815 816 error = bus_dmamap_load(sc->sc_dmat, data->map, 817 mtod(mnew, void *), MCLBYTES, NULL, 818 BUS_DMA_READ | BUS_DMA_NOWAIT); 819 if (error != 0) { 820 m_freem(mnew); 821 822 /* try to reload the old mbuf */ 823 error = bus_dmamap_load(sc->sc_dmat, data->map, 824 mtod(data->m, void *), MCLBYTES, NULL, 825 BUS_DMA_READ | BUS_DMA_NOWAIT); 826 if (error != 0) { 827 /* very unlikely that it will fail.. */ 828 panic("%s: could not load old rx mbuf", 829 sc->sc_dev.dv_xname); 830 } 831 ifp->if_ierrors++; 832 goto skip; 833 } 834 physaddr = data->map->dm_segs[0].ds_addr; 835 } 836 837 /* 838 * New mbuf successfully loaded, update Rx ring and continue 839 * processing. 840 */ 841 m = data->m; 842 data->m = mnew; 843 844 mbufcopied: 845 /* finalize mbuf */ 846 m->m_pkthdr.len = m->m_len = len; 847 m->m_pkthdr.rcvif = ifp; 848 849 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 850 /* 851 * XXX 852 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 853 */ 854 if (flags & NFE_RX_IP_CSUMOK) { 855 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 856 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 857 sc->sc_dev.dv_xname)); 858 } 859 /* 860 * XXX 861 * no way to check M_CSUM_TCP_UDP_BAD or 862 * other protocols? 863 */ 864 if (flags & NFE_RX_UDP_CSUMOK) { 865 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 866 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 867 sc->sc_dev.dv_xname)); 868 } else if (flags & NFE_RX_TCP_CSUMOK) { 869 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 870 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 871 sc->sc_dev.dv_xname)); 872 } 873 } 874 875 #if NBPFILTER > 0 876 if (ifp->if_bpf) 877 bpf_mtap(ifp->if_bpf, m); 878 #endif 879 ifp->if_ipackets++; 880 (*ifp->if_input)(ifp, m); 881 882 skip1: 883 /* update mapping address in h/w descriptor */ 884 if (sc->sc_flags & NFE_40BIT_ADDR) { 885 #if defined(__LP64__) 886 desc64->physaddr[0] = htole32(physaddr >> 32); 887 #endif 888 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 889 } else { 890 desc32->physaddr = htole32(physaddr); 891 } 892 893 skip: 894 if (sc->sc_flags & NFE_40BIT_ADDR) { 895 desc64->length = htole16(sc->rxq.bufsz); 896 desc64->flags = htole16(NFE_RX_READY); 897 898 nfe_rxdesc64_sync(sc, desc64, 899 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 900 } else { 901 desc32->length = htole16(sc->rxq.bufsz); 902 desc32->flags = htole16(NFE_RX_READY); 903 904 nfe_rxdesc32_sync(sc, desc32, 905 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 906 } 907 } 908 /* update current RX pointer */ 909 sc->rxq.cur = i; 910 } 911 912 void 913 nfe_txeof(struct nfe_softc *sc) 914 { 915 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 916 struct nfe_desc32 *desc32; 917 struct nfe_desc64 *desc64; 918 struct nfe_tx_data *data = NULL; 919 int i; 920 uint16_t flags; 921 922 for (i = sc->txq.next; 923 sc->txq.queued > 0; 924 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 925 if (sc->sc_flags & NFE_40BIT_ADDR) { 926 desc64 = &sc->txq.desc64[i]; 927 nfe_txdesc64_sync(sc, desc64, 928 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 929 930 flags = le16toh(desc64->flags); 931 } else { 932 desc32 = &sc->txq.desc32[i]; 933 nfe_txdesc32_sync(sc, desc32, 934 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 935 936 flags = le16toh(desc32->flags); 937 } 938 939 if ((flags & NFE_TX_VALID) != 0) 940 break; 941 942 data = &sc->txq.data[i]; 943 944 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 945 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 946 data->m == NULL) 947 continue; 948 949 if ((flags & NFE_TX_ERROR_V1) != 0) { 950 printf("%s: tx v1 error 0x%04x\n", 951 sc->sc_dev.dv_xname, flags); 952 ifp->if_oerrors++; 953 } else 954 ifp->if_opackets++; 955 } else { 956 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 957 data->m == NULL) 958 continue; 959 960 if ((flags & NFE_TX_ERROR_V2) != 0) { 961 printf("%s: tx v2 error 0x%04x\n", 962 sc->sc_dev.dv_xname, flags); 963 ifp->if_oerrors++; 964 } else 965 ifp->if_opackets++; 966 } 967 968 if (data->m == NULL) { /* should not get there */ 969 printf("%s: last fragment bit w/o associated mbuf!\n", 970 sc->sc_dev.dv_xname); 971 continue; 972 } 973 974 /* last fragment of the mbuf chain transmitted */ 975 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 976 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 977 bus_dmamap_unload(sc->sc_dmat, data->active); 978 m_freem(data->m); 979 data->m = NULL; 980 } 981 982 sc->txq.next = i; 983 984 if (sc->txq.queued < NFE_TX_RING_COUNT) { 985 /* at least one slot freed */ 986 ifp->if_flags &= ~IFF_OACTIVE; 987 } 988 989 if (sc->txq.queued == 0) { 990 /* all queued packets are sent */ 991 ifp->if_timer = 0; 992 } 993 } 994 995 int 996 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 997 { 998 struct nfe_desc32 *desc32; 999 struct nfe_desc64 *desc64; 1000 struct nfe_tx_data *data; 1001 bus_dmamap_t map; 1002 uint16_t flags, csumflags; 1003 #if NVLAN > 0 1004 struct m_tag *mtag; 1005 uint32_t vtag = 0; 1006 #endif 1007 int error, i, first; 1008 1009 desc32 = NULL; 1010 desc64 = NULL; 1011 data = NULL; 1012 1013 flags = 0; 1014 csumflags = 0; 1015 first = sc->txq.cur; 1016 1017 map = sc->txq.data[first].map; 1018 1019 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1020 if (error != 0) { 1021 printf("%s: could not map mbuf (error %d)\n", 1022 sc->sc_dev.dv_xname, error); 1023 return error; 1024 } 1025 1026 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1027 bus_dmamap_unload(sc->sc_dmat, map); 1028 return ENOBUFS; 1029 } 1030 1031 #if NVLAN > 0 1032 /* setup h/w VLAN tagging */ 1033 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1034 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1035 #endif 1036 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1037 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1038 csumflags |= NFE_TX_IP_CSUM; 1039 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1040 csumflags |= NFE_TX_TCP_UDP_CSUM; 1041 } 1042 1043 for (i = 0; i < map->dm_nsegs; i++) { 1044 data = &sc->txq.data[sc->txq.cur]; 1045 1046 if (sc->sc_flags & NFE_40BIT_ADDR) { 1047 desc64 = &sc->txq.desc64[sc->txq.cur]; 1048 #if defined(__LP64__) 1049 desc64->physaddr[0] = 1050 htole32(map->dm_segs[i].ds_addr >> 32); 1051 #endif 1052 desc64->physaddr[1] = 1053 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1054 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1055 desc64->flags = htole16(flags); 1056 desc64->vtag = 0; 1057 } else { 1058 desc32 = &sc->txq.desc32[sc->txq.cur]; 1059 1060 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1061 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1062 desc32->flags = htole16(flags); 1063 } 1064 1065 /* 1066 * Setting of the valid bit in the first descriptor is 1067 * deferred until the whole chain is fully setup. 1068 */ 1069 flags |= NFE_TX_VALID; 1070 1071 sc->txq.queued++; 1072 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1073 } 1074 1075 /* the whole mbuf chain has been setup */ 1076 if (sc->sc_flags & NFE_40BIT_ADDR) { 1077 /* fix last descriptor */ 1078 flags |= NFE_TX_LASTFRAG_V2; 1079 desc64->flags = htole16(flags); 1080 1081 /* Checksum flags and vtag belong to the first fragment only. */ 1082 #if NVLAN > 0 1083 sc->txq.desc64[first].vtag = htole32(vtag); 1084 #endif 1085 sc->txq.desc64[first].flags |= htole16(csumflags); 1086 1087 /* finally, set the valid bit in the first descriptor */ 1088 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1089 } else { 1090 /* fix last descriptor */ 1091 if (sc->sc_flags & NFE_JUMBO_SUP) 1092 flags |= NFE_TX_LASTFRAG_V2; 1093 else 1094 flags |= NFE_TX_LASTFRAG_V1; 1095 desc32->flags = htole16(flags); 1096 1097 /* Checksum flags belong to the first fragment only. */ 1098 sc->txq.desc32[first].flags |= htole16(csumflags); 1099 1100 /* finally, set the valid bit in the first descriptor */ 1101 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1102 } 1103 1104 data->m = m0; 1105 data->active = map; 1106 1107 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1108 BUS_DMASYNC_PREWRITE); 1109 1110 return 0; 1111 } 1112 1113 void 1114 nfe_start(struct ifnet *ifp) 1115 { 1116 struct nfe_softc *sc = ifp->if_softc; 1117 int old = sc->txq.queued; 1118 struct mbuf *m0; 1119 1120 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 1121 return; 1122 1123 for (;;) { 1124 IFQ_POLL(&ifp->if_snd, m0); 1125 if (m0 == NULL) 1126 break; 1127 1128 if (nfe_encap(sc, m0) != 0) { 1129 ifp->if_flags |= IFF_OACTIVE; 1130 break; 1131 } 1132 1133 /* packet put in h/w queue, remove from s/w queue */ 1134 IFQ_DEQUEUE(&ifp->if_snd, m0); 1135 1136 #if NBPFILTER > 0 1137 if (ifp->if_bpf != NULL) 1138 bpf_mtap(ifp->if_bpf, m0); 1139 #endif 1140 } 1141 1142 if (sc->txq.queued != old) { 1143 /* packets are queued */ 1144 if (sc->sc_flags & NFE_40BIT_ADDR) 1145 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1146 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1147 else 1148 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1149 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1150 /* kick Tx */ 1151 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1152 1153 /* 1154 * Set a timeout in case the chip goes out to lunch. 1155 */ 1156 ifp->if_timer = 5; 1157 } 1158 } 1159 1160 void 1161 nfe_watchdog(struct ifnet *ifp) 1162 { 1163 struct nfe_softc *sc = ifp->if_softc; 1164 1165 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1166 1167 ifp->if_flags &= ~IFF_RUNNING; 1168 nfe_init(ifp); 1169 1170 ifp->if_oerrors++; 1171 } 1172 1173 int 1174 nfe_init(struct ifnet *ifp) 1175 { 1176 struct nfe_softc *sc = ifp->if_softc; 1177 uint32_t tmp; 1178 int s; 1179 1180 if (ifp->if_flags & IFF_RUNNING) 1181 return 0; 1182 1183 nfe_stop(ifp, 0); 1184 1185 NFE_WRITE(sc, NFE_TX_UNK, 0); 1186 NFE_WRITE(sc, NFE_STATUS, 0); 1187 1188 sc->rxtxctl = NFE_RXTX_BIT2; 1189 if (sc->sc_flags & NFE_40BIT_ADDR) 1190 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1191 else if (sc->sc_flags & NFE_JUMBO_SUP) 1192 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1193 if (sc->sc_flags & NFE_HW_CSUM) 1194 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1195 #if NVLAN > 0 1196 /* 1197 * Although the adapter is capable of stripping VLAN tags from received 1198 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1199 * purpose. This will be done in software by our network stack. 1200 */ 1201 if (sc->sc_flags & NFE_HW_VLAN) 1202 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1203 #endif 1204 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1205 DELAY(10); 1206 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1207 1208 #if NVLAN 1209 if (sc->sc_flags & NFE_HW_VLAN) 1210 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1211 #endif 1212 1213 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1214 1215 /* set MAC address */ 1216 nfe_set_macaddr(sc, sc->sc_enaddr); 1217 1218 /* tell MAC where rings are in memory */ 1219 #ifdef __LP64__ 1220 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1221 #endif 1222 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1223 #ifdef __LP64__ 1224 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1225 #endif 1226 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1227 1228 NFE_WRITE(sc, NFE_RING_SIZE, 1229 (NFE_RX_RING_COUNT - 1) << 16 | 1230 (NFE_TX_RING_COUNT - 1)); 1231 1232 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1233 1234 /* force MAC to wakeup */ 1235 tmp = NFE_READ(sc, NFE_PWR_STATE); 1236 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1237 DELAY(10); 1238 tmp = NFE_READ(sc, NFE_PWR_STATE); 1239 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1240 1241 s = splnet(); 1242 nfe_intr(sc); /* XXX clear IRQ status registers */ 1243 splx(s); 1244 1245 #if 1 1246 /* configure interrupts coalescing/mitigation */ 1247 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1248 #else 1249 /* no interrupt mitigation: one interrupt per packet */ 1250 NFE_WRITE(sc, NFE_IMTIMER, 970); 1251 #endif 1252 1253 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1254 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1255 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1256 1257 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1258 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1259 1260 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1261 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC); 1262 1263 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1264 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1265 DELAY(10); 1266 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1267 1268 /* set Rx filter */ 1269 nfe_setmulti(sc); 1270 1271 nfe_ifmedia_upd(ifp); 1272 1273 nfe_tick(sc); 1274 1275 /* enable Rx */ 1276 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1277 1278 /* enable Tx */ 1279 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1280 1281 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1282 1283 /* enable interrupts */ 1284 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1285 1286 callout_schedule(&sc->sc_tick_ch, hz); 1287 1288 ifp->if_flags |= IFF_RUNNING; 1289 ifp->if_flags &= ~IFF_OACTIVE; 1290 1291 return 0; 1292 } 1293 1294 void 1295 nfe_stop(struct ifnet *ifp, int disable) 1296 { 1297 struct nfe_softc *sc = ifp->if_softc; 1298 1299 callout_stop(&sc->sc_tick_ch); 1300 1301 ifp->if_timer = 0; 1302 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1303 1304 mii_down(&sc->sc_mii); 1305 1306 /* abort Tx */ 1307 NFE_WRITE(sc, NFE_TX_CTL, 0); 1308 1309 /* disable Rx */ 1310 NFE_WRITE(sc, NFE_RX_CTL, 0); 1311 1312 /* disable interrupts */ 1313 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1314 1315 /* reset Tx and Rx rings */ 1316 nfe_reset_tx_ring(sc, &sc->txq); 1317 nfe_reset_rx_ring(sc, &sc->rxq); 1318 } 1319 1320 int 1321 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1322 { 1323 struct nfe_desc32 *desc32; 1324 struct nfe_desc64 *desc64; 1325 struct nfe_rx_data *data; 1326 struct nfe_jbuf *jbuf; 1327 void **desc; 1328 bus_addr_t physaddr; 1329 int i, nsegs, error, descsize; 1330 1331 if (sc->sc_flags & NFE_40BIT_ADDR) { 1332 desc = (void **)&ring->desc64; 1333 descsize = sizeof (struct nfe_desc64); 1334 } else { 1335 desc = (void **)&ring->desc32; 1336 descsize = sizeof (struct nfe_desc32); 1337 } 1338 1339 ring->cur = ring->next = 0; 1340 ring->bufsz = MCLBYTES; 1341 1342 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1343 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1344 if (error != 0) { 1345 printf("%s: could not create desc DMA map\n", 1346 sc->sc_dev.dv_xname); 1347 goto fail; 1348 } 1349 1350 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1351 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1352 if (error != 0) { 1353 printf("%s: could not allocate DMA memory\n", 1354 sc->sc_dev.dv_xname); 1355 goto fail; 1356 } 1357 1358 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1359 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1360 if (error != 0) { 1361 printf("%s: could not map desc DMA memory\n", 1362 sc->sc_dev.dv_xname); 1363 goto fail; 1364 } 1365 1366 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1367 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1368 if (error != 0) { 1369 printf("%s: could not load desc DMA map\n", 1370 sc->sc_dev.dv_xname); 1371 goto fail; 1372 } 1373 1374 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1375 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1376 1377 if (sc->sc_flags & NFE_USE_JUMBO) { 1378 ring->bufsz = NFE_JBYTES; 1379 if ((error = nfe_jpool_alloc(sc)) != 0) { 1380 printf("%s: could not allocate jumbo frames\n", 1381 sc->sc_dev.dv_xname); 1382 goto fail; 1383 } 1384 } 1385 1386 /* 1387 * Pre-allocate Rx buffers and populate Rx ring. 1388 */ 1389 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1390 data = &sc->rxq.data[i]; 1391 1392 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1393 if (data->m == NULL) { 1394 printf("%s: could not allocate rx mbuf\n", 1395 sc->sc_dev.dv_xname); 1396 error = ENOMEM; 1397 goto fail; 1398 } 1399 1400 if (sc->sc_flags & NFE_USE_JUMBO) { 1401 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1402 printf("%s: could not allocate jumbo buffer\n", 1403 sc->sc_dev.dv_xname); 1404 goto fail; 1405 } 1406 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1407 sc); 1408 1409 physaddr = jbuf->physaddr; 1410 } else { 1411 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1412 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1413 if (error != 0) { 1414 printf("%s: could not create DMA map\n", 1415 sc->sc_dev.dv_xname); 1416 goto fail; 1417 } 1418 MCLGET(data->m, M_DONTWAIT); 1419 if (!(data->m->m_flags & M_EXT)) { 1420 printf("%s: could not allocate mbuf cluster\n", 1421 sc->sc_dev.dv_xname); 1422 error = ENOMEM; 1423 goto fail; 1424 } 1425 1426 error = bus_dmamap_load(sc->sc_dmat, data->map, 1427 mtod(data->m, void *), MCLBYTES, NULL, 1428 BUS_DMA_READ | BUS_DMA_NOWAIT); 1429 if (error != 0) { 1430 printf("%s: could not load rx buf DMA map", 1431 sc->sc_dev.dv_xname); 1432 goto fail; 1433 } 1434 physaddr = data->map->dm_segs[0].ds_addr; 1435 } 1436 1437 if (sc->sc_flags & NFE_40BIT_ADDR) { 1438 desc64 = &sc->rxq.desc64[i]; 1439 #if defined(__LP64__) 1440 desc64->physaddr[0] = htole32(physaddr >> 32); 1441 #endif 1442 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1443 desc64->length = htole16(sc->rxq.bufsz); 1444 desc64->flags = htole16(NFE_RX_READY); 1445 } else { 1446 desc32 = &sc->rxq.desc32[i]; 1447 desc32->physaddr = htole32(physaddr); 1448 desc32->length = htole16(sc->rxq.bufsz); 1449 desc32->flags = htole16(NFE_RX_READY); 1450 } 1451 } 1452 1453 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1454 BUS_DMASYNC_PREWRITE); 1455 1456 return 0; 1457 1458 fail: nfe_free_rx_ring(sc, ring); 1459 return error; 1460 } 1461 1462 void 1463 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1464 { 1465 int i; 1466 1467 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1468 if (sc->sc_flags & NFE_40BIT_ADDR) { 1469 ring->desc64[i].length = htole16(ring->bufsz); 1470 ring->desc64[i].flags = htole16(NFE_RX_READY); 1471 } else { 1472 ring->desc32[i].length = htole16(ring->bufsz); 1473 ring->desc32[i].flags = htole16(NFE_RX_READY); 1474 } 1475 } 1476 1477 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1478 BUS_DMASYNC_PREWRITE); 1479 1480 ring->cur = ring->next = 0; 1481 } 1482 1483 void 1484 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1485 { 1486 struct nfe_rx_data *data; 1487 void *desc; 1488 int i, descsize; 1489 1490 if (sc->sc_flags & NFE_40BIT_ADDR) { 1491 desc = ring->desc64; 1492 descsize = sizeof (struct nfe_desc64); 1493 } else { 1494 desc = ring->desc32; 1495 descsize = sizeof (struct nfe_desc32); 1496 } 1497 1498 if (desc != NULL) { 1499 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1500 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1501 bus_dmamap_unload(sc->sc_dmat, ring->map); 1502 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1503 NFE_RX_RING_COUNT * descsize); 1504 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1505 } 1506 1507 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1508 data = &ring->data[i]; 1509 1510 if (data->map != NULL) { 1511 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1512 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1513 bus_dmamap_unload(sc->sc_dmat, data->map); 1514 bus_dmamap_destroy(sc->sc_dmat, data->map); 1515 } 1516 if (data->m != NULL) 1517 m_freem(data->m); 1518 } 1519 } 1520 1521 struct nfe_jbuf * 1522 nfe_jalloc(struct nfe_softc *sc, int i) 1523 { 1524 struct nfe_jbuf *jbuf; 1525 1526 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1527 if (jbuf == NULL) 1528 return NULL; 1529 sc->rxq.jbufmap[i] = 1530 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1531 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1532 return jbuf; 1533 } 1534 1535 /* 1536 * This is called automatically by the network stack when the mbuf is freed. 1537 * Caution must be taken that the NIC might be reset by the time the mbuf is 1538 * freed. 1539 */ 1540 void 1541 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1542 { 1543 struct nfe_softc *sc = arg; 1544 struct nfe_jbuf *jbuf; 1545 int i; 1546 1547 /* find the jbuf from the base pointer */ 1548 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1549 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1550 printf("%s: request to free a buffer (%p) not managed by us\n", 1551 sc->sc_dev.dv_xname, buf); 1552 return; 1553 } 1554 jbuf = &sc->rxq.jbuf[i]; 1555 1556 /* ..and put it back in the free list */ 1557 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1558 1559 if (m != NULL) 1560 pool_cache_put(mb_cache, m); 1561 } 1562 1563 int 1564 nfe_jpool_alloc(struct nfe_softc *sc) 1565 { 1566 struct nfe_rx_ring *ring = &sc->rxq; 1567 struct nfe_jbuf *jbuf; 1568 bus_addr_t physaddr; 1569 char *buf; 1570 int i, nsegs, error; 1571 1572 /* 1573 * Allocate a big chunk of DMA'able memory. 1574 */ 1575 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1576 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1577 if (error != 0) { 1578 printf("%s: could not create jumbo DMA map\n", 1579 sc->sc_dev.dv_xname); 1580 goto fail; 1581 } 1582 1583 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1584 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1585 if (error != 0) { 1586 printf("%s could not allocate jumbo DMA memory\n", 1587 sc->sc_dev.dv_xname); 1588 goto fail; 1589 } 1590 1591 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1592 &ring->jpool, BUS_DMA_NOWAIT); 1593 if (error != 0) { 1594 printf("%s: could not map jumbo DMA memory\n", 1595 sc->sc_dev.dv_xname); 1596 goto fail; 1597 } 1598 1599 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1600 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1601 if (error != 0) { 1602 printf("%s: could not load jumbo DMA map\n", 1603 sc->sc_dev.dv_xname); 1604 goto fail; 1605 } 1606 1607 /* ..and split it into 9KB chunks */ 1608 SLIST_INIT(&ring->jfreelist); 1609 1610 buf = ring->jpool; 1611 physaddr = ring->jmap->dm_segs[0].ds_addr; 1612 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1613 jbuf = &ring->jbuf[i]; 1614 1615 jbuf->buf = buf; 1616 jbuf->physaddr = physaddr; 1617 1618 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1619 1620 buf += NFE_JBYTES; 1621 physaddr += NFE_JBYTES; 1622 } 1623 1624 return 0; 1625 1626 fail: nfe_jpool_free(sc); 1627 return error; 1628 } 1629 1630 void 1631 nfe_jpool_free(struct nfe_softc *sc) 1632 { 1633 struct nfe_rx_ring *ring = &sc->rxq; 1634 1635 if (ring->jmap != NULL) { 1636 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1637 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1638 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1639 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1640 } 1641 if (ring->jpool != NULL) { 1642 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1643 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1644 } 1645 } 1646 1647 int 1648 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1649 { 1650 int i, nsegs, error; 1651 void **desc; 1652 int descsize; 1653 1654 if (sc->sc_flags & NFE_40BIT_ADDR) { 1655 desc = (void **)&ring->desc64; 1656 descsize = sizeof (struct nfe_desc64); 1657 } else { 1658 desc = (void **)&ring->desc32; 1659 descsize = sizeof (struct nfe_desc32); 1660 } 1661 1662 ring->queued = 0; 1663 ring->cur = ring->next = 0; 1664 1665 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1666 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1667 1668 if (error != 0) { 1669 printf("%s: could not create desc DMA map\n", 1670 sc->sc_dev.dv_xname); 1671 goto fail; 1672 } 1673 1674 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1675 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1676 if (error != 0) { 1677 printf("%s: could not allocate DMA memory\n", 1678 sc->sc_dev.dv_xname); 1679 goto fail; 1680 } 1681 1682 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1683 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1684 if (error != 0) { 1685 printf("%s: could not map desc DMA memory\n", 1686 sc->sc_dev.dv_xname); 1687 goto fail; 1688 } 1689 1690 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1691 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1692 if (error != 0) { 1693 printf("%s: could not load desc DMA map\n", 1694 sc->sc_dev.dv_xname); 1695 goto fail; 1696 } 1697 1698 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1699 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1700 1701 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1702 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1703 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1704 &ring->data[i].map); 1705 if (error != 0) { 1706 printf("%s: could not create DMA map\n", 1707 sc->sc_dev.dv_xname); 1708 goto fail; 1709 } 1710 } 1711 1712 return 0; 1713 1714 fail: nfe_free_tx_ring(sc, ring); 1715 return error; 1716 } 1717 1718 void 1719 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1720 { 1721 struct nfe_tx_data *data; 1722 int i; 1723 1724 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1725 if (sc->sc_flags & NFE_40BIT_ADDR) 1726 ring->desc64[i].flags = 0; 1727 else 1728 ring->desc32[i].flags = 0; 1729 1730 data = &ring->data[i]; 1731 1732 if (data->m != NULL) { 1733 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1734 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1735 bus_dmamap_unload(sc->sc_dmat, data->active); 1736 m_freem(data->m); 1737 data->m = NULL; 1738 } 1739 } 1740 1741 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1742 BUS_DMASYNC_PREWRITE); 1743 1744 ring->queued = 0; 1745 ring->cur = ring->next = 0; 1746 } 1747 1748 void 1749 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1750 { 1751 struct nfe_tx_data *data; 1752 void *desc; 1753 int i, descsize; 1754 1755 if (sc->sc_flags & NFE_40BIT_ADDR) { 1756 desc = ring->desc64; 1757 descsize = sizeof (struct nfe_desc64); 1758 } else { 1759 desc = ring->desc32; 1760 descsize = sizeof (struct nfe_desc32); 1761 } 1762 1763 if (desc != NULL) { 1764 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1765 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1766 bus_dmamap_unload(sc->sc_dmat, ring->map); 1767 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1768 NFE_TX_RING_COUNT * descsize); 1769 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1770 } 1771 1772 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1773 data = &ring->data[i]; 1774 1775 if (data->m != NULL) { 1776 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1777 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1778 bus_dmamap_unload(sc->sc_dmat, data->active); 1779 m_freem(data->m); 1780 } 1781 } 1782 1783 /* ..and now actually destroy the DMA mappings */ 1784 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1785 data = &ring->data[i]; 1786 if (data->map == NULL) 1787 continue; 1788 bus_dmamap_destroy(sc->sc_dmat, data->map); 1789 } 1790 } 1791 1792 int 1793 nfe_ifmedia_upd(struct ifnet *ifp) 1794 { 1795 struct nfe_softc *sc = ifp->if_softc; 1796 struct mii_data *mii = &sc->sc_mii; 1797 struct mii_softc *miisc; 1798 1799 if (mii->mii_instance != 0) { 1800 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1801 mii_phy_reset(miisc); 1802 } 1803 return mii_mediachg(mii); 1804 } 1805 1806 void 1807 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1808 { 1809 struct nfe_softc *sc = ifp->if_softc; 1810 struct mii_data *mii = &sc->sc_mii; 1811 1812 mii_pollstat(mii); 1813 ifmr->ifm_status = mii->mii_media_status; 1814 ifmr->ifm_active = mii->mii_media_active; 1815 } 1816 1817 void 1818 nfe_setmulti(struct nfe_softc *sc) 1819 { 1820 struct ethercom *ec = &sc->sc_ethercom; 1821 struct ifnet *ifp = &ec->ec_if; 1822 struct ether_multi *enm; 1823 struct ether_multistep step; 1824 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1825 uint32_t filter = NFE_RXFILTER_MAGIC; 1826 int i; 1827 1828 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1829 bzero(addr, ETHER_ADDR_LEN); 1830 bzero(mask, ETHER_ADDR_LEN); 1831 goto done; 1832 } 1833 1834 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1835 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1836 1837 ETHER_FIRST_MULTI(step, ec, enm); 1838 while (enm != NULL) { 1839 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1840 ifp->if_flags |= IFF_ALLMULTI; 1841 bzero(addr, ETHER_ADDR_LEN); 1842 bzero(mask, ETHER_ADDR_LEN); 1843 goto done; 1844 } 1845 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1846 addr[i] &= enm->enm_addrlo[i]; 1847 mask[i] &= ~enm->enm_addrlo[i]; 1848 } 1849 ETHER_NEXT_MULTI(step, enm); 1850 } 1851 for (i = 0; i < ETHER_ADDR_LEN; i++) 1852 mask[i] |= addr[i]; 1853 1854 done: 1855 addr[0] |= 0x01; /* make sure multicast bit is set */ 1856 1857 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1858 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1859 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1860 addr[5] << 8 | addr[4]); 1861 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1862 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1863 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1864 mask[5] << 8 | mask[4]); 1865 1866 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1867 NFE_WRITE(sc, NFE_RXFILTER, filter); 1868 } 1869 1870 void 1871 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1872 { 1873 uint32_t tmp; 1874 1875 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1876 addr[0] = (tmp >> 8) & 0xff; 1877 addr[1] = (tmp & 0xff); 1878 1879 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1880 addr[2] = (tmp >> 24) & 0xff; 1881 addr[3] = (tmp >> 16) & 0xff; 1882 addr[4] = (tmp >> 8) & 0xff; 1883 addr[5] = (tmp & 0xff); 1884 } 1885 1886 void 1887 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1888 { 1889 NFE_WRITE(sc, NFE_MACADDR_LO, 1890 addr[5] << 8 | addr[4]); 1891 NFE_WRITE(sc, NFE_MACADDR_HI, 1892 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1893 } 1894 1895 void 1896 nfe_tick(void *arg) 1897 { 1898 struct nfe_softc *sc = arg; 1899 int s; 1900 1901 s = splnet(); 1902 mii_tick(&sc->sc_mii); 1903 splx(s); 1904 1905 callout_schedule(&sc->sc_tick_ch, hz); 1906 } 1907
Indexes created Tue Sep 30 07:10:03 GMT 2025