if_nfe.c revision 1.23
1 /* $NetBSD: if_nfe.c,v 1.23 2007/11/14 14:59:50 xtraeme Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.52 2006/03/02 09:04:00 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.23 2007/11/14 14:59:50 xtraeme Exp $"); 25 26 #include "opt_inet.h" 27 #include "bpfilter.h" 28 #include "vlan.h" 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/types.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/queue.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/socket.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/pci/if_nfereg.h> 74 #include <dev/pci/if_nfevar.h> 75 76 int nfe_match(struct device *, struct cfdata *, void *); 77 void nfe_attach(struct device *, struct device *, void *); 78 void nfe_power(int, void *); 79 void nfe_miibus_statchg(struct device *); 80 int nfe_miibus_readreg(struct device *, int, int); 81 void nfe_miibus_writereg(struct device *, int, int, int); 82 int nfe_intr(void *); 83 int nfe_ioctl(struct ifnet *, u_long, void *); 84 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 85 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 86 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 87 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 88 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 89 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 90 void nfe_rxeof(struct nfe_softc *); 91 void nfe_txeof(struct nfe_softc *); 92 int nfe_encap(struct nfe_softc *, struct mbuf *); 93 void nfe_start(struct ifnet *); 94 void nfe_watchdog(struct ifnet *); 95 int nfe_init(struct ifnet *); 96 void nfe_stop(struct ifnet *, int); 97 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 98 void nfe_jfree(struct mbuf *, void *, size_t, void *); 99 int nfe_jpool_alloc(struct nfe_softc *); 100 void nfe_jpool_free(struct nfe_softc *); 101 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 102 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 105 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 int nfe_ifmedia_upd(struct ifnet *); 108 void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 109 void nfe_setmulti(struct nfe_softc *); 110 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 111 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 112 void nfe_tick(void *); 113 114 CFATTACH_DECL(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, NULL, NULL); 115 116 /*#define NFE_NO_JUMBO*/ 117 118 #ifdef NFE_DEBUG 119 int nfedebug = 0; 120 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 121 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 122 #else 123 #define DPRINTF(x) 124 #define DPRINTFN(n,x) 125 #endif 126 127 /* deal with naming differences */ 128 129 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 130 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 134 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 135 136 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 137 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 140 141 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 142 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 145 146 #ifdef _LP64 147 #define __LP64__ 1 148 #endif 149 150 const struct nfe_product { 151 pci_vendor_id_t vendor; 152 pci_product_id_t product; 153 } nfe_devices[] = { 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 155 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 183 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 184 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 } 185 }; 186 187 int 188 nfe_match(struct device *dev, struct cfdata *match, void *aux) 189 { 190 struct pci_attach_args *pa = aux; 191 const struct nfe_product *np; 192 int i; 193 194 for (i = 0; i < sizeof(nfe_devices) / sizeof(nfe_devices[0]); i++) { 195 np = &nfe_devices[i]; 196 if (PCI_VENDOR(pa->pa_id) == np->vendor && 197 PCI_PRODUCT(pa->pa_id) == np->product) 198 return 1; 199 } 200 return 0; 201 } 202 203 void 204 nfe_attach(struct device *parent, struct device *self, void *aux) 205 { 206 struct nfe_softc *sc = (struct nfe_softc *)self; 207 struct pci_attach_args *pa = aux; 208 pci_chipset_tag_t pc = pa->pa_pc; 209 pci_intr_handle_t ih; 210 const char *intrstr; 211 struct ifnet *ifp; 212 bus_size_t memsize; 213 pcireg_t memtype; 214 char devinfo[256]; 215 216 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 217 aprint_normal(": %s (rev. 0x%02x)\n", 218 devinfo, PCI_REVISION(pa->pa_class)); 219 220 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 221 switch (memtype) { 222 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 223 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 224 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 225 &sc->sc_memh, NULL, &memsize) == 0) 226 break; 227 /* FALLTHROUGH */ 228 default: 229 printf("%s: could not map mem space\n", sc->sc_dev.dv_xname); 230 return; 231 } 232 233 if (pci_intr_map(pa, &ih) != 0) { 234 printf("%s: could not map interrupt\n", sc->sc_dev.dv_xname); 235 return; 236 } 237 238 intrstr = pci_intr_string(pc, ih); 239 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 240 if (sc->sc_ih == NULL) { 241 printf("%s: could not establish interrupt", 242 sc->sc_dev.dv_xname); 243 if (intrstr != NULL) 244 printf(" at %s", intrstr); 245 printf("\n"); 246 return; 247 } 248 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 249 250 sc->sc_dmat = pa->pa_dmat; 251 252 nfe_get_macaddr(sc, sc->sc_enaddr); 253 printf("%s: Ethernet address %s\n", 254 sc->sc_dev.dv_xname, ether_sprintf(sc->sc_enaddr)); 255 256 sc->sc_flags = 0; 257 258 switch (PCI_PRODUCT(pa->pa_id)) { 259 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 260 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 261 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 262 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 263 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 264 break; 265 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 266 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 267 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 268 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 269 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 270 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 271 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 272 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 273 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 274 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 275 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 276 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 277 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 278 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 279 sc->sc_flags |= NFE_40BIT_ADDR; 280 break; 281 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 282 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 283 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 284 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 285 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 286 break; 287 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 288 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 289 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 290 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 291 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 292 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 293 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 294 NFE_HW_VLAN; 295 break; 296 } 297 298 #ifndef NFE_NO_JUMBO 299 /* enable jumbo frames for adapters that support it */ 300 if (sc->sc_flags & NFE_JUMBO_SUP) 301 sc->sc_flags |= NFE_USE_JUMBO; 302 #endif 303 304 /* 305 * Allocate Tx and Rx rings. 306 */ 307 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 308 printf("%s: could not allocate Tx ring\n", 309 sc->sc_dev.dv_xname); 310 return; 311 } 312 313 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 314 printf("%s: could not allocate Rx ring\n", 315 sc->sc_dev.dv_xname); 316 nfe_free_tx_ring(sc, &sc->txq); 317 return; 318 } 319 320 ifp = &sc->sc_ethercom.ec_if; 321 ifp->if_softc = sc; 322 ifp->if_mtu = ETHERMTU; 323 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 324 ifp->if_ioctl = nfe_ioctl; 325 ifp->if_start = nfe_start; 326 ifp->if_watchdog = nfe_watchdog; 327 ifp->if_init = nfe_init; 328 ifp->if_baudrate = IF_Gbps(1); 329 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 330 IFQ_SET_READY(&ifp->if_snd); 331 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 332 333 #if NVLAN > 0 334 if (sc->sc_flags & NFE_HW_VLAN) 335 sc->sc_ethercom.ec_capabilities |= 336 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 337 #endif 338 if (sc->sc_flags & NFE_HW_CSUM) { 339 ifp->if_capabilities |= 340 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 341 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 342 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 343 } 344 345 sc->sc_mii.mii_ifp = ifp; 346 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 347 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 348 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 349 350 ifmedia_init(&sc->sc_mii.mii_media, 0, nfe_ifmedia_upd, 351 nfe_ifmedia_sts); 352 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 353 MII_OFFSET_ANY, 0); 354 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 355 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 356 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 357 0, NULL); 358 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 359 } else 360 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 361 362 if_attach(ifp); 363 ether_ifattach(ifp, sc->sc_enaddr); 364 365 callout_init(&sc->sc_tick_ch, 0); 366 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 367 368 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 369 nfe_power, sc); 370 } 371 372 void 373 nfe_power(int why, void *arg) 374 { 375 struct nfe_softc *sc = arg; 376 struct ifnet *ifp; 377 378 if (why == PWR_RESUME) { 379 ifp = &sc->sc_ethercom.ec_if; 380 if (ifp->if_flags & IFF_UP) { 381 ifp->if_flags &= ~IFF_RUNNING; 382 nfe_init(ifp); 383 if (ifp->if_flags & IFF_RUNNING) 384 nfe_start(ifp); 385 } 386 } 387 } 388 389 void 390 nfe_miibus_statchg(struct device *dev) 391 { 392 struct nfe_softc *sc = (struct nfe_softc *)dev; 393 struct mii_data *mii = &sc->sc_mii; 394 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 395 396 phy = NFE_READ(sc, NFE_PHY_IFACE); 397 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 398 399 seed = NFE_READ(sc, NFE_RNDSEED); 400 seed &= ~NFE_SEED_MASK; 401 402 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 403 phy |= NFE_PHY_HDX; /* half-duplex */ 404 misc |= NFE_MISC1_HDX; 405 } 406 407 switch (IFM_SUBTYPE(mii->mii_media_active)) { 408 case IFM_1000_T: /* full-duplex only */ 409 link |= NFE_MEDIA_1000T; 410 seed |= NFE_SEED_1000T; 411 phy |= NFE_PHY_1000T; 412 break; 413 case IFM_100_TX: 414 link |= NFE_MEDIA_100TX; 415 seed |= NFE_SEED_100TX; 416 phy |= NFE_PHY_100TX; 417 break; 418 case IFM_10_T: 419 link |= NFE_MEDIA_10T; 420 seed |= NFE_SEED_10T; 421 break; 422 } 423 424 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 425 426 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 427 NFE_WRITE(sc, NFE_MISC1, misc); 428 NFE_WRITE(sc, NFE_LINKSPEED, link); 429 } 430 431 int 432 nfe_miibus_readreg(struct device *dev, int phy, int reg) 433 { 434 struct nfe_softc *sc = (struct nfe_softc *)dev; 435 uint32_t val; 436 int ntries; 437 438 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 439 440 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 441 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 442 DELAY(100); 443 } 444 445 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 446 447 for (ntries = 0; ntries < 1000; ntries++) { 448 DELAY(100); 449 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 450 break; 451 } 452 if (ntries == 1000) { 453 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 454 sc->sc_dev.dv_xname)); 455 return 0; 456 } 457 458 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 459 DPRINTFN(2, ("%s: could not read PHY\n", 460 sc->sc_dev.dv_xname)); 461 return 0; 462 } 463 464 val = NFE_READ(sc, NFE_PHY_DATA); 465 if (val != 0xffffffff && val != 0) 466 sc->mii_phyaddr = phy; 467 468 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 469 sc->sc_dev.dv_xname, phy, reg, val)); 470 471 return val; 472 } 473 474 void 475 nfe_miibus_writereg(struct device *dev, int phy, int reg, int val) 476 { 477 struct nfe_softc *sc = (struct nfe_softc *)dev; 478 uint32_t ctl; 479 int ntries; 480 481 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 482 483 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 484 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 485 DELAY(100); 486 } 487 488 NFE_WRITE(sc, NFE_PHY_DATA, val); 489 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 490 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 491 492 for (ntries = 0; ntries < 1000; ntries++) { 493 DELAY(100); 494 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 495 break; 496 } 497 #ifdef NFE_DEBUG 498 if (nfedebug >= 2 && ntries == 1000) 499 printf("could not write to PHY\n"); 500 #endif 501 } 502 503 int 504 nfe_intr(void *arg) 505 { 506 struct nfe_softc *sc = arg; 507 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 508 uint32_t r; 509 int handled; 510 511 if ((ifp->if_flags & IFF_UP) == 0) 512 return 0; 513 514 handled = 0; 515 516 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 517 518 for (;;) { 519 r = NFE_READ(sc, NFE_IRQ_STATUS); 520 if ((r & NFE_IRQ_WANTED) == 0) 521 break; 522 523 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 524 handled = 1; 525 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 526 527 if ((r & (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX)) 528 != 0) { 529 /* check Rx ring */ 530 nfe_rxeof(sc); 531 } 532 533 if ((r & (NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE)) 534 != 0) { 535 /* check Tx ring */ 536 nfe_txeof(sc); 537 } 538 539 if ((r & NFE_IRQ_LINK) != 0) { 540 NFE_READ(sc, NFE_PHY_STATUS); 541 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 542 DPRINTF(("%s: link state changed\n", 543 sc->sc_dev.dv_xname)); 544 } 545 } 546 547 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 548 549 if (handled && !IF_IS_EMPTY(&ifp->if_snd)) 550 nfe_start(ifp); 551 552 return handled; 553 } 554 555 int 556 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 557 { 558 struct nfe_softc *sc = ifp->if_softc; 559 struct ifreq *ifr = (struct ifreq *)data; 560 struct ifaddr *ifa = (struct ifaddr *)data; 561 int s, error = 0; 562 563 s = splnet(); 564 565 switch (cmd) { 566 case SIOCSIFADDR: 567 ifp->if_flags |= IFF_UP; 568 nfe_init(ifp); 569 switch (ifa->ifa_addr->sa_family) { 570 #ifdef INET 571 case AF_INET: 572 arp_ifinit(ifp, ifa); 573 break; 574 #endif 575 default: 576 break; 577 } 578 break; 579 case SIOCSIFMTU: 580 if (ifr->ifr_mtu < ETHERMIN || 581 ((sc->sc_flags & NFE_USE_JUMBO) && 582 ifr->ifr_mtu > ETHERMTU_JUMBO) || 583 (!(sc->sc_flags & NFE_USE_JUMBO) && 584 ifr->ifr_mtu > ETHERMTU)) 585 error = EINVAL; 586 else if (ifp->if_mtu != ifr->ifr_mtu) 587 ifp->if_mtu = ifr->ifr_mtu; 588 break; 589 case SIOCSIFFLAGS: 590 if (ifp->if_flags & IFF_UP) { 591 /* 592 * If only the PROMISC or ALLMULTI flag changes, then 593 * don't do a full re-init of the chip, just update 594 * the Rx filter. 595 */ 596 if ((ifp->if_flags & IFF_RUNNING) && 597 ((ifp->if_flags ^ sc->sc_if_flags) & 598 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 599 nfe_setmulti(sc); 600 else 601 nfe_init(ifp); 602 } else { 603 if (ifp->if_flags & IFF_RUNNING) 604 nfe_stop(ifp, 1); 605 } 606 sc->sc_if_flags = ifp->if_flags; 607 break; 608 case SIOCADDMULTI: 609 case SIOCDELMULTI: 610 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 611 if (ifp->if_flags & IFF_RUNNING) 612 nfe_setmulti(sc); 613 error = 0; 614 } 615 break; 616 case SIOCSIFMEDIA: 617 case SIOCGIFMEDIA: 618 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 619 break; 620 default: 621 error = ether_ioctl(ifp, cmd, data); 622 if (error == ENETRESET) { 623 if (ifp->if_flags & IFF_RUNNING) 624 nfe_setmulti(sc); 625 error = 0; 626 } 627 break; 628 629 } 630 631 splx(s); 632 633 return error; 634 } 635 636 void 637 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 638 { 639 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 640 (char *)desc32 - (char *)sc->txq.desc32, 641 sizeof (struct nfe_desc32), ops); 642 } 643 644 void 645 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 646 { 647 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 648 (char *)desc64 - (char *)sc->txq.desc64, 649 sizeof (struct nfe_desc64), ops); 650 } 651 652 void 653 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 654 { 655 if (end > start) { 656 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 657 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 658 (char *)&sc->txq.desc32[end] - 659 (char *)&sc->txq.desc32[start], ops); 660 return; 661 } 662 /* sync from 'start' to end of ring */ 663 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 664 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 665 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 666 (char *)&sc->txq.desc32[start], ops); 667 668 /* sync from start of ring to 'end' */ 669 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 670 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 671 } 672 673 void 674 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 675 { 676 if (end > start) { 677 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 678 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 679 (char *)&sc->txq.desc64[end] - 680 (char *)&sc->txq.desc64[start], ops); 681 return; 682 } 683 /* sync from 'start' to end of ring */ 684 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 685 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 686 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 687 (char *)&sc->txq.desc64[start], ops); 688 689 /* sync from start of ring to 'end' */ 690 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 691 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 692 } 693 694 void 695 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 696 { 697 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 698 (char *)desc32 - (char *)sc->rxq.desc32, 699 sizeof (struct nfe_desc32), ops); 700 } 701 702 void 703 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 704 { 705 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 706 (char *)desc64 - (char *)sc->rxq.desc64, 707 sizeof (struct nfe_desc64), ops); 708 } 709 710 void 711 nfe_rxeof(struct nfe_softc *sc) 712 { 713 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 714 struct nfe_desc32 *desc32; 715 struct nfe_desc64 *desc64; 716 struct nfe_rx_data *data; 717 struct nfe_jbuf *jbuf; 718 struct mbuf *m, *mnew; 719 bus_addr_t physaddr; 720 uint16_t flags; 721 int error, len, i; 722 723 desc32 = NULL; 724 desc64 = NULL; 725 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 726 data = &sc->rxq.data[i]; 727 728 if (sc->sc_flags & NFE_40BIT_ADDR) { 729 desc64 = &sc->rxq.desc64[i]; 730 nfe_rxdesc64_sync(sc, desc64, 731 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 732 733 flags = le16toh(desc64->flags); 734 len = le16toh(desc64->length) & 0x3fff; 735 } else { 736 desc32 = &sc->rxq.desc32[i]; 737 nfe_rxdesc32_sync(sc, desc32, 738 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 739 740 flags = le16toh(desc32->flags); 741 len = le16toh(desc32->length) & 0x3fff; 742 } 743 744 if ((flags & NFE_RX_READY) != 0) 745 break; 746 747 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 748 if ((flags & NFE_RX_VALID_V1) == 0) 749 goto skip; 750 751 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 752 flags &= ~NFE_RX_ERROR; 753 len--; /* fix buffer length */ 754 } 755 } else { 756 if ((flags & NFE_RX_VALID_V2) == 0) 757 goto skip; 758 759 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 760 flags &= ~NFE_RX_ERROR; 761 len--; /* fix buffer length */ 762 } 763 } 764 765 if (flags & NFE_RX_ERROR) { 766 ifp->if_ierrors++; 767 goto skip; 768 } 769 770 /* 771 * Try to allocate a new mbuf for this ring element and load 772 * it before processing the current mbuf. If the ring element 773 * cannot be loaded, drop the received packet and reuse the 774 * old mbuf. In the unlikely case that the old mbuf can't be 775 * reloaded either, explicitly panic. 776 */ 777 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 778 if (mnew == NULL) { 779 ifp->if_ierrors++; 780 goto skip; 781 } 782 783 if (sc->sc_flags & NFE_USE_JUMBO) { 784 physaddr = 785 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 786 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 787 if (len > MCLBYTES) { 788 m_freem(mnew); 789 ifp->if_ierrors++; 790 goto skip1; 791 } 792 MCLGET(mnew, M_DONTWAIT); 793 if ((mnew->m_flags & M_EXT) == 0) { 794 m_freem(mnew); 795 ifp->if_ierrors++; 796 goto skip1; 797 } 798 799 memcpy(mtod(mnew, void *), 800 mtod(data->m, const void *), len); 801 m = mnew; 802 goto mbufcopied; 803 } else { 804 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 805 806 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 807 mtod(data->m, char *) - (char *)sc->rxq.jpool, 808 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 809 810 physaddr = jbuf->physaddr; 811 } 812 } else { 813 MCLGET(mnew, M_DONTWAIT); 814 if ((mnew->m_flags & M_EXT) == 0) { 815 m_freem(mnew); 816 ifp->if_ierrors++; 817 goto skip; 818 } 819 820 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 821 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 822 bus_dmamap_unload(sc->sc_dmat, data->map); 823 824 error = bus_dmamap_load(sc->sc_dmat, data->map, 825 mtod(mnew, void *), MCLBYTES, NULL, 826 BUS_DMA_READ | BUS_DMA_NOWAIT); 827 if (error != 0) { 828 m_freem(mnew); 829 830 /* try to reload the old mbuf */ 831 error = bus_dmamap_load(sc->sc_dmat, data->map, 832 mtod(data->m, void *), MCLBYTES, NULL, 833 BUS_DMA_READ | BUS_DMA_NOWAIT); 834 if (error != 0) { 835 /* very unlikely that it will fail.. */ 836 panic("%s: could not load old rx mbuf", 837 sc->sc_dev.dv_xname); 838 } 839 ifp->if_ierrors++; 840 goto skip; 841 } 842 physaddr = data->map->dm_segs[0].ds_addr; 843 } 844 845 /* 846 * New mbuf successfully loaded, update Rx ring and continue 847 * processing. 848 */ 849 m = data->m; 850 data->m = mnew; 851 852 mbufcopied: 853 /* finalize mbuf */ 854 m->m_pkthdr.len = m->m_len = len; 855 m->m_pkthdr.rcvif = ifp; 856 857 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 858 /* 859 * XXX 860 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 861 */ 862 if (flags & NFE_RX_IP_CSUMOK) { 863 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 864 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 865 sc->sc_dev.dv_xname)); 866 } 867 /* 868 * XXX 869 * no way to check M_CSUM_TCP_UDP_BAD or 870 * other protocols? 871 */ 872 if (flags & NFE_RX_UDP_CSUMOK) { 873 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 874 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 875 sc->sc_dev.dv_xname)); 876 } else if (flags & NFE_RX_TCP_CSUMOK) { 877 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 878 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 879 sc->sc_dev.dv_xname)); 880 } 881 } 882 883 #if NBPFILTER > 0 884 if (ifp->if_bpf) 885 bpf_mtap(ifp->if_bpf, m); 886 #endif 887 ifp->if_ipackets++; 888 (*ifp->if_input)(ifp, m); 889 890 skip1: 891 /* update mapping address in h/w descriptor */ 892 if (sc->sc_flags & NFE_40BIT_ADDR) { 893 #if defined(__LP64__) 894 desc64->physaddr[0] = htole32(physaddr >> 32); 895 #endif 896 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 897 } else { 898 desc32->physaddr = htole32(physaddr); 899 } 900 901 skip: 902 if (sc->sc_flags & NFE_40BIT_ADDR) { 903 desc64->length = htole16(sc->rxq.bufsz); 904 desc64->flags = htole16(NFE_RX_READY); 905 906 nfe_rxdesc64_sync(sc, desc64, 907 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 908 } else { 909 desc32->length = htole16(sc->rxq.bufsz); 910 desc32->flags = htole16(NFE_RX_READY); 911 912 nfe_rxdesc32_sync(sc, desc32, 913 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 914 } 915 } 916 /* update current RX pointer */ 917 sc->rxq.cur = i; 918 } 919 920 void 921 nfe_txeof(struct nfe_softc *sc) 922 { 923 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 924 struct nfe_desc32 *desc32; 925 struct nfe_desc64 *desc64; 926 struct nfe_tx_data *data = NULL; 927 int i; 928 uint16_t flags; 929 930 for (i = sc->txq.next; 931 sc->txq.queued > 0; 932 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 933 if (sc->sc_flags & NFE_40BIT_ADDR) { 934 desc64 = &sc->txq.desc64[i]; 935 nfe_txdesc64_sync(sc, desc64, 936 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 937 938 flags = le16toh(desc64->flags); 939 } else { 940 desc32 = &sc->txq.desc32[i]; 941 nfe_txdesc32_sync(sc, desc32, 942 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 943 944 flags = le16toh(desc32->flags); 945 } 946 947 if ((flags & NFE_TX_VALID) != 0) 948 break; 949 950 data = &sc->txq.data[i]; 951 952 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 953 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 954 data->m == NULL) 955 continue; 956 957 if ((flags & NFE_TX_ERROR_V1) != 0) { 958 printf("%s: tx v1 error 0x%04x\n", 959 sc->sc_dev.dv_xname, flags); 960 ifp->if_oerrors++; 961 } else 962 ifp->if_opackets++; 963 } else { 964 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 965 data->m == NULL) 966 continue; 967 968 if ((flags & NFE_TX_ERROR_V2) != 0) { 969 printf("%s: tx v2 error 0x%04x\n", 970 sc->sc_dev.dv_xname, flags); 971 ifp->if_oerrors++; 972 } else 973 ifp->if_opackets++; 974 } 975 976 if (data->m == NULL) { /* should not get there */ 977 printf("%s: last fragment bit w/o associated mbuf!\n", 978 sc->sc_dev.dv_xname); 979 continue; 980 } 981 982 /* last fragment of the mbuf chain transmitted */ 983 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 984 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 985 bus_dmamap_unload(sc->sc_dmat, data->active); 986 m_freem(data->m); 987 data->m = NULL; 988 } 989 990 sc->txq.next = i; 991 992 if (sc->txq.queued < NFE_TX_RING_COUNT) { 993 /* at least one slot freed */ 994 ifp->if_flags &= ~IFF_OACTIVE; 995 } 996 997 if (sc->txq.queued == 0) { 998 /* all queued packets are sent */ 999 ifp->if_timer = 0; 1000 } 1001 } 1002 1003 int 1004 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 1005 { 1006 struct nfe_desc32 *desc32; 1007 struct nfe_desc64 *desc64; 1008 struct nfe_tx_data *data; 1009 bus_dmamap_t map; 1010 uint16_t flags, csumflags; 1011 #if NVLAN > 0 1012 struct m_tag *mtag; 1013 uint32_t vtag = 0; 1014 #endif 1015 int error, i, first; 1016 1017 desc32 = NULL; 1018 desc64 = NULL; 1019 data = NULL; 1020 1021 flags = 0; 1022 csumflags = 0; 1023 first = sc->txq.cur; 1024 1025 map = sc->txq.data[first].map; 1026 1027 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1028 if (error != 0) { 1029 printf("%s: could not map mbuf (error %d)\n", 1030 sc->sc_dev.dv_xname, error); 1031 return error; 1032 } 1033 1034 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1035 bus_dmamap_unload(sc->sc_dmat, map); 1036 return ENOBUFS; 1037 } 1038 1039 #if NVLAN > 0 1040 /* setup h/w VLAN tagging */ 1041 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1042 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1043 #endif 1044 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1045 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1046 csumflags |= NFE_TX_IP_CSUM; 1047 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1048 csumflags |= NFE_TX_TCP_UDP_CSUM; 1049 } 1050 1051 for (i = 0; i < map->dm_nsegs; i++) { 1052 data = &sc->txq.data[sc->txq.cur]; 1053 1054 if (sc->sc_flags & NFE_40BIT_ADDR) { 1055 desc64 = &sc->txq.desc64[sc->txq.cur]; 1056 #if defined(__LP64__) 1057 desc64->physaddr[0] = 1058 htole32(map->dm_segs[i].ds_addr >> 32); 1059 #endif 1060 desc64->physaddr[1] = 1061 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1062 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1063 desc64->flags = htole16(flags); 1064 desc64->vtag = 0; 1065 } else { 1066 desc32 = &sc->txq.desc32[sc->txq.cur]; 1067 1068 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1069 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1070 desc32->flags = htole16(flags); 1071 } 1072 1073 /* 1074 * Setting of the valid bit in the first descriptor is 1075 * deferred until the whole chain is fully setup. 1076 */ 1077 flags |= NFE_TX_VALID; 1078 1079 sc->txq.queued++; 1080 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1081 } 1082 1083 /* the whole mbuf chain has been setup */ 1084 if (sc->sc_flags & NFE_40BIT_ADDR) { 1085 /* fix last descriptor */ 1086 flags |= NFE_TX_LASTFRAG_V2; 1087 desc64->flags = htole16(flags); 1088 1089 /* Checksum flags and vtag belong to the first fragment only. */ 1090 #if NVLAN > 0 1091 sc->txq.desc64[first].vtag = htole32(vtag); 1092 #endif 1093 sc->txq.desc64[first].flags |= htole16(csumflags); 1094 1095 /* finally, set the valid bit in the first descriptor */ 1096 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1097 } else { 1098 /* fix last descriptor */ 1099 if (sc->sc_flags & NFE_JUMBO_SUP) 1100 flags |= NFE_TX_LASTFRAG_V2; 1101 else 1102 flags |= NFE_TX_LASTFRAG_V1; 1103 desc32->flags = htole16(flags); 1104 1105 /* Checksum flags belong to the first fragment only. */ 1106 sc->txq.desc32[first].flags |= htole16(csumflags); 1107 1108 /* finally, set the valid bit in the first descriptor */ 1109 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1110 } 1111 1112 data->m = m0; 1113 data->active = map; 1114 1115 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1116 BUS_DMASYNC_PREWRITE); 1117 1118 return 0; 1119 } 1120 1121 void 1122 nfe_start(struct ifnet *ifp) 1123 { 1124 struct nfe_softc *sc = ifp->if_softc; 1125 int old = sc->txq.queued; 1126 struct mbuf *m0; 1127 1128 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 1129 return; 1130 1131 for (;;) { 1132 IFQ_POLL(&ifp->if_snd, m0); 1133 if (m0 == NULL) 1134 break; 1135 1136 if (nfe_encap(sc, m0) != 0) { 1137 ifp->if_flags |= IFF_OACTIVE; 1138 break; 1139 } 1140 1141 /* packet put in h/w queue, remove from s/w queue */ 1142 IFQ_DEQUEUE(&ifp->if_snd, m0); 1143 1144 #if NBPFILTER > 0 1145 if (ifp->if_bpf != NULL) 1146 bpf_mtap(ifp->if_bpf, m0); 1147 #endif 1148 } 1149 1150 if (sc->txq.queued != old) { 1151 /* packets are queued */ 1152 if (sc->sc_flags & NFE_40BIT_ADDR) 1153 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1154 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1155 else 1156 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1157 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1158 /* kick Tx */ 1159 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1160 1161 /* 1162 * Set a timeout in case the chip goes out to lunch. 1163 */ 1164 ifp->if_timer = 5; 1165 } 1166 } 1167 1168 void 1169 nfe_watchdog(struct ifnet *ifp) 1170 { 1171 struct nfe_softc *sc = ifp->if_softc; 1172 1173 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1174 1175 ifp->if_flags &= ~IFF_RUNNING; 1176 nfe_init(ifp); 1177 1178 ifp->if_oerrors++; 1179 } 1180 1181 int 1182 nfe_init(struct ifnet *ifp) 1183 { 1184 struct nfe_softc *sc = ifp->if_softc; 1185 uint32_t tmp; 1186 int s; 1187 1188 if (ifp->if_flags & IFF_RUNNING) 1189 return 0; 1190 1191 nfe_stop(ifp, 0); 1192 1193 NFE_WRITE(sc, NFE_TX_UNK, 0); 1194 NFE_WRITE(sc, NFE_STATUS, 0); 1195 1196 sc->rxtxctl = NFE_RXTX_BIT2; 1197 if (sc->sc_flags & NFE_40BIT_ADDR) 1198 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1199 else if (sc->sc_flags & NFE_JUMBO_SUP) 1200 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1201 if (sc->sc_flags & NFE_HW_CSUM) 1202 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1203 #if NVLAN > 0 1204 /* 1205 * Although the adapter is capable of stripping VLAN tags from received 1206 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1207 * purpose. This will be done in software by our network stack. 1208 */ 1209 if (sc->sc_flags & NFE_HW_VLAN) 1210 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1211 #endif 1212 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1213 DELAY(10); 1214 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1215 1216 #if NVLAN 1217 if (sc->sc_flags & NFE_HW_VLAN) 1218 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1219 #endif 1220 1221 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1222 1223 /* set MAC address */ 1224 nfe_set_macaddr(sc, sc->sc_enaddr); 1225 1226 /* tell MAC where rings are in memory */ 1227 #ifdef __LP64__ 1228 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1229 #endif 1230 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1231 #ifdef __LP64__ 1232 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1233 #endif 1234 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1235 1236 NFE_WRITE(sc, NFE_RING_SIZE, 1237 (NFE_RX_RING_COUNT - 1) << 16 | 1238 (NFE_TX_RING_COUNT - 1)); 1239 1240 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1241 1242 /* force MAC to wakeup */ 1243 tmp = NFE_READ(sc, NFE_PWR_STATE); 1244 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1245 DELAY(10); 1246 tmp = NFE_READ(sc, NFE_PWR_STATE); 1247 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1248 1249 s = splnet(); 1250 nfe_intr(sc); /* XXX clear IRQ status registers */ 1251 splx(s); 1252 1253 #if 1 1254 /* configure interrupts coalescing/mitigation */ 1255 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1256 #else 1257 /* no interrupt mitigation: one interrupt per packet */ 1258 NFE_WRITE(sc, NFE_IMTIMER, 970); 1259 #endif 1260 1261 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1262 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1263 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1264 1265 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1266 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1267 1268 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1269 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC); 1270 1271 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1272 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1273 DELAY(10); 1274 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1275 1276 /* set Rx filter */ 1277 nfe_setmulti(sc); 1278 1279 nfe_ifmedia_upd(ifp); 1280 1281 nfe_tick(sc); 1282 1283 /* enable Rx */ 1284 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1285 1286 /* enable Tx */ 1287 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1288 1289 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1290 1291 /* enable interrupts */ 1292 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1293 1294 callout_schedule(&sc->sc_tick_ch, hz); 1295 1296 ifp->if_flags |= IFF_RUNNING; 1297 ifp->if_flags &= ~IFF_OACTIVE; 1298 1299 return 0; 1300 } 1301 1302 void 1303 nfe_stop(struct ifnet *ifp, int disable) 1304 { 1305 struct nfe_softc *sc = ifp->if_softc; 1306 1307 callout_stop(&sc->sc_tick_ch); 1308 1309 ifp->if_timer = 0; 1310 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1311 1312 mii_down(&sc->sc_mii); 1313 1314 /* abort Tx */ 1315 NFE_WRITE(sc, NFE_TX_CTL, 0); 1316 1317 /* disable Rx */ 1318 NFE_WRITE(sc, NFE_RX_CTL, 0); 1319 1320 /* disable interrupts */ 1321 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1322 1323 /* reset Tx and Rx rings */ 1324 nfe_reset_tx_ring(sc, &sc->txq); 1325 nfe_reset_rx_ring(sc, &sc->rxq); 1326 } 1327 1328 int 1329 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1330 { 1331 struct nfe_desc32 *desc32; 1332 struct nfe_desc64 *desc64; 1333 struct nfe_rx_data *data; 1334 struct nfe_jbuf *jbuf; 1335 void **desc; 1336 bus_addr_t physaddr; 1337 int i, nsegs, error, descsize; 1338 1339 if (sc->sc_flags & NFE_40BIT_ADDR) { 1340 desc = (void **)&ring->desc64; 1341 descsize = sizeof (struct nfe_desc64); 1342 } else { 1343 desc = (void **)&ring->desc32; 1344 descsize = sizeof (struct nfe_desc32); 1345 } 1346 1347 ring->cur = ring->next = 0; 1348 ring->bufsz = MCLBYTES; 1349 1350 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1351 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1352 if (error != 0) { 1353 printf("%s: could not create desc DMA map\n", 1354 sc->sc_dev.dv_xname); 1355 goto fail; 1356 } 1357 1358 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1359 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1360 if (error != 0) { 1361 printf("%s: could not allocate DMA memory\n", 1362 sc->sc_dev.dv_xname); 1363 goto fail; 1364 } 1365 1366 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1367 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1368 if (error != 0) { 1369 printf("%s: could not map desc DMA memory\n", 1370 sc->sc_dev.dv_xname); 1371 goto fail; 1372 } 1373 1374 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1375 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1376 if (error != 0) { 1377 printf("%s: could not load desc DMA map\n", 1378 sc->sc_dev.dv_xname); 1379 goto fail; 1380 } 1381 1382 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1383 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1384 1385 if (sc->sc_flags & NFE_USE_JUMBO) { 1386 ring->bufsz = NFE_JBYTES; 1387 if ((error = nfe_jpool_alloc(sc)) != 0) { 1388 printf("%s: could not allocate jumbo frames\n", 1389 sc->sc_dev.dv_xname); 1390 goto fail; 1391 } 1392 } 1393 1394 /* 1395 * Pre-allocate Rx buffers and populate Rx ring. 1396 */ 1397 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1398 data = &sc->rxq.data[i]; 1399 1400 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1401 if (data->m == NULL) { 1402 printf("%s: could not allocate rx mbuf\n", 1403 sc->sc_dev.dv_xname); 1404 error = ENOMEM; 1405 goto fail; 1406 } 1407 1408 if (sc->sc_flags & NFE_USE_JUMBO) { 1409 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1410 printf("%s: could not allocate jumbo buffer\n", 1411 sc->sc_dev.dv_xname); 1412 goto fail; 1413 } 1414 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1415 sc); 1416 1417 physaddr = jbuf->physaddr; 1418 } else { 1419 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1420 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1421 if (error != 0) { 1422 printf("%s: could not create DMA map\n", 1423 sc->sc_dev.dv_xname); 1424 goto fail; 1425 } 1426 MCLGET(data->m, M_DONTWAIT); 1427 if (!(data->m->m_flags & M_EXT)) { 1428 printf("%s: could not allocate mbuf cluster\n", 1429 sc->sc_dev.dv_xname); 1430 error = ENOMEM; 1431 goto fail; 1432 } 1433 1434 error = bus_dmamap_load(sc->sc_dmat, data->map, 1435 mtod(data->m, void *), MCLBYTES, NULL, 1436 BUS_DMA_READ | BUS_DMA_NOWAIT); 1437 if (error != 0) { 1438 printf("%s: could not load rx buf DMA map", 1439 sc->sc_dev.dv_xname); 1440 goto fail; 1441 } 1442 physaddr = data->map->dm_segs[0].ds_addr; 1443 } 1444 1445 if (sc->sc_flags & NFE_40BIT_ADDR) { 1446 desc64 = &sc->rxq.desc64[i]; 1447 #if defined(__LP64__) 1448 desc64->physaddr[0] = htole32(physaddr >> 32); 1449 #endif 1450 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1451 desc64->length = htole16(sc->rxq.bufsz); 1452 desc64->flags = htole16(NFE_RX_READY); 1453 } else { 1454 desc32 = &sc->rxq.desc32[i]; 1455 desc32->physaddr = htole32(physaddr); 1456 desc32->length = htole16(sc->rxq.bufsz); 1457 desc32->flags = htole16(NFE_RX_READY); 1458 } 1459 } 1460 1461 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1462 BUS_DMASYNC_PREWRITE); 1463 1464 return 0; 1465 1466 fail: nfe_free_rx_ring(sc, ring); 1467 return error; 1468 } 1469 1470 void 1471 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1472 { 1473 int i; 1474 1475 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1476 if (sc->sc_flags & NFE_40BIT_ADDR) { 1477 ring->desc64[i].length = htole16(ring->bufsz); 1478 ring->desc64[i].flags = htole16(NFE_RX_READY); 1479 } else { 1480 ring->desc32[i].length = htole16(ring->bufsz); 1481 ring->desc32[i].flags = htole16(NFE_RX_READY); 1482 } 1483 } 1484 1485 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1486 BUS_DMASYNC_PREWRITE); 1487 1488 ring->cur = ring->next = 0; 1489 } 1490 1491 void 1492 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1493 { 1494 struct nfe_rx_data *data; 1495 void *desc; 1496 int i, descsize; 1497 1498 if (sc->sc_flags & NFE_40BIT_ADDR) { 1499 desc = ring->desc64; 1500 descsize = sizeof (struct nfe_desc64); 1501 } else { 1502 desc = ring->desc32; 1503 descsize = sizeof (struct nfe_desc32); 1504 } 1505 1506 if (desc != NULL) { 1507 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1508 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1509 bus_dmamap_unload(sc->sc_dmat, ring->map); 1510 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1511 NFE_RX_RING_COUNT * descsize); 1512 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1513 } 1514 1515 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1516 data = &ring->data[i]; 1517 1518 if (data->map != NULL) { 1519 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1520 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1521 bus_dmamap_unload(sc->sc_dmat, data->map); 1522 bus_dmamap_destroy(sc->sc_dmat, data->map); 1523 } 1524 if (data->m != NULL) 1525 m_freem(data->m); 1526 } 1527 } 1528 1529 struct nfe_jbuf * 1530 nfe_jalloc(struct nfe_softc *sc, int i) 1531 { 1532 struct nfe_jbuf *jbuf; 1533 1534 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1535 if (jbuf == NULL) 1536 return NULL; 1537 sc->rxq.jbufmap[i] = 1538 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1539 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1540 return jbuf; 1541 } 1542 1543 /* 1544 * This is called automatically by the network stack when the mbuf is freed. 1545 * Caution must be taken that the NIC might be reset by the time the mbuf is 1546 * freed. 1547 */ 1548 void 1549 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1550 { 1551 struct nfe_softc *sc = arg; 1552 struct nfe_jbuf *jbuf; 1553 int i; 1554 1555 /* find the jbuf from the base pointer */ 1556 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1557 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1558 printf("%s: request to free a buffer (%p) not managed by us\n", 1559 sc->sc_dev.dv_xname, buf); 1560 return; 1561 } 1562 jbuf = &sc->rxq.jbuf[i]; 1563 1564 /* ..and put it back in the free list */ 1565 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1566 1567 if (m != NULL) 1568 pool_cache_put(mb_cache, m); 1569 } 1570 1571 int 1572 nfe_jpool_alloc(struct nfe_softc *sc) 1573 { 1574 struct nfe_rx_ring *ring = &sc->rxq; 1575 struct nfe_jbuf *jbuf; 1576 bus_addr_t physaddr; 1577 char *buf; 1578 int i, nsegs, error; 1579 1580 /* 1581 * Allocate a big chunk of DMA'able memory. 1582 */ 1583 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1584 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1585 if (error != 0) { 1586 printf("%s: could not create jumbo DMA map\n", 1587 sc->sc_dev.dv_xname); 1588 goto fail; 1589 } 1590 1591 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1592 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1593 if (error != 0) { 1594 printf("%s could not allocate jumbo DMA memory\n", 1595 sc->sc_dev.dv_xname); 1596 goto fail; 1597 } 1598 1599 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1600 &ring->jpool, BUS_DMA_NOWAIT); 1601 if (error != 0) { 1602 printf("%s: could not map jumbo DMA memory\n", 1603 sc->sc_dev.dv_xname); 1604 goto fail; 1605 } 1606 1607 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1608 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1609 if (error != 0) { 1610 printf("%s: could not load jumbo DMA map\n", 1611 sc->sc_dev.dv_xname); 1612 goto fail; 1613 } 1614 1615 /* ..and split it into 9KB chunks */ 1616 SLIST_INIT(&ring->jfreelist); 1617 1618 buf = ring->jpool; 1619 physaddr = ring->jmap->dm_segs[0].ds_addr; 1620 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1621 jbuf = &ring->jbuf[i]; 1622 1623 jbuf->buf = buf; 1624 jbuf->physaddr = physaddr; 1625 1626 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1627 1628 buf += NFE_JBYTES; 1629 physaddr += NFE_JBYTES; 1630 } 1631 1632 return 0; 1633 1634 fail: nfe_jpool_free(sc); 1635 return error; 1636 } 1637 1638 void 1639 nfe_jpool_free(struct nfe_softc *sc) 1640 { 1641 struct nfe_rx_ring *ring = &sc->rxq; 1642 1643 if (ring->jmap != NULL) { 1644 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1645 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1646 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1647 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1648 } 1649 if (ring->jpool != NULL) { 1650 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1651 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1652 } 1653 } 1654 1655 int 1656 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1657 { 1658 int i, nsegs, error; 1659 void **desc; 1660 int descsize; 1661 1662 if (sc->sc_flags & NFE_40BIT_ADDR) { 1663 desc = (void **)&ring->desc64; 1664 descsize = sizeof (struct nfe_desc64); 1665 } else { 1666 desc = (void **)&ring->desc32; 1667 descsize = sizeof (struct nfe_desc32); 1668 } 1669 1670 ring->queued = 0; 1671 ring->cur = ring->next = 0; 1672 1673 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1674 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1675 1676 if (error != 0) { 1677 printf("%s: could not create desc DMA map\n", 1678 sc->sc_dev.dv_xname); 1679 goto fail; 1680 } 1681 1682 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1683 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1684 if (error != 0) { 1685 printf("%s: could not allocate DMA memory\n", 1686 sc->sc_dev.dv_xname); 1687 goto fail; 1688 } 1689 1690 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1691 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1692 if (error != 0) { 1693 printf("%s: could not map desc DMA memory\n", 1694 sc->sc_dev.dv_xname); 1695 goto fail; 1696 } 1697 1698 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1699 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1700 if (error != 0) { 1701 printf("%s: could not load desc DMA map\n", 1702 sc->sc_dev.dv_xname); 1703 goto fail; 1704 } 1705 1706 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1707 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1708 1709 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1710 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1711 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1712 &ring->data[i].map); 1713 if (error != 0) { 1714 printf("%s: could not create DMA map\n", 1715 sc->sc_dev.dv_xname); 1716 goto fail; 1717 } 1718 } 1719 1720 return 0; 1721 1722 fail: nfe_free_tx_ring(sc, ring); 1723 return error; 1724 } 1725 1726 void 1727 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1728 { 1729 struct nfe_tx_data *data; 1730 int i; 1731 1732 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1733 if (sc->sc_flags & NFE_40BIT_ADDR) 1734 ring->desc64[i].flags = 0; 1735 else 1736 ring->desc32[i].flags = 0; 1737 1738 data = &ring->data[i]; 1739 1740 if (data->m != NULL) { 1741 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1742 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1743 bus_dmamap_unload(sc->sc_dmat, data->active); 1744 m_freem(data->m); 1745 data->m = NULL; 1746 } 1747 } 1748 1749 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1750 BUS_DMASYNC_PREWRITE); 1751 1752 ring->queued = 0; 1753 ring->cur = ring->next = 0; 1754 } 1755 1756 void 1757 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1758 { 1759 struct nfe_tx_data *data; 1760 void *desc; 1761 int i, descsize; 1762 1763 if (sc->sc_flags & NFE_40BIT_ADDR) { 1764 desc = ring->desc64; 1765 descsize = sizeof (struct nfe_desc64); 1766 } else { 1767 desc = ring->desc32; 1768 descsize = sizeof (struct nfe_desc32); 1769 } 1770 1771 if (desc != NULL) { 1772 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1773 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1774 bus_dmamap_unload(sc->sc_dmat, ring->map); 1775 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1776 NFE_TX_RING_COUNT * descsize); 1777 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1778 } 1779 1780 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1781 data = &ring->data[i]; 1782 1783 if (data->m != NULL) { 1784 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1785 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1786 bus_dmamap_unload(sc->sc_dmat, data->active); 1787 m_freem(data->m); 1788 } 1789 } 1790 1791 /* ..and now actually destroy the DMA mappings */ 1792 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1793 data = &ring->data[i]; 1794 if (data->map == NULL) 1795 continue; 1796 bus_dmamap_destroy(sc->sc_dmat, data->map); 1797 } 1798 } 1799 1800 int 1801 nfe_ifmedia_upd(struct ifnet *ifp) 1802 { 1803 struct nfe_softc *sc = ifp->if_softc; 1804 struct mii_data *mii = &sc->sc_mii; 1805 struct mii_softc *miisc; 1806 1807 if (mii->mii_instance != 0) { 1808 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1809 mii_phy_reset(miisc); 1810 } 1811 return mii_mediachg(mii); 1812 } 1813 1814 void 1815 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1816 { 1817 struct nfe_softc *sc = ifp->if_softc; 1818 struct mii_data *mii = &sc->sc_mii; 1819 1820 mii_pollstat(mii); 1821 ifmr->ifm_status = mii->mii_media_status; 1822 ifmr->ifm_active = mii->mii_media_active; 1823 } 1824 1825 void 1826 nfe_setmulti(struct nfe_softc *sc) 1827 { 1828 struct ethercom *ec = &sc->sc_ethercom; 1829 struct ifnet *ifp = &ec->ec_if; 1830 struct ether_multi *enm; 1831 struct ether_multistep step; 1832 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1833 uint32_t filter = NFE_RXFILTER_MAGIC; 1834 int i; 1835 1836 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1837 bzero(addr, ETHER_ADDR_LEN); 1838 bzero(mask, ETHER_ADDR_LEN); 1839 goto done; 1840 } 1841 1842 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1843 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1844 1845 ETHER_FIRST_MULTI(step, ec, enm); 1846 while (enm != NULL) { 1847 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1848 ifp->if_flags |= IFF_ALLMULTI; 1849 bzero(addr, ETHER_ADDR_LEN); 1850 bzero(mask, ETHER_ADDR_LEN); 1851 goto done; 1852 } 1853 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1854 addr[i] &= enm->enm_addrlo[i]; 1855 mask[i] &= ~enm->enm_addrlo[i]; 1856 } 1857 ETHER_NEXT_MULTI(step, enm); 1858 } 1859 for (i = 0; i < ETHER_ADDR_LEN; i++) 1860 mask[i] |= addr[i]; 1861 1862 done: 1863 addr[0] |= 0x01; /* make sure multicast bit is set */ 1864 1865 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1866 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1867 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1868 addr[5] << 8 | addr[4]); 1869 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1870 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1871 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1872 mask[5] << 8 | mask[4]); 1873 1874 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1875 NFE_WRITE(sc, NFE_RXFILTER, filter); 1876 } 1877 1878 void 1879 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1880 { 1881 uint32_t tmp; 1882 1883 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1884 addr[0] = (tmp >> 8) & 0xff; 1885 addr[1] = (tmp & 0xff); 1886 1887 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1888 addr[2] = (tmp >> 24) & 0xff; 1889 addr[3] = (tmp >> 16) & 0xff; 1890 addr[4] = (tmp >> 8) & 0xff; 1891 addr[5] = (tmp & 0xff); 1892 } 1893 1894 void 1895 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1896 { 1897 NFE_WRITE(sc, NFE_MACADDR_LO, 1898 addr[5] << 8 | addr[4]); 1899 NFE_WRITE(sc, NFE_MACADDR_HI, 1900 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1901 } 1902 1903 void 1904 nfe_tick(void *arg) 1905 { 1906 struct nfe_softc *sc = arg; 1907 int s; 1908 1909 s = splnet(); 1910 mii_tick(&sc->sc_mii); 1911 splx(s); 1912 1913 callout_schedule(&sc->sc_tick_ch, hz); 1914 } 1915
Indexes created Tue Sep 30 07:10:03 GMT 2025