if_nfe.c revision 1.24
1 /* $NetBSD: if_nfe.c,v 1.24 2007/12/09 20:28:09 jmcneill Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.52 2006/03/02 09:04:00 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.24 2007/12/09 20:28:09 jmcneill Exp $"); 25 26 #include "opt_inet.h" 27 #include "bpfilter.h" 28 #include "vlan.h" 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/types.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/queue.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/socket.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/pci/if_nfereg.h> 74 #include <dev/pci/if_nfevar.h> 75 76 int nfe_match(struct device *, struct cfdata *, void *); 77 void nfe_attach(struct device *, struct device *, void *); 78 void nfe_power(int, void *); 79 void nfe_miibus_statchg(struct device *); 80 int nfe_miibus_readreg(struct device *, int, int); 81 void nfe_miibus_writereg(struct device *, int, int, int); 82 int nfe_intr(void *); 83 int nfe_ioctl(struct ifnet *, u_long, void *); 84 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 85 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 86 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 87 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 88 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 89 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 90 void nfe_rxeof(struct nfe_softc *); 91 void nfe_txeof(struct nfe_softc *); 92 int nfe_encap(struct nfe_softc *, struct mbuf *); 93 void nfe_start(struct ifnet *); 94 void nfe_watchdog(struct ifnet *); 95 int nfe_init(struct ifnet *); 96 void nfe_stop(struct ifnet *, int); 97 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 98 void nfe_jfree(struct mbuf *, void *, size_t, void *); 99 int nfe_jpool_alloc(struct nfe_softc *); 100 void nfe_jpool_free(struct nfe_softc *); 101 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 102 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 105 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 int nfe_ifmedia_upd(struct ifnet *); 108 void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 109 void nfe_setmulti(struct nfe_softc *); 110 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 111 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 112 void nfe_tick(void *); 113 114 CFATTACH_DECL(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, NULL, NULL); 115 116 /*#define NFE_NO_JUMBO*/ 117 118 #ifdef NFE_DEBUG 119 int nfedebug = 0; 120 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 121 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 122 #else 123 #define DPRINTF(x) 124 #define DPRINTFN(n,x) 125 #endif 126 127 /* deal with naming differences */ 128 129 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 130 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 134 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 135 136 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 137 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 140 141 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 142 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 145 146 #ifdef _LP64 147 #define __LP64__ 1 148 #endif 149 150 const struct nfe_product { 151 pci_vendor_id_t vendor; 152 pci_product_id_t product; 153 } nfe_devices[] = { 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 155 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 183 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 184 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 } 185 }; 186 187 int 188 nfe_match(struct device *dev, struct cfdata *match, void *aux) 189 { 190 struct pci_attach_args *pa = aux; 191 const struct nfe_product *np; 192 int i; 193 194 for (i = 0; i < sizeof(nfe_devices) / sizeof(nfe_devices[0]); i++) { 195 np = &nfe_devices[i]; 196 if (PCI_VENDOR(pa->pa_id) == np->vendor && 197 PCI_PRODUCT(pa->pa_id) == np->product) 198 return 1; 199 } 200 return 0; 201 } 202 203 void 204 nfe_attach(struct device *parent, struct device *self, void *aux) 205 { 206 struct nfe_softc *sc = (struct nfe_softc *)self; 207 struct pci_attach_args *pa = aux; 208 pci_chipset_tag_t pc = pa->pa_pc; 209 pci_intr_handle_t ih; 210 const char *intrstr; 211 struct ifnet *ifp; 212 bus_size_t memsize; 213 pcireg_t memtype; 214 char devinfo[256]; 215 216 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 217 aprint_normal(": %s (rev. 0x%02x)\n", 218 devinfo, PCI_REVISION(pa->pa_class)); 219 220 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 221 switch (memtype) { 222 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 223 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 224 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 225 &sc->sc_memh, NULL, &memsize) == 0) 226 break; 227 /* FALLTHROUGH */ 228 default: 229 printf("%s: could not map mem space\n", sc->sc_dev.dv_xname); 230 return; 231 } 232 233 if (pci_intr_map(pa, &ih) != 0) { 234 printf("%s: could not map interrupt\n", sc->sc_dev.dv_xname); 235 return; 236 } 237 238 intrstr = pci_intr_string(pc, ih); 239 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 240 if (sc->sc_ih == NULL) { 241 printf("%s: could not establish interrupt", 242 sc->sc_dev.dv_xname); 243 if (intrstr != NULL) 244 printf(" at %s", intrstr); 245 printf("\n"); 246 return; 247 } 248 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 249 250 sc->sc_dmat = pa->pa_dmat; 251 252 nfe_get_macaddr(sc, sc->sc_enaddr); 253 printf("%s: Ethernet address %s\n", 254 sc->sc_dev.dv_xname, ether_sprintf(sc->sc_enaddr)); 255 256 sc->sc_flags = 0; 257 258 switch (PCI_PRODUCT(pa->pa_id)) { 259 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 260 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 261 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 262 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 263 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 264 break; 265 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 266 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 267 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 268 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 269 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 270 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 271 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 272 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 273 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 274 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 275 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 276 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 277 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 278 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 279 sc->sc_flags |= NFE_40BIT_ADDR; 280 break; 281 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 282 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 283 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 284 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 285 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 286 break; 287 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 288 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 289 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 290 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 291 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 292 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 293 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 294 NFE_HW_VLAN; 295 break; 296 } 297 298 #ifndef NFE_NO_JUMBO 299 /* enable jumbo frames for adapters that support it */ 300 if (sc->sc_flags & NFE_JUMBO_SUP) 301 sc->sc_flags |= NFE_USE_JUMBO; 302 #endif 303 304 /* 305 * Allocate Tx and Rx rings. 306 */ 307 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 308 printf("%s: could not allocate Tx ring\n", 309 sc->sc_dev.dv_xname); 310 return; 311 } 312 313 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 314 printf("%s: could not allocate Rx ring\n", 315 sc->sc_dev.dv_xname); 316 nfe_free_tx_ring(sc, &sc->txq); 317 return; 318 } 319 320 ifp = &sc->sc_ethercom.ec_if; 321 ifp->if_softc = sc; 322 ifp->if_mtu = ETHERMTU; 323 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 324 ifp->if_ioctl = nfe_ioctl; 325 ifp->if_start = nfe_start; 326 ifp->if_stop = nfe_stop; 327 ifp->if_watchdog = nfe_watchdog; 328 ifp->if_init = nfe_init; 329 ifp->if_baudrate = IF_Gbps(1); 330 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 331 IFQ_SET_READY(&ifp->if_snd); 332 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 333 334 #if NVLAN > 0 335 if (sc->sc_flags & NFE_HW_VLAN) 336 sc->sc_ethercom.ec_capabilities |= 337 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 338 #endif 339 if (sc->sc_flags & NFE_HW_CSUM) { 340 ifp->if_capabilities |= 341 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 342 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 343 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 344 } 345 346 sc->sc_mii.mii_ifp = ifp; 347 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 348 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 349 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 350 351 ifmedia_init(&sc->sc_mii.mii_media, 0, nfe_ifmedia_upd, 352 nfe_ifmedia_sts); 353 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 354 MII_OFFSET_ANY, 0); 355 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 356 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 357 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 358 0, NULL); 359 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 360 } else 361 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 362 363 if_attach(ifp); 364 ether_ifattach(ifp, sc->sc_enaddr); 365 366 callout_init(&sc->sc_tick_ch, 0); 367 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 368 369 if (!pmf_device_register(self, NULL, NULL)) 370 aprint_error_dev(self, "couldn't establish power handler\n"); 371 else 372 pmf_class_network_register(self, ifp); 373 } 374 375 void 376 nfe_miibus_statchg(struct device *dev) 377 { 378 struct nfe_softc *sc = (struct nfe_softc *)dev; 379 struct mii_data *mii = &sc->sc_mii; 380 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 381 382 phy = NFE_READ(sc, NFE_PHY_IFACE); 383 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 384 385 seed = NFE_READ(sc, NFE_RNDSEED); 386 seed &= ~NFE_SEED_MASK; 387 388 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 389 phy |= NFE_PHY_HDX; /* half-duplex */ 390 misc |= NFE_MISC1_HDX; 391 } 392 393 switch (IFM_SUBTYPE(mii->mii_media_active)) { 394 case IFM_1000_T: /* full-duplex only */ 395 link |= NFE_MEDIA_1000T; 396 seed |= NFE_SEED_1000T; 397 phy |= NFE_PHY_1000T; 398 break; 399 case IFM_100_TX: 400 link |= NFE_MEDIA_100TX; 401 seed |= NFE_SEED_100TX; 402 phy |= NFE_PHY_100TX; 403 break; 404 case IFM_10_T: 405 link |= NFE_MEDIA_10T; 406 seed |= NFE_SEED_10T; 407 break; 408 } 409 410 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 411 412 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 413 NFE_WRITE(sc, NFE_MISC1, misc); 414 NFE_WRITE(sc, NFE_LINKSPEED, link); 415 } 416 417 int 418 nfe_miibus_readreg(struct device *dev, int phy, int reg) 419 { 420 struct nfe_softc *sc = (struct nfe_softc *)dev; 421 uint32_t val; 422 int ntries; 423 424 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 425 426 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 427 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 428 DELAY(100); 429 } 430 431 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 432 433 for (ntries = 0; ntries < 1000; ntries++) { 434 DELAY(100); 435 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 436 break; 437 } 438 if (ntries == 1000) { 439 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 440 sc->sc_dev.dv_xname)); 441 return 0; 442 } 443 444 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 445 DPRINTFN(2, ("%s: could not read PHY\n", 446 sc->sc_dev.dv_xname)); 447 return 0; 448 } 449 450 val = NFE_READ(sc, NFE_PHY_DATA); 451 if (val != 0xffffffff && val != 0) 452 sc->mii_phyaddr = phy; 453 454 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 455 sc->sc_dev.dv_xname, phy, reg, val)); 456 457 return val; 458 } 459 460 void 461 nfe_miibus_writereg(struct device *dev, int phy, int reg, int val) 462 { 463 struct nfe_softc *sc = (struct nfe_softc *)dev; 464 uint32_t ctl; 465 int ntries; 466 467 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 468 469 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 470 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 471 DELAY(100); 472 } 473 474 NFE_WRITE(sc, NFE_PHY_DATA, val); 475 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 476 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 477 478 for (ntries = 0; ntries < 1000; ntries++) { 479 DELAY(100); 480 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 481 break; 482 } 483 #ifdef NFE_DEBUG 484 if (nfedebug >= 2 && ntries == 1000) 485 printf("could not write to PHY\n"); 486 #endif 487 } 488 489 int 490 nfe_intr(void *arg) 491 { 492 struct nfe_softc *sc = arg; 493 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 494 uint32_t r; 495 int handled; 496 497 if ((ifp->if_flags & IFF_UP) == 0) 498 return 0; 499 500 handled = 0; 501 502 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 503 504 for (;;) { 505 r = NFE_READ(sc, NFE_IRQ_STATUS); 506 if ((r & NFE_IRQ_WANTED) == 0) 507 break; 508 509 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 510 handled = 1; 511 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 512 513 if ((r & (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX)) 514 != 0) { 515 /* check Rx ring */ 516 nfe_rxeof(sc); 517 } 518 519 if ((r & (NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE)) 520 != 0) { 521 /* check Tx ring */ 522 nfe_txeof(sc); 523 } 524 525 if ((r & NFE_IRQ_LINK) != 0) { 526 NFE_READ(sc, NFE_PHY_STATUS); 527 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 528 DPRINTF(("%s: link state changed\n", 529 sc->sc_dev.dv_xname)); 530 } 531 } 532 533 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 534 535 if (handled && !IF_IS_EMPTY(&ifp->if_snd)) 536 nfe_start(ifp); 537 538 return handled; 539 } 540 541 int 542 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 543 { 544 struct nfe_softc *sc = ifp->if_softc; 545 struct ifreq *ifr = (struct ifreq *)data; 546 struct ifaddr *ifa = (struct ifaddr *)data; 547 int s, error = 0; 548 549 s = splnet(); 550 551 switch (cmd) { 552 case SIOCSIFADDR: 553 ifp->if_flags |= IFF_UP; 554 nfe_init(ifp); 555 switch (ifa->ifa_addr->sa_family) { 556 #ifdef INET 557 case AF_INET: 558 arp_ifinit(ifp, ifa); 559 break; 560 #endif 561 default: 562 break; 563 } 564 break; 565 case SIOCSIFMTU: 566 if (ifr->ifr_mtu < ETHERMIN || 567 ((sc->sc_flags & NFE_USE_JUMBO) && 568 ifr->ifr_mtu > ETHERMTU_JUMBO) || 569 (!(sc->sc_flags & NFE_USE_JUMBO) && 570 ifr->ifr_mtu > ETHERMTU)) 571 error = EINVAL; 572 else if (ifp->if_mtu != ifr->ifr_mtu) 573 ifp->if_mtu = ifr->ifr_mtu; 574 break; 575 case SIOCSIFFLAGS: 576 if (ifp->if_flags & IFF_UP) { 577 /* 578 * If only the PROMISC or ALLMULTI flag changes, then 579 * don't do a full re-init of the chip, just update 580 * the Rx filter. 581 */ 582 if ((ifp->if_flags & IFF_RUNNING) && 583 ((ifp->if_flags ^ sc->sc_if_flags) & 584 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 585 nfe_setmulti(sc); 586 else 587 nfe_init(ifp); 588 } else { 589 if (ifp->if_flags & IFF_RUNNING) 590 nfe_stop(ifp, 1); 591 } 592 sc->sc_if_flags = ifp->if_flags; 593 break; 594 case SIOCADDMULTI: 595 case SIOCDELMULTI: 596 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 597 if (ifp->if_flags & IFF_RUNNING) 598 nfe_setmulti(sc); 599 error = 0; 600 } 601 break; 602 case SIOCSIFMEDIA: 603 case SIOCGIFMEDIA: 604 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 605 break; 606 default: 607 error = ether_ioctl(ifp, cmd, data); 608 if (error == ENETRESET) { 609 if (ifp->if_flags & IFF_RUNNING) 610 nfe_setmulti(sc); 611 error = 0; 612 } 613 break; 614 615 } 616 617 splx(s); 618 619 return error; 620 } 621 622 void 623 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 624 { 625 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 626 (char *)desc32 - (char *)sc->txq.desc32, 627 sizeof (struct nfe_desc32), ops); 628 } 629 630 void 631 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 632 { 633 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 634 (char *)desc64 - (char *)sc->txq.desc64, 635 sizeof (struct nfe_desc64), ops); 636 } 637 638 void 639 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 640 { 641 if (end > start) { 642 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 643 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 644 (char *)&sc->txq.desc32[end] - 645 (char *)&sc->txq.desc32[start], ops); 646 return; 647 } 648 /* sync from 'start' to end of ring */ 649 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 650 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 651 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 652 (char *)&sc->txq.desc32[start], ops); 653 654 /* sync from start of ring to 'end' */ 655 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 656 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 657 } 658 659 void 660 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 661 { 662 if (end > start) { 663 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 664 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 665 (char *)&sc->txq.desc64[end] - 666 (char *)&sc->txq.desc64[start], ops); 667 return; 668 } 669 /* sync from 'start' to end of ring */ 670 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 671 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 672 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 673 (char *)&sc->txq.desc64[start], ops); 674 675 /* sync from start of ring to 'end' */ 676 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 677 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 678 } 679 680 void 681 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 682 { 683 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 684 (char *)desc32 - (char *)sc->rxq.desc32, 685 sizeof (struct nfe_desc32), ops); 686 } 687 688 void 689 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 690 { 691 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 692 (char *)desc64 - (char *)sc->rxq.desc64, 693 sizeof (struct nfe_desc64), ops); 694 } 695 696 void 697 nfe_rxeof(struct nfe_softc *sc) 698 { 699 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 700 struct nfe_desc32 *desc32; 701 struct nfe_desc64 *desc64; 702 struct nfe_rx_data *data; 703 struct nfe_jbuf *jbuf; 704 struct mbuf *m, *mnew; 705 bus_addr_t physaddr; 706 uint16_t flags; 707 int error, len, i; 708 709 desc32 = NULL; 710 desc64 = NULL; 711 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 712 data = &sc->rxq.data[i]; 713 714 if (sc->sc_flags & NFE_40BIT_ADDR) { 715 desc64 = &sc->rxq.desc64[i]; 716 nfe_rxdesc64_sync(sc, desc64, 717 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 718 719 flags = le16toh(desc64->flags); 720 len = le16toh(desc64->length) & 0x3fff; 721 } else { 722 desc32 = &sc->rxq.desc32[i]; 723 nfe_rxdesc32_sync(sc, desc32, 724 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 725 726 flags = le16toh(desc32->flags); 727 len = le16toh(desc32->length) & 0x3fff; 728 } 729 730 if ((flags & NFE_RX_READY) != 0) 731 break; 732 733 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 734 if ((flags & NFE_RX_VALID_V1) == 0) 735 goto skip; 736 737 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 738 flags &= ~NFE_RX_ERROR; 739 len--; /* fix buffer length */ 740 } 741 } else { 742 if ((flags & NFE_RX_VALID_V2) == 0) 743 goto skip; 744 745 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 746 flags &= ~NFE_RX_ERROR; 747 len--; /* fix buffer length */ 748 } 749 } 750 751 if (flags & NFE_RX_ERROR) { 752 ifp->if_ierrors++; 753 goto skip; 754 } 755 756 /* 757 * Try to allocate a new mbuf for this ring element and load 758 * it before processing the current mbuf. If the ring element 759 * cannot be loaded, drop the received packet and reuse the 760 * old mbuf. In the unlikely case that the old mbuf can't be 761 * reloaded either, explicitly panic. 762 */ 763 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 764 if (mnew == NULL) { 765 ifp->if_ierrors++; 766 goto skip; 767 } 768 769 if (sc->sc_flags & NFE_USE_JUMBO) { 770 physaddr = 771 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 772 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 773 if (len > MCLBYTES) { 774 m_freem(mnew); 775 ifp->if_ierrors++; 776 goto skip1; 777 } 778 MCLGET(mnew, M_DONTWAIT); 779 if ((mnew->m_flags & M_EXT) == 0) { 780 m_freem(mnew); 781 ifp->if_ierrors++; 782 goto skip1; 783 } 784 785 memcpy(mtod(mnew, void *), 786 mtod(data->m, const void *), len); 787 m = mnew; 788 goto mbufcopied; 789 } else { 790 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 791 792 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 793 mtod(data->m, char *) - (char *)sc->rxq.jpool, 794 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 795 796 physaddr = jbuf->physaddr; 797 } 798 } else { 799 MCLGET(mnew, M_DONTWAIT); 800 if ((mnew->m_flags & M_EXT) == 0) { 801 m_freem(mnew); 802 ifp->if_ierrors++; 803 goto skip; 804 } 805 806 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 807 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 808 bus_dmamap_unload(sc->sc_dmat, data->map); 809 810 error = bus_dmamap_load(sc->sc_dmat, data->map, 811 mtod(mnew, void *), MCLBYTES, NULL, 812 BUS_DMA_READ | BUS_DMA_NOWAIT); 813 if (error != 0) { 814 m_freem(mnew); 815 816 /* try to reload the old mbuf */ 817 error = bus_dmamap_load(sc->sc_dmat, data->map, 818 mtod(data->m, void *), MCLBYTES, NULL, 819 BUS_DMA_READ | BUS_DMA_NOWAIT); 820 if (error != 0) { 821 /* very unlikely that it will fail.. */ 822 panic("%s: could not load old rx mbuf", 823 sc->sc_dev.dv_xname); 824 } 825 ifp->if_ierrors++; 826 goto skip; 827 } 828 physaddr = data->map->dm_segs[0].ds_addr; 829 } 830 831 /* 832 * New mbuf successfully loaded, update Rx ring and continue 833 * processing. 834 */ 835 m = data->m; 836 data->m = mnew; 837 838 mbufcopied: 839 /* finalize mbuf */ 840 m->m_pkthdr.len = m->m_len = len; 841 m->m_pkthdr.rcvif = ifp; 842 843 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 844 /* 845 * XXX 846 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 847 */ 848 if (flags & NFE_RX_IP_CSUMOK) { 849 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 850 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 851 sc->sc_dev.dv_xname)); 852 } 853 /* 854 * XXX 855 * no way to check M_CSUM_TCP_UDP_BAD or 856 * other protocols? 857 */ 858 if (flags & NFE_RX_UDP_CSUMOK) { 859 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 860 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 861 sc->sc_dev.dv_xname)); 862 } else if (flags & NFE_RX_TCP_CSUMOK) { 863 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 864 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 865 sc->sc_dev.dv_xname)); 866 } 867 } 868 869 #if NBPFILTER > 0 870 if (ifp->if_bpf) 871 bpf_mtap(ifp->if_bpf, m); 872 #endif 873 ifp->if_ipackets++; 874 (*ifp->if_input)(ifp, m); 875 876 skip1: 877 /* update mapping address in h/w descriptor */ 878 if (sc->sc_flags & NFE_40BIT_ADDR) { 879 #if defined(__LP64__) 880 desc64->physaddr[0] = htole32(physaddr >> 32); 881 #endif 882 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 883 } else { 884 desc32->physaddr = htole32(physaddr); 885 } 886 887 skip: 888 if (sc->sc_flags & NFE_40BIT_ADDR) { 889 desc64->length = htole16(sc->rxq.bufsz); 890 desc64->flags = htole16(NFE_RX_READY); 891 892 nfe_rxdesc64_sync(sc, desc64, 893 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 894 } else { 895 desc32->length = htole16(sc->rxq.bufsz); 896 desc32->flags = htole16(NFE_RX_READY); 897 898 nfe_rxdesc32_sync(sc, desc32, 899 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 900 } 901 } 902 /* update current RX pointer */ 903 sc->rxq.cur = i; 904 } 905 906 void 907 nfe_txeof(struct nfe_softc *sc) 908 { 909 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 910 struct nfe_desc32 *desc32; 911 struct nfe_desc64 *desc64; 912 struct nfe_tx_data *data = NULL; 913 int i; 914 uint16_t flags; 915 916 for (i = sc->txq.next; 917 sc->txq.queued > 0; 918 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 919 if (sc->sc_flags & NFE_40BIT_ADDR) { 920 desc64 = &sc->txq.desc64[i]; 921 nfe_txdesc64_sync(sc, desc64, 922 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 923 924 flags = le16toh(desc64->flags); 925 } else { 926 desc32 = &sc->txq.desc32[i]; 927 nfe_txdesc32_sync(sc, desc32, 928 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 929 930 flags = le16toh(desc32->flags); 931 } 932 933 if ((flags & NFE_TX_VALID) != 0) 934 break; 935 936 data = &sc->txq.data[i]; 937 938 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 939 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 940 data->m == NULL) 941 continue; 942 943 if ((flags & NFE_TX_ERROR_V1) != 0) { 944 printf("%s: tx v1 error 0x%04x\n", 945 sc->sc_dev.dv_xname, flags); 946 ifp->if_oerrors++; 947 } else 948 ifp->if_opackets++; 949 } else { 950 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 951 data->m == NULL) 952 continue; 953 954 if ((flags & NFE_TX_ERROR_V2) != 0) { 955 printf("%s: tx v2 error 0x%04x\n", 956 sc->sc_dev.dv_xname, flags); 957 ifp->if_oerrors++; 958 } else 959 ifp->if_opackets++; 960 } 961 962 if (data->m == NULL) { /* should not get there */ 963 printf("%s: last fragment bit w/o associated mbuf!\n", 964 sc->sc_dev.dv_xname); 965 continue; 966 } 967 968 /* last fragment of the mbuf chain transmitted */ 969 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 970 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 971 bus_dmamap_unload(sc->sc_dmat, data->active); 972 m_freem(data->m); 973 data->m = NULL; 974 } 975 976 sc->txq.next = i; 977 978 if (sc->txq.queued < NFE_TX_RING_COUNT) { 979 /* at least one slot freed */ 980 ifp->if_flags &= ~IFF_OACTIVE; 981 } 982 983 if (sc->txq.queued == 0) { 984 /* all queued packets are sent */ 985 ifp->if_timer = 0; 986 } 987 } 988 989 int 990 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 991 { 992 struct nfe_desc32 *desc32; 993 struct nfe_desc64 *desc64; 994 struct nfe_tx_data *data; 995 bus_dmamap_t map; 996 uint16_t flags, csumflags; 997 #if NVLAN > 0 998 struct m_tag *mtag; 999 uint32_t vtag = 0; 1000 #endif 1001 int error, i, first; 1002 1003 desc32 = NULL; 1004 desc64 = NULL; 1005 data = NULL; 1006 1007 flags = 0; 1008 csumflags = 0; 1009 first = sc->txq.cur; 1010 1011 map = sc->txq.data[first].map; 1012 1013 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1014 if (error != 0) { 1015 printf("%s: could not map mbuf (error %d)\n", 1016 sc->sc_dev.dv_xname, error); 1017 return error; 1018 } 1019 1020 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1021 bus_dmamap_unload(sc->sc_dmat, map); 1022 return ENOBUFS; 1023 } 1024 1025 #if NVLAN > 0 1026 /* setup h/w VLAN tagging */ 1027 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1028 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1029 #endif 1030 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1031 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1032 csumflags |= NFE_TX_IP_CSUM; 1033 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1034 csumflags |= NFE_TX_TCP_UDP_CSUM; 1035 } 1036 1037 for (i = 0; i < map->dm_nsegs; i++) { 1038 data = &sc->txq.data[sc->txq.cur]; 1039 1040 if (sc->sc_flags & NFE_40BIT_ADDR) { 1041 desc64 = &sc->txq.desc64[sc->txq.cur]; 1042 #if defined(__LP64__) 1043 desc64->physaddr[0] = 1044 htole32(map->dm_segs[i].ds_addr >> 32); 1045 #endif 1046 desc64->physaddr[1] = 1047 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1048 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1049 desc64->flags = htole16(flags); 1050 desc64->vtag = 0; 1051 } else { 1052 desc32 = &sc->txq.desc32[sc->txq.cur]; 1053 1054 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1055 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1056 desc32->flags = htole16(flags); 1057 } 1058 1059 /* 1060 * Setting of the valid bit in the first descriptor is 1061 * deferred until the whole chain is fully setup. 1062 */ 1063 flags |= NFE_TX_VALID; 1064 1065 sc->txq.queued++; 1066 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1067 } 1068 1069 /* the whole mbuf chain has been setup */ 1070 if (sc->sc_flags & NFE_40BIT_ADDR) { 1071 /* fix last descriptor */ 1072 flags |= NFE_TX_LASTFRAG_V2; 1073 desc64->flags = htole16(flags); 1074 1075 /* Checksum flags and vtag belong to the first fragment only. */ 1076 #if NVLAN > 0 1077 sc->txq.desc64[first].vtag = htole32(vtag); 1078 #endif 1079 sc->txq.desc64[first].flags |= htole16(csumflags); 1080 1081 /* finally, set the valid bit in the first descriptor */ 1082 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1083 } else { 1084 /* fix last descriptor */ 1085 if (sc->sc_flags & NFE_JUMBO_SUP) 1086 flags |= NFE_TX_LASTFRAG_V2; 1087 else 1088 flags |= NFE_TX_LASTFRAG_V1; 1089 desc32->flags = htole16(flags); 1090 1091 /* Checksum flags belong to the first fragment only. */ 1092 sc->txq.desc32[first].flags |= htole16(csumflags); 1093 1094 /* finally, set the valid bit in the first descriptor */ 1095 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1096 } 1097 1098 data->m = m0; 1099 data->active = map; 1100 1101 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1102 BUS_DMASYNC_PREWRITE); 1103 1104 return 0; 1105 } 1106 1107 void 1108 nfe_start(struct ifnet *ifp) 1109 { 1110 struct nfe_softc *sc = ifp->if_softc; 1111 int old = sc->txq.queued; 1112 struct mbuf *m0; 1113 1114 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 1115 return; 1116 1117 for (;;) { 1118 IFQ_POLL(&ifp->if_snd, m0); 1119 if (m0 == NULL) 1120 break; 1121 1122 if (nfe_encap(sc, m0) != 0) { 1123 ifp->if_flags |= IFF_OACTIVE; 1124 break; 1125 } 1126 1127 /* packet put in h/w queue, remove from s/w queue */ 1128 IFQ_DEQUEUE(&ifp->if_snd, m0); 1129 1130 #if NBPFILTER > 0 1131 if (ifp->if_bpf != NULL) 1132 bpf_mtap(ifp->if_bpf, m0); 1133 #endif 1134 } 1135 1136 if (sc->txq.queued != old) { 1137 /* packets are queued */ 1138 if (sc->sc_flags & NFE_40BIT_ADDR) 1139 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1140 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1141 else 1142 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1143 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1144 /* kick Tx */ 1145 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1146 1147 /* 1148 * Set a timeout in case the chip goes out to lunch. 1149 */ 1150 ifp->if_timer = 5; 1151 } 1152 } 1153 1154 void 1155 nfe_watchdog(struct ifnet *ifp) 1156 { 1157 struct nfe_softc *sc = ifp->if_softc; 1158 1159 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1160 1161 ifp->if_flags &= ~IFF_RUNNING; 1162 nfe_init(ifp); 1163 1164 ifp->if_oerrors++; 1165 } 1166 1167 int 1168 nfe_init(struct ifnet *ifp) 1169 { 1170 struct nfe_softc *sc = ifp->if_softc; 1171 uint32_t tmp; 1172 int s; 1173 1174 if (ifp->if_flags & IFF_RUNNING) 1175 return 0; 1176 1177 nfe_stop(ifp, 0); 1178 1179 NFE_WRITE(sc, NFE_TX_UNK, 0); 1180 NFE_WRITE(sc, NFE_STATUS, 0); 1181 1182 sc->rxtxctl = NFE_RXTX_BIT2; 1183 if (sc->sc_flags & NFE_40BIT_ADDR) 1184 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1185 else if (sc->sc_flags & NFE_JUMBO_SUP) 1186 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1187 if (sc->sc_flags & NFE_HW_CSUM) 1188 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1189 #if NVLAN > 0 1190 /* 1191 * Although the adapter is capable of stripping VLAN tags from received 1192 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1193 * purpose. This will be done in software by our network stack. 1194 */ 1195 if (sc->sc_flags & NFE_HW_VLAN) 1196 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1197 #endif 1198 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1199 DELAY(10); 1200 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1201 1202 #if NVLAN 1203 if (sc->sc_flags & NFE_HW_VLAN) 1204 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1205 #endif 1206 1207 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1208 1209 /* set MAC address */ 1210 nfe_set_macaddr(sc, sc->sc_enaddr); 1211 1212 /* tell MAC where rings are in memory */ 1213 #ifdef __LP64__ 1214 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1215 #endif 1216 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1217 #ifdef __LP64__ 1218 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1219 #endif 1220 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1221 1222 NFE_WRITE(sc, NFE_RING_SIZE, 1223 (NFE_RX_RING_COUNT - 1) << 16 | 1224 (NFE_TX_RING_COUNT - 1)); 1225 1226 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1227 1228 /* force MAC to wakeup */ 1229 tmp = NFE_READ(sc, NFE_PWR_STATE); 1230 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1231 DELAY(10); 1232 tmp = NFE_READ(sc, NFE_PWR_STATE); 1233 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1234 1235 s = splnet(); 1236 nfe_intr(sc); /* XXX clear IRQ status registers */ 1237 splx(s); 1238 1239 #if 1 1240 /* configure interrupts coalescing/mitigation */ 1241 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1242 #else 1243 /* no interrupt mitigation: one interrupt per packet */ 1244 NFE_WRITE(sc, NFE_IMTIMER, 970); 1245 #endif 1246 1247 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1248 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1249 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1250 1251 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1252 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1253 1254 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1255 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC); 1256 1257 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1258 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1259 DELAY(10); 1260 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1261 1262 /* set Rx filter */ 1263 nfe_setmulti(sc); 1264 1265 nfe_ifmedia_upd(ifp); 1266 1267 nfe_tick(sc); 1268 1269 /* enable Rx */ 1270 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1271 1272 /* enable Tx */ 1273 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1274 1275 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1276 1277 /* enable interrupts */ 1278 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1279 1280 callout_schedule(&sc->sc_tick_ch, hz); 1281 1282 ifp->if_flags |= IFF_RUNNING; 1283 ifp->if_flags &= ~IFF_OACTIVE; 1284 1285 return 0; 1286 } 1287 1288 void 1289 nfe_stop(struct ifnet *ifp, int disable) 1290 { 1291 struct nfe_softc *sc = ifp->if_softc; 1292 1293 callout_stop(&sc->sc_tick_ch); 1294 1295 ifp->if_timer = 0; 1296 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1297 1298 mii_down(&sc->sc_mii); 1299 1300 /* abort Tx */ 1301 NFE_WRITE(sc, NFE_TX_CTL, 0); 1302 1303 /* disable Rx */ 1304 NFE_WRITE(sc, NFE_RX_CTL, 0); 1305 1306 /* disable interrupts */ 1307 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1308 1309 /* reset Tx and Rx rings */ 1310 nfe_reset_tx_ring(sc, &sc->txq); 1311 nfe_reset_rx_ring(sc, &sc->rxq); 1312 } 1313 1314 int 1315 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1316 { 1317 struct nfe_desc32 *desc32; 1318 struct nfe_desc64 *desc64; 1319 struct nfe_rx_data *data; 1320 struct nfe_jbuf *jbuf; 1321 void **desc; 1322 bus_addr_t physaddr; 1323 int i, nsegs, error, descsize; 1324 1325 if (sc->sc_flags & NFE_40BIT_ADDR) { 1326 desc = (void **)&ring->desc64; 1327 descsize = sizeof (struct nfe_desc64); 1328 } else { 1329 desc = (void **)&ring->desc32; 1330 descsize = sizeof (struct nfe_desc32); 1331 } 1332 1333 ring->cur = ring->next = 0; 1334 ring->bufsz = MCLBYTES; 1335 1336 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1337 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1338 if (error != 0) { 1339 printf("%s: could not create desc DMA map\n", 1340 sc->sc_dev.dv_xname); 1341 goto fail; 1342 } 1343 1344 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1345 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1346 if (error != 0) { 1347 printf("%s: could not allocate DMA memory\n", 1348 sc->sc_dev.dv_xname); 1349 goto fail; 1350 } 1351 1352 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1353 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1354 if (error != 0) { 1355 printf("%s: could not map desc DMA memory\n", 1356 sc->sc_dev.dv_xname); 1357 goto fail; 1358 } 1359 1360 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1361 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1362 if (error != 0) { 1363 printf("%s: could not load desc DMA map\n", 1364 sc->sc_dev.dv_xname); 1365 goto fail; 1366 } 1367 1368 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1369 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1370 1371 if (sc->sc_flags & NFE_USE_JUMBO) { 1372 ring->bufsz = NFE_JBYTES; 1373 if ((error = nfe_jpool_alloc(sc)) != 0) { 1374 printf("%s: could not allocate jumbo frames\n", 1375 sc->sc_dev.dv_xname); 1376 goto fail; 1377 } 1378 } 1379 1380 /* 1381 * Pre-allocate Rx buffers and populate Rx ring. 1382 */ 1383 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1384 data = &sc->rxq.data[i]; 1385 1386 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1387 if (data->m == NULL) { 1388 printf("%s: could not allocate rx mbuf\n", 1389 sc->sc_dev.dv_xname); 1390 error = ENOMEM; 1391 goto fail; 1392 } 1393 1394 if (sc->sc_flags & NFE_USE_JUMBO) { 1395 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1396 printf("%s: could not allocate jumbo buffer\n", 1397 sc->sc_dev.dv_xname); 1398 goto fail; 1399 } 1400 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1401 sc); 1402 1403 physaddr = jbuf->physaddr; 1404 } else { 1405 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1406 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1407 if (error != 0) { 1408 printf("%s: could not create DMA map\n", 1409 sc->sc_dev.dv_xname); 1410 goto fail; 1411 } 1412 MCLGET(data->m, M_DONTWAIT); 1413 if (!(data->m->m_flags & M_EXT)) { 1414 printf("%s: could not allocate mbuf cluster\n", 1415 sc->sc_dev.dv_xname); 1416 error = ENOMEM; 1417 goto fail; 1418 } 1419 1420 error = bus_dmamap_load(sc->sc_dmat, data->map, 1421 mtod(data->m, void *), MCLBYTES, NULL, 1422 BUS_DMA_READ | BUS_DMA_NOWAIT); 1423 if (error != 0) { 1424 printf("%s: could not load rx buf DMA map", 1425 sc->sc_dev.dv_xname); 1426 goto fail; 1427 } 1428 physaddr = data->map->dm_segs[0].ds_addr; 1429 } 1430 1431 if (sc->sc_flags & NFE_40BIT_ADDR) { 1432 desc64 = &sc->rxq.desc64[i]; 1433 #if defined(__LP64__) 1434 desc64->physaddr[0] = htole32(physaddr >> 32); 1435 #endif 1436 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1437 desc64->length = htole16(sc->rxq.bufsz); 1438 desc64->flags = htole16(NFE_RX_READY); 1439 } else { 1440 desc32 = &sc->rxq.desc32[i]; 1441 desc32->physaddr = htole32(physaddr); 1442 desc32->length = htole16(sc->rxq.bufsz); 1443 desc32->flags = htole16(NFE_RX_READY); 1444 } 1445 } 1446 1447 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1448 BUS_DMASYNC_PREWRITE); 1449 1450 return 0; 1451 1452 fail: nfe_free_rx_ring(sc, ring); 1453 return error; 1454 } 1455 1456 void 1457 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1458 { 1459 int i; 1460 1461 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1462 if (sc->sc_flags & NFE_40BIT_ADDR) { 1463 ring->desc64[i].length = htole16(ring->bufsz); 1464 ring->desc64[i].flags = htole16(NFE_RX_READY); 1465 } else { 1466 ring->desc32[i].length = htole16(ring->bufsz); 1467 ring->desc32[i].flags = htole16(NFE_RX_READY); 1468 } 1469 } 1470 1471 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1472 BUS_DMASYNC_PREWRITE); 1473 1474 ring->cur = ring->next = 0; 1475 } 1476 1477 void 1478 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1479 { 1480 struct nfe_rx_data *data; 1481 void *desc; 1482 int i, descsize; 1483 1484 if (sc->sc_flags & NFE_40BIT_ADDR) { 1485 desc = ring->desc64; 1486 descsize = sizeof (struct nfe_desc64); 1487 } else { 1488 desc = ring->desc32; 1489 descsize = sizeof (struct nfe_desc32); 1490 } 1491 1492 if (desc != NULL) { 1493 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1494 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1495 bus_dmamap_unload(sc->sc_dmat, ring->map); 1496 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1497 NFE_RX_RING_COUNT * descsize); 1498 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1499 } 1500 1501 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1502 data = &ring->data[i]; 1503 1504 if (data->map != NULL) { 1505 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1506 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1507 bus_dmamap_unload(sc->sc_dmat, data->map); 1508 bus_dmamap_destroy(sc->sc_dmat, data->map); 1509 } 1510 if (data->m != NULL) 1511 m_freem(data->m); 1512 } 1513 } 1514 1515 struct nfe_jbuf * 1516 nfe_jalloc(struct nfe_softc *sc, int i) 1517 { 1518 struct nfe_jbuf *jbuf; 1519 1520 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1521 if (jbuf == NULL) 1522 return NULL; 1523 sc->rxq.jbufmap[i] = 1524 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1525 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1526 return jbuf; 1527 } 1528 1529 /* 1530 * This is called automatically by the network stack when the mbuf is freed. 1531 * Caution must be taken that the NIC might be reset by the time the mbuf is 1532 * freed. 1533 */ 1534 void 1535 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1536 { 1537 struct nfe_softc *sc = arg; 1538 struct nfe_jbuf *jbuf; 1539 int i; 1540 1541 /* find the jbuf from the base pointer */ 1542 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1543 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1544 printf("%s: request to free a buffer (%p) not managed by us\n", 1545 sc->sc_dev.dv_xname, buf); 1546 return; 1547 } 1548 jbuf = &sc->rxq.jbuf[i]; 1549 1550 /* ..and put it back in the free list */ 1551 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1552 1553 if (m != NULL) 1554 pool_cache_put(mb_cache, m); 1555 } 1556 1557 int 1558 nfe_jpool_alloc(struct nfe_softc *sc) 1559 { 1560 struct nfe_rx_ring *ring = &sc->rxq; 1561 struct nfe_jbuf *jbuf; 1562 bus_addr_t physaddr; 1563 char *buf; 1564 int i, nsegs, error; 1565 1566 /* 1567 * Allocate a big chunk of DMA'able memory. 1568 */ 1569 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1570 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1571 if (error != 0) { 1572 printf("%s: could not create jumbo DMA map\n", 1573 sc->sc_dev.dv_xname); 1574 goto fail; 1575 } 1576 1577 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1578 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1579 if (error != 0) { 1580 printf("%s could not allocate jumbo DMA memory\n", 1581 sc->sc_dev.dv_xname); 1582 goto fail; 1583 } 1584 1585 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1586 &ring->jpool, BUS_DMA_NOWAIT); 1587 if (error != 0) { 1588 printf("%s: could not map jumbo DMA memory\n", 1589 sc->sc_dev.dv_xname); 1590 goto fail; 1591 } 1592 1593 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1594 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1595 if (error != 0) { 1596 printf("%s: could not load jumbo DMA map\n", 1597 sc->sc_dev.dv_xname); 1598 goto fail; 1599 } 1600 1601 /* ..and split it into 9KB chunks */ 1602 SLIST_INIT(&ring->jfreelist); 1603 1604 buf = ring->jpool; 1605 physaddr = ring->jmap->dm_segs[0].ds_addr; 1606 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1607 jbuf = &ring->jbuf[i]; 1608 1609 jbuf->buf = buf; 1610 jbuf->physaddr = physaddr; 1611 1612 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1613 1614 buf += NFE_JBYTES; 1615 physaddr += NFE_JBYTES; 1616 } 1617 1618 return 0; 1619 1620 fail: nfe_jpool_free(sc); 1621 return error; 1622 } 1623 1624 void 1625 nfe_jpool_free(struct nfe_softc *sc) 1626 { 1627 struct nfe_rx_ring *ring = &sc->rxq; 1628 1629 if (ring->jmap != NULL) { 1630 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1631 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1632 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1633 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1634 } 1635 if (ring->jpool != NULL) { 1636 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1637 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1638 } 1639 } 1640 1641 int 1642 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1643 { 1644 int i, nsegs, error; 1645 void **desc; 1646 int descsize; 1647 1648 if (sc->sc_flags & NFE_40BIT_ADDR) { 1649 desc = (void **)&ring->desc64; 1650 descsize = sizeof (struct nfe_desc64); 1651 } else { 1652 desc = (void **)&ring->desc32; 1653 descsize = sizeof (struct nfe_desc32); 1654 } 1655 1656 ring->queued = 0; 1657 ring->cur = ring->next = 0; 1658 1659 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1660 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1661 1662 if (error != 0) { 1663 printf("%s: could not create desc DMA map\n", 1664 sc->sc_dev.dv_xname); 1665 goto fail; 1666 } 1667 1668 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1669 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1670 if (error != 0) { 1671 printf("%s: could not allocate DMA memory\n", 1672 sc->sc_dev.dv_xname); 1673 goto fail; 1674 } 1675 1676 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1677 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1678 if (error != 0) { 1679 printf("%s: could not map desc DMA memory\n", 1680 sc->sc_dev.dv_xname); 1681 goto fail; 1682 } 1683 1684 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1685 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1686 if (error != 0) { 1687 printf("%s: could not load desc DMA map\n", 1688 sc->sc_dev.dv_xname); 1689 goto fail; 1690 } 1691 1692 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1693 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1694 1695 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1696 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1697 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1698 &ring->data[i].map); 1699 if (error != 0) { 1700 printf("%s: could not create DMA map\n", 1701 sc->sc_dev.dv_xname); 1702 goto fail; 1703 } 1704 } 1705 1706 return 0; 1707 1708 fail: nfe_free_tx_ring(sc, ring); 1709 return error; 1710 } 1711 1712 void 1713 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1714 { 1715 struct nfe_tx_data *data; 1716 int i; 1717 1718 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1719 if (sc->sc_flags & NFE_40BIT_ADDR) 1720 ring->desc64[i].flags = 0; 1721 else 1722 ring->desc32[i].flags = 0; 1723 1724 data = &ring->data[i]; 1725 1726 if (data->m != NULL) { 1727 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1728 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1729 bus_dmamap_unload(sc->sc_dmat, data->active); 1730 m_freem(data->m); 1731 data->m = NULL; 1732 } 1733 } 1734 1735 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1736 BUS_DMASYNC_PREWRITE); 1737 1738 ring->queued = 0; 1739 ring->cur = ring->next = 0; 1740 } 1741 1742 void 1743 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1744 { 1745 struct nfe_tx_data *data; 1746 void *desc; 1747 int i, descsize; 1748 1749 if (sc->sc_flags & NFE_40BIT_ADDR) { 1750 desc = ring->desc64; 1751 descsize = sizeof (struct nfe_desc64); 1752 } else { 1753 desc = ring->desc32; 1754 descsize = sizeof (struct nfe_desc32); 1755 } 1756 1757 if (desc != NULL) { 1758 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1759 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1760 bus_dmamap_unload(sc->sc_dmat, ring->map); 1761 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1762 NFE_TX_RING_COUNT * descsize); 1763 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1764 } 1765 1766 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1767 data = &ring->data[i]; 1768 1769 if (data->m != NULL) { 1770 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1771 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1772 bus_dmamap_unload(sc->sc_dmat, data->active); 1773 m_freem(data->m); 1774 } 1775 } 1776 1777 /* ..and now actually destroy the DMA mappings */ 1778 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1779 data = &ring->data[i]; 1780 if (data->map == NULL) 1781 continue; 1782 bus_dmamap_destroy(sc->sc_dmat, data->map); 1783 } 1784 } 1785 1786 int 1787 nfe_ifmedia_upd(struct ifnet *ifp) 1788 { 1789 struct nfe_softc *sc = ifp->if_softc; 1790 struct mii_data *mii = &sc->sc_mii; 1791 struct mii_softc *miisc; 1792 1793 if (mii->mii_instance != 0) { 1794 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1795 mii_phy_reset(miisc); 1796 } 1797 return mii_mediachg(mii); 1798 } 1799 1800 void 1801 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1802 { 1803 struct nfe_softc *sc = ifp->if_softc; 1804 struct mii_data *mii = &sc->sc_mii; 1805 1806 mii_pollstat(mii); 1807 ifmr->ifm_status = mii->mii_media_status; 1808 ifmr->ifm_active = mii->mii_media_active; 1809 } 1810 1811 void 1812 nfe_setmulti(struct nfe_softc *sc) 1813 { 1814 struct ethercom *ec = &sc->sc_ethercom; 1815 struct ifnet *ifp = &ec->ec_if; 1816 struct ether_multi *enm; 1817 struct ether_multistep step; 1818 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1819 uint32_t filter = NFE_RXFILTER_MAGIC; 1820 int i; 1821 1822 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1823 bzero(addr, ETHER_ADDR_LEN); 1824 bzero(mask, ETHER_ADDR_LEN); 1825 goto done; 1826 } 1827 1828 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1829 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1830 1831 ETHER_FIRST_MULTI(step, ec, enm); 1832 while (enm != NULL) { 1833 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1834 ifp->if_flags |= IFF_ALLMULTI; 1835 bzero(addr, ETHER_ADDR_LEN); 1836 bzero(mask, ETHER_ADDR_LEN); 1837 goto done; 1838 } 1839 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1840 addr[i] &= enm->enm_addrlo[i]; 1841 mask[i] &= ~enm->enm_addrlo[i]; 1842 } 1843 ETHER_NEXT_MULTI(step, enm); 1844 } 1845 for (i = 0; i < ETHER_ADDR_LEN; i++) 1846 mask[i] |= addr[i]; 1847 1848 done: 1849 addr[0] |= 0x01; /* make sure multicast bit is set */ 1850 1851 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1852 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1853 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1854 addr[5] << 8 | addr[4]); 1855 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1856 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1857 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1858 mask[5] << 8 | mask[4]); 1859 1860 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1861 NFE_WRITE(sc, NFE_RXFILTER, filter); 1862 } 1863 1864 void 1865 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1866 { 1867 uint32_t tmp; 1868 1869 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1870 addr[0] = (tmp >> 8) & 0xff; 1871 addr[1] = (tmp & 0xff); 1872 1873 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1874 addr[2] = (tmp >> 24) & 0xff; 1875 addr[3] = (tmp >> 16) & 0xff; 1876 addr[4] = (tmp >> 8) & 0xff; 1877 addr[5] = (tmp & 0xff); 1878 } 1879 1880 void 1881 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1882 { 1883 NFE_WRITE(sc, NFE_MACADDR_LO, 1884 addr[5] << 8 | addr[4]); 1885 NFE_WRITE(sc, NFE_MACADDR_HI, 1886 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1887 } 1888 1889 void 1890 nfe_tick(void *arg) 1891 { 1892 struct nfe_softc *sc = arg; 1893 int s; 1894 1895 s = splnet(); 1896 mii_tick(&sc->sc_mii); 1897 splx(s); 1898 1899 callout_schedule(&sc->sc_tick_ch, hz); 1900 } 1901
Indexes created Tue Sep 30 07:10:03 GMT 2025