if_nfe.c revision 1.25
1 /* $NetBSD: if_nfe.c,v 1.25 2007/12/17 12:41:06 tsutsui Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.52 2006/03/02 09:04:00 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.25 2007/12/17 12:41:06 tsutsui Exp $"); 25 26 #include "opt_inet.h" 27 #include "bpfilter.h" 28 #include "vlan.h" 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/types.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/queue.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/socket.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/pci/if_nfereg.h> 74 #include <dev/pci/if_nfevar.h> 75 76 int nfe_match(struct device *, struct cfdata *, void *); 77 void nfe_attach(struct device *, struct device *, void *); 78 void nfe_power(int, void *); 79 void nfe_miibus_statchg(struct device *); 80 int nfe_miibus_readreg(struct device *, int, int); 81 void nfe_miibus_writereg(struct device *, int, int, int); 82 int nfe_intr(void *); 83 int nfe_ioctl(struct ifnet *, u_long, void *); 84 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 85 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 86 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 87 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 88 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 89 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 90 void nfe_rxeof(struct nfe_softc *); 91 void nfe_txeof(struct nfe_softc *); 92 int nfe_encap(struct nfe_softc *, struct mbuf *); 93 void nfe_start(struct ifnet *); 94 void nfe_watchdog(struct ifnet *); 95 int nfe_init(struct ifnet *); 96 void nfe_stop(struct ifnet *, int); 97 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 98 void nfe_jfree(struct mbuf *, void *, size_t, void *); 99 int nfe_jpool_alloc(struct nfe_softc *); 100 void nfe_jpool_free(struct nfe_softc *); 101 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 102 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 105 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 int nfe_ifmedia_upd(struct ifnet *); 108 void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 109 void nfe_setmulti(struct nfe_softc *); 110 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 111 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 112 void nfe_tick(void *); 113 114 CFATTACH_DECL(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, NULL, NULL); 115 116 /*#define NFE_NO_JUMBO*/ 117 118 #ifdef NFE_DEBUG 119 int nfedebug = 0; 120 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 121 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 122 #else 123 #define DPRINTF(x) 124 #define DPRINTFN(n,x) 125 #endif 126 127 /* deal with naming differences */ 128 129 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 130 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 134 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 135 136 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 137 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 140 141 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 142 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 145 146 #ifdef _LP64 147 #define __LP64__ 1 148 #endif 149 150 const struct nfe_product { 151 pci_vendor_id_t vendor; 152 pci_product_id_t product; 153 } nfe_devices[] = { 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 155 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 183 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 184 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 } 185 }; 186 187 int 188 nfe_match(struct device *dev, struct cfdata *match, void *aux) 189 { 190 struct pci_attach_args *pa = aux; 191 const struct nfe_product *np; 192 int i; 193 194 for (i = 0; i < sizeof(nfe_devices) / sizeof(nfe_devices[0]); i++) { 195 np = &nfe_devices[i]; 196 if (PCI_VENDOR(pa->pa_id) == np->vendor && 197 PCI_PRODUCT(pa->pa_id) == np->product) 198 return 1; 199 } 200 return 0; 201 } 202 203 void 204 nfe_attach(struct device *parent, struct device *self, void *aux) 205 { 206 struct nfe_softc *sc = (struct nfe_softc *)self; 207 struct pci_attach_args *pa = aux; 208 pci_chipset_tag_t pc = pa->pa_pc; 209 pci_intr_handle_t ih; 210 const char *intrstr; 211 struct ifnet *ifp; 212 bus_size_t memsize; 213 pcireg_t memtype; 214 char devinfo[256]; 215 216 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 217 aprint_normal(": %s (rev. 0x%02x)\n", 218 devinfo, PCI_REVISION(pa->pa_class)); 219 220 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 221 switch (memtype) { 222 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 223 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 224 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 225 &sc->sc_memh, NULL, &memsize) == 0) 226 break; 227 /* FALLTHROUGH */ 228 default: 229 printf("%s: could not map mem space\n", sc->sc_dev.dv_xname); 230 return; 231 } 232 233 if (pci_intr_map(pa, &ih) != 0) { 234 printf("%s: could not map interrupt\n", sc->sc_dev.dv_xname); 235 return; 236 } 237 238 intrstr = pci_intr_string(pc, ih); 239 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 240 if (sc->sc_ih == NULL) { 241 printf("%s: could not establish interrupt", 242 sc->sc_dev.dv_xname); 243 if (intrstr != NULL) 244 printf(" at %s", intrstr); 245 printf("\n"); 246 return; 247 } 248 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 249 250 sc->sc_dmat = pa->pa_dmat; 251 252 /* Check for reversed ethernet address */ 253 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 254 sc->sc_flags |= NFE_CORRECT_MACADDR; 255 256 nfe_get_macaddr(sc, sc->sc_enaddr); 257 printf("%s: Ethernet address %s\n", 258 sc->sc_dev.dv_xname, ether_sprintf(sc->sc_enaddr)); 259 260 sc->sc_flags = 0; 261 262 switch (PCI_PRODUCT(pa->pa_id)) { 263 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 264 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 265 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 266 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 267 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 268 break; 269 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 270 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 271 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 272 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 273 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 274 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 275 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 276 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 277 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 278 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 279 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 280 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 281 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 282 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 283 sc->sc_flags |= NFE_40BIT_ADDR; 284 break; 285 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 286 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 287 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 288 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 289 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 290 break; 291 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 292 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 293 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 294 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 295 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 296 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 297 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 298 NFE_HW_VLAN; 299 break; 300 } 301 302 #ifndef NFE_NO_JUMBO 303 /* enable jumbo frames for adapters that support it */ 304 if (sc->sc_flags & NFE_JUMBO_SUP) 305 sc->sc_flags |= NFE_USE_JUMBO; 306 #endif 307 308 /* 309 * Allocate Tx and Rx rings. 310 */ 311 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 312 printf("%s: could not allocate Tx ring\n", 313 sc->sc_dev.dv_xname); 314 return; 315 } 316 317 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 318 printf("%s: could not allocate Rx ring\n", 319 sc->sc_dev.dv_xname); 320 nfe_free_tx_ring(sc, &sc->txq); 321 return; 322 } 323 324 ifp = &sc->sc_ethercom.ec_if; 325 ifp->if_softc = sc; 326 ifp->if_mtu = ETHERMTU; 327 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 328 ifp->if_ioctl = nfe_ioctl; 329 ifp->if_start = nfe_start; 330 ifp->if_stop = nfe_stop; 331 ifp->if_watchdog = nfe_watchdog; 332 ifp->if_init = nfe_init; 333 ifp->if_baudrate = IF_Gbps(1); 334 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 335 IFQ_SET_READY(&ifp->if_snd); 336 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 337 338 #if NVLAN > 0 339 if (sc->sc_flags & NFE_HW_VLAN) 340 sc->sc_ethercom.ec_capabilities |= 341 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 342 #endif 343 if (sc->sc_flags & NFE_HW_CSUM) { 344 ifp->if_capabilities |= 345 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 346 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 347 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 348 } 349 350 sc->sc_mii.mii_ifp = ifp; 351 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 352 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 353 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 354 355 ifmedia_init(&sc->sc_mii.mii_media, 0, nfe_ifmedia_upd, 356 nfe_ifmedia_sts); 357 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 358 MII_OFFSET_ANY, 0); 359 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 360 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 361 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 362 0, NULL); 363 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 364 } else 365 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 366 367 if_attach(ifp); 368 ether_ifattach(ifp, sc->sc_enaddr); 369 370 callout_init(&sc->sc_tick_ch, 0); 371 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 372 373 if (!pmf_device_register(self, NULL, NULL)) 374 aprint_error_dev(self, "couldn't establish power handler\n"); 375 else 376 pmf_class_network_register(self, ifp); 377 } 378 379 void 380 nfe_miibus_statchg(struct device *dev) 381 { 382 struct nfe_softc *sc = (struct nfe_softc *)dev; 383 struct mii_data *mii = &sc->sc_mii; 384 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 385 386 phy = NFE_READ(sc, NFE_PHY_IFACE); 387 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 388 389 seed = NFE_READ(sc, NFE_RNDSEED); 390 seed &= ~NFE_SEED_MASK; 391 392 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 393 phy |= NFE_PHY_HDX; /* half-duplex */ 394 misc |= NFE_MISC1_HDX; 395 } 396 397 switch (IFM_SUBTYPE(mii->mii_media_active)) { 398 case IFM_1000_T: /* full-duplex only */ 399 link |= NFE_MEDIA_1000T; 400 seed |= NFE_SEED_1000T; 401 phy |= NFE_PHY_1000T; 402 break; 403 case IFM_100_TX: 404 link |= NFE_MEDIA_100TX; 405 seed |= NFE_SEED_100TX; 406 phy |= NFE_PHY_100TX; 407 break; 408 case IFM_10_T: 409 link |= NFE_MEDIA_10T; 410 seed |= NFE_SEED_10T; 411 break; 412 } 413 414 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 415 416 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 417 NFE_WRITE(sc, NFE_MISC1, misc); 418 NFE_WRITE(sc, NFE_LINKSPEED, link); 419 } 420 421 int 422 nfe_miibus_readreg(struct device *dev, int phy, int reg) 423 { 424 struct nfe_softc *sc = (struct nfe_softc *)dev; 425 uint32_t val; 426 int ntries; 427 428 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 429 430 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 431 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 432 DELAY(100); 433 } 434 435 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 436 437 for (ntries = 0; ntries < 1000; ntries++) { 438 DELAY(100); 439 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 440 break; 441 } 442 if (ntries == 1000) { 443 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 444 sc->sc_dev.dv_xname)); 445 return 0; 446 } 447 448 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 449 DPRINTFN(2, ("%s: could not read PHY\n", 450 sc->sc_dev.dv_xname)); 451 return 0; 452 } 453 454 val = NFE_READ(sc, NFE_PHY_DATA); 455 if (val != 0xffffffff && val != 0) 456 sc->mii_phyaddr = phy; 457 458 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 459 sc->sc_dev.dv_xname, phy, reg, val)); 460 461 return val; 462 } 463 464 void 465 nfe_miibus_writereg(struct device *dev, int phy, int reg, int val) 466 { 467 struct nfe_softc *sc = (struct nfe_softc *)dev; 468 uint32_t ctl; 469 int ntries; 470 471 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 472 473 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 474 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 475 DELAY(100); 476 } 477 478 NFE_WRITE(sc, NFE_PHY_DATA, val); 479 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 480 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 481 482 for (ntries = 0; ntries < 1000; ntries++) { 483 DELAY(100); 484 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 485 break; 486 } 487 #ifdef NFE_DEBUG 488 if (nfedebug >= 2 && ntries == 1000) 489 printf("could not write to PHY\n"); 490 #endif 491 } 492 493 int 494 nfe_intr(void *arg) 495 { 496 struct nfe_softc *sc = arg; 497 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 498 uint32_t r; 499 int handled; 500 501 if ((ifp->if_flags & IFF_UP) == 0) 502 return 0; 503 504 handled = 0; 505 506 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 507 508 for (;;) { 509 r = NFE_READ(sc, NFE_IRQ_STATUS); 510 if ((r & NFE_IRQ_WANTED) == 0) 511 break; 512 513 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 514 handled = 1; 515 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 516 517 if ((r & (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX)) 518 != 0) { 519 /* check Rx ring */ 520 nfe_rxeof(sc); 521 } 522 523 if ((r & (NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE)) 524 != 0) { 525 /* check Tx ring */ 526 nfe_txeof(sc); 527 } 528 529 if ((r & NFE_IRQ_LINK) != 0) { 530 NFE_READ(sc, NFE_PHY_STATUS); 531 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 532 DPRINTF(("%s: link state changed\n", 533 sc->sc_dev.dv_xname)); 534 } 535 } 536 537 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 538 539 if (handled && !IF_IS_EMPTY(&ifp->if_snd)) 540 nfe_start(ifp); 541 542 return handled; 543 } 544 545 int 546 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 547 { 548 struct nfe_softc *sc = ifp->if_softc; 549 struct ifreq *ifr = (struct ifreq *)data; 550 struct ifaddr *ifa = (struct ifaddr *)data; 551 int s, error = 0; 552 553 s = splnet(); 554 555 switch (cmd) { 556 case SIOCSIFADDR: 557 ifp->if_flags |= IFF_UP; 558 nfe_init(ifp); 559 switch (ifa->ifa_addr->sa_family) { 560 #ifdef INET 561 case AF_INET: 562 arp_ifinit(ifp, ifa); 563 break; 564 #endif 565 default: 566 break; 567 } 568 break; 569 case SIOCSIFMTU: 570 if (ifr->ifr_mtu < ETHERMIN || 571 ((sc->sc_flags & NFE_USE_JUMBO) && 572 ifr->ifr_mtu > ETHERMTU_JUMBO) || 573 (!(sc->sc_flags & NFE_USE_JUMBO) && 574 ifr->ifr_mtu > ETHERMTU)) 575 error = EINVAL; 576 else if (ifp->if_mtu != ifr->ifr_mtu) 577 ifp->if_mtu = ifr->ifr_mtu; 578 break; 579 case SIOCSIFFLAGS: 580 if (ifp->if_flags & IFF_UP) { 581 /* 582 * If only the PROMISC or ALLMULTI flag changes, then 583 * don't do a full re-init of the chip, just update 584 * the Rx filter. 585 */ 586 if ((ifp->if_flags & IFF_RUNNING) && 587 ((ifp->if_flags ^ sc->sc_if_flags) & 588 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 589 nfe_setmulti(sc); 590 else 591 nfe_init(ifp); 592 } else { 593 if (ifp->if_flags & IFF_RUNNING) 594 nfe_stop(ifp, 1); 595 } 596 sc->sc_if_flags = ifp->if_flags; 597 break; 598 case SIOCADDMULTI: 599 case SIOCDELMULTI: 600 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 601 if (ifp->if_flags & IFF_RUNNING) 602 nfe_setmulti(sc); 603 error = 0; 604 } 605 break; 606 case SIOCSIFMEDIA: 607 case SIOCGIFMEDIA: 608 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 609 break; 610 default: 611 error = ether_ioctl(ifp, cmd, data); 612 if (error == ENETRESET) { 613 if (ifp->if_flags & IFF_RUNNING) 614 nfe_setmulti(sc); 615 error = 0; 616 } 617 break; 618 619 } 620 621 splx(s); 622 623 return error; 624 } 625 626 void 627 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 628 { 629 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 630 (char *)desc32 - (char *)sc->txq.desc32, 631 sizeof (struct nfe_desc32), ops); 632 } 633 634 void 635 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 636 { 637 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 638 (char *)desc64 - (char *)sc->txq.desc64, 639 sizeof (struct nfe_desc64), ops); 640 } 641 642 void 643 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 644 { 645 if (end > start) { 646 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 647 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 648 (char *)&sc->txq.desc32[end] - 649 (char *)&sc->txq.desc32[start], ops); 650 return; 651 } 652 /* sync from 'start' to end of ring */ 653 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 654 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 655 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 656 (char *)&sc->txq.desc32[start], ops); 657 658 /* sync from start of ring to 'end' */ 659 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 660 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 661 } 662 663 void 664 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 665 { 666 if (end > start) { 667 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 668 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 669 (char *)&sc->txq.desc64[end] - 670 (char *)&sc->txq.desc64[start], ops); 671 return; 672 } 673 /* sync from 'start' to end of ring */ 674 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 675 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 676 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 677 (char *)&sc->txq.desc64[start], ops); 678 679 /* sync from start of ring to 'end' */ 680 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 681 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 682 } 683 684 void 685 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 686 { 687 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 688 (char *)desc32 - (char *)sc->rxq.desc32, 689 sizeof (struct nfe_desc32), ops); 690 } 691 692 void 693 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 694 { 695 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 696 (char *)desc64 - (char *)sc->rxq.desc64, 697 sizeof (struct nfe_desc64), ops); 698 } 699 700 void 701 nfe_rxeof(struct nfe_softc *sc) 702 { 703 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 704 struct nfe_desc32 *desc32; 705 struct nfe_desc64 *desc64; 706 struct nfe_rx_data *data; 707 struct nfe_jbuf *jbuf; 708 struct mbuf *m, *mnew; 709 bus_addr_t physaddr; 710 uint16_t flags; 711 int error, len, i; 712 713 desc32 = NULL; 714 desc64 = NULL; 715 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 716 data = &sc->rxq.data[i]; 717 718 if (sc->sc_flags & NFE_40BIT_ADDR) { 719 desc64 = &sc->rxq.desc64[i]; 720 nfe_rxdesc64_sync(sc, desc64, 721 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 722 723 flags = le16toh(desc64->flags); 724 len = le16toh(desc64->length) & 0x3fff; 725 } else { 726 desc32 = &sc->rxq.desc32[i]; 727 nfe_rxdesc32_sync(sc, desc32, 728 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 729 730 flags = le16toh(desc32->flags); 731 len = le16toh(desc32->length) & 0x3fff; 732 } 733 734 if ((flags & NFE_RX_READY) != 0) 735 break; 736 737 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 738 if ((flags & NFE_RX_VALID_V1) == 0) 739 goto skip; 740 741 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 742 flags &= ~NFE_RX_ERROR; 743 len--; /* fix buffer length */ 744 } 745 } else { 746 if ((flags & NFE_RX_VALID_V2) == 0) 747 goto skip; 748 749 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 750 flags &= ~NFE_RX_ERROR; 751 len--; /* fix buffer length */ 752 } 753 } 754 755 if (flags & NFE_RX_ERROR) { 756 ifp->if_ierrors++; 757 goto skip; 758 } 759 760 /* 761 * Try to allocate a new mbuf for this ring element and load 762 * it before processing the current mbuf. If the ring element 763 * cannot be loaded, drop the received packet and reuse the 764 * old mbuf. In the unlikely case that the old mbuf can't be 765 * reloaded either, explicitly panic. 766 */ 767 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 768 if (mnew == NULL) { 769 ifp->if_ierrors++; 770 goto skip; 771 } 772 773 if (sc->sc_flags & NFE_USE_JUMBO) { 774 physaddr = 775 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 776 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 777 if (len > MCLBYTES) { 778 m_freem(mnew); 779 ifp->if_ierrors++; 780 goto skip1; 781 } 782 MCLGET(mnew, M_DONTWAIT); 783 if ((mnew->m_flags & M_EXT) == 0) { 784 m_freem(mnew); 785 ifp->if_ierrors++; 786 goto skip1; 787 } 788 789 memcpy(mtod(mnew, void *), 790 mtod(data->m, const void *), len); 791 m = mnew; 792 goto mbufcopied; 793 } else { 794 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 795 796 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 797 mtod(data->m, char *) - (char *)sc->rxq.jpool, 798 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 799 800 physaddr = jbuf->physaddr; 801 } 802 } else { 803 MCLGET(mnew, M_DONTWAIT); 804 if ((mnew->m_flags & M_EXT) == 0) { 805 m_freem(mnew); 806 ifp->if_ierrors++; 807 goto skip; 808 } 809 810 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 811 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 812 bus_dmamap_unload(sc->sc_dmat, data->map); 813 814 error = bus_dmamap_load(sc->sc_dmat, data->map, 815 mtod(mnew, void *), MCLBYTES, NULL, 816 BUS_DMA_READ | BUS_DMA_NOWAIT); 817 if (error != 0) { 818 m_freem(mnew); 819 820 /* try to reload the old mbuf */ 821 error = bus_dmamap_load(sc->sc_dmat, data->map, 822 mtod(data->m, void *), MCLBYTES, NULL, 823 BUS_DMA_READ | BUS_DMA_NOWAIT); 824 if (error != 0) { 825 /* very unlikely that it will fail.. */ 826 panic("%s: could not load old rx mbuf", 827 sc->sc_dev.dv_xname); 828 } 829 ifp->if_ierrors++; 830 goto skip; 831 } 832 physaddr = data->map->dm_segs[0].ds_addr; 833 } 834 835 /* 836 * New mbuf successfully loaded, update Rx ring and continue 837 * processing. 838 */ 839 m = data->m; 840 data->m = mnew; 841 842 mbufcopied: 843 /* finalize mbuf */ 844 m->m_pkthdr.len = m->m_len = len; 845 m->m_pkthdr.rcvif = ifp; 846 847 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 848 /* 849 * XXX 850 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 851 */ 852 if (flags & NFE_RX_IP_CSUMOK) { 853 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 854 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 855 sc->sc_dev.dv_xname)); 856 } 857 /* 858 * XXX 859 * no way to check M_CSUM_TCP_UDP_BAD or 860 * other protocols? 861 */ 862 if (flags & NFE_RX_UDP_CSUMOK) { 863 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 864 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 865 sc->sc_dev.dv_xname)); 866 } else if (flags & NFE_RX_TCP_CSUMOK) { 867 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 868 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 869 sc->sc_dev.dv_xname)); 870 } 871 } 872 873 #if NBPFILTER > 0 874 if (ifp->if_bpf) 875 bpf_mtap(ifp->if_bpf, m); 876 #endif 877 ifp->if_ipackets++; 878 (*ifp->if_input)(ifp, m); 879 880 skip1: 881 /* update mapping address in h/w descriptor */ 882 if (sc->sc_flags & NFE_40BIT_ADDR) { 883 #if defined(__LP64__) 884 desc64->physaddr[0] = htole32(physaddr >> 32); 885 #endif 886 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 887 } else { 888 desc32->physaddr = htole32(physaddr); 889 } 890 891 skip: 892 if (sc->sc_flags & NFE_40BIT_ADDR) { 893 desc64->length = htole16(sc->rxq.bufsz); 894 desc64->flags = htole16(NFE_RX_READY); 895 896 nfe_rxdesc64_sync(sc, desc64, 897 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 898 } else { 899 desc32->length = htole16(sc->rxq.bufsz); 900 desc32->flags = htole16(NFE_RX_READY); 901 902 nfe_rxdesc32_sync(sc, desc32, 903 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 904 } 905 } 906 /* update current RX pointer */ 907 sc->rxq.cur = i; 908 } 909 910 void 911 nfe_txeof(struct nfe_softc *sc) 912 { 913 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 914 struct nfe_desc32 *desc32; 915 struct nfe_desc64 *desc64; 916 struct nfe_tx_data *data = NULL; 917 int i; 918 uint16_t flags; 919 920 for (i = sc->txq.next; 921 sc->txq.queued > 0; 922 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 923 if (sc->sc_flags & NFE_40BIT_ADDR) { 924 desc64 = &sc->txq.desc64[i]; 925 nfe_txdesc64_sync(sc, desc64, 926 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 927 928 flags = le16toh(desc64->flags); 929 } else { 930 desc32 = &sc->txq.desc32[i]; 931 nfe_txdesc32_sync(sc, desc32, 932 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 933 934 flags = le16toh(desc32->flags); 935 } 936 937 if ((flags & NFE_TX_VALID) != 0) 938 break; 939 940 data = &sc->txq.data[i]; 941 942 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 943 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 944 data->m == NULL) 945 continue; 946 947 if ((flags & NFE_TX_ERROR_V1) != 0) { 948 printf("%s: tx v1 error 0x%04x\n", 949 sc->sc_dev.dv_xname, flags); 950 ifp->if_oerrors++; 951 } else 952 ifp->if_opackets++; 953 } else { 954 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 955 data->m == NULL) 956 continue; 957 958 if ((flags & NFE_TX_ERROR_V2) != 0) { 959 printf("%s: tx v2 error 0x%04x\n", 960 sc->sc_dev.dv_xname, flags); 961 ifp->if_oerrors++; 962 } else 963 ifp->if_opackets++; 964 } 965 966 if (data->m == NULL) { /* should not get there */ 967 printf("%s: last fragment bit w/o associated mbuf!\n", 968 sc->sc_dev.dv_xname); 969 continue; 970 } 971 972 /* last fragment of the mbuf chain transmitted */ 973 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 974 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 975 bus_dmamap_unload(sc->sc_dmat, data->active); 976 m_freem(data->m); 977 data->m = NULL; 978 } 979 980 sc->txq.next = i; 981 982 if (sc->txq.queued < NFE_TX_RING_COUNT) { 983 /* at least one slot freed */ 984 ifp->if_flags &= ~IFF_OACTIVE; 985 } 986 987 if (sc->txq.queued == 0) { 988 /* all queued packets are sent */ 989 ifp->if_timer = 0; 990 } 991 } 992 993 int 994 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 995 { 996 struct nfe_desc32 *desc32; 997 struct nfe_desc64 *desc64; 998 struct nfe_tx_data *data; 999 bus_dmamap_t map; 1000 uint16_t flags, csumflags; 1001 #if NVLAN > 0 1002 struct m_tag *mtag; 1003 uint32_t vtag = 0; 1004 #endif 1005 int error, i, first; 1006 1007 desc32 = NULL; 1008 desc64 = NULL; 1009 data = NULL; 1010 1011 flags = 0; 1012 csumflags = 0; 1013 first = sc->txq.cur; 1014 1015 map = sc->txq.data[first].map; 1016 1017 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1018 if (error != 0) { 1019 printf("%s: could not map mbuf (error %d)\n", 1020 sc->sc_dev.dv_xname, error); 1021 return error; 1022 } 1023 1024 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1025 bus_dmamap_unload(sc->sc_dmat, map); 1026 return ENOBUFS; 1027 } 1028 1029 #if NVLAN > 0 1030 /* setup h/w VLAN tagging */ 1031 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1032 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1033 #endif 1034 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1035 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1036 csumflags |= NFE_TX_IP_CSUM; 1037 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1038 csumflags |= NFE_TX_TCP_UDP_CSUM; 1039 } 1040 1041 for (i = 0; i < map->dm_nsegs; i++) { 1042 data = &sc->txq.data[sc->txq.cur]; 1043 1044 if (sc->sc_flags & NFE_40BIT_ADDR) { 1045 desc64 = &sc->txq.desc64[sc->txq.cur]; 1046 #if defined(__LP64__) 1047 desc64->physaddr[0] = 1048 htole32(map->dm_segs[i].ds_addr >> 32); 1049 #endif 1050 desc64->physaddr[1] = 1051 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1052 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1053 desc64->flags = htole16(flags); 1054 desc64->vtag = 0; 1055 } else { 1056 desc32 = &sc->txq.desc32[sc->txq.cur]; 1057 1058 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1059 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1060 desc32->flags = htole16(flags); 1061 } 1062 1063 /* 1064 * Setting of the valid bit in the first descriptor is 1065 * deferred until the whole chain is fully setup. 1066 */ 1067 flags |= NFE_TX_VALID; 1068 1069 sc->txq.queued++; 1070 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1071 } 1072 1073 /* the whole mbuf chain has been setup */ 1074 if (sc->sc_flags & NFE_40BIT_ADDR) { 1075 /* fix last descriptor */ 1076 flags |= NFE_TX_LASTFRAG_V2; 1077 desc64->flags = htole16(flags); 1078 1079 /* Checksum flags and vtag belong to the first fragment only. */ 1080 #if NVLAN > 0 1081 sc->txq.desc64[first].vtag = htole32(vtag); 1082 #endif 1083 sc->txq.desc64[first].flags |= htole16(csumflags); 1084 1085 /* finally, set the valid bit in the first descriptor */ 1086 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1087 } else { 1088 /* fix last descriptor */ 1089 if (sc->sc_flags & NFE_JUMBO_SUP) 1090 flags |= NFE_TX_LASTFRAG_V2; 1091 else 1092 flags |= NFE_TX_LASTFRAG_V1; 1093 desc32->flags = htole16(flags); 1094 1095 /* Checksum flags belong to the first fragment only. */ 1096 sc->txq.desc32[first].flags |= htole16(csumflags); 1097 1098 /* finally, set the valid bit in the first descriptor */ 1099 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1100 } 1101 1102 data->m = m0; 1103 data->active = map; 1104 1105 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1106 BUS_DMASYNC_PREWRITE); 1107 1108 return 0; 1109 } 1110 1111 void 1112 nfe_start(struct ifnet *ifp) 1113 { 1114 struct nfe_softc *sc = ifp->if_softc; 1115 int old = sc->txq.queued; 1116 struct mbuf *m0; 1117 1118 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 1119 return; 1120 1121 for (;;) { 1122 IFQ_POLL(&ifp->if_snd, m0); 1123 if (m0 == NULL) 1124 break; 1125 1126 if (nfe_encap(sc, m0) != 0) { 1127 ifp->if_flags |= IFF_OACTIVE; 1128 break; 1129 } 1130 1131 /* packet put in h/w queue, remove from s/w queue */ 1132 IFQ_DEQUEUE(&ifp->if_snd, m0); 1133 1134 #if NBPFILTER > 0 1135 if (ifp->if_bpf != NULL) 1136 bpf_mtap(ifp->if_bpf, m0); 1137 #endif 1138 } 1139 1140 if (sc->txq.queued != old) { 1141 /* packets are queued */ 1142 if (sc->sc_flags & NFE_40BIT_ADDR) 1143 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1144 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1145 else 1146 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1147 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1148 /* kick Tx */ 1149 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1150 1151 /* 1152 * Set a timeout in case the chip goes out to lunch. 1153 */ 1154 ifp->if_timer = 5; 1155 } 1156 } 1157 1158 void 1159 nfe_watchdog(struct ifnet *ifp) 1160 { 1161 struct nfe_softc *sc = ifp->if_softc; 1162 1163 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1164 1165 ifp->if_flags &= ~IFF_RUNNING; 1166 nfe_init(ifp); 1167 1168 ifp->if_oerrors++; 1169 } 1170 1171 int 1172 nfe_init(struct ifnet *ifp) 1173 { 1174 struct nfe_softc *sc = ifp->if_softc; 1175 uint32_t tmp; 1176 int s; 1177 1178 if (ifp->if_flags & IFF_RUNNING) 1179 return 0; 1180 1181 nfe_stop(ifp, 0); 1182 1183 NFE_WRITE(sc, NFE_TX_UNK, 0); 1184 NFE_WRITE(sc, NFE_STATUS, 0); 1185 1186 sc->rxtxctl = NFE_RXTX_BIT2; 1187 if (sc->sc_flags & NFE_40BIT_ADDR) 1188 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1189 else if (sc->sc_flags & NFE_JUMBO_SUP) 1190 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1191 if (sc->sc_flags & NFE_HW_CSUM) 1192 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1193 #if NVLAN > 0 1194 /* 1195 * Although the adapter is capable of stripping VLAN tags from received 1196 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1197 * purpose. This will be done in software by our network stack. 1198 */ 1199 if (sc->sc_flags & NFE_HW_VLAN) 1200 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1201 #endif 1202 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1203 DELAY(10); 1204 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1205 1206 #if NVLAN 1207 if (sc->sc_flags & NFE_HW_VLAN) 1208 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1209 #endif 1210 1211 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1212 1213 /* set MAC address */ 1214 nfe_set_macaddr(sc, sc->sc_enaddr); 1215 1216 /* tell MAC where rings are in memory */ 1217 #ifdef __LP64__ 1218 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1219 #endif 1220 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1221 #ifdef __LP64__ 1222 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1223 #endif 1224 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1225 1226 NFE_WRITE(sc, NFE_RING_SIZE, 1227 (NFE_RX_RING_COUNT - 1) << 16 | 1228 (NFE_TX_RING_COUNT - 1)); 1229 1230 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1231 1232 /* force MAC to wakeup */ 1233 tmp = NFE_READ(sc, NFE_PWR_STATE); 1234 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1235 DELAY(10); 1236 tmp = NFE_READ(sc, NFE_PWR_STATE); 1237 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1238 1239 s = splnet(); 1240 nfe_intr(sc); /* XXX clear IRQ status registers */ 1241 splx(s); 1242 1243 #if 1 1244 /* configure interrupts coalescing/mitigation */ 1245 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1246 #else 1247 /* no interrupt mitigation: one interrupt per packet */ 1248 NFE_WRITE(sc, NFE_IMTIMER, 970); 1249 #endif 1250 1251 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1252 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1253 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1254 1255 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1256 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1257 1258 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1259 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC); 1260 1261 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1262 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1263 DELAY(10); 1264 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1265 1266 /* set Rx filter */ 1267 nfe_setmulti(sc); 1268 1269 nfe_ifmedia_upd(ifp); 1270 1271 nfe_tick(sc); 1272 1273 /* enable Rx */ 1274 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1275 1276 /* enable Tx */ 1277 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1278 1279 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1280 1281 /* enable interrupts */ 1282 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1283 1284 callout_schedule(&sc->sc_tick_ch, hz); 1285 1286 ifp->if_flags |= IFF_RUNNING; 1287 ifp->if_flags &= ~IFF_OACTIVE; 1288 1289 return 0; 1290 } 1291 1292 void 1293 nfe_stop(struct ifnet *ifp, int disable) 1294 { 1295 struct nfe_softc *sc = ifp->if_softc; 1296 1297 callout_stop(&sc->sc_tick_ch); 1298 1299 ifp->if_timer = 0; 1300 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1301 1302 mii_down(&sc->sc_mii); 1303 1304 /* abort Tx */ 1305 NFE_WRITE(sc, NFE_TX_CTL, 0); 1306 1307 /* disable Rx */ 1308 NFE_WRITE(sc, NFE_RX_CTL, 0); 1309 1310 /* disable interrupts */ 1311 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1312 1313 /* reset Tx and Rx rings */ 1314 nfe_reset_tx_ring(sc, &sc->txq); 1315 nfe_reset_rx_ring(sc, &sc->rxq); 1316 } 1317 1318 int 1319 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1320 { 1321 struct nfe_desc32 *desc32; 1322 struct nfe_desc64 *desc64; 1323 struct nfe_rx_data *data; 1324 struct nfe_jbuf *jbuf; 1325 void **desc; 1326 bus_addr_t physaddr; 1327 int i, nsegs, error, descsize; 1328 1329 if (sc->sc_flags & NFE_40BIT_ADDR) { 1330 desc = (void **)&ring->desc64; 1331 descsize = sizeof (struct nfe_desc64); 1332 } else { 1333 desc = (void **)&ring->desc32; 1334 descsize = sizeof (struct nfe_desc32); 1335 } 1336 1337 ring->cur = ring->next = 0; 1338 ring->bufsz = MCLBYTES; 1339 1340 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1341 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1342 if (error != 0) { 1343 printf("%s: could not create desc DMA map\n", 1344 sc->sc_dev.dv_xname); 1345 goto fail; 1346 } 1347 1348 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1349 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1350 if (error != 0) { 1351 printf("%s: could not allocate DMA memory\n", 1352 sc->sc_dev.dv_xname); 1353 goto fail; 1354 } 1355 1356 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1357 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1358 if (error != 0) { 1359 printf("%s: could not map desc DMA memory\n", 1360 sc->sc_dev.dv_xname); 1361 goto fail; 1362 } 1363 1364 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1365 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1366 if (error != 0) { 1367 printf("%s: could not load desc DMA map\n", 1368 sc->sc_dev.dv_xname); 1369 goto fail; 1370 } 1371 1372 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1373 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1374 1375 if (sc->sc_flags & NFE_USE_JUMBO) { 1376 ring->bufsz = NFE_JBYTES; 1377 if ((error = nfe_jpool_alloc(sc)) != 0) { 1378 printf("%s: could not allocate jumbo frames\n", 1379 sc->sc_dev.dv_xname); 1380 goto fail; 1381 } 1382 } 1383 1384 /* 1385 * Pre-allocate Rx buffers and populate Rx ring. 1386 */ 1387 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1388 data = &sc->rxq.data[i]; 1389 1390 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1391 if (data->m == NULL) { 1392 printf("%s: could not allocate rx mbuf\n", 1393 sc->sc_dev.dv_xname); 1394 error = ENOMEM; 1395 goto fail; 1396 } 1397 1398 if (sc->sc_flags & NFE_USE_JUMBO) { 1399 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1400 printf("%s: could not allocate jumbo buffer\n", 1401 sc->sc_dev.dv_xname); 1402 goto fail; 1403 } 1404 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1405 sc); 1406 1407 physaddr = jbuf->physaddr; 1408 } else { 1409 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1410 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1411 if (error != 0) { 1412 printf("%s: could not create DMA map\n", 1413 sc->sc_dev.dv_xname); 1414 goto fail; 1415 } 1416 MCLGET(data->m, M_DONTWAIT); 1417 if (!(data->m->m_flags & M_EXT)) { 1418 printf("%s: could not allocate mbuf cluster\n", 1419 sc->sc_dev.dv_xname); 1420 error = ENOMEM; 1421 goto fail; 1422 } 1423 1424 error = bus_dmamap_load(sc->sc_dmat, data->map, 1425 mtod(data->m, void *), MCLBYTES, NULL, 1426 BUS_DMA_READ | BUS_DMA_NOWAIT); 1427 if (error != 0) { 1428 printf("%s: could not load rx buf DMA map", 1429 sc->sc_dev.dv_xname); 1430 goto fail; 1431 } 1432 physaddr = data->map->dm_segs[0].ds_addr; 1433 } 1434 1435 if (sc->sc_flags & NFE_40BIT_ADDR) { 1436 desc64 = &sc->rxq.desc64[i]; 1437 #if defined(__LP64__) 1438 desc64->physaddr[0] = htole32(physaddr >> 32); 1439 #endif 1440 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1441 desc64->length = htole16(sc->rxq.bufsz); 1442 desc64->flags = htole16(NFE_RX_READY); 1443 } else { 1444 desc32 = &sc->rxq.desc32[i]; 1445 desc32->physaddr = htole32(physaddr); 1446 desc32->length = htole16(sc->rxq.bufsz); 1447 desc32->flags = htole16(NFE_RX_READY); 1448 } 1449 } 1450 1451 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1452 BUS_DMASYNC_PREWRITE); 1453 1454 return 0; 1455 1456 fail: nfe_free_rx_ring(sc, ring); 1457 return error; 1458 } 1459 1460 void 1461 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1462 { 1463 int i; 1464 1465 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1466 if (sc->sc_flags & NFE_40BIT_ADDR) { 1467 ring->desc64[i].length = htole16(ring->bufsz); 1468 ring->desc64[i].flags = htole16(NFE_RX_READY); 1469 } else { 1470 ring->desc32[i].length = htole16(ring->bufsz); 1471 ring->desc32[i].flags = htole16(NFE_RX_READY); 1472 } 1473 } 1474 1475 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1476 BUS_DMASYNC_PREWRITE); 1477 1478 ring->cur = ring->next = 0; 1479 } 1480 1481 void 1482 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1483 { 1484 struct nfe_rx_data *data; 1485 void *desc; 1486 int i, descsize; 1487 1488 if (sc->sc_flags & NFE_40BIT_ADDR) { 1489 desc = ring->desc64; 1490 descsize = sizeof (struct nfe_desc64); 1491 } else { 1492 desc = ring->desc32; 1493 descsize = sizeof (struct nfe_desc32); 1494 } 1495 1496 if (desc != NULL) { 1497 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1498 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1499 bus_dmamap_unload(sc->sc_dmat, ring->map); 1500 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1501 NFE_RX_RING_COUNT * descsize); 1502 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1503 } 1504 1505 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1506 data = &ring->data[i]; 1507 1508 if (data->map != NULL) { 1509 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1510 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1511 bus_dmamap_unload(sc->sc_dmat, data->map); 1512 bus_dmamap_destroy(sc->sc_dmat, data->map); 1513 } 1514 if (data->m != NULL) 1515 m_freem(data->m); 1516 } 1517 } 1518 1519 struct nfe_jbuf * 1520 nfe_jalloc(struct nfe_softc *sc, int i) 1521 { 1522 struct nfe_jbuf *jbuf; 1523 1524 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1525 if (jbuf == NULL) 1526 return NULL; 1527 sc->rxq.jbufmap[i] = 1528 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1529 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1530 return jbuf; 1531 } 1532 1533 /* 1534 * This is called automatically by the network stack when the mbuf is freed. 1535 * Caution must be taken that the NIC might be reset by the time the mbuf is 1536 * freed. 1537 */ 1538 void 1539 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1540 { 1541 struct nfe_softc *sc = arg; 1542 struct nfe_jbuf *jbuf; 1543 int i; 1544 1545 /* find the jbuf from the base pointer */ 1546 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1547 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1548 printf("%s: request to free a buffer (%p) not managed by us\n", 1549 sc->sc_dev.dv_xname, buf); 1550 return; 1551 } 1552 jbuf = &sc->rxq.jbuf[i]; 1553 1554 /* ..and put it back in the free list */ 1555 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1556 1557 if (m != NULL) 1558 pool_cache_put(mb_cache, m); 1559 } 1560 1561 int 1562 nfe_jpool_alloc(struct nfe_softc *sc) 1563 { 1564 struct nfe_rx_ring *ring = &sc->rxq; 1565 struct nfe_jbuf *jbuf; 1566 bus_addr_t physaddr; 1567 char *buf; 1568 int i, nsegs, error; 1569 1570 /* 1571 * Allocate a big chunk of DMA'able memory. 1572 */ 1573 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1574 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1575 if (error != 0) { 1576 printf("%s: could not create jumbo DMA map\n", 1577 sc->sc_dev.dv_xname); 1578 goto fail; 1579 } 1580 1581 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1582 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1583 if (error != 0) { 1584 printf("%s could not allocate jumbo DMA memory\n", 1585 sc->sc_dev.dv_xname); 1586 goto fail; 1587 } 1588 1589 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1590 &ring->jpool, BUS_DMA_NOWAIT); 1591 if (error != 0) { 1592 printf("%s: could not map jumbo DMA memory\n", 1593 sc->sc_dev.dv_xname); 1594 goto fail; 1595 } 1596 1597 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1598 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1599 if (error != 0) { 1600 printf("%s: could not load jumbo DMA map\n", 1601 sc->sc_dev.dv_xname); 1602 goto fail; 1603 } 1604 1605 /* ..and split it into 9KB chunks */ 1606 SLIST_INIT(&ring->jfreelist); 1607 1608 buf = ring->jpool; 1609 physaddr = ring->jmap->dm_segs[0].ds_addr; 1610 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1611 jbuf = &ring->jbuf[i]; 1612 1613 jbuf->buf = buf; 1614 jbuf->physaddr = physaddr; 1615 1616 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1617 1618 buf += NFE_JBYTES; 1619 physaddr += NFE_JBYTES; 1620 } 1621 1622 return 0; 1623 1624 fail: nfe_jpool_free(sc); 1625 return error; 1626 } 1627 1628 void 1629 nfe_jpool_free(struct nfe_softc *sc) 1630 { 1631 struct nfe_rx_ring *ring = &sc->rxq; 1632 1633 if (ring->jmap != NULL) { 1634 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1635 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1636 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1637 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1638 } 1639 if (ring->jpool != NULL) { 1640 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1641 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1642 } 1643 } 1644 1645 int 1646 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1647 { 1648 int i, nsegs, error; 1649 void **desc; 1650 int descsize; 1651 1652 if (sc->sc_flags & NFE_40BIT_ADDR) { 1653 desc = (void **)&ring->desc64; 1654 descsize = sizeof (struct nfe_desc64); 1655 } else { 1656 desc = (void **)&ring->desc32; 1657 descsize = sizeof (struct nfe_desc32); 1658 } 1659 1660 ring->queued = 0; 1661 ring->cur = ring->next = 0; 1662 1663 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1664 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1665 1666 if (error != 0) { 1667 printf("%s: could not create desc DMA map\n", 1668 sc->sc_dev.dv_xname); 1669 goto fail; 1670 } 1671 1672 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1673 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1674 if (error != 0) { 1675 printf("%s: could not allocate DMA memory\n", 1676 sc->sc_dev.dv_xname); 1677 goto fail; 1678 } 1679 1680 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1681 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1682 if (error != 0) { 1683 printf("%s: could not map desc DMA memory\n", 1684 sc->sc_dev.dv_xname); 1685 goto fail; 1686 } 1687 1688 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1689 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1690 if (error != 0) { 1691 printf("%s: could not load desc DMA map\n", 1692 sc->sc_dev.dv_xname); 1693 goto fail; 1694 } 1695 1696 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1697 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1698 1699 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1700 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1701 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1702 &ring->data[i].map); 1703 if (error != 0) { 1704 printf("%s: could not create DMA map\n", 1705 sc->sc_dev.dv_xname); 1706 goto fail; 1707 } 1708 } 1709 1710 return 0; 1711 1712 fail: nfe_free_tx_ring(sc, ring); 1713 return error; 1714 } 1715 1716 void 1717 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1718 { 1719 struct nfe_tx_data *data; 1720 int i; 1721 1722 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1723 if (sc->sc_flags & NFE_40BIT_ADDR) 1724 ring->desc64[i].flags = 0; 1725 else 1726 ring->desc32[i].flags = 0; 1727 1728 data = &ring->data[i]; 1729 1730 if (data->m != NULL) { 1731 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1732 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1733 bus_dmamap_unload(sc->sc_dmat, data->active); 1734 m_freem(data->m); 1735 data->m = NULL; 1736 } 1737 } 1738 1739 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1740 BUS_DMASYNC_PREWRITE); 1741 1742 ring->queued = 0; 1743 ring->cur = ring->next = 0; 1744 } 1745 1746 void 1747 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1748 { 1749 struct nfe_tx_data *data; 1750 void *desc; 1751 int i, descsize; 1752 1753 if (sc->sc_flags & NFE_40BIT_ADDR) { 1754 desc = ring->desc64; 1755 descsize = sizeof (struct nfe_desc64); 1756 } else { 1757 desc = ring->desc32; 1758 descsize = sizeof (struct nfe_desc32); 1759 } 1760 1761 if (desc != NULL) { 1762 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1763 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1764 bus_dmamap_unload(sc->sc_dmat, ring->map); 1765 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1766 NFE_TX_RING_COUNT * descsize); 1767 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1768 } 1769 1770 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1771 data = &ring->data[i]; 1772 1773 if (data->m != NULL) { 1774 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1775 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1776 bus_dmamap_unload(sc->sc_dmat, data->active); 1777 m_freem(data->m); 1778 } 1779 } 1780 1781 /* ..and now actually destroy the DMA mappings */ 1782 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1783 data = &ring->data[i]; 1784 if (data->map == NULL) 1785 continue; 1786 bus_dmamap_destroy(sc->sc_dmat, data->map); 1787 } 1788 } 1789 1790 int 1791 nfe_ifmedia_upd(struct ifnet *ifp) 1792 { 1793 struct nfe_softc *sc = ifp->if_softc; 1794 struct mii_data *mii = &sc->sc_mii; 1795 struct mii_softc *miisc; 1796 1797 if (mii->mii_instance != 0) { 1798 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1799 mii_phy_reset(miisc); 1800 } 1801 return mii_mediachg(mii); 1802 } 1803 1804 void 1805 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1806 { 1807 struct nfe_softc *sc = ifp->if_softc; 1808 struct mii_data *mii = &sc->sc_mii; 1809 1810 mii_pollstat(mii); 1811 ifmr->ifm_status = mii->mii_media_status; 1812 ifmr->ifm_active = mii->mii_media_active; 1813 } 1814 1815 void 1816 nfe_setmulti(struct nfe_softc *sc) 1817 { 1818 struct ethercom *ec = &sc->sc_ethercom; 1819 struct ifnet *ifp = &ec->ec_if; 1820 struct ether_multi *enm; 1821 struct ether_multistep step; 1822 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1823 uint32_t filter = NFE_RXFILTER_MAGIC; 1824 int i; 1825 1826 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1827 bzero(addr, ETHER_ADDR_LEN); 1828 bzero(mask, ETHER_ADDR_LEN); 1829 goto done; 1830 } 1831 1832 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1833 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1834 1835 ETHER_FIRST_MULTI(step, ec, enm); 1836 while (enm != NULL) { 1837 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1838 ifp->if_flags |= IFF_ALLMULTI; 1839 bzero(addr, ETHER_ADDR_LEN); 1840 bzero(mask, ETHER_ADDR_LEN); 1841 goto done; 1842 } 1843 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1844 addr[i] &= enm->enm_addrlo[i]; 1845 mask[i] &= ~enm->enm_addrlo[i]; 1846 } 1847 ETHER_NEXT_MULTI(step, enm); 1848 } 1849 for (i = 0; i < ETHER_ADDR_LEN; i++) 1850 mask[i] |= addr[i]; 1851 1852 done: 1853 addr[0] |= 0x01; /* make sure multicast bit is set */ 1854 1855 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1856 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1857 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1858 addr[5] << 8 | addr[4]); 1859 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1860 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1861 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1862 mask[5] << 8 | mask[4]); 1863 1864 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1865 NFE_WRITE(sc, NFE_RXFILTER, filter); 1866 } 1867 1868 void 1869 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1870 { 1871 uint32_t tmp; 1872 1873 if ((sc->sc_flags & NFE_CORRECT_MACADDR) == 0) { 1874 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1875 addr[0] = (tmp >> 8) & 0xff; 1876 addr[1] = (tmp & 0xff); 1877 1878 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1879 addr[2] = (tmp >> 24) & 0xff; 1880 addr[3] = (tmp >> 16) & 0xff; 1881 addr[4] = (tmp >> 8) & 0xff; 1882 addr[5] = (tmp & 0xff); 1883 } else { 1884 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1885 addr[5] = (tmp >> 8) & 0xff; 1886 addr[4] = (tmp & 0xff); 1887 1888 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1889 addr[3] = (tmp >> 24) & 0xff; 1890 addr[2] = (tmp >> 16) & 0xff; 1891 addr[1] = (tmp >> 8) & 0xff; 1892 addr[0] = (tmp & 0xff); 1893 } 1894 } 1895 1896 void 1897 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1898 { 1899 NFE_WRITE(sc, NFE_MACADDR_LO, 1900 addr[5] << 8 | addr[4]); 1901 NFE_WRITE(sc, NFE_MACADDR_HI, 1902 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1903 } 1904 1905 void 1906 nfe_tick(void *arg) 1907 { 1908 struct nfe_softc *sc = arg; 1909 int s; 1910 1911 s = splnet(); 1912 mii_tick(&sc->sc_mii); 1913 splx(s); 1914 1915 callout_schedule(&sc->sc_tick_ch, hz); 1916 } 1917
Indexes created Tue Sep 30 07:10:03 GMT 2025