if_nfe.c revision 1.26
1 /* $NetBSD: if_nfe.c,v 1.26 2008/01/19 22:10:18 dyoung Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.52 2006/03/02 09:04:00 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.26 2008/01/19 22:10:18 dyoung Exp $"); 25 26 #include "opt_inet.h" 27 #include "bpfilter.h" 28 #include "vlan.h" 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/types.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/queue.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/socket.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/pci/if_nfereg.h> 74 #include <dev/pci/if_nfevar.h> 75 76 int nfe_match(struct device *, struct cfdata *, void *); 77 void nfe_attach(struct device *, struct device *, void *); 78 void nfe_power(int, void *); 79 void nfe_miibus_statchg(struct device *); 80 int nfe_miibus_readreg(struct device *, int, int); 81 void nfe_miibus_writereg(struct device *, int, int, int); 82 int nfe_intr(void *); 83 int nfe_ioctl(struct ifnet *, u_long, void *); 84 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 85 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 86 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 87 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 88 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 89 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 90 void nfe_rxeof(struct nfe_softc *); 91 void nfe_txeof(struct nfe_softc *); 92 int nfe_encap(struct nfe_softc *, struct mbuf *); 93 void nfe_start(struct ifnet *); 94 void nfe_watchdog(struct ifnet *); 95 int nfe_init(struct ifnet *); 96 void nfe_stop(struct ifnet *, int); 97 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 98 void nfe_jfree(struct mbuf *, void *, size_t, void *); 99 int nfe_jpool_alloc(struct nfe_softc *); 100 void nfe_jpool_free(struct nfe_softc *); 101 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 102 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 105 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 void nfe_setmulti(struct nfe_softc *); 108 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 109 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 110 void nfe_tick(void *); 111 112 CFATTACH_DECL(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, NULL, NULL); 113 114 /*#define NFE_NO_JUMBO*/ 115 116 #ifdef NFE_DEBUG 117 int nfedebug = 0; 118 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 119 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 120 #else 121 #define DPRINTF(x) 122 #define DPRINTFN(n,x) 123 #endif 124 125 /* deal with naming differences */ 126 127 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 128 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 129 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 130 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 132 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 133 134 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 135 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 136 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 137 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 138 139 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 140 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 141 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 142 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 143 144 #ifdef _LP64 145 #define __LP64__ 1 146 #endif 147 148 const struct nfe_product { 149 pci_vendor_id_t vendor; 150 pci_product_id_t product; 151 } nfe_devices[] = { 152 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 153 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 155 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 } 183 }; 184 185 int 186 nfe_match(struct device *dev, struct cfdata *match, void *aux) 187 { 188 struct pci_attach_args *pa = aux; 189 const struct nfe_product *np; 190 int i; 191 192 for (i = 0; i < sizeof(nfe_devices) / sizeof(nfe_devices[0]); i++) { 193 np = &nfe_devices[i]; 194 if (PCI_VENDOR(pa->pa_id) == np->vendor && 195 PCI_PRODUCT(pa->pa_id) == np->product) 196 return 1; 197 } 198 return 0; 199 } 200 201 void 202 nfe_attach(struct device *parent, struct device *self, void *aux) 203 { 204 struct nfe_softc *sc = (struct nfe_softc *)self; 205 struct pci_attach_args *pa = aux; 206 pci_chipset_tag_t pc = pa->pa_pc; 207 pci_intr_handle_t ih; 208 const char *intrstr; 209 struct ifnet *ifp; 210 bus_size_t memsize; 211 pcireg_t memtype; 212 char devinfo[256]; 213 214 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 215 aprint_normal(": %s (rev. 0x%02x)\n", 216 devinfo, PCI_REVISION(pa->pa_class)); 217 218 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 219 switch (memtype) { 220 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 221 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 222 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 223 &sc->sc_memh, NULL, &memsize) == 0) 224 break; 225 /* FALLTHROUGH */ 226 default: 227 printf("%s: could not map mem space\n", sc->sc_dev.dv_xname); 228 return; 229 } 230 231 if (pci_intr_map(pa, &ih) != 0) { 232 printf("%s: could not map interrupt\n", sc->sc_dev.dv_xname); 233 return; 234 } 235 236 intrstr = pci_intr_string(pc, ih); 237 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 238 if (sc->sc_ih == NULL) { 239 printf("%s: could not establish interrupt", 240 sc->sc_dev.dv_xname); 241 if (intrstr != NULL) 242 printf(" at %s", intrstr); 243 printf("\n"); 244 return; 245 } 246 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 247 248 sc->sc_dmat = pa->pa_dmat; 249 250 /* Check for reversed ethernet address */ 251 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 252 sc->sc_flags |= NFE_CORRECT_MACADDR; 253 254 nfe_get_macaddr(sc, sc->sc_enaddr); 255 printf("%s: Ethernet address %s\n", 256 sc->sc_dev.dv_xname, ether_sprintf(sc->sc_enaddr)); 257 258 sc->sc_flags = 0; 259 260 switch (PCI_PRODUCT(pa->pa_id)) { 261 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 262 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 263 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 264 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 265 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 266 break; 267 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 268 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 269 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 270 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 271 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 272 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 273 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 274 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 275 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 276 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 277 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 278 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 279 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 280 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 281 sc->sc_flags |= NFE_40BIT_ADDR; 282 break; 283 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 284 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 285 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 286 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 287 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 288 break; 289 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 290 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 291 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 292 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 293 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 294 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 295 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 296 NFE_HW_VLAN; 297 break; 298 } 299 300 #ifndef NFE_NO_JUMBO 301 /* enable jumbo frames for adapters that support it */ 302 if (sc->sc_flags & NFE_JUMBO_SUP) 303 sc->sc_flags |= NFE_USE_JUMBO; 304 #endif 305 306 /* 307 * Allocate Tx and Rx rings. 308 */ 309 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 310 printf("%s: could not allocate Tx ring\n", 311 sc->sc_dev.dv_xname); 312 return; 313 } 314 315 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 316 printf("%s: could not allocate Rx ring\n", 317 sc->sc_dev.dv_xname); 318 nfe_free_tx_ring(sc, &sc->txq); 319 return; 320 } 321 322 ifp = &sc->sc_ethercom.ec_if; 323 ifp->if_softc = sc; 324 ifp->if_mtu = ETHERMTU; 325 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 326 ifp->if_ioctl = nfe_ioctl; 327 ifp->if_start = nfe_start; 328 ifp->if_stop = nfe_stop; 329 ifp->if_watchdog = nfe_watchdog; 330 ifp->if_init = nfe_init; 331 ifp->if_baudrate = IF_Gbps(1); 332 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 333 IFQ_SET_READY(&ifp->if_snd); 334 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 335 336 #if NVLAN > 0 337 if (sc->sc_flags & NFE_HW_VLAN) 338 sc->sc_ethercom.ec_capabilities |= 339 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 340 #endif 341 if (sc->sc_flags & NFE_HW_CSUM) { 342 ifp->if_capabilities |= 343 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 344 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 345 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 346 } 347 348 sc->sc_mii.mii_ifp = ifp; 349 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 350 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 351 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 352 353 sc->sc_ethercom.ec_mii = &sc->sc_mii; 354 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 355 ether_mediastatus); 356 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 357 MII_OFFSET_ANY, 0); 358 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 359 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 360 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 361 0, NULL); 362 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 363 } else 364 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 365 366 if_attach(ifp); 367 ether_ifattach(ifp, sc->sc_enaddr); 368 369 callout_init(&sc->sc_tick_ch, 0); 370 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 371 372 if (!pmf_device_register(self, NULL, NULL)) 373 aprint_error_dev(self, "couldn't establish power handler\n"); 374 else 375 pmf_class_network_register(self, ifp); 376 } 377 378 void 379 nfe_miibus_statchg(struct device *dev) 380 { 381 struct nfe_softc *sc = (struct nfe_softc *)dev; 382 struct mii_data *mii = &sc->sc_mii; 383 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 384 385 phy = NFE_READ(sc, NFE_PHY_IFACE); 386 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 387 388 seed = NFE_READ(sc, NFE_RNDSEED); 389 seed &= ~NFE_SEED_MASK; 390 391 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 392 phy |= NFE_PHY_HDX; /* half-duplex */ 393 misc |= NFE_MISC1_HDX; 394 } 395 396 switch (IFM_SUBTYPE(mii->mii_media_active)) { 397 case IFM_1000_T: /* full-duplex only */ 398 link |= NFE_MEDIA_1000T; 399 seed |= NFE_SEED_1000T; 400 phy |= NFE_PHY_1000T; 401 break; 402 case IFM_100_TX: 403 link |= NFE_MEDIA_100TX; 404 seed |= NFE_SEED_100TX; 405 phy |= NFE_PHY_100TX; 406 break; 407 case IFM_10_T: 408 link |= NFE_MEDIA_10T; 409 seed |= NFE_SEED_10T; 410 break; 411 } 412 413 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 414 415 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 416 NFE_WRITE(sc, NFE_MISC1, misc); 417 NFE_WRITE(sc, NFE_LINKSPEED, link); 418 } 419 420 int 421 nfe_miibus_readreg(struct device *dev, int phy, int reg) 422 { 423 struct nfe_softc *sc = (struct nfe_softc *)dev; 424 uint32_t val; 425 int ntries; 426 427 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 428 429 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 430 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 431 DELAY(100); 432 } 433 434 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 435 436 for (ntries = 0; ntries < 1000; ntries++) { 437 DELAY(100); 438 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 439 break; 440 } 441 if (ntries == 1000) { 442 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 443 sc->sc_dev.dv_xname)); 444 return 0; 445 } 446 447 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 448 DPRINTFN(2, ("%s: could not read PHY\n", 449 sc->sc_dev.dv_xname)); 450 return 0; 451 } 452 453 val = NFE_READ(sc, NFE_PHY_DATA); 454 if (val != 0xffffffff && val != 0) 455 sc->mii_phyaddr = phy; 456 457 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 458 sc->sc_dev.dv_xname, phy, reg, val)); 459 460 return val; 461 } 462 463 void 464 nfe_miibus_writereg(struct device *dev, int phy, int reg, int val) 465 { 466 struct nfe_softc *sc = (struct nfe_softc *)dev; 467 uint32_t ctl; 468 int ntries; 469 470 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 471 472 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 473 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 474 DELAY(100); 475 } 476 477 NFE_WRITE(sc, NFE_PHY_DATA, val); 478 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 479 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 480 481 for (ntries = 0; ntries < 1000; ntries++) { 482 DELAY(100); 483 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 484 break; 485 } 486 #ifdef NFE_DEBUG 487 if (nfedebug >= 2 && ntries == 1000) 488 printf("could not write to PHY\n"); 489 #endif 490 } 491 492 int 493 nfe_intr(void *arg) 494 { 495 struct nfe_softc *sc = arg; 496 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 497 uint32_t r; 498 int handled; 499 500 if ((ifp->if_flags & IFF_UP) == 0) 501 return 0; 502 503 handled = 0; 504 505 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 506 507 for (;;) { 508 r = NFE_READ(sc, NFE_IRQ_STATUS); 509 if ((r & NFE_IRQ_WANTED) == 0) 510 break; 511 512 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 513 handled = 1; 514 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 515 516 if ((r & (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX)) 517 != 0) { 518 /* check Rx ring */ 519 nfe_rxeof(sc); 520 } 521 522 if ((r & (NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE)) 523 != 0) { 524 /* check Tx ring */ 525 nfe_txeof(sc); 526 } 527 528 if ((r & NFE_IRQ_LINK) != 0) { 529 NFE_READ(sc, NFE_PHY_STATUS); 530 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 531 DPRINTF(("%s: link state changed\n", 532 sc->sc_dev.dv_xname)); 533 } 534 } 535 536 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 537 538 if (handled && !IF_IS_EMPTY(&ifp->if_snd)) 539 nfe_start(ifp); 540 541 return handled; 542 } 543 544 int 545 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 546 { 547 struct nfe_softc *sc = ifp->if_softc; 548 struct ifreq *ifr = (struct ifreq *)data; 549 struct ifaddr *ifa = (struct ifaddr *)data; 550 int s, error = 0; 551 552 s = splnet(); 553 554 switch (cmd) { 555 case SIOCSIFADDR: 556 ifp->if_flags |= IFF_UP; 557 nfe_init(ifp); 558 switch (ifa->ifa_addr->sa_family) { 559 #ifdef INET 560 case AF_INET: 561 arp_ifinit(ifp, ifa); 562 break; 563 #endif 564 default: 565 break; 566 } 567 break; 568 case SIOCSIFMTU: 569 if (ifr->ifr_mtu < ETHERMIN || 570 ((sc->sc_flags & NFE_USE_JUMBO) && 571 ifr->ifr_mtu > ETHERMTU_JUMBO) || 572 (!(sc->sc_flags & NFE_USE_JUMBO) && 573 ifr->ifr_mtu > ETHERMTU)) 574 error = EINVAL; 575 else if (ifp->if_mtu != ifr->ifr_mtu) 576 ifp->if_mtu = ifr->ifr_mtu; 577 break; 578 case SIOCSIFFLAGS: 579 if (ifp->if_flags & IFF_UP) { 580 /* 581 * If only the PROMISC or ALLMULTI flag changes, then 582 * don't do a full re-init of the chip, just update 583 * the Rx filter. 584 */ 585 if ((ifp->if_flags & IFF_RUNNING) && 586 ((ifp->if_flags ^ sc->sc_if_flags) & 587 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 588 nfe_setmulti(sc); 589 else 590 nfe_init(ifp); 591 } else { 592 if (ifp->if_flags & IFF_RUNNING) 593 nfe_stop(ifp, 1); 594 } 595 sc->sc_if_flags = ifp->if_flags; 596 break; 597 default: 598 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 599 if (ifp->if_flags & IFF_RUNNING) 600 nfe_setmulti(sc); 601 error = 0; 602 } 603 break; 604 } 605 606 splx(s); 607 608 return error; 609 } 610 611 void 612 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 613 { 614 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 615 (char *)desc32 - (char *)sc->txq.desc32, 616 sizeof (struct nfe_desc32), ops); 617 } 618 619 void 620 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 621 { 622 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 623 (char *)desc64 - (char *)sc->txq.desc64, 624 sizeof (struct nfe_desc64), ops); 625 } 626 627 void 628 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 629 { 630 if (end > start) { 631 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 632 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 633 (char *)&sc->txq.desc32[end] - 634 (char *)&sc->txq.desc32[start], ops); 635 return; 636 } 637 /* sync from 'start' to end of ring */ 638 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 639 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 640 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 641 (char *)&sc->txq.desc32[start], ops); 642 643 /* sync from start of ring to 'end' */ 644 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 645 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 646 } 647 648 void 649 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 650 { 651 if (end > start) { 652 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 653 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 654 (char *)&sc->txq.desc64[end] - 655 (char *)&sc->txq.desc64[start], ops); 656 return; 657 } 658 /* sync from 'start' to end of ring */ 659 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 660 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 661 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 662 (char *)&sc->txq.desc64[start], ops); 663 664 /* sync from start of ring to 'end' */ 665 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 666 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 667 } 668 669 void 670 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 671 { 672 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 673 (char *)desc32 - (char *)sc->rxq.desc32, 674 sizeof (struct nfe_desc32), ops); 675 } 676 677 void 678 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 679 { 680 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 681 (char *)desc64 - (char *)sc->rxq.desc64, 682 sizeof (struct nfe_desc64), ops); 683 } 684 685 void 686 nfe_rxeof(struct nfe_softc *sc) 687 { 688 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 689 struct nfe_desc32 *desc32; 690 struct nfe_desc64 *desc64; 691 struct nfe_rx_data *data; 692 struct nfe_jbuf *jbuf; 693 struct mbuf *m, *mnew; 694 bus_addr_t physaddr; 695 uint16_t flags; 696 int error, len, i; 697 698 desc32 = NULL; 699 desc64 = NULL; 700 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 701 data = &sc->rxq.data[i]; 702 703 if (sc->sc_flags & NFE_40BIT_ADDR) { 704 desc64 = &sc->rxq.desc64[i]; 705 nfe_rxdesc64_sync(sc, desc64, 706 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 707 708 flags = le16toh(desc64->flags); 709 len = le16toh(desc64->length) & 0x3fff; 710 } else { 711 desc32 = &sc->rxq.desc32[i]; 712 nfe_rxdesc32_sync(sc, desc32, 713 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 714 715 flags = le16toh(desc32->flags); 716 len = le16toh(desc32->length) & 0x3fff; 717 } 718 719 if ((flags & NFE_RX_READY) != 0) 720 break; 721 722 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 723 if ((flags & NFE_RX_VALID_V1) == 0) 724 goto skip; 725 726 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 727 flags &= ~NFE_RX_ERROR; 728 len--; /* fix buffer length */ 729 } 730 } else { 731 if ((flags & NFE_RX_VALID_V2) == 0) 732 goto skip; 733 734 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 735 flags &= ~NFE_RX_ERROR; 736 len--; /* fix buffer length */ 737 } 738 } 739 740 if (flags & NFE_RX_ERROR) { 741 ifp->if_ierrors++; 742 goto skip; 743 } 744 745 /* 746 * Try to allocate a new mbuf for this ring element and load 747 * it before processing the current mbuf. If the ring element 748 * cannot be loaded, drop the received packet and reuse the 749 * old mbuf. In the unlikely case that the old mbuf can't be 750 * reloaded either, explicitly panic. 751 */ 752 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 753 if (mnew == NULL) { 754 ifp->if_ierrors++; 755 goto skip; 756 } 757 758 if (sc->sc_flags & NFE_USE_JUMBO) { 759 physaddr = 760 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 761 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 762 if (len > MCLBYTES) { 763 m_freem(mnew); 764 ifp->if_ierrors++; 765 goto skip1; 766 } 767 MCLGET(mnew, M_DONTWAIT); 768 if ((mnew->m_flags & M_EXT) == 0) { 769 m_freem(mnew); 770 ifp->if_ierrors++; 771 goto skip1; 772 } 773 774 memcpy(mtod(mnew, void *), 775 mtod(data->m, const void *), len); 776 m = mnew; 777 goto mbufcopied; 778 } else { 779 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 780 781 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 782 mtod(data->m, char *) - (char *)sc->rxq.jpool, 783 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 784 785 physaddr = jbuf->physaddr; 786 } 787 } else { 788 MCLGET(mnew, M_DONTWAIT); 789 if ((mnew->m_flags & M_EXT) == 0) { 790 m_freem(mnew); 791 ifp->if_ierrors++; 792 goto skip; 793 } 794 795 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 796 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 797 bus_dmamap_unload(sc->sc_dmat, data->map); 798 799 error = bus_dmamap_load(sc->sc_dmat, data->map, 800 mtod(mnew, void *), MCLBYTES, NULL, 801 BUS_DMA_READ | BUS_DMA_NOWAIT); 802 if (error != 0) { 803 m_freem(mnew); 804 805 /* try to reload the old mbuf */ 806 error = bus_dmamap_load(sc->sc_dmat, data->map, 807 mtod(data->m, void *), MCLBYTES, NULL, 808 BUS_DMA_READ | BUS_DMA_NOWAIT); 809 if (error != 0) { 810 /* very unlikely that it will fail.. */ 811 panic("%s: could not load old rx mbuf", 812 sc->sc_dev.dv_xname); 813 } 814 ifp->if_ierrors++; 815 goto skip; 816 } 817 physaddr = data->map->dm_segs[0].ds_addr; 818 } 819 820 /* 821 * New mbuf successfully loaded, update Rx ring and continue 822 * processing. 823 */ 824 m = data->m; 825 data->m = mnew; 826 827 mbufcopied: 828 /* finalize mbuf */ 829 m->m_pkthdr.len = m->m_len = len; 830 m->m_pkthdr.rcvif = ifp; 831 832 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 833 /* 834 * XXX 835 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 836 */ 837 if (flags & NFE_RX_IP_CSUMOK) { 838 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 839 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 840 sc->sc_dev.dv_xname)); 841 } 842 /* 843 * XXX 844 * no way to check M_CSUM_TCP_UDP_BAD or 845 * other protocols? 846 */ 847 if (flags & NFE_RX_UDP_CSUMOK) { 848 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 849 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 850 sc->sc_dev.dv_xname)); 851 } else if (flags & NFE_RX_TCP_CSUMOK) { 852 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 853 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 854 sc->sc_dev.dv_xname)); 855 } 856 } 857 858 #if NBPFILTER > 0 859 if (ifp->if_bpf) 860 bpf_mtap(ifp->if_bpf, m); 861 #endif 862 ifp->if_ipackets++; 863 (*ifp->if_input)(ifp, m); 864 865 skip1: 866 /* update mapping address in h/w descriptor */ 867 if (sc->sc_flags & NFE_40BIT_ADDR) { 868 #if defined(__LP64__) 869 desc64->physaddr[0] = htole32(physaddr >> 32); 870 #endif 871 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 872 } else { 873 desc32->physaddr = htole32(physaddr); 874 } 875 876 skip: 877 if (sc->sc_flags & NFE_40BIT_ADDR) { 878 desc64->length = htole16(sc->rxq.bufsz); 879 desc64->flags = htole16(NFE_RX_READY); 880 881 nfe_rxdesc64_sync(sc, desc64, 882 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 883 } else { 884 desc32->length = htole16(sc->rxq.bufsz); 885 desc32->flags = htole16(NFE_RX_READY); 886 887 nfe_rxdesc32_sync(sc, desc32, 888 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 889 } 890 } 891 /* update current RX pointer */ 892 sc->rxq.cur = i; 893 } 894 895 void 896 nfe_txeof(struct nfe_softc *sc) 897 { 898 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 899 struct nfe_desc32 *desc32; 900 struct nfe_desc64 *desc64; 901 struct nfe_tx_data *data = NULL; 902 int i; 903 uint16_t flags; 904 905 for (i = sc->txq.next; 906 sc->txq.queued > 0; 907 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 908 if (sc->sc_flags & NFE_40BIT_ADDR) { 909 desc64 = &sc->txq.desc64[i]; 910 nfe_txdesc64_sync(sc, desc64, 911 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 912 913 flags = le16toh(desc64->flags); 914 } else { 915 desc32 = &sc->txq.desc32[i]; 916 nfe_txdesc32_sync(sc, desc32, 917 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 918 919 flags = le16toh(desc32->flags); 920 } 921 922 if ((flags & NFE_TX_VALID) != 0) 923 break; 924 925 data = &sc->txq.data[i]; 926 927 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 928 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 929 data->m == NULL) 930 continue; 931 932 if ((flags & NFE_TX_ERROR_V1) != 0) { 933 printf("%s: tx v1 error 0x%04x\n", 934 sc->sc_dev.dv_xname, flags); 935 ifp->if_oerrors++; 936 } else 937 ifp->if_opackets++; 938 } else { 939 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 940 data->m == NULL) 941 continue; 942 943 if ((flags & NFE_TX_ERROR_V2) != 0) { 944 printf("%s: tx v2 error 0x%04x\n", 945 sc->sc_dev.dv_xname, flags); 946 ifp->if_oerrors++; 947 } else 948 ifp->if_opackets++; 949 } 950 951 if (data->m == NULL) { /* should not get there */ 952 printf("%s: last fragment bit w/o associated mbuf!\n", 953 sc->sc_dev.dv_xname); 954 continue; 955 } 956 957 /* last fragment of the mbuf chain transmitted */ 958 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 959 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 960 bus_dmamap_unload(sc->sc_dmat, data->active); 961 m_freem(data->m); 962 data->m = NULL; 963 } 964 965 sc->txq.next = i; 966 967 if (sc->txq.queued < NFE_TX_RING_COUNT) { 968 /* at least one slot freed */ 969 ifp->if_flags &= ~IFF_OACTIVE; 970 } 971 972 if (sc->txq.queued == 0) { 973 /* all queued packets are sent */ 974 ifp->if_timer = 0; 975 } 976 } 977 978 int 979 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 980 { 981 struct nfe_desc32 *desc32; 982 struct nfe_desc64 *desc64; 983 struct nfe_tx_data *data; 984 bus_dmamap_t map; 985 uint16_t flags, csumflags; 986 #if NVLAN > 0 987 struct m_tag *mtag; 988 uint32_t vtag = 0; 989 #endif 990 int error, i, first; 991 992 desc32 = NULL; 993 desc64 = NULL; 994 data = NULL; 995 996 flags = 0; 997 csumflags = 0; 998 first = sc->txq.cur; 999 1000 map = sc->txq.data[first].map; 1001 1002 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1003 if (error != 0) { 1004 printf("%s: could not map mbuf (error %d)\n", 1005 sc->sc_dev.dv_xname, error); 1006 return error; 1007 } 1008 1009 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1010 bus_dmamap_unload(sc->sc_dmat, map); 1011 return ENOBUFS; 1012 } 1013 1014 #if NVLAN > 0 1015 /* setup h/w VLAN tagging */ 1016 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1017 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1018 #endif 1019 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1020 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1021 csumflags |= NFE_TX_IP_CSUM; 1022 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1023 csumflags |= NFE_TX_TCP_UDP_CSUM; 1024 } 1025 1026 for (i = 0; i < map->dm_nsegs; i++) { 1027 data = &sc->txq.data[sc->txq.cur]; 1028 1029 if (sc->sc_flags & NFE_40BIT_ADDR) { 1030 desc64 = &sc->txq.desc64[sc->txq.cur]; 1031 #if defined(__LP64__) 1032 desc64->physaddr[0] = 1033 htole32(map->dm_segs[i].ds_addr >> 32); 1034 #endif 1035 desc64->physaddr[1] = 1036 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1037 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1038 desc64->flags = htole16(flags); 1039 desc64->vtag = 0; 1040 } else { 1041 desc32 = &sc->txq.desc32[sc->txq.cur]; 1042 1043 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1044 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1045 desc32->flags = htole16(flags); 1046 } 1047 1048 /* 1049 * Setting of the valid bit in the first descriptor is 1050 * deferred until the whole chain is fully setup. 1051 */ 1052 flags |= NFE_TX_VALID; 1053 1054 sc->txq.queued++; 1055 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1056 } 1057 1058 /* the whole mbuf chain has been setup */ 1059 if (sc->sc_flags & NFE_40BIT_ADDR) { 1060 /* fix last descriptor */ 1061 flags |= NFE_TX_LASTFRAG_V2; 1062 desc64->flags = htole16(flags); 1063 1064 /* Checksum flags and vtag belong to the first fragment only. */ 1065 #if NVLAN > 0 1066 sc->txq.desc64[first].vtag = htole32(vtag); 1067 #endif 1068 sc->txq.desc64[first].flags |= htole16(csumflags); 1069 1070 /* finally, set the valid bit in the first descriptor */ 1071 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1072 } else { 1073 /* fix last descriptor */ 1074 if (sc->sc_flags & NFE_JUMBO_SUP) 1075 flags |= NFE_TX_LASTFRAG_V2; 1076 else 1077 flags |= NFE_TX_LASTFRAG_V1; 1078 desc32->flags = htole16(flags); 1079 1080 /* Checksum flags belong to the first fragment only. */ 1081 sc->txq.desc32[first].flags |= htole16(csumflags); 1082 1083 /* finally, set the valid bit in the first descriptor */ 1084 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1085 } 1086 1087 data->m = m0; 1088 data->active = map; 1089 1090 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1091 BUS_DMASYNC_PREWRITE); 1092 1093 return 0; 1094 } 1095 1096 void 1097 nfe_start(struct ifnet *ifp) 1098 { 1099 struct nfe_softc *sc = ifp->if_softc; 1100 int old = sc->txq.queued; 1101 struct mbuf *m0; 1102 1103 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 1104 return; 1105 1106 for (;;) { 1107 IFQ_POLL(&ifp->if_snd, m0); 1108 if (m0 == NULL) 1109 break; 1110 1111 if (nfe_encap(sc, m0) != 0) { 1112 ifp->if_flags |= IFF_OACTIVE; 1113 break; 1114 } 1115 1116 /* packet put in h/w queue, remove from s/w queue */ 1117 IFQ_DEQUEUE(&ifp->if_snd, m0); 1118 1119 #if NBPFILTER > 0 1120 if (ifp->if_bpf != NULL) 1121 bpf_mtap(ifp->if_bpf, m0); 1122 #endif 1123 } 1124 1125 if (sc->txq.queued != old) { 1126 /* packets are queued */ 1127 if (sc->sc_flags & NFE_40BIT_ADDR) 1128 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1129 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1130 else 1131 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1132 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1133 /* kick Tx */ 1134 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1135 1136 /* 1137 * Set a timeout in case the chip goes out to lunch. 1138 */ 1139 ifp->if_timer = 5; 1140 } 1141 } 1142 1143 void 1144 nfe_watchdog(struct ifnet *ifp) 1145 { 1146 struct nfe_softc *sc = ifp->if_softc; 1147 1148 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1149 1150 ifp->if_flags &= ~IFF_RUNNING; 1151 nfe_init(ifp); 1152 1153 ifp->if_oerrors++; 1154 } 1155 1156 int 1157 nfe_init(struct ifnet *ifp) 1158 { 1159 struct nfe_softc *sc = ifp->if_softc; 1160 uint32_t tmp; 1161 int rc = 0, s; 1162 1163 if (ifp->if_flags & IFF_RUNNING) 1164 return 0; 1165 1166 nfe_stop(ifp, 0); 1167 1168 NFE_WRITE(sc, NFE_TX_UNK, 0); 1169 NFE_WRITE(sc, NFE_STATUS, 0); 1170 1171 sc->rxtxctl = NFE_RXTX_BIT2; 1172 if (sc->sc_flags & NFE_40BIT_ADDR) 1173 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1174 else if (sc->sc_flags & NFE_JUMBO_SUP) 1175 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1176 if (sc->sc_flags & NFE_HW_CSUM) 1177 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1178 #if NVLAN > 0 1179 /* 1180 * Although the adapter is capable of stripping VLAN tags from received 1181 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1182 * purpose. This will be done in software by our network stack. 1183 */ 1184 if (sc->sc_flags & NFE_HW_VLAN) 1185 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1186 #endif 1187 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1188 DELAY(10); 1189 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1190 1191 #if NVLAN 1192 if (sc->sc_flags & NFE_HW_VLAN) 1193 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1194 #endif 1195 1196 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1197 1198 /* set MAC address */ 1199 nfe_set_macaddr(sc, sc->sc_enaddr); 1200 1201 /* tell MAC where rings are in memory */ 1202 #ifdef __LP64__ 1203 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1204 #endif 1205 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1206 #ifdef __LP64__ 1207 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1208 #endif 1209 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1210 1211 NFE_WRITE(sc, NFE_RING_SIZE, 1212 (NFE_RX_RING_COUNT - 1) << 16 | 1213 (NFE_TX_RING_COUNT - 1)); 1214 1215 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1216 1217 /* force MAC to wakeup */ 1218 tmp = NFE_READ(sc, NFE_PWR_STATE); 1219 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1220 DELAY(10); 1221 tmp = NFE_READ(sc, NFE_PWR_STATE); 1222 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1223 1224 s = splnet(); 1225 nfe_intr(sc); /* XXX clear IRQ status registers */ 1226 splx(s); 1227 1228 #if 1 1229 /* configure interrupts coalescing/mitigation */ 1230 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1231 #else 1232 /* no interrupt mitigation: one interrupt per packet */ 1233 NFE_WRITE(sc, NFE_IMTIMER, 970); 1234 #endif 1235 1236 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1237 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1238 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1239 1240 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1241 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1242 1243 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1244 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC); 1245 1246 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1247 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1248 DELAY(10); 1249 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1250 1251 /* set Rx filter */ 1252 nfe_setmulti(sc); 1253 1254 if ((rc = ether_mediachange(ifp)) != 0) 1255 goto out; 1256 1257 nfe_tick(sc); 1258 1259 /* enable Rx */ 1260 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1261 1262 /* enable Tx */ 1263 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1264 1265 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1266 1267 /* enable interrupts */ 1268 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1269 1270 callout_schedule(&sc->sc_tick_ch, hz); 1271 1272 ifp->if_flags |= IFF_RUNNING; 1273 ifp->if_flags &= ~IFF_OACTIVE; 1274 1275 out: 1276 return rc; 1277 } 1278 1279 void 1280 nfe_stop(struct ifnet *ifp, int disable) 1281 { 1282 struct nfe_softc *sc = ifp->if_softc; 1283 1284 callout_stop(&sc->sc_tick_ch); 1285 1286 ifp->if_timer = 0; 1287 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1288 1289 mii_down(&sc->sc_mii); 1290 1291 /* abort Tx */ 1292 NFE_WRITE(sc, NFE_TX_CTL, 0); 1293 1294 /* disable Rx */ 1295 NFE_WRITE(sc, NFE_RX_CTL, 0); 1296 1297 /* disable interrupts */ 1298 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1299 1300 /* reset Tx and Rx rings */ 1301 nfe_reset_tx_ring(sc, &sc->txq); 1302 nfe_reset_rx_ring(sc, &sc->rxq); 1303 } 1304 1305 int 1306 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1307 { 1308 struct nfe_desc32 *desc32; 1309 struct nfe_desc64 *desc64; 1310 struct nfe_rx_data *data; 1311 struct nfe_jbuf *jbuf; 1312 void **desc; 1313 bus_addr_t physaddr; 1314 int i, nsegs, error, descsize; 1315 1316 if (sc->sc_flags & NFE_40BIT_ADDR) { 1317 desc = (void **)&ring->desc64; 1318 descsize = sizeof (struct nfe_desc64); 1319 } else { 1320 desc = (void **)&ring->desc32; 1321 descsize = sizeof (struct nfe_desc32); 1322 } 1323 1324 ring->cur = ring->next = 0; 1325 ring->bufsz = MCLBYTES; 1326 1327 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1328 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1329 if (error != 0) { 1330 printf("%s: could not create desc DMA map\n", 1331 sc->sc_dev.dv_xname); 1332 goto fail; 1333 } 1334 1335 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1336 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1337 if (error != 0) { 1338 printf("%s: could not allocate DMA memory\n", 1339 sc->sc_dev.dv_xname); 1340 goto fail; 1341 } 1342 1343 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1344 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1345 if (error != 0) { 1346 printf("%s: could not map desc DMA memory\n", 1347 sc->sc_dev.dv_xname); 1348 goto fail; 1349 } 1350 1351 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1352 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1353 if (error != 0) { 1354 printf("%s: could not load desc DMA map\n", 1355 sc->sc_dev.dv_xname); 1356 goto fail; 1357 } 1358 1359 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1360 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1361 1362 if (sc->sc_flags & NFE_USE_JUMBO) { 1363 ring->bufsz = NFE_JBYTES; 1364 if ((error = nfe_jpool_alloc(sc)) != 0) { 1365 printf("%s: could not allocate jumbo frames\n", 1366 sc->sc_dev.dv_xname); 1367 goto fail; 1368 } 1369 } 1370 1371 /* 1372 * Pre-allocate Rx buffers and populate Rx ring. 1373 */ 1374 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1375 data = &sc->rxq.data[i]; 1376 1377 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1378 if (data->m == NULL) { 1379 printf("%s: could not allocate rx mbuf\n", 1380 sc->sc_dev.dv_xname); 1381 error = ENOMEM; 1382 goto fail; 1383 } 1384 1385 if (sc->sc_flags & NFE_USE_JUMBO) { 1386 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1387 printf("%s: could not allocate jumbo buffer\n", 1388 sc->sc_dev.dv_xname); 1389 goto fail; 1390 } 1391 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1392 sc); 1393 1394 physaddr = jbuf->physaddr; 1395 } else { 1396 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1397 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1398 if (error != 0) { 1399 printf("%s: could not create DMA map\n", 1400 sc->sc_dev.dv_xname); 1401 goto fail; 1402 } 1403 MCLGET(data->m, M_DONTWAIT); 1404 if (!(data->m->m_flags & M_EXT)) { 1405 printf("%s: could not allocate mbuf cluster\n", 1406 sc->sc_dev.dv_xname); 1407 error = ENOMEM; 1408 goto fail; 1409 } 1410 1411 error = bus_dmamap_load(sc->sc_dmat, data->map, 1412 mtod(data->m, void *), MCLBYTES, NULL, 1413 BUS_DMA_READ | BUS_DMA_NOWAIT); 1414 if (error != 0) { 1415 printf("%s: could not load rx buf DMA map", 1416 sc->sc_dev.dv_xname); 1417 goto fail; 1418 } 1419 physaddr = data->map->dm_segs[0].ds_addr; 1420 } 1421 1422 if (sc->sc_flags & NFE_40BIT_ADDR) { 1423 desc64 = &sc->rxq.desc64[i]; 1424 #if defined(__LP64__) 1425 desc64->physaddr[0] = htole32(physaddr >> 32); 1426 #endif 1427 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1428 desc64->length = htole16(sc->rxq.bufsz); 1429 desc64->flags = htole16(NFE_RX_READY); 1430 } else { 1431 desc32 = &sc->rxq.desc32[i]; 1432 desc32->physaddr = htole32(physaddr); 1433 desc32->length = htole16(sc->rxq.bufsz); 1434 desc32->flags = htole16(NFE_RX_READY); 1435 } 1436 } 1437 1438 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1439 BUS_DMASYNC_PREWRITE); 1440 1441 return 0; 1442 1443 fail: nfe_free_rx_ring(sc, ring); 1444 return error; 1445 } 1446 1447 void 1448 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1449 { 1450 int i; 1451 1452 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1453 if (sc->sc_flags & NFE_40BIT_ADDR) { 1454 ring->desc64[i].length = htole16(ring->bufsz); 1455 ring->desc64[i].flags = htole16(NFE_RX_READY); 1456 } else { 1457 ring->desc32[i].length = htole16(ring->bufsz); 1458 ring->desc32[i].flags = htole16(NFE_RX_READY); 1459 } 1460 } 1461 1462 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1463 BUS_DMASYNC_PREWRITE); 1464 1465 ring->cur = ring->next = 0; 1466 } 1467 1468 void 1469 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1470 { 1471 struct nfe_rx_data *data; 1472 void *desc; 1473 int i, descsize; 1474 1475 if (sc->sc_flags & NFE_40BIT_ADDR) { 1476 desc = ring->desc64; 1477 descsize = sizeof (struct nfe_desc64); 1478 } else { 1479 desc = ring->desc32; 1480 descsize = sizeof (struct nfe_desc32); 1481 } 1482 1483 if (desc != NULL) { 1484 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1485 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1486 bus_dmamap_unload(sc->sc_dmat, ring->map); 1487 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1488 NFE_RX_RING_COUNT * descsize); 1489 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1490 } 1491 1492 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1493 data = &ring->data[i]; 1494 1495 if (data->map != NULL) { 1496 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1497 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1498 bus_dmamap_unload(sc->sc_dmat, data->map); 1499 bus_dmamap_destroy(sc->sc_dmat, data->map); 1500 } 1501 if (data->m != NULL) 1502 m_freem(data->m); 1503 } 1504 } 1505 1506 struct nfe_jbuf * 1507 nfe_jalloc(struct nfe_softc *sc, int i) 1508 { 1509 struct nfe_jbuf *jbuf; 1510 1511 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1512 if (jbuf == NULL) 1513 return NULL; 1514 sc->rxq.jbufmap[i] = 1515 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1516 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1517 return jbuf; 1518 } 1519 1520 /* 1521 * This is called automatically by the network stack when the mbuf is freed. 1522 * Caution must be taken that the NIC might be reset by the time the mbuf is 1523 * freed. 1524 */ 1525 void 1526 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1527 { 1528 struct nfe_softc *sc = arg; 1529 struct nfe_jbuf *jbuf; 1530 int i; 1531 1532 /* find the jbuf from the base pointer */ 1533 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1534 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1535 printf("%s: request to free a buffer (%p) not managed by us\n", 1536 sc->sc_dev.dv_xname, buf); 1537 return; 1538 } 1539 jbuf = &sc->rxq.jbuf[i]; 1540 1541 /* ..and put it back in the free list */ 1542 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1543 1544 if (m != NULL) 1545 pool_cache_put(mb_cache, m); 1546 } 1547 1548 int 1549 nfe_jpool_alloc(struct nfe_softc *sc) 1550 { 1551 struct nfe_rx_ring *ring = &sc->rxq; 1552 struct nfe_jbuf *jbuf; 1553 bus_addr_t physaddr; 1554 char *buf; 1555 int i, nsegs, error; 1556 1557 /* 1558 * Allocate a big chunk of DMA'able memory. 1559 */ 1560 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1561 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1562 if (error != 0) { 1563 printf("%s: could not create jumbo DMA map\n", 1564 sc->sc_dev.dv_xname); 1565 goto fail; 1566 } 1567 1568 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1569 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1570 if (error != 0) { 1571 printf("%s could not allocate jumbo DMA memory\n", 1572 sc->sc_dev.dv_xname); 1573 goto fail; 1574 } 1575 1576 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1577 &ring->jpool, BUS_DMA_NOWAIT); 1578 if (error != 0) { 1579 printf("%s: could not map jumbo DMA memory\n", 1580 sc->sc_dev.dv_xname); 1581 goto fail; 1582 } 1583 1584 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1585 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1586 if (error != 0) { 1587 printf("%s: could not load jumbo DMA map\n", 1588 sc->sc_dev.dv_xname); 1589 goto fail; 1590 } 1591 1592 /* ..and split it into 9KB chunks */ 1593 SLIST_INIT(&ring->jfreelist); 1594 1595 buf = ring->jpool; 1596 physaddr = ring->jmap->dm_segs[0].ds_addr; 1597 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1598 jbuf = &ring->jbuf[i]; 1599 1600 jbuf->buf = buf; 1601 jbuf->physaddr = physaddr; 1602 1603 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1604 1605 buf += NFE_JBYTES; 1606 physaddr += NFE_JBYTES; 1607 } 1608 1609 return 0; 1610 1611 fail: nfe_jpool_free(sc); 1612 return error; 1613 } 1614 1615 void 1616 nfe_jpool_free(struct nfe_softc *sc) 1617 { 1618 struct nfe_rx_ring *ring = &sc->rxq; 1619 1620 if (ring->jmap != NULL) { 1621 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1622 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1623 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1624 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1625 } 1626 if (ring->jpool != NULL) { 1627 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1628 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1629 } 1630 } 1631 1632 int 1633 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1634 { 1635 int i, nsegs, error; 1636 void **desc; 1637 int descsize; 1638 1639 if (sc->sc_flags & NFE_40BIT_ADDR) { 1640 desc = (void **)&ring->desc64; 1641 descsize = sizeof (struct nfe_desc64); 1642 } else { 1643 desc = (void **)&ring->desc32; 1644 descsize = sizeof (struct nfe_desc32); 1645 } 1646 1647 ring->queued = 0; 1648 ring->cur = ring->next = 0; 1649 1650 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1651 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1652 1653 if (error != 0) { 1654 printf("%s: could not create desc DMA map\n", 1655 sc->sc_dev.dv_xname); 1656 goto fail; 1657 } 1658 1659 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1660 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1661 if (error != 0) { 1662 printf("%s: could not allocate DMA memory\n", 1663 sc->sc_dev.dv_xname); 1664 goto fail; 1665 } 1666 1667 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1668 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1669 if (error != 0) { 1670 printf("%s: could not map desc DMA memory\n", 1671 sc->sc_dev.dv_xname); 1672 goto fail; 1673 } 1674 1675 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1676 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1677 if (error != 0) { 1678 printf("%s: could not load desc DMA map\n", 1679 sc->sc_dev.dv_xname); 1680 goto fail; 1681 } 1682 1683 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1684 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1685 1686 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1687 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1688 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1689 &ring->data[i].map); 1690 if (error != 0) { 1691 printf("%s: could not create DMA map\n", 1692 sc->sc_dev.dv_xname); 1693 goto fail; 1694 } 1695 } 1696 1697 return 0; 1698 1699 fail: nfe_free_tx_ring(sc, ring); 1700 return error; 1701 } 1702 1703 void 1704 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1705 { 1706 struct nfe_tx_data *data; 1707 int i; 1708 1709 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1710 if (sc->sc_flags & NFE_40BIT_ADDR) 1711 ring->desc64[i].flags = 0; 1712 else 1713 ring->desc32[i].flags = 0; 1714 1715 data = &ring->data[i]; 1716 1717 if (data->m != NULL) { 1718 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1719 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1720 bus_dmamap_unload(sc->sc_dmat, data->active); 1721 m_freem(data->m); 1722 data->m = NULL; 1723 } 1724 } 1725 1726 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1727 BUS_DMASYNC_PREWRITE); 1728 1729 ring->queued = 0; 1730 ring->cur = ring->next = 0; 1731 } 1732 1733 void 1734 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1735 { 1736 struct nfe_tx_data *data; 1737 void *desc; 1738 int i, descsize; 1739 1740 if (sc->sc_flags & NFE_40BIT_ADDR) { 1741 desc = ring->desc64; 1742 descsize = sizeof (struct nfe_desc64); 1743 } else { 1744 desc = ring->desc32; 1745 descsize = sizeof (struct nfe_desc32); 1746 } 1747 1748 if (desc != NULL) { 1749 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1750 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1751 bus_dmamap_unload(sc->sc_dmat, ring->map); 1752 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1753 NFE_TX_RING_COUNT * descsize); 1754 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1755 } 1756 1757 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1758 data = &ring->data[i]; 1759 1760 if (data->m != NULL) { 1761 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1762 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1763 bus_dmamap_unload(sc->sc_dmat, data->active); 1764 m_freem(data->m); 1765 } 1766 } 1767 1768 /* ..and now actually destroy the DMA mappings */ 1769 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1770 data = &ring->data[i]; 1771 if (data->map == NULL) 1772 continue; 1773 bus_dmamap_destroy(sc->sc_dmat, data->map); 1774 } 1775 } 1776 1777 void 1778 nfe_setmulti(struct nfe_softc *sc) 1779 { 1780 struct ethercom *ec = &sc->sc_ethercom; 1781 struct ifnet *ifp = &ec->ec_if; 1782 struct ether_multi *enm; 1783 struct ether_multistep step; 1784 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1785 uint32_t filter = NFE_RXFILTER_MAGIC; 1786 int i; 1787 1788 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1789 bzero(addr, ETHER_ADDR_LEN); 1790 bzero(mask, ETHER_ADDR_LEN); 1791 goto done; 1792 } 1793 1794 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1795 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1796 1797 ETHER_FIRST_MULTI(step, ec, enm); 1798 while (enm != NULL) { 1799 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1800 ifp->if_flags |= IFF_ALLMULTI; 1801 bzero(addr, ETHER_ADDR_LEN); 1802 bzero(mask, ETHER_ADDR_LEN); 1803 goto done; 1804 } 1805 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1806 addr[i] &= enm->enm_addrlo[i]; 1807 mask[i] &= ~enm->enm_addrlo[i]; 1808 } 1809 ETHER_NEXT_MULTI(step, enm); 1810 } 1811 for (i = 0; i < ETHER_ADDR_LEN; i++) 1812 mask[i] |= addr[i]; 1813 1814 done: 1815 addr[0] |= 0x01; /* make sure multicast bit is set */ 1816 1817 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1818 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1819 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1820 addr[5] << 8 | addr[4]); 1821 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1822 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1823 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1824 mask[5] << 8 | mask[4]); 1825 1826 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1827 NFE_WRITE(sc, NFE_RXFILTER, filter); 1828 } 1829 1830 void 1831 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1832 { 1833 uint32_t tmp; 1834 1835 if ((sc->sc_flags & NFE_CORRECT_MACADDR) == 0) { 1836 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1837 addr[0] = (tmp >> 8) & 0xff; 1838 addr[1] = (tmp & 0xff); 1839 1840 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1841 addr[2] = (tmp >> 24) & 0xff; 1842 addr[3] = (tmp >> 16) & 0xff; 1843 addr[4] = (tmp >> 8) & 0xff; 1844 addr[5] = (tmp & 0xff); 1845 } else { 1846 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1847 addr[5] = (tmp >> 8) & 0xff; 1848 addr[4] = (tmp & 0xff); 1849 1850 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1851 addr[3] = (tmp >> 24) & 0xff; 1852 addr[2] = (tmp >> 16) & 0xff; 1853 addr[1] = (tmp >> 8) & 0xff; 1854 addr[0] = (tmp & 0xff); 1855 } 1856 } 1857 1858 void 1859 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1860 { 1861 NFE_WRITE(sc, NFE_MACADDR_LO, 1862 addr[5] << 8 | addr[4]); 1863 NFE_WRITE(sc, NFE_MACADDR_HI, 1864 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1865 } 1866 1867 void 1868 nfe_tick(void *arg) 1869 { 1870 struct nfe_softc *sc = arg; 1871 int s; 1872 1873 s = splnet(); 1874 mii_tick(&sc->sc_mii); 1875 splx(s); 1876 1877 callout_schedule(&sc->sc_tick_ch, hz); 1878 } 1879
Indexes created Tue Sep 30 07:10:03 GMT 2025