if_nfe.c revision 1.27
1 /* $NetBSD: if_nfe.c,v 1.27 2008/01/26 14:13:06 tsutsui Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.52 2006/03/02 09:04:00 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.27 2008/01/26 14:13:06 tsutsui Exp $"); 25 26 #include "opt_inet.h" 27 #include "bpfilter.h" 28 #include "vlan.h" 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/types.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/queue.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/socket.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/pci/if_nfereg.h> 74 #include <dev/pci/if_nfevar.h> 75 76 int nfe_match(struct device *, struct cfdata *, void *); 77 void nfe_attach(struct device *, struct device *, void *); 78 void nfe_power(int, void *); 79 void nfe_miibus_statchg(struct device *); 80 int nfe_miibus_readreg(struct device *, int, int); 81 void nfe_miibus_writereg(struct device *, int, int, int); 82 int nfe_intr(void *); 83 int nfe_ioctl(struct ifnet *, u_long, void *); 84 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 85 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 86 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 87 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 88 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 89 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 90 void nfe_rxeof(struct nfe_softc *); 91 void nfe_txeof(struct nfe_softc *); 92 int nfe_encap(struct nfe_softc *, struct mbuf *); 93 void nfe_start(struct ifnet *); 94 void nfe_watchdog(struct ifnet *); 95 int nfe_init(struct ifnet *); 96 void nfe_stop(struct ifnet *, int); 97 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 98 void nfe_jfree(struct mbuf *, void *, size_t, void *); 99 int nfe_jpool_alloc(struct nfe_softc *); 100 void nfe_jpool_free(struct nfe_softc *); 101 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 102 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 105 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 void nfe_setmulti(struct nfe_softc *); 108 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 109 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 110 void nfe_tick(void *); 111 112 CFATTACH_DECL(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, NULL, NULL); 113 114 /*#define NFE_NO_JUMBO*/ 115 116 #ifdef NFE_DEBUG 117 int nfedebug = 0; 118 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 119 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 120 #else 121 #define DPRINTF(x) 122 #define DPRINTFN(n,x) 123 #endif 124 125 /* deal with naming differences */ 126 127 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 128 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 129 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 130 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 132 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 133 134 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 135 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 136 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 137 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 138 139 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 140 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 141 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 142 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 143 144 #ifdef _LP64 145 #define __LP64__ 1 146 #endif 147 148 const struct nfe_product { 149 pci_vendor_id_t vendor; 150 pci_product_id_t product; 151 } nfe_devices[] = { 152 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 153 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 155 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 } 183 }; 184 185 int 186 nfe_match(struct device *dev, struct cfdata *match, void *aux) 187 { 188 struct pci_attach_args *pa = aux; 189 const struct nfe_product *np; 190 int i; 191 192 for (i = 0; i < sizeof(nfe_devices) / sizeof(nfe_devices[0]); i++) { 193 np = &nfe_devices[i]; 194 if (PCI_VENDOR(pa->pa_id) == np->vendor && 195 PCI_PRODUCT(pa->pa_id) == np->product) 196 return 1; 197 } 198 return 0; 199 } 200 201 void 202 nfe_attach(struct device *parent, struct device *self, void *aux) 203 { 204 struct nfe_softc *sc = (struct nfe_softc *)self; 205 struct pci_attach_args *pa = aux; 206 pci_chipset_tag_t pc = pa->pa_pc; 207 pci_intr_handle_t ih; 208 const char *intrstr; 209 struct ifnet *ifp; 210 bus_size_t memsize; 211 pcireg_t memtype; 212 char devinfo[256]; 213 214 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 215 aprint_normal(": %s (rev. 0x%02x)\n", 216 devinfo, PCI_REVISION(pa->pa_class)); 217 218 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 219 switch (memtype) { 220 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 221 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 222 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 223 &sc->sc_memh, NULL, &memsize) == 0) 224 break; 225 /* FALLTHROUGH */ 226 default: 227 printf("%s: could not map mem space\n", sc->sc_dev.dv_xname); 228 return; 229 } 230 231 if (pci_intr_map(pa, &ih) != 0) { 232 printf("%s: could not map interrupt\n", sc->sc_dev.dv_xname); 233 return; 234 } 235 236 intrstr = pci_intr_string(pc, ih); 237 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 238 if (sc->sc_ih == NULL) { 239 printf("%s: could not establish interrupt", 240 sc->sc_dev.dv_xname); 241 if (intrstr != NULL) 242 printf(" at %s", intrstr); 243 printf("\n"); 244 return; 245 } 246 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 247 248 sc->sc_dmat = pa->pa_dmat; 249 250 /* Check for reversed ethernet address */ 251 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 252 sc->sc_flags |= NFE_CORRECT_MACADDR; 253 254 nfe_get_macaddr(sc, sc->sc_enaddr); 255 printf("%s: Ethernet address %s\n", 256 sc->sc_dev.dv_xname, ether_sprintf(sc->sc_enaddr)); 257 258 sc->sc_flags = 0; 259 260 switch (PCI_PRODUCT(pa->pa_id)) { 261 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 262 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 263 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 264 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 265 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 266 break; 267 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 268 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 269 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 270 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 271 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 272 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 273 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 274 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 275 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 276 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 277 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 278 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 279 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 280 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 281 sc->sc_flags |= NFE_40BIT_ADDR |NFE_PWR_MGMT; 282 break; 283 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 284 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 285 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 286 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 287 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 288 break; 289 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 290 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 291 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 292 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 293 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 294 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 295 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 296 NFE_HW_VLAN | NFE_PWR_MGMT; 297 break; 298 } 299 300 if ((sc->sc_flags & NFE_PWR_MGMT) != 0) { 301 /* wakeup some newer chips from powerdown mode */ 302 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 303 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 304 DELAY(100); 305 NFE_WRITE(sc, NFE_MAC_RESET, 0); 306 DELAY(100); 307 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 308 NFE_WRITE(sc, NFE_PWR2_CTL, 309 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_WAKEUP_MASK); 310 } 311 312 #ifndef NFE_NO_JUMBO 313 /* enable jumbo frames for adapters that support it */ 314 if (sc->sc_flags & NFE_JUMBO_SUP) 315 sc->sc_flags |= NFE_USE_JUMBO; 316 #endif 317 318 /* 319 * Allocate Tx and Rx rings. 320 */ 321 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 322 printf("%s: could not allocate Tx ring\n", 323 sc->sc_dev.dv_xname); 324 return; 325 } 326 327 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 328 printf("%s: could not allocate Rx ring\n", 329 sc->sc_dev.dv_xname); 330 nfe_free_tx_ring(sc, &sc->txq); 331 return; 332 } 333 334 ifp = &sc->sc_ethercom.ec_if; 335 ifp->if_softc = sc; 336 ifp->if_mtu = ETHERMTU; 337 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 338 ifp->if_ioctl = nfe_ioctl; 339 ifp->if_start = nfe_start; 340 ifp->if_stop = nfe_stop; 341 ifp->if_watchdog = nfe_watchdog; 342 ifp->if_init = nfe_init; 343 ifp->if_baudrate = IF_Gbps(1); 344 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 345 IFQ_SET_READY(&ifp->if_snd); 346 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 347 348 #if NVLAN > 0 349 if (sc->sc_flags & NFE_HW_VLAN) 350 sc->sc_ethercom.ec_capabilities |= 351 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 352 #endif 353 if (sc->sc_flags & NFE_HW_CSUM) { 354 ifp->if_capabilities |= 355 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 356 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 357 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 358 } 359 360 sc->sc_mii.mii_ifp = ifp; 361 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 362 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 363 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 364 365 sc->sc_ethercom.ec_mii = &sc->sc_mii; 366 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 367 ether_mediastatus); 368 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 369 MII_OFFSET_ANY, 0); 370 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 371 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 372 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 373 0, NULL); 374 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 375 } else 376 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 377 378 if_attach(ifp); 379 ether_ifattach(ifp, sc->sc_enaddr); 380 381 callout_init(&sc->sc_tick_ch, 0); 382 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 383 384 if (!pmf_device_register(self, NULL, NULL)) 385 aprint_error_dev(self, "couldn't establish power handler\n"); 386 else 387 pmf_class_network_register(self, ifp); 388 } 389 390 void 391 nfe_miibus_statchg(struct device *dev) 392 { 393 struct nfe_softc *sc = (struct nfe_softc *)dev; 394 struct mii_data *mii = &sc->sc_mii; 395 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 396 397 phy = NFE_READ(sc, NFE_PHY_IFACE); 398 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 399 400 seed = NFE_READ(sc, NFE_RNDSEED); 401 seed &= ~NFE_SEED_MASK; 402 403 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 404 phy |= NFE_PHY_HDX; /* half-duplex */ 405 misc |= NFE_MISC1_HDX; 406 } 407 408 switch (IFM_SUBTYPE(mii->mii_media_active)) { 409 case IFM_1000_T: /* full-duplex only */ 410 link |= NFE_MEDIA_1000T; 411 seed |= NFE_SEED_1000T; 412 phy |= NFE_PHY_1000T; 413 break; 414 case IFM_100_TX: 415 link |= NFE_MEDIA_100TX; 416 seed |= NFE_SEED_100TX; 417 phy |= NFE_PHY_100TX; 418 break; 419 case IFM_10_T: 420 link |= NFE_MEDIA_10T; 421 seed |= NFE_SEED_10T; 422 break; 423 } 424 425 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 426 427 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 428 NFE_WRITE(sc, NFE_MISC1, misc); 429 NFE_WRITE(sc, NFE_LINKSPEED, link); 430 } 431 432 int 433 nfe_miibus_readreg(struct device *dev, int phy, int reg) 434 { 435 struct nfe_softc *sc = (struct nfe_softc *)dev; 436 uint32_t val; 437 int ntries; 438 439 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 440 441 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 442 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 443 DELAY(100); 444 } 445 446 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 447 448 for (ntries = 0; ntries < 1000; ntries++) { 449 DELAY(100); 450 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 451 break; 452 } 453 if (ntries == 1000) { 454 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 455 sc->sc_dev.dv_xname)); 456 return 0; 457 } 458 459 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 460 DPRINTFN(2, ("%s: could not read PHY\n", 461 sc->sc_dev.dv_xname)); 462 return 0; 463 } 464 465 val = NFE_READ(sc, NFE_PHY_DATA); 466 if (val != 0xffffffff && val != 0) 467 sc->mii_phyaddr = phy; 468 469 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 470 sc->sc_dev.dv_xname, phy, reg, val)); 471 472 return val; 473 } 474 475 void 476 nfe_miibus_writereg(struct device *dev, int phy, int reg, int val) 477 { 478 struct nfe_softc *sc = (struct nfe_softc *)dev; 479 uint32_t ctl; 480 int ntries; 481 482 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 483 484 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 485 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 486 DELAY(100); 487 } 488 489 NFE_WRITE(sc, NFE_PHY_DATA, val); 490 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 491 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 492 493 for (ntries = 0; ntries < 1000; ntries++) { 494 DELAY(100); 495 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 496 break; 497 } 498 #ifdef NFE_DEBUG 499 if (nfedebug >= 2 && ntries == 1000) 500 printf("could not write to PHY\n"); 501 #endif 502 } 503 504 int 505 nfe_intr(void *arg) 506 { 507 struct nfe_softc *sc = arg; 508 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 509 uint32_t r; 510 int handled; 511 512 if ((ifp->if_flags & IFF_UP) == 0) 513 return 0; 514 515 handled = 0; 516 517 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 518 519 for (;;) { 520 r = NFE_READ(sc, NFE_IRQ_STATUS); 521 if ((r & NFE_IRQ_WANTED) == 0) 522 break; 523 524 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 525 handled = 1; 526 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 527 528 if ((r & (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX)) 529 != 0) { 530 /* check Rx ring */ 531 nfe_rxeof(sc); 532 } 533 534 if ((r & (NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE)) 535 != 0) { 536 /* check Tx ring */ 537 nfe_txeof(sc); 538 } 539 540 if ((r & NFE_IRQ_LINK) != 0) { 541 NFE_READ(sc, NFE_PHY_STATUS); 542 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 543 DPRINTF(("%s: link state changed\n", 544 sc->sc_dev.dv_xname)); 545 } 546 } 547 548 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 549 550 if (handled && !IF_IS_EMPTY(&ifp->if_snd)) 551 nfe_start(ifp); 552 553 return handled; 554 } 555 556 int 557 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 558 { 559 struct nfe_softc *sc = ifp->if_softc; 560 struct ifreq *ifr = (struct ifreq *)data; 561 struct ifaddr *ifa = (struct ifaddr *)data; 562 int s, error = 0; 563 564 s = splnet(); 565 566 switch (cmd) { 567 case SIOCSIFADDR: 568 ifp->if_flags |= IFF_UP; 569 nfe_init(ifp); 570 switch (ifa->ifa_addr->sa_family) { 571 #ifdef INET 572 case AF_INET: 573 arp_ifinit(ifp, ifa); 574 break; 575 #endif 576 default: 577 break; 578 } 579 break; 580 case SIOCSIFMTU: 581 if (ifr->ifr_mtu < ETHERMIN || 582 ((sc->sc_flags & NFE_USE_JUMBO) && 583 ifr->ifr_mtu > ETHERMTU_JUMBO) || 584 (!(sc->sc_flags & NFE_USE_JUMBO) && 585 ifr->ifr_mtu > ETHERMTU)) 586 error = EINVAL; 587 else if (ifp->if_mtu != ifr->ifr_mtu) 588 ifp->if_mtu = ifr->ifr_mtu; 589 break; 590 case SIOCSIFFLAGS: 591 if (ifp->if_flags & IFF_UP) { 592 /* 593 * If only the PROMISC or ALLMULTI flag changes, then 594 * don't do a full re-init of the chip, just update 595 * the Rx filter. 596 */ 597 if ((ifp->if_flags & IFF_RUNNING) && 598 ((ifp->if_flags ^ sc->sc_if_flags) & 599 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 600 nfe_setmulti(sc); 601 else 602 nfe_init(ifp); 603 } else { 604 if (ifp->if_flags & IFF_RUNNING) 605 nfe_stop(ifp, 1); 606 } 607 sc->sc_if_flags = ifp->if_flags; 608 break; 609 default: 610 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 611 if (ifp->if_flags & IFF_RUNNING) 612 nfe_setmulti(sc); 613 error = 0; 614 } 615 break; 616 } 617 618 splx(s); 619 620 return error; 621 } 622 623 void 624 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 625 { 626 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 627 (char *)desc32 - (char *)sc->txq.desc32, 628 sizeof (struct nfe_desc32), ops); 629 } 630 631 void 632 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 633 { 634 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 635 (char *)desc64 - (char *)sc->txq.desc64, 636 sizeof (struct nfe_desc64), ops); 637 } 638 639 void 640 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 641 { 642 if (end > start) { 643 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 644 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 645 (char *)&sc->txq.desc32[end] - 646 (char *)&sc->txq.desc32[start], ops); 647 return; 648 } 649 /* sync from 'start' to end of ring */ 650 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 651 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 652 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 653 (char *)&sc->txq.desc32[start], ops); 654 655 /* sync from start of ring to 'end' */ 656 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 657 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 658 } 659 660 void 661 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 662 { 663 if (end > start) { 664 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 665 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 666 (char *)&sc->txq.desc64[end] - 667 (char *)&sc->txq.desc64[start], ops); 668 return; 669 } 670 /* sync from 'start' to end of ring */ 671 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 672 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 673 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 674 (char *)&sc->txq.desc64[start], ops); 675 676 /* sync from start of ring to 'end' */ 677 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 678 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 679 } 680 681 void 682 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 683 { 684 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 685 (char *)desc32 - (char *)sc->rxq.desc32, 686 sizeof (struct nfe_desc32), ops); 687 } 688 689 void 690 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 691 { 692 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 693 (char *)desc64 - (char *)sc->rxq.desc64, 694 sizeof (struct nfe_desc64), ops); 695 } 696 697 void 698 nfe_rxeof(struct nfe_softc *sc) 699 { 700 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 701 struct nfe_desc32 *desc32; 702 struct nfe_desc64 *desc64; 703 struct nfe_rx_data *data; 704 struct nfe_jbuf *jbuf; 705 struct mbuf *m, *mnew; 706 bus_addr_t physaddr; 707 uint16_t flags; 708 int error, len, i; 709 710 desc32 = NULL; 711 desc64 = NULL; 712 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 713 data = &sc->rxq.data[i]; 714 715 if (sc->sc_flags & NFE_40BIT_ADDR) { 716 desc64 = &sc->rxq.desc64[i]; 717 nfe_rxdesc64_sync(sc, desc64, 718 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 719 720 flags = le16toh(desc64->flags); 721 len = le16toh(desc64->length) & 0x3fff; 722 } else { 723 desc32 = &sc->rxq.desc32[i]; 724 nfe_rxdesc32_sync(sc, desc32, 725 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 726 727 flags = le16toh(desc32->flags); 728 len = le16toh(desc32->length) & 0x3fff; 729 } 730 731 if ((flags & NFE_RX_READY) != 0) 732 break; 733 734 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 735 if ((flags & NFE_RX_VALID_V1) == 0) 736 goto skip; 737 738 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 739 flags &= ~NFE_RX_ERROR; 740 len--; /* fix buffer length */ 741 } 742 } else { 743 if ((flags & NFE_RX_VALID_V2) == 0) 744 goto skip; 745 746 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 747 flags &= ~NFE_RX_ERROR; 748 len--; /* fix buffer length */ 749 } 750 } 751 752 if (flags & NFE_RX_ERROR) { 753 ifp->if_ierrors++; 754 goto skip; 755 } 756 757 /* 758 * Try to allocate a new mbuf for this ring element and load 759 * it before processing the current mbuf. If the ring element 760 * cannot be loaded, drop the received packet and reuse the 761 * old mbuf. In the unlikely case that the old mbuf can't be 762 * reloaded either, explicitly panic. 763 */ 764 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 765 if (mnew == NULL) { 766 ifp->if_ierrors++; 767 goto skip; 768 } 769 770 if (sc->sc_flags & NFE_USE_JUMBO) { 771 physaddr = 772 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 773 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 774 if (len > MCLBYTES) { 775 m_freem(mnew); 776 ifp->if_ierrors++; 777 goto skip1; 778 } 779 MCLGET(mnew, M_DONTWAIT); 780 if ((mnew->m_flags & M_EXT) == 0) { 781 m_freem(mnew); 782 ifp->if_ierrors++; 783 goto skip1; 784 } 785 786 memcpy(mtod(mnew, void *), 787 mtod(data->m, const void *), len); 788 m = mnew; 789 goto mbufcopied; 790 } else { 791 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 792 793 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 794 mtod(data->m, char *) - (char *)sc->rxq.jpool, 795 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 796 797 physaddr = jbuf->physaddr; 798 } 799 } else { 800 MCLGET(mnew, M_DONTWAIT); 801 if ((mnew->m_flags & M_EXT) == 0) { 802 m_freem(mnew); 803 ifp->if_ierrors++; 804 goto skip; 805 } 806 807 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 808 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 809 bus_dmamap_unload(sc->sc_dmat, data->map); 810 811 error = bus_dmamap_load(sc->sc_dmat, data->map, 812 mtod(mnew, void *), MCLBYTES, NULL, 813 BUS_DMA_READ | BUS_DMA_NOWAIT); 814 if (error != 0) { 815 m_freem(mnew); 816 817 /* try to reload the old mbuf */ 818 error = bus_dmamap_load(sc->sc_dmat, data->map, 819 mtod(data->m, void *), MCLBYTES, NULL, 820 BUS_DMA_READ | BUS_DMA_NOWAIT); 821 if (error != 0) { 822 /* very unlikely that it will fail.. */ 823 panic("%s: could not load old rx mbuf", 824 sc->sc_dev.dv_xname); 825 } 826 ifp->if_ierrors++; 827 goto skip; 828 } 829 physaddr = data->map->dm_segs[0].ds_addr; 830 } 831 832 /* 833 * New mbuf successfully loaded, update Rx ring and continue 834 * processing. 835 */ 836 m = data->m; 837 data->m = mnew; 838 839 mbufcopied: 840 /* finalize mbuf */ 841 m->m_pkthdr.len = m->m_len = len; 842 m->m_pkthdr.rcvif = ifp; 843 844 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 845 /* 846 * XXX 847 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 848 */ 849 if (flags & NFE_RX_IP_CSUMOK) { 850 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 851 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 852 sc->sc_dev.dv_xname)); 853 } 854 /* 855 * XXX 856 * no way to check M_CSUM_TCP_UDP_BAD or 857 * other protocols? 858 */ 859 if (flags & NFE_RX_UDP_CSUMOK) { 860 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 861 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 862 sc->sc_dev.dv_xname)); 863 } else if (flags & NFE_RX_TCP_CSUMOK) { 864 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 865 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 866 sc->sc_dev.dv_xname)); 867 } 868 } 869 870 #if NBPFILTER > 0 871 if (ifp->if_bpf) 872 bpf_mtap(ifp->if_bpf, m); 873 #endif 874 ifp->if_ipackets++; 875 (*ifp->if_input)(ifp, m); 876 877 skip1: 878 /* update mapping address in h/w descriptor */ 879 if (sc->sc_flags & NFE_40BIT_ADDR) { 880 #if defined(__LP64__) 881 desc64->physaddr[0] = htole32(physaddr >> 32); 882 #endif 883 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 884 } else { 885 desc32->physaddr = htole32(physaddr); 886 } 887 888 skip: 889 if (sc->sc_flags & NFE_40BIT_ADDR) { 890 desc64->length = htole16(sc->rxq.bufsz); 891 desc64->flags = htole16(NFE_RX_READY); 892 893 nfe_rxdesc64_sync(sc, desc64, 894 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 895 } else { 896 desc32->length = htole16(sc->rxq.bufsz); 897 desc32->flags = htole16(NFE_RX_READY); 898 899 nfe_rxdesc32_sync(sc, desc32, 900 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 901 } 902 } 903 /* update current RX pointer */ 904 sc->rxq.cur = i; 905 } 906 907 void 908 nfe_txeof(struct nfe_softc *sc) 909 { 910 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 911 struct nfe_desc32 *desc32; 912 struct nfe_desc64 *desc64; 913 struct nfe_tx_data *data = NULL; 914 int i; 915 uint16_t flags; 916 917 for (i = sc->txq.next; 918 sc->txq.queued > 0; 919 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 920 if (sc->sc_flags & NFE_40BIT_ADDR) { 921 desc64 = &sc->txq.desc64[i]; 922 nfe_txdesc64_sync(sc, desc64, 923 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 924 925 flags = le16toh(desc64->flags); 926 } else { 927 desc32 = &sc->txq.desc32[i]; 928 nfe_txdesc32_sync(sc, desc32, 929 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 930 931 flags = le16toh(desc32->flags); 932 } 933 934 if ((flags & NFE_TX_VALID) != 0) 935 break; 936 937 data = &sc->txq.data[i]; 938 939 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 940 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 941 data->m == NULL) 942 continue; 943 944 if ((flags & NFE_TX_ERROR_V1) != 0) { 945 printf("%s: tx v1 error 0x%04x\n", 946 sc->sc_dev.dv_xname, flags); 947 ifp->if_oerrors++; 948 } else 949 ifp->if_opackets++; 950 } else { 951 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 952 data->m == NULL) 953 continue; 954 955 if ((flags & NFE_TX_ERROR_V2) != 0) { 956 printf("%s: tx v2 error 0x%04x\n", 957 sc->sc_dev.dv_xname, flags); 958 ifp->if_oerrors++; 959 } else 960 ifp->if_opackets++; 961 } 962 963 if (data->m == NULL) { /* should not get there */ 964 printf("%s: last fragment bit w/o associated mbuf!\n", 965 sc->sc_dev.dv_xname); 966 continue; 967 } 968 969 /* last fragment of the mbuf chain transmitted */ 970 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 971 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 972 bus_dmamap_unload(sc->sc_dmat, data->active); 973 m_freem(data->m); 974 data->m = NULL; 975 } 976 977 sc->txq.next = i; 978 979 if (sc->txq.queued < NFE_TX_RING_COUNT) { 980 /* at least one slot freed */ 981 ifp->if_flags &= ~IFF_OACTIVE; 982 } 983 984 if (sc->txq.queued == 0) { 985 /* all queued packets are sent */ 986 ifp->if_timer = 0; 987 } 988 } 989 990 int 991 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 992 { 993 struct nfe_desc32 *desc32; 994 struct nfe_desc64 *desc64; 995 struct nfe_tx_data *data; 996 bus_dmamap_t map; 997 uint16_t flags, csumflags; 998 #if NVLAN > 0 999 struct m_tag *mtag; 1000 uint32_t vtag = 0; 1001 #endif 1002 int error, i, first; 1003 1004 desc32 = NULL; 1005 desc64 = NULL; 1006 data = NULL; 1007 1008 flags = 0; 1009 csumflags = 0; 1010 first = sc->txq.cur; 1011 1012 map = sc->txq.data[first].map; 1013 1014 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1015 if (error != 0) { 1016 printf("%s: could not map mbuf (error %d)\n", 1017 sc->sc_dev.dv_xname, error); 1018 return error; 1019 } 1020 1021 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1022 bus_dmamap_unload(sc->sc_dmat, map); 1023 return ENOBUFS; 1024 } 1025 1026 #if NVLAN > 0 1027 /* setup h/w VLAN tagging */ 1028 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1029 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1030 #endif 1031 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1032 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1033 csumflags |= NFE_TX_IP_CSUM; 1034 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1035 csumflags |= NFE_TX_TCP_UDP_CSUM; 1036 } 1037 1038 for (i = 0; i < map->dm_nsegs; i++) { 1039 data = &sc->txq.data[sc->txq.cur]; 1040 1041 if (sc->sc_flags & NFE_40BIT_ADDR) { 1042 desc64 = &sc->txq.desc64[sc->txq.cur]; 1043 #if defined(__LP64__) 1044 desc64->physaddr[0] = 1045 htole32(map->dm_segs[i].ds_addr >> 32); 1046 #endif 1047 desc64->physaddr[1] = 1048 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1049 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1050 desc64->flags = htole16(flags); 1051 desc64->vtag = 0; 1052 } else { 1053 desc32 = &sc->txq.desc32[sc->txq.cur]; 1054 1055 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1056 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1057 desc32->flags = htole16(flags); 1058 } 1059 1060 /* 1061 * Setting of the valid bit in the first descriptor is 1062 * deferred until the whole chain is fully setup. 1063 */ 1064 flags |= NFE_TX_VALID; 1065 1066 sc->txq.queued++; 1067 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1068 } 1069 1070 /* the whole mbuf chain has been setup */ 1071 if (sc->sc_flags & NFE_40BIT_ADDR) { 1072 /* fix last descriptor */ 1073 flags |= NFE_TX_LASTFRAG_V2; 1074 desc64->flags = htole16(flags); 1075 1076 /* Checksum flags and vtag belong to the first fragment only. */ 1077 #if NVLAN > 0 1078 sc->txq.desc64[first].vtag = htole32(vtag); 1079 #endif 1080 sc->txq.desc64[first].flags |= htole16(csumflags); 1081 1082 /* finally, set the valid bit in the first descriptor */ 1083 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1084 } else { 1085 /* fix last descriptor */ 1086 if (sc->sc_flags & NFE_JUMBO_SUP) 1087 flags |= NFE_TX_LASTFRAG_V2; 1088 else 1089 flags |= NFE_TX_LASTFRAG_V1; 1090 desc32->flags = htole16(flags); 1091 1092 /* Checksum flags belong to the first fragment only. */ 1093 sc->txq.desc32[first].flags |= htole16(csumflags); 1094 1095 /* finally, set the valid bit in the first descriptor */ 1096 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1097 } 1098 1099 data->m = m0; 1100 data->active = map; 1101 1102 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1103 BUS_DMASYNC_PREWRITE); 1104 1105 return 0; 1106 } 1107 1108 void 1109 nfe_start(struct ifnet *ifp) 1110 { 1111 struct nfe_softc *sc = ifp->if_softc; 1112 int old = sc->txq.queued; 1113 struct mbuf *m0; 1114 1115 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 1116 return; 1117 1118 for (;;) { 1119 IFQ_POLL(&ifp->if_snd, m0); 1120 if (m0 == NULL) 1121 break; 1122 1123 if (nfe_encap(sc, m0) != 0) { 1124 ifp->if_flags |= IFF_OACTIVE; 1125 break; 1126 } 1127 1128 /* packet put in h/w queue, remove from s/w queue */ 1129 IFQ_DEQUEUE(&ifp->if_snd, m0); 1130 1131 #if NBPFILTER > 0 1132 if (ifp->if_bpf != NULL) 1133 bpf_mtap(ifp->if_bpf, m0); 1134 #endif 1135 } 1136 1137 if (sc->txq.queued != old) { 1138 /* packets are queued */ 1139 if (sc->sc_flags & NFE_40BIT_ADDR) 1140 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1141 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1142 else 1143 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1144 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1145 /* kick Tx */ 1146 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1147 1148 /* 1149 * Set a timeout in case the chip goes out to lunch. 1150 */ 1151 ifp->if_timer = 5; 1152 } 1153 } 1154 1155 void 1156 nfe_watchdog(struct ifnet *ifp) 1157 { 1158 struct nfe_softc *sc = ifp->if_softc; 1159 1160 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1161 1162 ifp->if_flags &= ~IFF_RUNNING; 1163 nfe_init(ifp); 1164 1165 ifp->if_oerrors++; 1166 } 1167 1168 int 1169 nfe_init(struct ifnet *ifp) 1170 { 1171 struct nfe_softc *sc = ifp->if_softc; 1172 uint32_t tmp; 1173 int rc = 0, s; 1174 1175 if (ifp->if_flags & IFF_RUNNING) 1176 return 0; 1177 1178 nfe_stop(ifp, 0); 1179 1180 NFE_WRITE(sc, NFE_TX_UNK, 0); 1181 NFE_WRITE(sc, NFE_STATUS, 0); 1182 1183 sc->rxtxctl = NFE_RXTX_BIT2; 1184 if (sc->sc_flags & NFE_40BIT_ADDR) 1185 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1186 else if (sc->sc_flags & NFE_JUMBO_SUP) 1187 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1188 if (sc->sc_flags & NFE_HW_CSUM) 1189 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1190 #if NVLAN > 0 1191 /* 1192 * Although the adapter is capable of stripping VLAN tags from received 1193 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1194 * purpose. This will be done in software by our network stack. 1195 */ 1196 if (sc->sc_flags & NFE_HW_VLAN) 1197 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1198 #endif 1199 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1200 DELAY(10); 1201 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1202 1203 #if NVLAN 1204 if (sc->sc_flags & NFE_HW_VLAN) 1205 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1206 #endif 1207 1208 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1209 1210 /* set MAC address */ 1211 nfe_set_macaddr(sc, sc->sc_enaddr); 1212 1213 /* tell MAC where rings are in memory */ 1214 #ifdef __LP64__ 1215 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1216 #endif 1217 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1218 #ifdef __LP64__ 1219 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1220 #endif 1221 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1222 1223 NFE_WRITE(sc, NFE_RING_SIZE, 1224 (NFE_RX_RING_COUNT - 1) << 16 | 1225 (NFE_TX_RING_COUNT - 1)); 1226 1227 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1228 1229 /* force MAC to wakeup */ 1230 tmp = NFE_READ(sc, NFE_PWR_STATE); 1231 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1232 DELAY(10); 1233 tmp = NFE_READ(sc, NFE_PWR_STATE); 1234 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1235 1236 s = splnet(); 1237 nfe_intr(sc); /* XXX clear IRQ status registers */ 1238 splx(s); 1239 1240 #if 1 1241 /* configure interrupts coalescing/mitigation */ 1242 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1243 #else 1244 /* no interrupt mitigation: one interrupt per packet */ 1245 NFE_WRITE(sc, NFE_IMTIMER, 970); 1246 #endif 1247 1248 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1249 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1250 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1251 1252 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1253 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1254 1255 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1256 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC); 1257 1258 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1259 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1260 DELAY(10); 1261 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1262 1263 /* set Rx filter */ 1264 nfe_setmulti(sc); 1265 1266 if ((rc = ether_mediachange(ifp)) != 0) 1267 goto out; 1268 1269 nfe_tick(sc); 1270 1271 /* enable Rx */ 1272 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1273 1274 /* enable Tx */ 1275 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1276 1277 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1278 1279 /* enable interrupts */ 1280 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1281 1282 callout_schedule(&sc->sc_tick_ch, hz); 1283 1284 ifp->if_flags |= IFF_RUNNING; 1285 ifp->if_flags &= ~IFF_OACTIVE; 1286 1287 out: 1288 return rc; 1289 } 1290 1291 void 1292 nfe_stop(struct ifnet *ifp, int disable) 1293 { 1294 struct nfe_softc *sc = ifp->if_softc; 1295 1296 callout_stop(&sc->sc_tick_ch); 1297 1298 ifp->if_timer = 0; 1299 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1300 1301 mii_down(&sc->sc_mii); 1302 1303 /* abort Tx */ 1304 NFE_WRITE(sc, NFE_TX_CTL, 0); 1305 1306 /* disable Rx */ 1307 NFE_WRITE(sc, NFE_RX_CTL, 0); 1308 1309 /* disable interrupts */ 1310 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1311 1312 /* reset Tx and Rx rings */ 1313 nfe_reset_tx_ring(sc, &sc->txq); 1314 nfe_reset_rx_ring(sc, &sc->rxq); 1315 } 1316 1317 int 1318 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1319 { 1320 struct nfe_desc32 *desc32; 1321 struct nfe_desc64 *desc64; 1322 struct nfe_rx_data *data; 1323 struct nfe_jbuf *jbuf; 1324 void **desc; 1325 bus_addr_t physaddr; 1326 int i, nsegs, error, descsize; 1327 1328 if (sc->sc_flags & NFE_40BIT_ADDR) { 1329 desc = (void **)&ring->desc64; 1330 descsize = sizeof (struct nfe_desc64); 1331 } else { 1332 desc = (void **)&ring->desc32; 1333 descsize = sizeof (struct nfe_desc32); 1334 } 1335 1336 ring->cur = ring->next = 0; 1337 ring->bufsz = MCLBYTES; 1338 1339 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1340 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1341 if (error != 0) { 1342 printf("%s: could not create desc DMA map\n", 1343 sc->sc_dev.dv_xname); 1344 goto fail; 1345 } 1346 1347 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1348 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1349 if (error != 0) { 1350 printf("%s: could not allocate DMA memory\n", 1351 sc->sc_dev.dv_xname); 1352 goto fail; 1353 } 1354 1355 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1356 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1357 if (error != 0) { 1358 printf("%s: could not map desc DMA memory\n", 1359 sc->sc_dev.dv_xname); 1360 goto fail; 1361 } 1362 1363 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1364 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1365 if (error != 0) { 1366 printf("%s: could not load desc DMA map\n", 1367 sc->sc_dev.dv_xname); 1368 goto fail; 1369 } 1370 1371 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1372 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1373 1374 if (sc->sc_flags & NFE_USE_JUMBO) { 1375 ring->bufsz = NFE_JBYTES; 1376 if ((error = nfe_jpool_alloc(sc)) != 0) { 1377 printf("%s: could not allocate jumbo frames\n", 1378 sc->sc_dev.dv_xname); 1379 goto fail; 1380 } 1381 } 1382 1383 /* 1384 * Pre-allocate Rx buffers and populate Rx ring. 1385 */ 1386 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1387 data = &sc->rxq.data[i]; 1388 1389 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1390 if (data->m == NULL) { 1391 printf("%s: could not allocate rx mbuf\n", 1392 sc->sc_dev.dv_xname); 1393 error = ENOMEM; 1394 goto fail; 1395 } 1396 1397 if (sc->sc_flags & NFE_USE_JUMBO) { 1398 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1399 printf("%s: could not allocate jumbo buffer\n", 1400 sc->sc_dev.dv_xname); 1401 goto fail; 1402 } 1403 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1404 sc); 1405 1406 physaddr = jbuf->physaddr; 1407 } else { 1408 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1409 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1410 if (error != 0) { 1411 printf("%s: could not create DMA map\n", 1412 sc->sc_dev.dv_xname); 1413 goto fail; 1414 } 1415 MCLGET(data->m, M_DONTWAIT); 1416 if (!(data->m->m_flags & M_EXT)) { 1417 printf("%s: could not allocate mbuf cluster\n", 1418 sc->sc_dev.dv_xname); 1419 error = ENOMEM; 1420 goto fail; 1421 } 1422 1423 error = bus_dmamap_load(sc->sc_dmat, data->map, 1424 mtod(data->m, void *), MCLBYTES, NULL, 1425 BUS_DMA_READ | BUS_DMA_NOWAIT); 1426 if (error != 0) { 1427 printf("%s: could not load rx buf DMA map", 1428 sc->sc_dev.dv_xname); 1429 goto fail; 1430 } 1431 physaddr = data->map->dm_segs[0].ds_addr; 1432 } 1433 1434 if (sc->sc_flags & NFE_40BIT_ADDR) { 1435 desc64 = &sc->rxq.desc64[i]; 1436 #if defined(__LP64__) 1437 desc64->physaddr[0] = htole32(physaddr >> 32); 1438 #endif 1439 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1440 desc64->length = htole16(sc->rxq.bufsz); 1441 desc64->flags = htole16(NFE_RX_READY); 1442 } else { 1443 desc32 = &sc->rxq.desc32[i]; 1444 desc32->physaddr = htole32(physaddr); 1445 desc32->length = htole16(sc->rxq.bufsz); 1446 desc32->flags = htole16(NFE_RX_READY); 1447 } 1448 } 1449 1450 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1451 BUS_DMASYNC_PREWRITE); 1452 1453 return 0; 1454 1455 fail: nfe_free_rx_ring(sc, ring); 1456 return error; 1457 } 1458 1459 void 1460 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1461 { 1462 int i; 1463 1464 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1465 if (sc->sc_flags & NFE_40BIT_ADDR) { 1466 ring->desc64[i].length = htole16(ring->bufsz); 1467 ring->desc64[i].flags = htole16(NFE_RX_READY); 1468 } else { 1469 ring->desc32[i].length = htole16(ring->bufsz); 1470 ring->desc32[i].flags = htole16(NFE_RX_READY); 1471 } 1472 } 1473 1474 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1475 BUS_DMASYNC_PREWRITE); 1476 1477 ring->cur = ring->next = 0; 1478 } 1479 1480 void 1481 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1482 { 1483 struct nfe_rx_data *data; 1484 void *desc; 1485 int i, descsize; 1486 1487 if (sc->sc_flags & NFE_40BIT_ADDR) { 1488 desc = ring->desc64; 1489 descsize = sizeof (struct nfe_desc64); 1490 } else { 1491 desc = ring->desc32; 1492 descsize = sizeof (struct nfe_desc32); 1493 } 1494 1495 if (desc != NULL) { 1496 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1497 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1498 bus_dmamap_unload(sc->sc_dmat, ring->map); 1499 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1500 NFE_RX_RING_COUNT * descsize); 1501 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1502 } 1503 1504 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1505 data = &ring->data[i]; 1506 1507 if (data->map != NULL) { 1508 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1509 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1510 bus_dmamap_unload(sc->sc_dmat, data->map); 1511 bus_dmamap_destroy(sc->sc_dmat, data->map); 1512 } 1513 if (data->m != NULL) 1514 m_freem(data->m); 1515 } 1516 } 1517 1518 struct nfe_jbuf * 1519 nfe_jalloc(struct nfe_softc *sc, int i) 1520 { 1521 struct nfe_jbuf *jbuf; 1522 1523 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1524 if (jbuf == NULL) 1525 return NULL; 1526 sc->rxq.jbufmap[i] = 1527 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1528 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1529 return jbuf; 1530 } 1531 1532 /* 1533 * This is called automatically by the network stack when the mbuf is freed. 1534 * Caution must be taken that the NIC might be reset by the time the mbuf is 1535 * freed. 1536 */ 1537 void 1538 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1539 { 1540 struct nfe_softc *sc = arg; 1541 struct nfe_jbuf *jbuf; 1542 int i; 1543 1544 /* find the jbuf from the base pointer */ 1545 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1546 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1547 printf("%s: request to free a buffer (%p) not managed by us\n", 1548 sc->sc_dev.dv_xname, buf); 1549 return; 1550 } 1551 jbuf = &sc->rxq.jbuf[i]; 1552 1553 /* ..and put it back in the free list */ 1554 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1555 1556 if (m != NULL) 1557 pool_cache_put(mb_cache, m); 1558 } 1559 1560 int 1561 nfe_jpool_alloc(struct nfe_softc *sc) 1562 { 1563 struct nfe_rx_ring *ring = &sc->rxq; 1564 struct nfe_jbuf *jbuf; 1565 bus_addr_t physaddr; 1566 char *buf; 1567 int i, nsegs, error; 1568 1569 /* 1570 * Allocate a big chunk of DMA'able memory. 1571 */ 1572 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1573 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1574 if (error != 0) { 1575 printf("%s: could not create jumbo DMA map\n", 1576 sc->sc_dev.dv_xname); 1577 goto fail; 1578 } 1579 1580 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1581 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1582 if (error != 0) { 1583 printf("%s could not allocate jumbo DMA memory\n", 1584 sc->sc_dev.dv_xname); 1585 goto fail; 1586 } 1587 1588 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1589 &ring->jpool, BUS_DMA_NOWAIT); 1590 if (error != 0) { 1591 printf("%s: could not map jumbo DMA memory\n", 1592 sc->sc_dev.dv_xname); 1593 goto fail; 1594 } 1595 1596 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1597 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1598 if (error != 0) { 1599 printf("%s: could not load jumbo DMA map\n", 1600 sc->sc_dev.dv_xname); 1601 goto fail; 1602 } 1603 1604 /* ..and split it into 9KB chunks */ 1605 SLIST_INIT(&ring->jfreelist); 1606 1607 buf = ring->jpool; 1608 physaddr = ring->jmap->dm_segs[0].ds_addr; 1609 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1610 jbuf = &ring->jbuf[i]; 1611 1612 jbuf->buf = buf; 1613 jbuf->physaddr = physaddr; 1614 1615 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1616 1617 buf += NFE_JBYTES; 1618 physaddr += NFE_JBYTES; 1619 } 1620 1621 return 0; 1622 1623 fail: nfe_jpool_free(sc); 1624 return error; 1625 } 1626 1627 void 1628 nfe_jpool_free(struct nfe_softc *sc) 1629 { 1630 struct nfe_rx_ring *ring = &sc->rxq; 1631 1632 if (ring->jmap != NULL) { 1633 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1634 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1635 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1636 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1637 } 1638 if (ring->jpool != NULL) { 1639 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1640 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1641 } 1642 } 1643 1644 int 1645 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1646 { 1647 int i, nsegs, error; 1648 void **desc; 1649 int descsize; 1650 1651 if (sc->sc_flags & NFE_40BIT_ADDR) { 1652 desc = (void **)&ring->desc64; 1653 descsize = sizeof (struct nfe_desc64); 1654 } else { 1655 desc = (void **)&ring->desc32; 1656 descsize = sizeof (struct nfe_desc32); 1657 } 1658 1659 ring->queued = 0; 1660 ring->cur = ring->next = 0; 1661 1662 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1663 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1664 1665 if (error != 0) { 1666 printf("%s: could not create desc DMA map\n", 1667 sc->sc_dev.dv_xname); 1668 goto fail; 1669 } 1670 1671 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1672 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1673 if (error != 0) { 1674 printf("%s: could not allocate DMA memory\n", 1675 sc->sc_dev.dv_xname); 1676 goto fail; 1677 } 1678 1679 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1680 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1681 if (error != 0) { 1682 printf("%s: could not map desc DMA memory\n", 1683 sc->sc_dev.dv_xname); 1684 goto fail; 1685 } 1686 1687 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1688 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1689 if (error != 0) { 1690 printf("%s: could not load desc DMA map\n", 1691 sc->sc_dev.dv_xname); 1692 goto fail; 1693 } 1694 1695 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1696 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1697 1698 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1699 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1700 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1701 &ring->data[i].map); 1702 if (error != 0) { 1703 printf("%s: could not create DMA map\n", 1704 sc->sc_dev.dv_xname); 1705 goto fail; 1706 } 1707 } 1708 1709 return 0; 1710 1711 fail: nfe_free_tx_ring(sc, ring); 1712 return error; 1713 } 1714 1715 void 1716 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1717 { 1718 struct nfe_tx_data *data; 1719 int i; 1720 1721 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1722 if (sc->sc_flags & NFE_40BIT_ADDR) 1723 ring->desc64[i].flags = 0; 1724 else 1725 ring->desc32[i].flags = 0; 1726 1727 data = &ring->data[i]; 1728 1729 if (data->m != NULL) { 1730 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1731 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1732 bus_dmamap_unload(sc->sc_dmat, data->active); 1733 m_freem(data->m); 1734 data->m = NULL; 1735 } 1736 } 1737 1738 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1739 BUS_DMASYNC_PREWRITE); 1740 1741 ring->queued = 0; 1742 ring->cur = ring->next = 0; 1743 } 1744 1745 void 1746 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1747 { 1748 struct nfe_tx_data *data; 1749 void *desc; 1750 int i, descsize; 1751 1752 if (sc->sc_flags & NFE_40BIT_ADDR) { 1753 desc = ring->desc64; 1754 descsize = sizeof (struct nfe_desc64); 1755 } else { 1756 desc = ring->desc32; 1757 descsize = sizeof (struct nfe_desc32); 1758 } 1759 1760 if (desc != NULL) { 1761 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1762 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1763 bus_dmamap_unload(sc->sc_dmat, ring->map); 1764 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1765 NFE_TX_RING_COUNT * descsize); 1766 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1767 } 1768 1769 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1770 data = &ring->data[i]; 1771 1772 if (data->m != NULL) { 1773 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1774 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1775 bus_dmamap_unload(sc->sc_dmat, data->active); 1776 m_freem(data->m); 1777 } 1778 } 1779 1780 /* ..and now actually destroy the DMA mappings */ 1781 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1782 data = &ring->data[i]; 1783 if (data->map == NULL) 1784 continue; 1785 bus_dmamap_destroy(sc->sc_dmat, data->map); 1786 } 1787 } 1788 1789 void 1790 nfe_setmulti(struct nfe_softc *sc) 1791 { 1792 struct ethercom *ec = &sc->sc_ethercom; 1793 struct ifnet *ifp = &ec->ec_if; 1794 struct ether_multi *enm; 1795 struct ether_multistep step; 1796 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1797 uint32_t filter = NFE_RXFILTER_MAGIC; 1798 int i; 1799 1800 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1801 bzero(addr, ETHER_ADDR_LEN); 1802 bzero(mask, ETHER_ADDR_LEN); 1803 goto done; 1804 } 1805 1806 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1807 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1808 1809 ETHER_FIRST_MULTI(step, ec, enm); 1810 while (enm != NULL) { 1811 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1812 ifp->if_flags |= IFF_ALLMULTI; 1813 bzero(addr, ETHER_ADDR_LEN); 1814 bzero(mask, ETHER_ADDR_LEN); 1815 goto done; 1816 } 1817 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1818 addr[i] &= enm->enm_addrlo[i]; 1819 mask[i] &= ~enm->enm_addrlo[i]; 1820 } 1821 ETHER_NEXT_MULTI(step, enm); 1822 } 1823 for (i = 0; i < ETHER_ADDR_LEN; i++) 1824 mask[i] |= addr[i]; 1825 1826 done: 1827 addr[0] |= 0x01; /* make sure multicast bit is set */ 1828 1829 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1830 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1831 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1832 addr[5] << 8 | addr[4]); 1833 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1834 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1835 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1836 mask[5] << 8 | mask[4]); 1837 1838 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1839 NFE_WRITE(sc, NFE_RXFILTER, filter); 1840 } 1841 1842 void 1843 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1844 { 1845 uint32_t tmp; 1846 1847 if ((sc->sc_flags & NFE_CORRECT_MACADDR) == 0) { 1848 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1849 addr[0] = (tmp >> 8) & 0xff; 1850 addr[1] = (tmp & 0xff); 1851 1852 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1853 addr[2] = (tmp >> 24) & 0xff; 1854 addr[3] = (tmp >> 16) & 0xff; 1855 addr[4] = (tmp >> 8) & 0xff; 1856 addr[5] = (tmp & 0xff); 1857 } else { 1858 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1859 addr[5] = (tmp >> 8) & 0xff; 1860 addr[4] = (tmp & 0xff); 1861 1862 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1863 addr[3] = (tmp >> 24) & 0xff; 1864 addr[2] = (tmp >> 16) & 0xff; 1865 addr[1] = (tmp >> 8) & 0xff; 1866 addr[0] = (tmp & 0xff); 1867 } 1868 } 1869 1870 void 1871 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1872 { 1873 NFE_WRITE(sc, NFE_MACADDR_LO, 1874 addr[5] << 8 | addr[4]); 1875 NFE_WRITE(sc, NFE_MACADDR_HI, 1876 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1877 } 1878 1879 void 1880 nfe_tick(void *arg) 1881 { 1882 struct nfe_softc *sc = arg; 1883 int s; 1884 1885 s = splnet(); 1886 mii_tick(&sc->sc_mii); 1887 splx(s); 1888 1889 callout_schedule(&sc->sc_tick_ch, hz); 1890 } 1891
Indexes created Tue Sep 30 07:10:03 GMT 2025