if_nfe.c revision 1.28
1 /* $NetBSD: if_nfe.c,v 1.28 2008/02/07 01:21:56 dyoung Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.52 2006/03/02 09:04:00 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.28 2008/02/07 01:21:56 dyoung Exp $"); 25 26 #include "opt_inet.h" 27 #include "bpfilter.h" 28 #include "vlan.h" 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/types.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/queue.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/socket.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/pci/if_nfereg.h> 74 #include <dev/pci/if_nfevar.h> 75 76 int nfe_match(struct device *, struct cfdata *, void *); 77 void nfe_attach(struct device *, struct device *, void *); 78 void nfe_power(int, void *); 79 void nfe_miibus_statchg(struct device *); 80 int nfe_miibus_readreg(struct device *, int, int); 81 void nfe_miibus_writereg(struct device *, int, int, int); 82 int nfe_intr(void *); 83 int nfe_ioctl(struct ifnet *, u_long, void *); 84 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 85 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 86 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 87 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 88 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 89 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 90 void nfe_rxeof(struct nfe_softc *); 91 void nfe_txeof(struct nfe_softc *); 92 int nfe_encap(struct nfe_softc *, struct mbuf *); 93 void nfe_start(struct ifnet *); 94 void nfe_watchdog(struct ifnet *); 95 int nfe_init(struct ifnet *); 96 void nfe_stop(struct ifnet *, int); 97 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 98 void nfe_jfree(struct mbuf *, void *, size_t, void *); 99 int nfe_jpool_alloc(struct nfe_softc *); 100 void nfe_jpool_free(struct nfe_softc *); 101 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 102 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 105 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 void nfe_setmulti(struct nfe_softc *); 108 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 109 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 110 void nfe_tick(void *); 111 112 CFATTACH_DECL(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, NULL, NULL); 113 114 /*#define NFE_NO_JUMBO*/ 115 116 #ifdef NFE_DEBUG 117 int nfedebug = 0; 118 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 119 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 120 #else 121 #define DPRINTF(x) 122 #define DPRINTFN(n,x) 123 #endif 124 125 /* deal with naming differences */ 126 127 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 128 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 129 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 130 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 132 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 133 134 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 135 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 136 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 137 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 138 139 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 140 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 141 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 142 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 143 144 #ifdef _LP64 145 #define __LP64__ 1 146 #endif 147 148 const struct nfe_product { 149 pci_vendor_id_t vendor; 150 pci_product_id_t product; 151 } nfe_devices[] = { 152 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 153 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 155 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 } 183 }; 184 185 int 186 nfe_match(struct device *dev, struct cfdata *match, void *aux) 187 { 188 struct pci_attach_args *pa = aux; 189 const struct nfe_product *np; 190 int i; 191 192 for (i = 0; i < sizeof(nfe_devices) / sizeof(nfe_devices[0]); i++) { 193 np = &nfe_devices[i]; 194 if (PCI_VENDOR(pa->pa_id) == np->vendor && 195 PCI_PRODUCT(pa->pa_id) == np->product) 196 return 1; 197 } 198 return 0; 199 } 200 201 void 202 nfe_attach(struct device *parent, struct device *self, void *aux) 203 { 204 struct nfe_softc *sc = (struct nfe_softc *)self; 205 struct pci_attach_args *pa = aux; 206 pci_chipset_tag_t pc = pa->pa_pc; 207 pci_intr_handle_t ih; 208 const char *intrstr; 209 struct ifnet *ifp; 210 bus_size_t memsize; 211 pcireg_t memtype; 212 char devinfo[256]; 213 214 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 215 aprint_normal(": %s (rev. 0x%02x)\n", 216 devinfo, PCI_REVISION(pa->pa_class)); 217 218 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 219 switch (memtype) { 220 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 221 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 222 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 223 &sc->sc_memh, NULL, &memsize) == 0) 224 break; 225 /* FALLTHROUGH */ 226 default: 227 printf("%s: could not map mem space\n", sc->sc_dev.dv_xname); 228 return; 229 } 230 231 if (pci_intr_map(pa, &ih) != 0) { 232 printf("%s: could not map interrupt\n", sc->sc_dev.dv_xname); 233 return; 234 } 235 236 intrstr = pci_intr_string(pc, ih); 237 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 238 if (sc->sc_ih == NULL) { 239 printf("%s: could not establish interrupt", 240 sc->sc_dev.dv_xname); 241 if (intrstr != NULL) 242 printf(" at %s", intrstr); 243 printf("\n"); 244 return; 245 } 246 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 247 248 sc->sc_dmat = pa->pa_dmat; 249 250 /* Check for reversed ethernet address */ 251 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 252 sc->sc_flags |= NFE_CORRECT_MACADDR; 253 254 nfe_get_macaddr(sc, sc->sc_enaddr); 255 printf("%s: Ethernet address %s\n", 256 sc->sc_dev.dv_xname, ether_sprintf(sc->sc_enaddr)); 257 258 sc->sc_flags = 0; 259 260 switch (PCI_PRODUCT(pa->pa_id)) { 261 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 262 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 263 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 264 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 265 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 266 break; 267 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 268 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 269 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 270 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 271 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 272 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 273 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 274 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 275 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 276 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 277 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 278 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 279 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 280 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 281 sc->sc_flags |= NFE_40BIT_ADDR |NFE_PWR_MGMT; 282 break; 283 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 284 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 285 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 286 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 287 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 288 break; 289 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 290 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 291 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 292 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 293 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 294 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 295 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 296 NFE_HW_VLAN | NFE_PWR_MGMT; 297 break; 298 } 299 300 if ((sc->sc_flags & NFE_PWR_MGMT) != 0) { 301 /* wakeup some newer chips from powerdown mode */ 302 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 303 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 304 DELAY(100); 305 NFE_WRITE(sc, NFE_MAC_RESET, 0); 306 DELAY(100); 307 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 308 NFE_WRITE(sc, NFE_PWR2_CTL, 309 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_WAKEUP_MASK); 310 } 311 312 #ifndef NFE_NO_JUMBO 313 /* enable jumbo frames for adapters that support it */ 314 if (sc->sc_flags & NFE_JUMBO_SUP) 315 sc->sc_flags |= NFE_USE_JUMBO; 316 #endif 317 318 /* 319 * Allocate Tx and Rx rings. 320 */ 321 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 322 printf("%s: could not allocate Tx ring\n", 323 sc->sc_dev.dv_xname); 324 return; 325 } 326 327 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 328 printf("%s: could not allocate Rx ring\n", 329 sc->sc_dev.dv_xname); 330 nfe_free_tx_ring(sc, &sc->txq); 331 return; 332 } 333 334 ifp = &sc->sc_ethercom.ec_if; 335 ifp->if_softc = sc; 336 ifp->if_mtu = ETHERMTU; 337 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 338 ifp->if_ioctl = nfe_ioctl; 339 ifp->if_start = nfe_start; 340 ifp->if_stop = nfe_stop; 341 ifp->if_watchdog = nfe_watchdog; 342 ifp->if_init = nfe_init; 343 ifp->if_baudrate = IF_Gbps(1); 344 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 345 IFQ_SET_READY(&ifp->if_snd); 346 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 347 348 #if NVLAN > 0 349 if (sc->sc_flags & NFE_HW_VLAN) 350 sc->sc_ethercom.ec_capabilities |= 351 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 352 #endif 353 if (sc->sc_flags & NFE_HW_CSUM) { 354 ifp->if_capabilities |= 355 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 356 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 357 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 358 } 359 360 sc->sc_mii.mii_ifp = ifp; 361 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 362 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 363 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 364 365 sc->sc_ethercom.ec_mii = &sc->sc_mii; 366 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 367 ether_mediastatus); 368 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 369 MII_OFFSET_ANY, 0); 370 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 371 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 372 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 373 0, NULL); 374 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 375 } else 376 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 377 378 if_attach(ifp); 379 ether_ifattach(ifp, sc->sc_enaddr); 380 381 callout_init(&sc->sc_tick_ch, 0); 382 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 383 384 if (!pmf_device_register(self, NULL, NULL)) 385 aprint_error_dev(self, "couldn't establish power handler\n"); 386 else 387 pmf_class_network_register(self, ifp); 388 } 389 390 void 391 nfe_miibus_statchg(struct device *dev) 392 { 393 struct nfe_softc *sc = (struct nfe_softc *)dev; 394 struct mii_data *mii = &sc->sc_mii; 395 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 396 397 phy = NFE_READ(sc, NFE_PHY_IFACE); 398 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 399 400 seed = NFE_READ(sc, NFE_RNDSEED); 401 seed &= ~NFE_SEED_MASK; 402 403 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 404 phy |= NFE_PHY_HDX; /* half-duplex */ 405 misc |= NFE_MISC1_HDX; 406 } 407 408 switch (IFM_SUBTYPE(mii->mii_media_active)) { 409 case IFM_1000_T: /* full-duplex only */ 410 link |= NFE_MEDIA_1000T; 411 seed |= NFE_SEED_1000T; 412 phy |= NFE_PHY_1000T; 413 break; 414 case IFM_100_TX: 415 link |= NFE_MEDIA_100TX; 416 seed |= NFE_SEED_100TX; 417 phy |= NFE_PHY_100TX; 418 break; 419 case IFM_10_T: 420 link |= NFE_MEDIA_10T; 421 seed |= NFE_SEED_10T; 422 break; 423 } 424 425 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 426 427 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 428 NFE_WRITE(sc, NFE_MISC1, misc); 429 NFE_WRITE(sc, NFE_LINKSPEED, link); 430 } 431 432 int 433 nfe_miibus_readreg(struct device *dev, int phy, int reg) 434 { 435 struct nfe_softc *sc = (struct nfe_softc *)dev; 436 uint32_t val; 437 int ntries; 438 439 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 440 441 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 442 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 443 DELAY(100); 444 } 445 446 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 447 448 for (ntries = 0; ntries < 1000; ntries++) { 449 DELAY(100); 450 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 451 break; 452 } 453 if (ntries == 1000) { 454 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 455 sc->sc_dev.dv_xname)); 456 return 0; 457 } 458 459 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 460 DPRINTFN(2, ("%s: could not read PHY\n", 461 sc->sc_dev.dv_xname)); 462 return 0; 463 } 464 465 val = NFE_READ(sc, NFE_PHY_DATA); 466 if (val != 0xffffffff && val != 0) 467 sc->mii_phyaddr = phy; 468 469 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 470 sc->sc_dev.dv_xname, phy, reg, val)); 471 472 return val; 473 } 474 475 void 476 nfe_miibus_writereg(struct device *dev, int phy, int reg, int val) 477 { 478 struct nfe_softc *sc = (struct nfe_softc *)dev; 479 uint32_t ctl; 480 int ntries; 481 482 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 483 484 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 485 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 486 DELAY(100); 487 } 488 489 NFE_WRITE(sc, NFE_PHY_DATA, val); 490 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 491 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 492 493 for (ntries = 0; ntries < 1000; ntries++) { 494 DELAY(100); 495 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 496 break; 497 } 498 #ifdef NFE_DEBUG 499 if (nfedebug >= 2 && ntries == 1000) 500 printf("could not write to PHY\n"); 501 #endif 502 } 503 504 int 505 nfe_intr(void *arg) 506 { 507 struct nfe_softc *sc = arg; 508 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 509 uint32_t r; 510 int handled; 511 512 if ((ifp->if_flags & IFF_UP) == 0) 513 return 0; 514 515 handled = 0; 516 517 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 518 519 for (;;) { 520 r = NFE_READ(sc, NFE_IRQ_STATUS); 521 if ((r & NFE_IRQ_WANTED) == 0) 522 break; 523 524 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 525 handled = 1; 526 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 527 528 if ((r & (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX)) 529 != 0) { 530 /* check Rx ring */ 531 nfe_rxeof(sc); 532 } 533 534 if ((r & (NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE)) 535 != 0) { 536 /* check Tx ring */ 537 nfe_txeof(sc); 538 } 539 540 if ((r & NFE_IRQ_LINK) != 0) { 541 NFE_READ(sc, NFE_PHY_STATUS); 542 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 543 DPRINTF(("%s: link state changed\n", 544 sc->sc_dev.dv_xname)); 545 } 546 } 547 548 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 549 550 if (handled && !IF_IS_EMPTY(&ifp->if_snd)) 551 nfe_start(ifp); 552 553 return handled; 554 } 555 556 int 557 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 558 { 559 struct nfe_softc *sc = ifp->if_softc; 560 struct ifreq *ifr = (struct ifreq *)data; 561 struct ifaddr *ifa = (struct ifaddr *)data; 562 int s, error = 0; 563 564 s = splnet(); 565 566 switch (cmd) { 567 case SIOCSIFADDR: 568 ifp->if_flags |= IFF_UP; 569 nfe_init(ifp); 570 switch (ifa->ifa_addr->sa_family) { 571 #ifdef INET 572 case AF_INET: 573 arp_ifinit(ifp, ifa); 574 break; 575 #endif 576 default: 577 break; 578 } 579 break; 580 case SIOCSIFMTU: 581 if (ifr->ifr_mtu < ETHERMIN || 582 ((sc->sc_flags & NFE_USE_JUMBO) && 583 ifr->ifr_mtu > ETHERMTU_JUMBO) || 584 (!(sc->sc_flags & NFE_USE_JUMBO) && 585 ifr->ifr_mtu > ETHERMTU)) 586 error = EINVAL; 587 else if ((error = ifioctl_common(ifp, cmd, data)) == ENETRESET) 588 error = 0; 589 break; 590 case SIOCSIFFLAGS: 591 if (ifp->if_flags & IFF_UP) { 592 /* 593 * If only the PROMISC or ALLMULTI flag changes, then 594 * don't do a full re-init of the chip, just update 595 * the Rx filter. 596 */ 597 if ((ifp->if_flags & IFF_RUNNING) && 598 ((ifp->if_flags ^ sc->sc_if_flags) & 599 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 600 nfe_setmulti(sc); 601 else 602 nfe_init(ifp); 603 } else { 604 if (ifp->if_flags & IFF_RUNNING) 605 nfe_stop(ifp, 1); 606 } 607 sc->sc_if_flags = ifp->if_flags; 608 break; 609 default: 610 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 611 break; 612 613 error = 0; 614 615 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 616 ; 617 else if (ifp->if_flags & IFF_RUNNING) 618 nfe_setmulti(sc); 619 break; 620 } 621 622 splx(s); 623 624 return error; 625 } 626 627 void 628 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 629 { 630 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 631 (char *)desc32 - (char *)sc->txq.desc32, 632 sizeof (struct nfe_desc32), ops); 633 } 634 635 void 636 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 637 { 638 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 639 (char *)desc64 - (char *)sc->txq.desc64, 640 sizeof (struct nfe_desc64), ops); 641 } 642 643 void 644 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 645 { 646 if (end > start) { 647 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 648 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 649 (char *)&sc->txq.desc32[end] - 650 (char *)&sc->txq.desc32[start], ops); 651 return; 652 } 653 /* sync from 'start' to end of ring */ 654 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 655 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 656 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 657 (char *)&sc->txq.desc32[start], ops); 658 659 /* sync from start of ring to 'end' */ 660 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 661 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 662 } 663 664 void 665 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 666 { 667 if (end > start) { 668 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 669 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 670 (char *)&sc->txq.desc64[end] - 671 (char *)&sc->txq.desc64[start], ops); 672 return; 673 } 674 /* sync from 'start' to end of ring */ 675 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 676 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 677 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 678 (char *)&sc->txq.desc64[start], ops); 679 680 /* sync from start of ring to 'end' */ 681 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 682 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 683 } 684 685 void 686 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 687 { 688 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 689 (char *)desc32 - (char *)sc->rxq.desc32, 690 sizeof (struct nfe_desc32), ops); 691 } 692 693 void 694 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 695 { 696 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 697 (char *)desc64 - (char *)sc->rxq.desc64, 698 sizeof (struct nfe_desc64), ops); 699 } 700 701 void 702 nfe_rxeof(struct nfe_softc *sc) 703 { 704 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 705 struct nfe_desc32 *desc32; 706 struct nfe_desc64 *desc64; 707 struct nfe_rx_data *data; 708 struct nfe_jbuf *jbuf; 709 struct mbuf *m, *mnew; 710 bus_addr_t physaddr; 711 uint16_t flags; 712 int error, len, i; 713 714 desc32 = NULL; 715 desc64 = NULL; 716 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 717 data = &sc->rxq.data[i]; 718 719 if (sc->sc_flags & NFE_40BIT_ADDR) { 720 desc64 = &sc->rxq.desc64[i]; 721 nfe_rxdesc64_sync(sc, desc64, 722 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 723 724 flags = le16toh(desc64->flags); 725 len = le16toh(desc64->length) & 0x3fff; 726 } else { 727 desc32 = &sc->rxq.desc32[i]; 728 nfe_rxdesc32_sync(sc, desc32, 729 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 730 731 flags = le16toh(desc32->flags); 732 len = le16toh(desc32->length) & 0x3fff; 733 } 734 735 if ((flags & NFE_RX_READY) != 0) 736 break; 737 738 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 739 if ((flags & NFE_RX_VALID_V1) == 0) 740 goto skip; 741 742 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 743 flags &= ~NFE_RX_ERROR; 744 len--; /* fix buffer length */ 745 } 746 } else { 747 if ((flags & NFE_RX_VALID_V2) == 0) 748 goto skip; 749 750 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 751 flags &= ~NFE_RX_ERROR; 752 len--; /* fix buffer length */ 753 } 754 } 755 756 if (flags & NFE_RX_ERROR) { 757 ifp->if_ierrors++; 758 goto skip; 759 } 760 761 /* 762 * Try to allocate a new mbuf for this ring element and load 763 * it before processing the current mbuf. If the ring element 764 * cannot be loaded, drop the received packet and reuse the 765 * old mbuf. In the unlikely case that the old mbuf can't be 766 * reloaded either, explicitly panic. 767 */ 768 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 769 if (mnew == NULL) { 770 ifp->if_ierrors++; 771 goto skip; 772 } 773 774 if (sc->sc_flags & NFE_USE_JUMBO) { 775 physaddr = 776 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 777 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 778 if (len > MCLBYTES) { 779 m_freem(mnew); 780 ifp->if_ierrors++; 781 goto skip1; 782 } 783 MCLGET(mnew, M_DONTWAIT); 784 if ((mnew->m_flags & M_EXT) == 0) { 785 m_freem(mnew); 786 ifp->if_ierrors++; 787 goto skip1; 788 } 789 790 memcpy(mtod(mnew, void *), 791 mtod(data->m, const void *), len); 792 m = mnew; 793 goto mbufcopied; 794 } else { 795 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 796 797 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 798 mtod(data->m, char *) - (char *)sc->rxq.jpool, 799 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 800 801 physaddr = jbuf->physaddr; 802 } 803 } else { 804 MCLGET(mnew, M_DONTWAIT); 805 if ((mnew->m_flags & M_EXT) == 0) { 806 m_freem(mnew); 807 ifp->if_ierrors++; 808 goto skip; 809 } 810 811 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 812 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 813 bus_dmamap_unload(sc->sc_dmat, data->map); 814 815 error = bus_dmamap_load(sc->sc_dmat, data->map, 816 mtod(mnew, void *), MCLBYTES, NULL, 817 BUS_DMA_READ | BUS_DMA_NOWAIT); 818 if (error != 0) { 819 m_freem(mnew); 820 821 /* try to reload the old mbuf */ 822 error = bus_dmamap_load(sc->sc_dmat, data->map, 823 mtod(data->m, void *), MCLBYTES, NULL, 824 BUS_DMA_READ | BUS_DMA_NOWAIT); 825 if (error != 0) { 826 /* very unlikely that it will fail.. */ 827 panic("%s: could not load old rx mbuf", 828 sc->sc_dev.dv_xname); 829 } 830 ifp->if_ierrors++; 831 goto skip; 832 } 833 physaddr = data->map->dm_segs[0].ds_addr; 834 } 835 836 /* 837 * New mbuf successfully loaded, update Rx ring and continue 838 * processing. 839 */ 840 m = data->m; 841 data->m = mnew; 842 843 mbufcopied: 844 /* finalize mbuf */ 845 m->m_pkthdr.len = m->m_len = len; 846 m->m_pkthdr.rcvif = ifp; 847 848 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 849 /* 850 * XXX 851 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 852 */ 853 if (flags & NFE_RX_IP_CSUMOK) { 854 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 855 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 856 sc->sc_dev.dv_xname)); 857 } 858 /* 859 * XXX 860 * no way to check M_CSUM_TCP_UDP_BAD or 861 * other protocols? 862 */ 863 if (flags & NFE_RX_UDP_CSUMOK) { 864 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 865 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 866 sc->sc_dev.dv_xname)); 867 } else if (flags & NFE_RX_TCP_CSUMOK) { 868 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 869 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 870 sc->sc_dev.dv_xname)); 871 } 872 } 873 874 #if NBPFILTER > 0 875 if (ifp->if_bpf) 876 bpf_mtap(ifp->if_bpf, m); 877 #endif 878 ifp->if_ipackets++; 879 (*ifp->if_input)(ifp, m); 880 881 skip1: 882 /* update mapping address in h/w descriptor */ 883 if (sc->sc_flags & NFE_40BIT_ADDR) { 884 #if defined(__LP64__) 885 desc64->physaddr[0] = htole32(physaddr >> 32); 886 #endif 887 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 888 } else { 889 desc32->physaddr = htole32(physaddr); 890 } 891 892 skip: 893 if (sc->sc_flags & NFE_40BIT_ADDR) { 894 desc64->length = htole16(sc->rxq.bufsz); 895 desc64->flags = htole16(NFE_RX_READY); 896 897 nfe_rxdesc64_sync(sc, desc64, 898 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 899 } else { 900 desc32->length = htole16(sc->rxq.bufsz); 901 desc32->flags = htole16(NFE_RX_READY); 902 903 nfe_rxdesc32_sync(sc, desc32, 904 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 905 } 906 } 907 /* update current RX pointer */ 908 sc->rxq.cur = i; 909 } 910 911 void 912 nfe_txeof(struct nfe_softc *sc) 913 { 914 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 915 struct nfe_desc32 *desc32; 916 struct nfe_desc64 *desc64; 917 struct nfe_tx_data *data = NULL; 918 int i; 919 uint16_t flags; 920 921 for (i = sc->txq.next; 922 sc->txq.queued > 0; 923 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 924 if (sc->sc_flags & NFE_40BIT_ADDR) { 925 desc64 = &sc->txq.desc64[i]; 926 nfe_txdesc64_sync(sc, desc64, 927 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 928 929 flags = le16toh(desc64->flags); 930 } else { 931 desc32 = &sc->txq.desc32[i]; 932 nfe_txdesc32_sync(sc, desc32, 933 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 934 935 flags = le16toh(desc32->flags); 936 } 937 938 if ((flags & NFE_TX_VALID) != 0) 939 break; 940 941 data = &sc->txq.data[i]; 942 943 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 944 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 945 data->m == NULL) 946 continue; 947 948 if ((flags & NFE_TX_ERROR_V1) != 0) { 949 printf("%s: tx v1 error 0x%04x\n", 950 sc->sc_dev.dv_xname, flags); 951 ifp->if_oerrors++; 952 } else 953 ifp->if_opackets++; 954 } else { 955 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 956 data->m == NULL) 957 continue; 958 959 if ((flags & NFE_TX_ERROR_V2) != 0) { 960 printf("%s: tx v2 error 0x%04x\n", 961 sc->sc_dev.dv_xname, flags); 962 ifp->if_oerrors++; 963 } else 964 ifp->if_opackets++; 965 } 966 967 if (data->m == NULL) { /* should not get there */ 968 printf("%s: last fragment bit w/o associated mbuf!\n", 969 sc->sc_dev.dv_xname); 970 continue; 971 } 972 973 /* last fragment of the mbuf chain transmitted */ 974 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 975 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 976 bus_dmamap_unload(sc->sc_dmat, data->active); 977 m_freem(data->m); 978 data->m = NULL; 979 } 980 981 sc->txq.next = i; 982 983 if (sc->txq.queued < NFE_TX_RING_COUNT) { 984 /* at least one slot freed */ 985 ifp->if_flags &= ~IFF_OACTIVE; 986 } 987 988 if (sc->txq.queued == 0) { 989 /* all queued packets are sent */ 990 ifp->if_timer = 0; 991 } 992 } 993 994 int 995 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 996 { 997 struct nfe_desc32 *desc32; 998 struct nfe_desc64 *desc64; 999 struct nfe_tx_data *data; 1000 bus_dmamap_t map; 1001 uint16_t flags, csumflags; 1002 #if NVLAN > 0 1003 struct m_tag *mtag; 1004 uint32_t vtag = 0; 1005 #endif 1006 int error, i, first; 1007 1008 desc32 = NULL; 1009 desc64 = NULL; 1010 data = NULL; 1011 1012 flags = 0; 1013 csumflags = 0; 1014 first = sc->txq.cur; 1015 1016 map = sc->txq.data[first].map; 1017 1018 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1019 if (error != 0) { 1020 printf("%s: could not map mbuf (error %d)\n", 1021 sc->sc_dev.dv_xname, error); 1022 return error; 1023 } 1024 1025 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1026 bus_dmamap_unload(sc->sc_dmat, map); 1027 return ENOBUFS; 1028 } 1029 1030 #if NVLAN > 0 1031 /* setup h/w VLAN tagging */ 1032 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1033 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1034 #endif 1035 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1036 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1037 csumflags |= NFE_TX_IP_CSUM; 1038 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1039 csumflags |= NFE_TX_TCP_UDP_CSUM; 1040 } 1041 1042 for (i = 0; i < map->dm_nsegs; i++) { 1043 data = &sc->txq.data[sc->txq.cur]; 1044 1045 if (sc->sc_flags & NFE_40BIT_ADDR) { 1046 desc64 = &sc->txq.desc64[sc->txq.cur]; 1047 #if defined(__LP64__) 1048 desc64->physaddr[0] = 1049 htole32(map->dm_segs[i].ds_addr >> 32); 1050 #endif 1051 desc64->physaddr[1] = 1052 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1053 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1054 desc64->flags = htole16(flags); 1055 desc64->vtag = 0; 1056 } else { 1057 desc32 = &sc->txq.desc32[sc->txq.cur]; 1058 1059 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1060 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1061 desc32->flags = htole16(flags); 1062 } 1063 1064 /* 1065 * Setting of the valid bit in the first descriptor is 1066 * deferred until the whole chain is fully setup. 1067 */ 1068 flags |= NFE_TX_VALID; 1069 1070 sc->txq.queued++; 1071 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1072 } 1073 1074 /* the whole mbuf chain has been setup */ 1075 if (sc->sc_flags & NFE_40BIT_ADDR) { 1076 /* fix last descriptor */ 1077 flags |= NFE_TX_LASTFRAG_V2; 1078 desc64->flags = htole16(flags); 1079 1080 /* Checksum flags and vtag belong to the first fragment only. */ 1081 #if NVLAN > 0 1082 sc->txq.desc64[first].vtag = htole32(vtag); 1083 #endif 1084 sc->txq.desc64[first].flags |= htole16(csumflags); 1085 1086 /* finally, set the valid bit in the first descriptor */ 1087 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1088 } else { 1089 /* fix last descriptor */ 1090 if (sc->sc_flags & NFE_JUMBO_SUP) 1091 flags |= NFE_TX_LASTFRAG_V2; 1092 else 1093 flags |= NFE_TX_LASTFRAG_V1; 1094 desc32->flags = htole16(flags); 1095 1096 /* Checksum flags belong to the first fragment only. */ 1097 sc->txq.desc32[first].flags |= htole16(csumflags); 1098 1099 /* finally, set the valid bit in the first descriptor */ 1100 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1101 } 1102 1103 data->m = m0; 1104 data->active = map; 1105 1106 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1107 BUS_DMASYNC_PREWRITE); 1108 1109 return 0; 1110 } 1111 1112 void 1113 nfe_start(struct ifnet *ifp) 1114 { 1115 struct nfe_softc *sc = ifp->if_softc; 1116 int old = sc->txq.queued; 1117 struct mbuf *m0; 1118 1119 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 1120 return; 1121 1122 for (;;) { 1123 IFQ_POLL(&ifp->if_snd, m0); 1124 if (m0 == NULL) 1125 break; 1126 1127 if (nfe_encap(sc, m0) != 0) { 1128 ifp->if_flags |= IFF_OACTIVE; 1129 break; 1130 } 1131 1132 /* packet put in h/w queue, remove from s/w queue */ 1133 IFQ_DEQUEUE(&ifp->if_snd, m0); 1134 1135 #if NBPFILTER > 0 1136 if (ifp->if_bpf != NULL) 1137 bpf_mtap(ifp->if_bpf, m0); 1138 #endif 1139 } 1140 1141 if (sc->txq.queued != old) { 1142 /* packets are queued */ 1143 if (sc->sc_flags & NFE_40BIT_ADDR) 1144 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1145 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1146 else 1147 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1148 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1149 /* kick Tx */ 1150 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1151 1152 /* 1153 * Set a timeout in case the chip goes out to lunch. 1154 */ 1155 ifp->if_timer = 5; 1156 } 1157 } 1158 1159 void 1160 nfe_watchdog(struct ifnet *ifp) 1161 { 1162 struct nfe_softc *sc = ifp->if_softc; 1163 1164 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1165 1166 ifp->if_flags &= ~IFF_RUNNING; 1167 nfe_init(ifp); 1168 1169 ifp->if_oerrors++; 1170 } 1171 1172 int 1173 nfe_init(struct ifnet *ifp) 1174 { 1175 struct nfe_softc *sc = ifp->if_softc; 1176 uint32_t tmp; 1177 int rc = 0, s; 1178 1179 if (ifp->if_flags & IFF_RUNNING) 1180 return 0; 1181 1182 nfe_stop(ifp, 0); 1183 1184 NFE_WRITE(sc, NFE_TX_UNK, 0); 1185 NFE_WRITE(sc, NFE_STATUS, 0); 1186 1187 sc->rxtxctl = NFE_RXTX_BIT2; 1188 if (sc->sc_flags & NFE_40BIT_ADDR) 1189 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1190 else if (sc->sc_flags & NFE_JUMBO_SUP) 1191 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1192 if (sc->sc_flags & NFE_HW_CSUM) 1193 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1194 #if NVLAN > 0 1195 /* 1196 * Although the adapter is capable of stripping VLAN tags from received 1197 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1198 * purpose. This will be done in software by our network stack. 1199 */ 1200 if (sc->sc_flags & NFE_HW_VLAN) 1201 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1202 #endif 1203 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1204 DELAY(10); 1205 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1206 1207 #if NVLAN 1208 if (sc->sc_flags & NFE_HW_VLAN) 1209 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1210 #endif 1211 1212 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1213 1214 /* set MAC address */ 1215 nfe_set_macaddr(sc, sc->sc_enaddr); 1216 1217 /* tell MAC where rings are in memory */ 1218 #ifdef __LP64__ 1219 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1220 #endif 1221 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1222 #ifdef __LP64__ 1223 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1224 #endif 1225 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1226 1227 NFE_WRITE(sc, NFE_RING_SIZE, 1228 (NFE_RX_RING_COUNT - 1) << 16 | 1229 (NFE_TX_RING_COUNT - 1)); 1230 1231 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1232 1233 /* force MAC to wakeup */ 1234 tmp = NFE_READ(sc, NFE_PWR_STATE); 1235 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1236 DELAY(10); 1237 tmp = NFE_READ(sc, NFE_PWR_STATE); 1238 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1239 1240 s = splnet(); 1241 nfe_intr(sc); /* XXX clear IRQ status registers */ 1242 splx(s); 1243 1244 #if 1 1245 /* configure interrupts coalescing/mitigation */ 1246 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1247 #else 1248 /* no interrupt mitigation: one interrupt per packet */ 1249 NFE_WRITE(sc, NFE_IMTIMER, 970); 1250 #endif 1251 1252 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1253 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1254 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1255 1256 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1257 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1258 1259 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1260 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC); 1261 1262 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1263 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1264 DELAY(10); 1265 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1266 1267 /* set Rx filter */ 1268 nfe_setmulti(sc); 1269 1270 if ((rc = ether_mediachange(ifp)) != 0) 1271 goto out; 1272 1273 nfe_tick(sc); 1274 1275 /* enable Rx */ 1276 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1277 1278 /* enable Tx */ 1279 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1280 1281 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1282 1283 /* enable interrupts */ 1284 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1285 1286 callout_schedule(&sc->sc_tick_ch, hz); 1287 1288 ifp->if_flags |= IFF_RUNNING; 1289 ifp->if_flags &= ~IFF_OACTIVE; 1290 1291 out: 1292 return rc; 1293 } 1294 1295 void 1296 nfe_stop(struct ifnet *ifp, int disable) 1297 { 1298 struct nfe_softc *sc = ifp->if_softc; 1299 1300 callout_stop(&sc->sc_tick_ch); 1301 1302 ifp->if_timer = 0; 1303 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1304 1305 mii_down(&sc->sc_mii); 1306 1307 /* abort Tx */ 1308 NFE_WRITE(sc, NFE_TX_CTL, 0); 1309 1310 /* disable Rx */ 1311 NFE_WRITE(sc, NFE_RX_CTL, 0); 1312 1313 /* disable interrupts */ 1314 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1315 1316 /* reset Tx and Rx rings */ 1317 nfe_reset_tx_ring(sc, &sc->txq); 1318 nfe_reset_rx_ring(sc, &sc->rxq); 1319 } 1320 1321 int 1322 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1323 { 1324 struct nfe_desc32 *desc32; 1325 struct nfe_desc64 *desc64; 1326 struct nfe_rx_data *data; 1327 struct nfe_jbuf *jbuf; 1328 void **desc; 1329 bus_addr_t physaddr; 1330 int i, nsegs, error, descsize; 1331 1332 if (sc->sc_flags & NFE_40BIT_ADDR) { 1333 desc = (void **)&ring->desc64; 1334 descsize = sizeof (struct nfe_desc64); 1335 } else { 1336 desc = (void **)&ring->desc32; 1337 descsize = sizeof (struct nfe_desc32); 1338 } 1339 1340 ring->cur = ring->next = 0; 1341 ring->bufsz = MCLBYTES; 1342 1343 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1344 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1345 if (error != 0) { 1346 printf("%s: could not create desc DMA map\n", 1347 sc->sc_dev.dv_xname); 1348 goto fail; 1349 } 1350 1351 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1352 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1353 if (error != 0) { 1354 printf("%s: could not allocate DMA memory\n", 1355 sc->sc_dev.dv_xname); 1356 goto fail; 1357 } 1358 1359 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1360 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1361 if (error != 0) { 1362 printf("%s: could not map desc DMA memory\n", 1363 sc->sc_dev.dv_xname); 1364 goto fail; 1365 } 1366 1367 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1368 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1369 if (error != 0) { 1370 printf("%s: could not load desc DMA map\n", 1371 sc->sc_dev.dv_xname); 1372 goto fail; 1373 } 1374 1375 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1376 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1377 1378 if (sc->sc_flags & NFE_USE_JUMBO) { 1379 ring->bufsz = NFE_JBYTES; 1380 if ((error = nfe_jpool_alloc(sc)) != 0) { 1381 printf("%s: could not allocate jumbo frames\n", 1382 sc->sc_dev.dv_xname); 1383 goto fail; 1384 } 1385 } 1386 1387 /* 1388 * Pre-allocate Rx buffers and populate Rx ring. 1389 */ 1390 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1391 data = &sc->rxq.data[i]; 1392 1393 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1394 if (data->m == NULL) { 1395 printf("%s: could not allocate rx mbuf\n", 1396 sc->sc_dev.dv_xname); 1397 error = ENOMEM; 1398 goto fail; 1399 } 1400 1401 if (sc->sc_flags & NFE_USE_JUMBO) { 1402 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1403 printf("%s: could not allocate jumbo buffer\n", 1404 sc->sc_dev.dv_xname); 1405 goto fail; 1406 } 1407 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1408 sc); 1409 1410 physaddr = jbuf->physaddr; 1411 } else { 1412 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1413 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1414 if (error != 0) { 1415 printf("%s: could not create DMA map\n", 1416 sc->sc_dev.dv_xname); 1417 goto fail; 1418 } 1419 MCLGET(data->m, M_DONTWAIT); 1420 if (!(data->m->m_flags & M_EXT)) { 1421 printf("%s: could not allocate mbuf cluster\n", 1422 sc->sc_dev.dv_xname); 1423 error = ENOMEM; 1424 goto fail; 1425 } 1426 1427 error = bus_dmamap_load(sc->sc_dmat, data->map, 1428 mtod(data->m, void *), MCLBYTES, NULL, 1429 BUS_DMA_READ | BUS_DMA_NOWAIT); 1430 if (error != 0) { 1431 printf("%s: could not load rx buf DMA map", 1432 sc->sc_dev.dv_xname); 1433 goto fail; 1434 } 1435 physaddr = data->map->dm_segs[0].ds_addr; 1436 } 1437 1438 if (sc->sc_flags & NFE_40BIT_ADDR) { 1439 desc64 = &sc->rxq.desc64[i]; 1440 #if defined(__LP64__) 1441 desc64->physaddr[0] = htole32(physaddr >> 32); 1442 #endif 1443 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1444 desc64->length = htole16(sc->rxq.bufsz); 1445 desc64->flags = htole16(NFE_RX_READY); 1446 } else { 1447 desc32 = &sc->rxq.desc32[i]; 1448 desc32->physaddr = htole32(physaddr); 1449 desc32->length = htole16(sc->rxq.bufsz); 1450 desc32->flags = htole16(NFE_RX_READY); 1451 } 1452 } 1453 1454 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1455 BUS_DMASYNC_PREWRITE); 1456 1457 return 0; 1458 1459 fail: nfe_free_rx_ring(sc, ring); 1460 return error; 1461 } 1462 1463 void 1464 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1465 { 1466 int i; 1467 1468 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1469 if (sc->sc_flags & NFE_40BIT_ADDR) { 1470 ring->desc64[i].length = htole16(ring->bufsz); 1471 ring->desc64[i].flags = htole16(NFE_RX_READY); 1472 } else { 1473 ring->desc32[i].length = htole16(ring->bufsz); 1474 ring->desc32[i].flags = htole16(NFE_RX_READY); 1475 } 1476 } 1477 1478 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1479 BUS_DMASYNC_PREWRITE); 1480 1481 ring->cur = ring->next = 0; 1482 } 1483 1484 void 1485 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1486 { 1487 struct nfe_rx_data *data; 1488 void *desc; 1489 int i, descsize; 1490 1491 if (sc->sc_flags & NFE_40BIT_ADDR) { 1492 desc = ring->desc64; 1493 descsize = sizeof (struct nfe_desc64); 1494 } else { 1495 desc = ring->desc32; 1496 descsize = sizeof (struct nfe_desc32); 1497 } 1498 1499 if (desc != NULL) { 1500 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1501 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1502 bus_dmamap_unload(sc->sc_dmat, ring->map); 1503 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1504 NFE_RX_RING_COUNT * descsize); 1505 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1506 } 1507 1508 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1509 data = &ring->data[i]; 1510 1511 if (data->map != NULL) { 1512 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1513 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1514 bus_dmamap_unload(sc->sc_dmat, data->map); 1515 bus_dmamap_destroy(sc->sc_dmat, data->map); 1516 } 1517 if (data->m != NULL) 1518 m_freem(data->m); 1519 } 1520 } 1521 1522 struct nfe_jbuf * 1523 nfe_jalloc(struct nfe_softc *sc, int i) 1524 { 1525 struct nfe_jbuf *jbuf; 1526 1527 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1528 if (jbuf == NULL) 1529 return NULL; 1530 sc->rxq.jbufmap[i] = 1531 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1532 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1533 return jbuf; 1534 } 1535 1536 /* 1537 * This is called automatically by the network stack when the mbuf is freed. 1538 * Caution must be taken that the NIC might be reset by the time the mbuf is 1539 * freed. 1540 */ 1541 void 1542 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1543 { 1544 struct nfe_softc *sc = arg; 1545 struct nfe_jbuf *jbuf; 1546 int i; 1547 1548 /* find the jbuf from the base pointer */ 1549 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1550 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1551 printf("%s: request to free a buffer (%p) not managed by us\n", 1552 sc->sc_dev.dv_xname, buf); 1553 return; 1554 } 1555 jbuf = &sc->rxq.jbuf[i]; 1556 1557 /* ..and put it back in the free list */ 1558 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1559 1560 if (m != NULL) 1561 pool_cache_put(mb_cache, m); 1562 } 1563 1564 int 1565 nfe_jpool_alloc(struct nfe_softc *sc) 1566 { 1567 struct nfe_rx_ring *ring = &sc->rxq; 1568 struct nfe_jbuf *jbuf; 1569 bus_addr_t physaddr; 1570 char *buf; 1571 int i, nsegs, error; 1572 1573 /* 1574 * Allocate a big chunk of DMA'able memory. 1575 */ 1576 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1577 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1578 if (error != 0) { 1579 printf("%s: could not create jumbo DMA map\n", 1580 sc->sc_dev.dv_xname); 1581 goto fail; 1582 } 1583 1584 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1585 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1586 if (error != 0) { 1587 printf("%s could not allocate jumbo DMA memory\n", 1588 sc->sc_dev.dv_xname); 1589 goto fail; 1590 } 1591 1592 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1593 &ring->jpool, BUS_DMA_NOWAIT); 1594 if (error != 0) { 1595 printf("%s: could not map jumbo DMA memory\n", 1596 sc->sc_dev.dv_xname); 1597 goto fail; 1598 } 1599 1600 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1601 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1602 if (error != 0) { 1603 printf("%s: could not load jumbo DMA map\n", 1604 sc->sc_dev.dv_xname); 1605 goto fail; 1606 } 1607 1608 /* ..and split it into 9KB chunks */ 1609 SLIST_INIT(&ring->jfreelist); 1610 1611 buf = ring->jpool; 1612 physaddr = ring->jmap->dm_segs[0].ds_addr; 1613 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1614 jbuf = &ring->jbuf[i]; 1615 1616 jbuf->buf = buf; 1617 jbuf->physaddr = physaddr; 1618 1619 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1620 1621 buf += NFE_JBYTES; 1622 physaddr += NFE_JBYTES; 1623 } 1624 1625 return 0; 1626 1627 fail: nfe_jpool_free(sc); 1628 return error; 1629 } 1630 1631 void 1632 nfe_jpool_free(struct nfe_softc *sc) 1633 { 1634 struct nfe_rx_ring *ring = &sc->rxq; 1635 1636 if (ring->jmap != NULL) { 1637 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1638 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1639 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1640 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1641 } 1642 if (ring->jpool != NULL) { 1643 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1644 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1645 } 1646 } 1647 1648 int 1649 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1650 { 1651 int i, nsegs, error; 1652 void **desc; 1653 int descsize; 1654 1655 if (sc->sc_flags & NFE_40BIT_ADDR) { 1656 desc = (void **)&ring->desc64; 1657 descsize = sizeof (struct nfe_desc64); 1658 } else { 1659 desc = (void **)&ring->desc32; 1660 descsize = sizeof (struct nfe_desc32); 1661 } 1662 1663 ring->queued = 0; 1664 ring->cur = ring->next = 0; 1665 1666 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1667 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1668 1669 if (error != 0) { 1670 printf("%s: could not create desc DMA map\n", 1671 sc->sc_dev.dv_xname); 1672 goto fail; 1673 } 1674 1675 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1676 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1677 if (error != 0) { 1678 printf("%s: could not allocate DMA memory\n", 1679 sc->sc_dev.dv_xname); 1680 goto fail; 1681 } 1682 1683 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1684 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1685 if (error != 0) { 1686 printf("%s: could not map desc DMA memory\n", 1687 sc->sc_dev.dv_xname); 1688 goto fail; 1689 } 1690 1691 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1692 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1693 if (error != 0) { 1694 printf("%s: could not load desc DMA map\n", 1695 sc->sc_dev.dv_xname); 1696 goto fail; 1697 } 1698 1699 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1700 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1701 1702 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1703 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1704 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1705 &ring->data[i].map); 1706 if (error != 0) { 1707 printf("%s: could not create DMA map\n", 1708 sc->sc_dev.dv_xname); 1709 goto fail; 1710 } 1711 } 1712 1713 return 0; 1714 1715 fail: nfe_free_tx_ring(sc, ring); 1716 return error; 1717 } 1718 1719 void 1720 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1721 { 1722 struct nfe_tx_data *data; 1723 int i; 1724 1725 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1726 if (sc->sc_flags & NFE_40BIT_ADDR) 1727 ring->desc64[i].flags = 0; 1728 else 1729 ring->desc32[i].flags = 0; 1730 1731 data = &ring->data[i]; 1732 1733 if (data->m != NULL) { 1734 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1735 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1736 bus_dmamap_unload(sc->sc_dmat, data->active); 1737 m_freem(data->m); 1738 data->m = NULL; 1739 } 1740 } 1741 1742 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1743 BUS_DMASYNC_PREWRITE); 1744 1745 ring->queued = 0; 1746 ring->cur = ring->next = 0; 1747 } 1748 1749 void 1750 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1751 { 1752 struct nfe_tx_data *data; 1753 void *desc; 1754 int i, descsize; 1755 1756 if (sc->sc_flags & NFE_40BIT_ADDR) { 1757 desc = ring->desc64; 1758 descsize = sizeof (struct nfe_desc64); 1759 } else { 1760 desc = ring->desc32; 1761 descsize = sizeof (struct nfe_desc32); 1762 } 1763 1764 if (desc != NULL) { 1765 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1766 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1767 bus_dmamap_unload(sc->sc_dmat, ring->map); 1768 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1769 NFE_TX_RING_COUNT * descsize); 1770 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1771 } 1772 1773 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1774 data = &ring->data[i]; 1775 1776 if (data->m != NULL) { 1777 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1778 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1779 bus_dmamap_unload(sc->sc_dmat, data->active); 1780 m_freem(data->m); 1781 } 1782 } 1783 1784 /* ..and now actually destroy the DMA mappings */ 1785 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1786 data = &ring->data[i]; 1787 if (data->map == NULL) 1788 continue; 1789 bus_dmamap_destroy(sc->sc_dmat, data->map); 1790 } 1791 } 1792 1793 void 1794 nfe_setmulti(struct nfe_softc *sc) 1795 { 1796 struct ethercom *ec = &sc->sc_ethercom; 1797 struct ifnet *ifp = &ec->ec_if; 1798 struct ether_multi *enm; 1799 struct ether_multistep step; 1800 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1801 uint32_t filter = NFE_RXFILTER_MAGIC; 1802 int i; 1803 1804 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1805 bzero(addr, ETHER_ADDR_LEN); 1806 bzero(mask, ETHER_ADDR_LEN); 1807 goto done; 1808 } 1809 1810 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1811 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1812 1813 ETHER_FIRST_MULTI(step, ec, enm); 1814 while (enm != NULL) { 1815 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1816 ifp->if_flags |= IFF_ALLMULTI; 1817 bzero(addr, ETHER_ADDR_LEN); 1818 bzero(mask, ETHER_ADDR_LEN); 1819 goto done; 1820 } 1821 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1822 addr[i] &= enm->enm_addrlo[i]; 1823 mask[i] &= ~enm->enm_addrlo[i]; 1824 } 1825 ETHER_NEXT_MULTI(step, enm); 1826 } 1827 for (i = 0; i < ETHER_ADDR_LEN; i++) 1828 mask[i] |= addr[i]; 1829 1830 done: 1831 addr[0] |= 0x01; /* make sure multicast bit is set */ 1832 1833 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1834 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1835 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1836 addr[5] << 8 | addr[4]); 1837 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1838 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1839 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1840 mask[5] << 8 | mask[4]); 1841 1842 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1843 NFE_WRITE(sc, NFE_RXFILTER, filter); 1844 } 1845 1846 void 1847 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1848 { 1849 uint32_t tmp; 1850 1851 if ((sc->sc_flags & NFE_CORRECT_MACADDR) == 0) { 1852 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1853 addr[0] = (tmp >> 8) & 0xff; 1854 addr[1] = (tmp & 0xff); 1855 1856 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1857 addr[2] = (tmp >> 24) & 0xff; 1858 addr[3] = (tmp >> 16) & 0xff; 1859 addr[4] = (tmp >> 8) & 0xff; 1860 addr[5] = (tmp & 0xff); 1861 } else { 1862 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1863 addr[5] = (tmp >> 8) & 0xff; 1864 addr[4] = (tmp & 0xff); 1865 1866 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1867 addr[3] = (tmp >> 24) & 0xff; 1868 addr[2] = (tmp >> 16) & 0xff; 1869 addr[1] = (tmp >> 8) & 0xff; 1870 addr[0] = (tmp & 0xff); 1871 } 1872 } 1873 1874 void 1875 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1876 { 1877 NFE_WRITE(sc, NFE_MACADDR_LO, 1878 addr[5] << 8 | addr[4]); 1879 NFE_WRITE(sc, NFE_MACADDR_HI, 1880 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1881 } 1882 1883 void 1884 nfe_tick(void *arg) 1885 { 1886 struct nfe_softc *sc = arg; 1887 int s; 1888 1889 s = splnet(); 1890 mii_tick(&sc->sc_mii); 1891 splx(s); 1892 1893 callout_schedule(&sc->sc_tick_ch, hz); 1894 } 1895
Indexes created Tue Sep 30 11:09:46 GMT 2025