if_nfe.c revision 1.3
1 /* $NetBSD: if_nfe.c,v 1.3 2006/03/26 00:34:14 chs Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.52 2006/03/02 09:04:00 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.3 2006/03/26 00:34:14 chs Exp $"); 25 26 #include "opt_inet.h" 27 #include "bpfilter.h" 28 #include "vlan.h" 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/types.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/queue.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/socket.h> 41 42 #include <machine/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/pci/if_nfereg.h> 74 #include <dev/pci/if_nfevar.h> 75 76 int nfe_match(struct device *, struct cfdata *, void *); 77 void nfe_attach(struct device *, struct device *, void *); 78 void nfe_power(int, void *); 79 void nfe_miibus_statchg(struct device *); 80 int nfe_miibus_readreg(struct device *, int, int); 81 void nfe_miibus_writereg(struct device *, int, int, int); 82 int nfe_intr(void *); 83 int nfe_ioctl(struct ifnet *, u_long, caddr_t); 84 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 85 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 86 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 87 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 88 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 89 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 90 void nfe_rxeof(struct nfe_softc *); 91 void nfe_txeof(struct nfe_softc *); 92 int nfe_encap(struct nfe_softc *, struct mbuf *); 93 void nfe_start(struct ifnet *); 94 void nfe_watchdog(struct ifnet *); 95 int nfe_init(struct ifnet *); 96 void nfe_stop(struct ifnet *, int); 97 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *); 98 void nfe_jfree(struct mbuf *, caddr_t, size_t, void *); 99 int nfe_jpool_alloc(struct nfe_softc *); 100 void nfe_jpool_free(struct nfe_softc *); 101 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 102 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 105 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 int nfe_ifmedia_upd(struct ifnet *); 108 void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 109 void nfe_setmulti(struct nfe_softc *); 110 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 111 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 112 void nfe_tick(void *); 113 114 CFATTACH_DECL(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, NULL, NULL); 115 116 /*#define NFE_NO_JUMBO*/ 117 118 #ifdef NFE_DEBUG 119 int nfedebug = 0; 120 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 121 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 122 #else 123 #define DPRINTF(x) 124 #define DPRINTFN(n,x) 125 #endif 126 127 /* deal with naming differences */ 128 129 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 130 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 134 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 135 136 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 137 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 140 141 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 142 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 145 146 #ifdef _LP64 147 #define __LP64__ 1 148 #endif 149 150 const struct nfe_product { 151 pci_vendor_id_t vendor; 152 pci_product_id_t product; 153 } nfe_devices[] = { 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 155 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 } 169 }; 170 171 int 172 nfe_match(struct device *dev, struct cfdata *match, void *aux) 173 { 174 struct pci_attach_args *pa = aux; 175 const struct nfe_product *np; 176 int i; 177 178 for (i = 0; i < sizeof(nfe_devices) / sizeof(nfe_devices[0]); i++) { 179 np = &nfe_devices[i]; 180 if (PCI_VENDOR(pa->pa_id) == np->vendor && 181 PCI_PRODUCT(pa->pa_id) == np->product) 182 return 1; 183 } 184 return 0; 185 } 186 187 void 188 nfe_attach(struct device *parent, struct device *self, void *aux) 189 { 190 struct nfe_softc *sc = (struct nfe_softc *)self; 191 struct pci_attach_args *pa = aux; 192 pci_chipset_tag_t pc = pa->pa_pc; 193 pci_intr_handle_t ih; 194 const char *intrstr; 195 struct ifnet *ifp; 196 bus_size_t memsize; 197 pcireg_t memtype; 198 199 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 200 switch (memtype) { 201 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 202 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 203 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 204 &sc->sc_memh, NULL, &memsize) == 0) 205 break; 206 /* FALLTHROUGH */ 207 default: 208 printf(": could not map mem space\n"); 209 return; 210 } 211 212 if (pci_intr_map(pa, &ih) != 0) { 213 printf(": could not map interrupt\n"); 214 return; 215 } 216 217 intrstr = pci_intr_string(pc, ih); 218 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 219 if (sc->sc_ih == NULL) { 220 printf(": could not establish interrupt"); 221 if (intrstr != NULL) 222 printf(" at %s", intrstr); 223 printf("\n"); 224 return; 225 } 226 printf(": %s", intrstr); 227 228 sc->sc_dmat = pa->pa_dmat; 229 230 nfe_get_macaddr(sc, sc->sc_enaddr); 231 printf(", address %s\n", ether_sprintf(sc->sc_enaddr)); 232 233 sc->sc_flags = 0; 234 235 switch (PCI_PRODUCT(pa->pa_id)) { 236 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 237 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 238 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 239 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 240 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 241 break; 242 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 243 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 244 sc->sc_flags |= NFE_40BIT_ADDR; 245 break; 246 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 247 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 248 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 249 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 250 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 251 break; 252 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 253 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 254 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 255 NFE_HW_VLAN; 256 break; 257 } 258 259 #ifndef NFE_NO_JUMBO 260 /* enable jumbo frames for adapters that support it */ 261 if (sc->sc_flags & NFE_JUMBO_SUP) 262 sc->sc_flags |= NFE_USE_JUMBO; 263 #endif 264 265 /* 266 * Allocate Tx and Rx rings. 267 */ 268 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 269 printf("%s: could not allocate Tx ring\n", 270 sc->sc_dev.dv_xname); 271 return; 272 } 273 274 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 275 printf("%s: could not allocate Rx ring\n", 276 sc->sc_dev.dv_xname); 277 nfe_free_tx_ring(sc, &sc->txq); 278 return; 279 } 280 281 ifp = &sc->sc_ethercom.ec_if; 282 ifp->if_softc = sc; 283 ifp->if_mtu = ETHERMTU; 284 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 285 ifp->if_ioctl = nfe_ioctl; 286 ifp->if_start = nfe_start; 287 ifp->if_watchdog = nfe_watchdog; 288 ifp->if_init = nfe_init; 289 ifp->if_baudrate = IF_Gbps(1); 290 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 291 IFQ_SET_READY(&ifp->if_snd); 292 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 293 294 #if NVLAN > 0 295 if (sc->sc_flags & NFE_HW_VLAN) 296 sc->sc_ethercom.ec_capabilities |= 297 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 298 #endif 299 #ifdef NFE_CSUM 300 if (sc->sc_flags & NFE_HW_CSUM) { 301 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 302 IFCAP_CSUM_UDPv4; 303 } 304 #endif 305 306 sc->sc_mii.mii_ifp = ifp; 307 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 308 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 309 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 310 311 ifmedia_init(&sc->sc_mii.mii_media, 0, nfe_ifmedia_upd, 312 nfe_ifmedia_sts); 313 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 314 MII_OFFSET_ANY, 0); 315 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 316 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 317 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 318 0, NULL); 319 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 320 } else 321 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 322 323 if_attach(ifp); 324 ether_ifattach(ifp, sc->sc_enaddr); 325 326 callout_init(&sc->sc_tick_ch); 327 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 328 329 sc->sc_powerhook = powerhook_establish(nfe_power, sc); 330 } 331 332 void 333 nfe_power(int why, void *arg) 334 { 335 struct nfe_softc *sc = arg; 336 struct ifnet *ifp; 337 338 if (why == PWR_RESUME) { 339 ifp = &sc->sc_ethercom.ec_if; 340 if (ifp->if_flags & IFF_UP) { 341 ifp->if_flags &= ~IFF_RUNNING; 342 nfe_init(ifp); 343 if (ifp->if_flags & IFF_RUNNING) 344 nfe_start(ifp); 345 } 346 } 347 } 348 349 void 350 nfe_miibus_statchg(struct device *dev) 351 { 352 struct nfe_softc *sc = (struct nfe_softc *)dev; 353 struct mii_data *mii = &sc->sc_mii; 354 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 355 356 phy = NFE_READ(sc, NFE_PHY_IFACE); 357 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 358 359 seed = NFE_READ(sc, NFE_RNDSEED); 360 seed &= ~NFE_SEED_MASK; 361 362 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 363 phy |= NFE_PHY_HDX; /* half-duplex */ 364 misc |= NFE_MISC1_HDX; 365 } 366 367 switch (IFM_SUBTYPE(mii->mii_media_active)) { 368 case IFM_1000_T: /* full-duplex only */ 369 link |= NFE_MEDIA_1000T; 370 seed |= NFE_SEED_1000T; 371 phy |= NFE_PHY_1000T; 372 break; 373 case IFM_100_TX: 374 link |= NFE_MEDIA_100TX; 375 seed |= NFE_SEED_100TX; 376 phy |= NFE_PHY_100TX; 377 break; 378 case IFM_10_T: 379 link |= NFE_MEDIA_10T; 380 seed |= NFE_SEED_10T; 381 break; 382 } 383 384 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 385 386 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 387 NFE_WRITE(sc, NFE_MISC1, misc); 388 NFE_WRITE(sc, NFE_LINKSPEED, link); 389 } 390 391 int 392 nfe_miibus_readreg(struct device *dev, int phy, int reg) 393 { 394 struct nfe_softc *sc = (struct nfe_softc *)dev; 395 uint32_t val; 396 int ntries; 397 398 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 399 400 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 401 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 402 DELAY(100); 403 } 404 405 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 406 407 for (ntries = 0; ntries < 1000; ntries++) { 408 DELAY(100); 409 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 410 break; 411 } 412 if (ntries == 1000) { 413 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 414 sc->sc_dev.dv_xname)); 415 return 0; 416 } 417 418 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 419 DPRINTFN(2, ("%s: could not read PHY\n", 420 sc->sc_dev.dv_xname)); 421 return 0; 422 } 423 424 val = NFE_READ(sc, NFE_PHY_DATA); 425 if (val != 0xffffffff && val != 0) 426 sc->mii_phyaddr = phy; 427 428 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 429 sc->sc_dev.dv_xname, phy, reg, val)); 430 431 return val; 432 } 433 434 void 435 nfe_miibus_writereg(struct device *dev, int phy, int reg, int val) 436 { 437 struct nfe_softc *sc = (struct nfe_softc *)dev; 438 uint32_t ctl; 439 int ntries; 440 441 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 442 443 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 444 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 445 DELAY(100); 446 } 447 448 NFE_WRITE(sc, NFE_PHY_DATA, val); 449 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 450 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 451 452 for (ntries = 0; ntries < 1000; ntries++) { 453 DELAY(100); 454 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 455 break; 456 } 457 #ifdef NFE_DEBUG 458 if (nfedebug >= 2 && ntries == 1000) 459 printf("could not write to PHY\n"); 460 #endif 461 } 462 463 int 464 nfe_intr(void *arg) 465 { 466 struct nfe_softc *sc = arg; 467 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 468 uint32_t r; 469 470 if ((r = NFE_READ(sc, NFE_IRQ_STATUS)) == 0) 471 return 0; /* not for us */ 472 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 473 474 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 475 476 if (r & NFE_IRQ_LINK) { 477 NFE_READ(sc, NFE_PHY_STATUS); 478 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 479 DPRINTF(("%s: link state changed\n", sc->sc_dev.dv_xname)); 480 } 481 482 if (ifp->if_flags & IFF_RUNNING) { 483 /* check Rx ring */ 484 nfe_rxeof(sc); 485 486 /* check Tx ring */ 487 nfe_txeof(sc); 488 } 489 490 return 1; 491 } 492 493 int 494 nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 495 { 496 struct nfe_softc *sc = ifp->if_softc; 497 struct ifreq *ifr = (struct ifreq *)data; 498 struct ifaddr *ifa = (struct ifaddr *)data; 499 int s, error = 0; 500 501 s = splnet(); 502 503 switch (cmd) { 504 case SIOCSIFADDR: 505 ifp->if_flags |= IFF_UP; 506 nfe_init(ifp); 507 switch (ifa->ifa_addr->sa_family) { 508 #ifdef INET 509 case AF_INET: 510 arp_ifinit(ifp, ifa); 511 break; 512 #endif 513 default: 514 break; 515 } 516 break; 517 case SIOCSIFMTU: 518 if (ifr->ifr_mtu < ETHERMIN || 519 ((sc->sc_flags & NFE_USE_JUMBO) && 520 ifr->ifr_mtu > ETHERMTU_JUMBO) || 521 (!(sc->sc_flags & NFE_USE_JUMBO) && 522 ifr->ifr_mtu > ETHERMTU)) 523 error = EINVAL; 524 else if (ifp->if_mtu != ifr->ifr_mtu) 525 ifp->if_mtu = ifr->ifr_mtu; 526 break; 527 case SIOCSIFFLAGS: 528 if (ifp->if_flags & IFF_UP) { 529 /* 530 * If only the PROMISC or ALLMULTI flag changes, then 531 * don't do a full re-init of the chip, just update 532 * the Rx filter. 533 */ 534 if ((ifp->if_flags & IFF_RUNNING) && 535 ((ifp->if_flags ^ sc->sc_if_flags) & 536 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 537 nfe_setmulti(sc); 538 else 539 nfe_init(ifp); 540 } else { 541 if (ifp->if_flags & IFF_RUNNING) 542 nfe_stop(ifp, 1); 543 } 544 sc->sc_if_flags = ifp->if_flags; 545 break; 546 case SIOCADDMULTI: 547 case SIOCDELMULTI: 548 error = (cmd == SIOCADDMULTI) ? 549 ether_addmulti(ifr, &sc->sc_ethercom) : 550 ether_delmulti(ifr, &sc->sc_ethercom); 551 552 if (error == ENETRESET) { 553 if (ifp->if_flags & IFF_RUNNING) 554 nfe_setmulti(sc); 555 error = 0; 556 } 557 break; 558 case SIOCSIFMEDIA: 559 case SIOCGIFMEDIA: 560 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 561 break; 562 default: 563 error = ether_ioctl(ifp, cmd, data); 564 if (error == ENETRESET) { 565 if (ifp->if_flags & IFF_RUNNING) 566 nfe_setmulti(sc); 567 error = 0; 568 } 569 break; 570 571 } 572 573 splx(s); 574 575 return error; 576 } 577 578 void 579 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 580 { 581 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 582 (caddr_t)desc32 - (caddr_t)sc->txq.desc32, 583 sizeof (struct nfe_desc32), ops); 584 } 585 586 void 587 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 588 { 589 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 590 (caddr_t)desc64 - (caddr_t)sc->txq.desc64, 591 sizeof (struct nfe_desc64), ops); 592 } 593 594 void 595 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 596 { 597 if (end > start) { 598 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 599 (caddr_t)&sc->txq.desc32[start] - (caddr_t)sc->txq.desc32, 600 (caddr_t)&sc->txq.desc32[end] - 601 (caddr_t)&sc->txq.desc32[start], ops); 602 return; 603 } 604 /* sync from 'start' to end of ring */ 605 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 606 (caddr_t)&sc->txq.desc32[start] - (caddr_t)sc->txq.desc32, 607 (caddr_t)&sc->txq.desc32[NFE_TX_RING_COUNT] - 608 (caddr_t)&sc->txq.desc32[start], ops); 609 610 /* sync from start of ring to 'end' */ 611 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 612 (caddr_t)&sc->txq.desc32[end] - (caddr_t)sc->txq.desc32, ops); 613 } 614 615 void 616 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 617 { 618 if (end > start) { 619 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 620 (caddr_t)&sc->txq.desc64[start] - (caddr_t)sc->txq.desc64, 621 (caddr_t)&sc->txq.desc64[end] - 622 (caddr_t)&sc->txq.desc64[start], ops); 623 return; 624 } 625 /* sync from 'start' to end of ring */ 626 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 627 (caddr_t)&sc->txq.desc64[start] - (caddr_t)sc->txq.desc64, 628 (caddr_t)&sc->txq.desc64[NFE_TX_RING_COUNT] - 629 (caddr_t)&sc->txq.desc64[start], ops); 630 631 /* sync from start of ring to 'end' */ 632 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 633 (caddr_t)&sc->txq.desc64[end] - (caddr_t)sc->txq.desc64, ops); 634 } 635 636 void 637 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 638 { 639 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 640 (caddr_t)desc32 - (caddr_t)sc->rxq.desc32, 641 sizeof (struct nfe_desc32), ops); 642 } 643 644 void 645 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 646 { 647 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 648 (caddr_t)desc64 - (caddr_t)sc->rxq.desc64, 649 sizeof (struct nfe_desc64), ops); 650 } 651 652 void 653 nfe_rxeof(struct nfe_softc *sc) 654 { 655 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 656 struct nfe_desc32 *desc32; 657 struct nfe_desc64 *desc64; 658 struct nfe_rx_data *data; 659 struct nfe_jbuf *jbuf; 660 struct mbuf *m, *mnew; 661 bus_addr_t physaddr; 662 uint16_t flags; 663 int error, len; 664 665 desc32 = NULL; 666 desc64 = NULL; 667 for (;;) { 668 data = &sc->rxq.data[sc->rxq.cur]; 669 670 if (sc->sc_flags & NFE_40BIT_ADDR) { 671 desc64 = &sc->rxq.desc64[sc->rxq.cur]; 672 nfe_rxdesc64_sync(sc, desc64, BUS_DMASYNC_POSTREAD); 673 674 flags = le16toh(desc64->flags); 675 len = le16toh(desc64->length) & 0x3fff; 676 } else { 677 desc32 = &sc->rxq.desc32[sc->rxq.cur]; 678 nfe_rxdesc32_sync(sc, desc32, BUS_DMASYNC_POSTREAD); 679 680 flags = le16toh(desc32->flags); 681 len = le16toh(desc32->length) & 0x3fff; 682 } 683 684 if (flags & NFE_RX_READY) 685 break; 686 687 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 688 if (!(flags & NFE_RX_VALID_V1)) 689 goto skip; 690 691 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 692 flags &= ~NFE_RX_ERROR; 693 len--; /* fix buffer length */ 694 } 695 } else { 696 if (!(flags & NFE_RX_VALID_V2)) 697 goto skip; 698 699 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 700 flags &= ~NFE_RX_ERROR; 701 len--; /* fix buffer length */ 702 } 703 } 704 705 if (flags & NFE_RX_ERROR) { 706 ifp->if_ierrors++; 707 goto skip; 708 } 709 710 /* 711 * Try to allocate a new mbuf for this ring element and load 712 * it before processing the current mbuf. If the ring element 713 * cannot be loaded, drop the received packet and reuse the 714 * old mbuf. In the unlikely case that the old mbuf can't be 715 * reloaded either, explicitly panic. 716 */ 717 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 718 if (mnew == NULL) { 719 ifp->if_ierrors++; 720 goto skip; 721 } 722 723 if (sc->sc_flags & NFE_USE_JUMBO) { 724 if ((jbuf = nfe_jalloc(sc)) == NULL) { 725 m_freem(mnew); 726 ifp->if_ierrors++; 727 goto skip; 728 } 729 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 730 731 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 732 mtod(data->m, caddr_t) - sc->rxq.jpool, NFE_JBYTES, 733 BUS_DMASYNC_POSTREAD); 734 735 physaddr = jbuf->physaddr; 736 } else { 737 MCLGET(mnew, M_DONTWAIT); 738 if (!(mnew->m_flags & M_EXT)) { 739 m_freem(mnew); 740 ifp->if_ierrors++; 741 goto skip; 742 } 743 744 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 745 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 746 bus_dmamap_unload(sc->sc_dmat, data->map); 747 748 error = bus_dmamap_load(sc->sc_dmat, data->map, 749 mtod(mnew, void *), MCLBYTES, NULL, 750 BUS_DMA_READ | BUS_DMA_NOWAIT); 751 if (error != 0) { 752 m_freem(mnew); 753 754 /* try to reload the old mbuf */ 755 error = bus_dmamap_load(sc->sc_dmat, data->map, 756 mtod(data->m, void *), MCLBYTES, NULL, 757 BUS_DMA_READ | BUS_DMA_NOWAIT); 758 if (error != 0) { 759 /* very unlikely that it will fail.. */ 760 panic("%s: could not load old rx mbuf", 761 sc->sc_dev.dv_xname); 762 } 763 ifp->if_ierrors++; 764 goto skip; 765 } 766 physaddr = data->map->dm_segs[0].ds_addr; 767 } 768 769 /* 770 * New mbuf successfully loaded, update Rx ring and continue 771 * processing. 772 */ 773 m = data->m; 774 data->m = mnew; 775 776 /* finalize mbuf */ 777 m->m_pkthdr.len = m->m_len = len; 778 m->m_pkthdr.rcvif = ifp; 779 780 #ifdef notyet 781 if (sc->sc_flags & NFE_HW_CSUM) { 782 if (flags & NFE_RX_IP_CSUMOK) 783 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 784 if (flags & NFE_RX_UDP_CSUMOK) 785 m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK; 786 if (flags & NFE_RX_TCP_CSUMOK) 787 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK; 788 } 789 #elif defined(NFE_CSUM) 790 if ((sc->sc_flags & NFE_HW_CSUM) && (flags & NFE_RX_CSUMOK)) 791 m->m_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK; 792 #endif 793 794 #if NBPFILTER > 0 795 if (ifp->if_bpf) 796 bpf_mtap(ifp->if_bpf, m); 797 #endif 798 ifp->if_ipackets++; 799 (*ifp->if_input)(ifp, m); 800 801 /* update mapping address in h/w descriptor */ 802 if (sc->sc_flags & NFE_40BIT_ADDR) { 803 #if defined(__LP64__) 804 desc64->physaddr[0] = htole32(physaddr >> 32); 805 #endif 806 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 807 } else { 808 desc32->physaddr = htole32(physaddr); 809 } 810 811 skip: if (sc->sc_flags & NFE_40BIT_ADDR) { 812 desc64->length = htole16(sc->rxq.bufsz); 813 desc64->flags = htole16(NFE_RX_READY); 814 815 nfe_rxdesc64_sync(sc, desc64, BUS_DMASYNC_PREWRITE); 816 } else { 817 desc32->length = htole16(sc->rxq.bufsz); 818 desc32->flags = htole16(NFE_RX_READY); 819 820 nfe_rxdesc32_sync(sc, desc32, BUS_DMASYNC_PREWRITE); 821 } 822 823 sc->rxq.cur = (sc->rxq.cur + 1) % NFE_RX_RING_COUNT; 824 } 825 } 826 827 void 828 nfe_txeof(struct nfe_softc *sc) 829 { 830 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 831 struct nfe_desc32 *desc32; 832 struct nfe_desc64 *desc64; 833 struct nfe_tx_data *data = NULL; 834 uint16_t flags; 835 836 while (sc->txq.next != sc->txq.cur) { 837 if (sc->sc_flags & NFE_40BIT_ADDR) { 838 desc64 = &sc->txq.desc64[sc->txq.next]; 839 nfe_txdesc64_sync(sc, desc64, BUS_DMASYNC_POSTREAD); 840 841 flags = le16toh(desc64->flags); 842 } else { 843 desc32 = &sc->txq.desc32[sc->txq.next]; 844 nfe_txdesc32_sync(sc, desc32, BUS_DMASYNC_POSTREAD); 845 846 flags = le16toh(desc32->flags); 847 } 848 849 if (flags & NFE_TX_VALID) 850 break; 851 852 data = &sc->txq.data[sc->txq.next]; 853 854 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 855 if (!(flags & NFE_TX_LASTFRAG_V1) && data->m == NULL) 856 goto skip; 857 858 if ((flags & NFE_TX_ERROR_V1) != 0) { 859 printf("%s: tx v1 error 0x%04x\n", 860 sc->sc_dev.dv_xname, flags); 861 ifp->if_oerrors++; 862 } else 863 ifp->if_opackets++; 864 } else { 865 if (!(flags & NFE_TX_LASTFRAG_V2) && data->m == NULL) 866 goto skip; 867 868 if ((flags & NFE_TX_ERROR_V2) != 0) { 869 printf("%s: tx v2 error 0x%04x\n", 870 sc->sc_dev.dv_xname, flags); 871 ifp->if_oerrors++; 872 } else 873 ifp->if_opackets++; 874 } 875 876 if (data->m == NULL) { /* should not get there */ 877 printf("%s: last fragment bit w/o associated mbuf!\n", 878 sc->sc_dev.dv_xname); 879 goto skip; 880 } 881 882 /* last fragment of the mbuf chain transmitted */ 883 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 884 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 885 bus_dmamap_unload(sc->sc_dmat, data->active); 886 m_freem(data->m); 887 data->m = NULL; 888 889 ifp->if_timer = 0; 890 891 skip: sc->txq.queued--; 892 sc->txq.next = (sc->txq.next + 1) % NFE_TX_RING_COUNT; 893 } 894 895 if (data != NULL) { /* at least one slot freed */ 896 ifp->if_flags &= ~IFF_OACTIVE; 897 nfe_start(ifp); 898 } 899 } 900 901 int 902 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 903 { 904 struct nfe_desc32 *desc32; 905 struct nfe_desc64 *desc64; 906 struct nfe_tx_data *data; 907 bus_dmamap_t map; 908 uint16_t flags = NFE_TX_VALID; 909 #if NVLAN > 0 910 struct m_tag *mtag; 911 uint32_t vtag = 0; 912 #endif 913 int error, i; 914 915 desc32 = NULL; 916 desc64 = NULL; 917 data = NULL; 918 map = sc->txq.data[sc->txq.cur].map; 919 920 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 921 if (error != 0) { 922 printf("%s: could not map mbuf (error %d)\n", 923 sc->sc_dev.dv_xname, error); 924 return error; 925 } 926 927 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 928 bus_dmamap_unload(sc->sc_dmat, map); 929 return ENOBUFS; 930 } 931 932 #if NVLAN > 0 933 /* setup h/w VLAN tagging */ 934 if (sc->sc_ethercom.ec_nvlans) { 935 mtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL); 936 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 937 } 938 #endif 939 #ifdef NFE_CSUM 940 if (m0->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 941 flags |= NFE_TX_IP_CSUM; 942 if (m0->m_pkthdr.csum_flags & (M_TCPV4_CSUM_OUT | M_UDPV4_CSUM_OUT)) 943 flags |= NFE_TX_TCP_CSUM; 944 #endif 945 946 for (i = 0; i < map->dm_nsegs; i++) { 947 data = &sc->txq.data[sc->txq.cur]; 948 949 if (sc->sc_flags & NFE_40BIT_ADDR) { 950 desc64 = &sc->txq.desc64[sc->txq.cur]; 951 #if defined(__LP64__) 952 desc64->physaddr[0] = 953 htole32(map->dm_segs[i].ds_addr >> 32); 954 #endif 955 desc64->physaddr[1] = 956 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 957 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 958 desc64->flags = htole16(flags); 959 #if NVLAN > 0 960 desc64->vtag = htole32(vtag); 961 #endif 962 } else { 963 desc32 = &sc->txq.desc32[sc->txq.cur]; 964 965 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 966 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 967 desc32->flags = htole16(flags); 968 } 969 970 /* csum flags and vtag belong to the first fragment only */ 971 if (map->dm_nsegs > 1) { 972 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_CSUM); 973 #if NVLAN > 0 974 vtag = 0; 975 #endif 976 } 977 978 sc->txq.queued++; 979 sc->txq.cur = (sc->txq.cur + 1) % NFE_TX_RING_COUNT; 980 } 981 982 /* the whole mbuf chain has been DMA mapped, fix last descriptor */ 983 if (sc->sc_flags & NFE_40BIT_ADDR) { 984 flags |= NFE_TX_LASTFRAG_V2; 985 desc64->flags = htole16(flags); 986 } else { 987 if (sc->sc_flags & NFE_JUMBO_SUP) 988 flags |= NFE_TX_LASTFRAG_V2; 989 else 990 flags |= NFE_TX_LASTFRAG_V1; 991 desc32->flags = htole16(flags); 992 } 993 994 data->m = m0; 995 data->active = map; 996 997 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 998 BUS_DMASYNC_PREWRITE); 999 1000 return 0; 1001 } 1002 1003 void 1004 nfe_start(struct ifnet *ifp) 1005 { 1006 struct nfe_softc *sc = ifp->if_softc; 1007 int old = sc->txq.cur; 1008 struct mbuf *m0; 1009 1010 for (;;) { 1011 IFQ_POLL(&ifp->if_snd, m0); 1012 if (m0 == NULL) 1013 break; 1014 1015 if (nfe_encap(sc, m0) != 0) { 1016 ifp->if_flags |= IFF_OACTIVE; 1017 break; 1018 } 1019 1020 /* packet put in h/w queue, remove from s/w queue */ 1021 IFQ_DEQUEUE(&ifp->if_snd, m0); 1022 1023 #if NBPFILTER > 0 1024 if (ifp->if_bpf != NULL) 1025 bpf_mtap(ifp->if_bpf, m0); 1026 #endif 1027 } 1028 if (sc->txq.cur == old) /* nothing sent */ 1029 return; 1030 1031 if (sc->sc_flags & NFE_40BIT_ADDR) 1032 nfe_txdesc64_rsync(sc, old, sc->txq.cur, BUS_DMASYNC_PREWRITE); 1033 else 1034 nfe_txdesc32_rsync(sc, old, sc->txq.cur, BUS_DMASYNC_PREWRITE); 1035 1036 /* kick Tx */ 1037 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1038 1039 /* 1040 * Set a timeout in case the chip goes out to lunch. 1041 */ 1042 ifp->if_timer = 5; 1043 } 1044 1045 void 1046 nfe_watchdog(struct ifnet *ifp) 1047 { 1048 struct nfe_softc *sc = ifp->if_softc; 1049 1050 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1051 1052 ifp->if_flags &= ~IFF_RUNNING; 1053 nfe_init(ifp); 1054 1055 ifp->if_oerrors++; 1056 } 1057 1058 int 1059 nfe_init(struct ifnet *ifp) 1060 { 1061 struct nfe_softc *sc = ifp->if_softc; 1062 uint32_t tmp; 1063 1064 if (ifp->if_flags & IFF_RUNNING) 1065 return 0; 1066 1067 nfe_stop(ifp, 0); 1068 1069 NFE_WRITE(sc, NFE_TX_UNK, 0); 1070 NFE_WRITE(sc, NFE_STATUS, 0); 1071 1072 sc->rxtxctl = NFE_RXTX_BIT2; 1073 if (sc->sc_flags & NFE_40BIT_ADDR) 1074 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1075 else if (sc->sc_flags & NFE_JUMBO_SUP) 1076 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1077 #ifdef NFE_CSUM 1078 if (sc->sc_flags & NFE_HW_CSUM) 1079 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1080 #endif 1081 #if NVLAN > 0 1082 /* 1083 * Although the adapter is capable of stripping VLAN tags from received 1084 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1085 * purpose. This will be done in software by our network stack. 1086 */ 1087 if (sc->sc_flags & NFE_HW_VLAN) 1088 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1089 #endif 1090 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1091 DELAY(10); 1092 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1093 1094 #if NVLAN 1095 if (sc->sc_flags & NFE_HW_VLAN) 1096 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1097 #endif 1098 1099 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1100 1101 /* set MAC address */ 1102 nfe_set_macaddr(sc, sc->sc_enaddr); 1103 1104 /* tell MAC where rings are in memory */ 1105 #ifdef __LP64__ 1106 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1107 #endif 1108 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1109 #ifdef __LP64__ 1110 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1111 #endif 1112 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1113 1114 NFE_WRITE(sc, NFE_RING_SIZE, 1115 (NFE_RX_RING_COUNT - 1) << 16 | 1116 (NFE_TX_RING_COUNT - 1)); 1117 1118 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1119 1120 /* force MAC to wakeup */ 1121 tmp = NFE_READ(sc, NFE_PWR_STATE); 1122 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1123 DELAY(10); 1124 tmp = NFE_READ(sc, NFE_PWR_STATE); 1125 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1126 1127 #if 1 1128 /* configure interrupts coalescing/mitigation */ 1129 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1130 #else 1131 /* no interrupt mitigation: one interrupt per packet */ 1132 NFE_WRITE(sc, NFE_IMTIMER, 970); 1133 #endif 1134 1135 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1136 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1137 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1138 1139 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1140 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1141 1142 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1143 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC); 1144 1145 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1146 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1147 DELAY(10); 1148 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1149 1150 /* set Rx filter */ 1151 nfe_setmulti(sc); 1152 1153 nfe_ifmedia_upd(ifp); 1154 1155 /* enable Rx */ 1156 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1157 1158 /* enable Tx */ 1159 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1160 1161 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1162 1163 /* enable interrupts */ 1164 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1165 1166 callout_schedule(&sc->sc_tick_ch, hz); 1167 1168 ifp->if_flags |= IFF_RUNNING; 1169 ifp->if_flags &= ~IFF_OACTIVE; 1170 1171 return 0; 1172 } 1173 1174 void 1175 nfe_stop(struct ifnet *ifp, int disable) 1176 { 1177 struct nfe_softc *sc = ifp->if_softc; 1178 1179 callout_stop(&sc->sc_tick_ch); 1180 1181 ifp->if_timer = 0; 1182 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1183 1184 mii_down(&sc->sc_mii); 1185 1186 /* abort Tx */ 1187 NFE_WRITE(sc, NFE_TX_CTL, 0); 1188 1189 /* disable Rx */ 1190 NFE_WRITE(sc, NFE_RX_CTL, 0); 1191 1192 /* disable interrupts */ 1193 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1194 1195 /* reset Tx and Rx rings */ 1196 nfe_reset_tx_ring(sc, &sc->txq); 1197 nfe_reset_rx_ring(sc, &sc->rxq); 1198 } 1199 1200 int 1201 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1202 { 1203 struct nfe_desc32 *desc32; 1204 struct nfe_desc64 *desc64; 1205 struct nfe_rx_data *data; 1206 struct nfe_jbuf *jbuf; 1207 void **desc; 1208 bus_addr_t physaddr; 1209 int i, nsegs, error, descsize; 1210 1211 if (sc->sc_flags & NFE_40BIT_ADDR) { 1212 desc = (void **)&ring->desc64; 1213 descsize = sizeof (struct nfe_desc64); 1214 } else { 1215 desc = (void **)&ring->desc32; 1216 descsize = sizeof (struct nfe_desc32); 1217 } 1218 1219 ring->cur = ring->next = 0; 1220 ring->bufsz = MCLBYTES; 1221 1222 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1223 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1224 if (error != 0) { 1225 printf("%s: could not create desc DMA map\n", 1226 sc->sc_dev.dv_xname); 1227 goto fail; 1228 } 1229 1230 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1231 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1232 if (error != 0) { 1233 printf("%s: could not allocate DMA memory\n", 1234 sc->sc_dev.dv_xname); 1235 goto fail; 1236 } 1237 1238 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1239 NFE_RX_RING_COUNT * descsize, (caddr_t *)desc, BUS_DMA_NOWAIT); 1240 if (error != 0) { 1241 printf("%s: could not map desc DMA memory\n", 1242 sc->sc_dev.dv_xname); 1243 goto fail; 1244 } 1245 1246 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1247 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1248 if (error != 0) { 1249 printf("%s: could not load desc DMA map\n", 1250 sc->sc_dev.dv_xname); 1251 goto fail; 1252 } 1253 1254 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1255 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1256 1257 if (sc->sc_flags & NFE_USE_JUMBO) { 1258 ring->bufsz = NFE_JBYTES; 1259 if ((error = nfe_jpool_alloc(sc)) != 0) { 1260 printf("%s: could not allocate jumbo frames\n", 1261 sc->sc_dev.dv_xname); 1262 goto fail; 1263 } 1264 } 1265 1266 /* 1267 * Pre-allocate Rx buffers and populate Rx ring. 1268 */ 1269 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1270 data = &sc->rxq.data[i]; 1271 1272 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1273 if (data->m == NULL) { 1274 printf("%s: could not allocate rx mbuf\n", 1275 sc->sc_dev.dv_xname); 1276 error = ENOMEM; 1277 goto fail; 1278 } 1279 1280 if (sc->sc_flags & NFE_USE_JUMBO) { 1281 if ((jbuf = nfe_jalloc(sc)) == NULL) { 1282 printf("%s: could not allocate jumbo buffer\n", 1283 sc->sc_dev.dv_xname); 1284 goto fail; 1285 } 1286 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1287 sc); 1288 1289 physaddr = jbuf->physaddr; 1290 } else { 1291 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1292 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1293 if (error != 0) { 1294 printf("%s: could not create DMA map\n", 1295 sc->sc_dev.dv_xname); 1296 goto fail; 1297 } 1298 MCLGET(data->m, M_DONTWAIT); 1299 if (!(data->m->m_flags & M_EXT)) { 1300 printf("%s: could not allocate mbuf cluster\n", 1301 sc->sc_dev.dv_xname); 1302 error = ENOMEM; 1303 goto fail; 1304 } 1305 1306 error = bus_dmamap_load(sc->sc_dmat, data->map, 1307 mtod(data->m, void *), MCLBYTES, NULL, 1308 BUS_DMA_READ | BUS_DMA_NOWAIT); 1309 if (error != 0) { 1310 printf("%s: could not load rx buf DMA map", 1311 sc->sc_dev.dv_xname); 1312 goto fail; 1313 } 1314 physaddr = data->map->dm_segs[0].ds_addr; 1315 } 1316 1317 if (sc->sc_flags & NFE_40BIT_ADDR) { 1318 desc64 = &sc->rxq.desc64[i]; 1319 #if defined(__LP64__) 1320 desc64->physaddr[0] = htole32(physaddr >> 32); 1321 #endif 1322 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1323 desc64->length = htole16(sc->rxq.bufsz); 1324 desc64->flags = htole16(NFE_RX_READY); 1325 } else { 1326 desc32 = &sc->rxq.desc32[i]; 1327 desc32->physaddr = htole32(physaddr); 1328 desc32->length = htole16(sc->rxq.bufsz); 1329 desc32->flags = htole16(NFE_RX_READY); 1330 } 1331 } 1332 1333 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1334 BUS_DMASYNC_PREWRITE); 1335 1336 return 0; 1337 1338 fail: nfe_free_rx_ring(sc, ring); 1339 return error; 1340 } 1341 1342 void 1343 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1344 { 1345 int i; 1346 1347 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1348 if (sc->sc_flags & NFE_40BIT_ADDR) { 1349 ring->desc64[i].length = htole16(ring->bufsz); 1350 ring->desc64[i].flags = htole16(NFE_RX_READY); 1351 } else { 1352 ring->desc32[i].length = htole16(ring->bufsz); 1353 ring->desc32[i].flags = htole16(NFE_RX_READY); 1354 } 1355 } 1356 1357 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1358 BUS_DMASYNC_PREWRITE); 1359 1360 ring->cur = ring->next = 0; 1361 } 1362 1363 void 1364 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1365 { 1366 struct nfe_rx_data *data; 1367 void *desc; 1368 int i, descsize; 1369 1370 if (sc->sc_flags & NFE_40BIT_ADDR) { 1371 desc = ring->desc64; 1372 descsize = sizeof (struct nfe_desc64); 1373 } else { 1374 desc = ring->desc32; 1375 descsize = sizeof (struct nfe_desc32); 1376 } 1377 1378 if (desc != NULL) { 1379 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1380 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1381 bus_dmamap_unload(sc->sc_dmat, ring->map); 1382 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)desc, 1383 NFE_RX_RING_COUNT * descsize); 1384 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1385 } 1386 1387 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1388 data = &ring->data[i]; 1389 1390 if (data->map != NULL) { 1391 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1392 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1393 bus_dmamap_unload(sc->sc_dmat, data->map); 1394 bus_dmamap_destroy(sc->sc_dmat, data->map); 1395 } 1396 if (data->m != NULL) 1397 m_freem(data->m); 1398 } 1399 } 1400 1401 struct nfe_jbuf * 1402 nfe_jalloc(struct nfe_softc *sc) 1403 { 1404 struct nfe_jbuf *jbuf; 1405 1406 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1407 if (jbuf == NULL) 1408 return NULL; 1409 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1410 return jbuf; 1411 } 1412 1413 /* 1414 * This is called automatically by the network stack when the mbuf is freed. 1415 * Caution must be taken that the NIC might be reset by the time the mbuf is 1416 * freed. 1417 */ 1418 void 1419 nfe_jfree(struct mbuf *m, caddr_t buf, size_t size, void *arg) 1420 { 1421 struct nfe_softc *sc = arg; 1422 struct nfe_jbuf *jbuf; 1423 int i; 1424 1425 /* find the jbuf from the base pointer */ 1426 i = (buf - sc->rxq.jpool) / NFE_JBYTES; 1427 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1428 printf("%s: request to free a buffer (%p) not managed by us\n", 1429 sc->sc_dev.dv_xname, buf); 1430 return; 1431 } 1432 jbuf = &sc->rxq.jbuf[i]; 1433 1434 /* ..and put it back in the free list */ 1435 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1436 1437 if (m != NULL) 1438 pool_cache_put(&mbpool_cache, m); 1439 } 1440 1441 int 1442 nfe_jpool_alloc(struct nfe_softc *sc) 1443 { 1444 struct nfe_rx_ring *ring = &sc->rxq; 1445 struct nfe_jbuf *jbuf; 1446 bus_addr_t physaddr; 1447 caddr_t buf; 1448 int i, nsegs, error; 1449 1450 /* 1451 * Allocate a big chunk of DMA'able memory. 1452 */ 1453 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1454 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1455 if (error != 0) { 1456 printf("%s: could not create jumbo DMA map\n", 1457 sc->sc_dev.dv_xname); 1458 goto fail; 1459 } 1460 1461 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1462 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1463 if (error != 0) { 1464 printf("%s could not allocate jumbo DMA memory\n", 1465 sc->sc_dev.dv_xname); 1466 goto fail; 1467 } 1468 1469 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1470 &ring->jpool, BUS_DMA_NOWAIT); 1471 if (error != 0) { 1472 printf("%s: could not map jumbo DMA memory\n", 1473 sc->sc_dev.dv_xname); 1474 goto fail; 1475 } 1476 1477 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1478 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1479 if (error != 0) { 1480 printf("%s: could not load jumbo DMA map\n", 1481 sc->sc_dev.dv_xname); 1482 goto fail; 1483 } 1484 1485 /* ..and split it into 9KB chunks */ 1486 SLIST_INIT(&ring->jfreelist); 1487 1488 buf = ring->jpool; 1489 physaddr = ring->jmap->dm_segs[0].ds_addr; 1490 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1491 jbuf = &ring->jbuf[i]; 1492 1493 jbuf->buf = buf; 1494 jbuf->physaddr = physaddr; 1495 1496 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1497 1498 buf += NFE_JBYTES; 1499 physaddr += NFE_JBYTES; 1500 } 1501 1502 return 0; 1503 1504 fail: nfe_jpool_free(sc); 1505 return error; 1506 } 1507 1508 void 1509 nfe_jpool_free(struct nfe_softc *sc) 1510 { 1511 struct nfe_rx_ring *ring = &sc->rxq; 1512 1513 if (ring->jmap != NULL) { 1514 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1515 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1516 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1517 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1518 } 1519 if (ring->jpool != NULL) { 1520 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1521 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1522 } 1523 } 1524 1525 int 1526 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1527 { 1528 int i, nsegs, error; 1529 void **desc; 1530 int descsize; 1531 1532 if (sc->sc_flags & NFE_40BIT_ADDR) { 1533 desc = (void **)&ring->desc64; 1534 descsize = sizeof (struct nfe_desc64); 1535 } else { 1536 desc = (void **)&ring->desc32; 1537 descsize = sizeof (struct nfe_desc32); 1538 } 1539 1540 ring->queued = 0; 1541 ring->cur = ring->next = 0; 1542 1543 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1544 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1545 1546 if (error != 0) { 1547 printf("%s: could not create desc DMA map\n", 1548 sc->sc_dev.dv_xname); 1549 goto fail; 1550 } 1551 1552 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1553 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1554 if (error != 0) { 1555 printf("%s: could not allocate DMA memory\n", 1556 sc->sc_dev.dv_xname); 1557 goto fail; 1558 } 1559 1560 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1561 NFE_TX_RING_COUNT * descsize, (caddr_t *)desc, BUS_DMA_NOWAIT); 1562 if (error != 0) { 1563 printf("%s: could not map desc DMA memory\n", 1564 sc->sc_dev.dv_xname); 1565 goto fail; 1566 } 1567 1568 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1569 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1570 if (error != 0) { 1571 printf("%s: could not load desc DMA map\n", 1572 sc->sc_dev.dv_xname); 1573 goto fail; 1574 } 1575 1576 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1577 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1578 1579 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1580 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1581 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1582 &ring->data[i].map); 1583 if (error != 0) { 1584 printf("%s: could not create DMA map\n", 1585 sc->sc_dev.dv_xname); 1586 goto fail; 1587 } 1588 } 1589 1590 return 0; 1591 1592 fail: nfe_free_tx_ring(sc, ring); 1593 return error; 1594 } 1595 1596 void 1597 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1598 { 1599 struct nfe_tx_data *data; 1600 int i; 1601 1602 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1603 if (sc->sc_flags & NFE_40BIT_ADDR) 1604 ring->desc64[i].flags = 0; 1605 else 1606 ring->desc32[i].flags = 0; 1607 1608 data = &ring->data[i]; 1609 1610 if (data->m != NULL) { 1611 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1612 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1613 bus_dmamap_unload(sc->sc_dmat, data->active); 1614 m_freem(data->m); 1615 data->m = NULL; 1616 } 1617 } 1618 1619 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1620 BUS_DMASYNC_PREWRITE); 1621 1622 ring->queued = 0; 1623 ring->cur = ring->next = 0; 1624 } 1625 1626 void 1627 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1628 { 1629 struct nfe_tx_data *data; 1630 void *desc; 1631 int i, descsize; 1632 1633 if (sc->sc_flags & NFE_40BIT_ADDR) { 1634 desc = ring->desc64; 1635 descsize = sizeof (struct nfe_desc64); 1636 } else { 1637 desc = ring->desc32; 1638 descsize = sizeof (struct nfe_desc32); 1639 } 1640 1641 if (desc != NULL) { 1642 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1643 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1644 bus_dmamap_unload(sc->sc_dmat, ring->map); 1645 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)desc, 1646 NFE_TX_RING_COUNT * descsize); 1647 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1648 } 1649 1650 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1651 data = &ring->data[i]; 1652 1653 if (data->m != NULL) { 1654 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1655 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1656 bus_dmamap_unload(sc->sc_dmat, data->active); 1657 m_freem(data->m); 1658 } 1659 } 1660 1661 /* ..and now actually destroy the DMA mappings */ 1662 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1663 data = &ring->data[i]; 1664 if (data->map == NULL) 1665 continue; 1666 bus_dmamap_destroy(sc->sc_dmat, data->map); 1667 } 1668 } 1669 1670 int 1671 nfe_ifmedia_upd(struct ifnet *ifp) 1672 { 1673 struct nfe_softc *sc = ifp->if_softc; 1674 struct mii_data *mii = &sc->sc_mii; 1675 struct mii_softc *miisc; 1676 1677 if (mii->mii_instance != 0) { 1678 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1679 mii_phy_reset(miisc); 1680 } 1681 return mii_mediachg(mii); 1682 } 1683 1684 void 1685 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1686 { 1687 struct nfe_softc *sc = ifp->if_softc; 1688 struct mii_data *mii = &sc->sc_mii; 1689 1690 mii_pollstat(mii); 1691 ifmr->ifm_status = mii->mii_media_status; 1692 ifmr->ifm_active = mii->mii_media_active; 1693 } 1694 1695 void 1696 nfe_setmulti(struct nfe_softc *sc) 1697 { 1698 struct ethercom *ec = &sc->sc_ethercom; 1699 struct ifnet *ifp = &ec->ec_if; 1700 struct ether_multi *enm; 1701 struct ether_multistep step; 1702 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1703 uint32_t filter = NFE_RXFILTER_MAGIC; 1704 int i; 1705 1706 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1707 bzero(addr, ETHER_ADDR_LEN); 1708 bzero(mask, ETHER_ADDR_LEN); 1709 goto done; 1710 } 1711 1712 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1713 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1714 1715 ETHER_FIRST_MULTI(step, ec, enm); 1716 while (enm != NULL) { 1717 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1718 ifp->if_flags |= IFF_ALLMULTI; 1719 bzero(addr, ETHER_ADDR_LEN); 1720 bzero(mask, ETHER_ADDR_LEN); 1721 goto done; 1722 } 1723 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1724 addr[i] &= enm->enm_addrlo[i]; 1725 mask[i] &= ~enm->enm_addrlo[i]; 1726 } 1727 ETHER_NEXT_MULTI(step, enm); 1728 } 1729 for (i = 0; i < ETHER_ADDR_LEN; i++) 1730 mask[i] |= addr[i]; 1731 1732 done: 1733 addr[0] |= 0x01; /* make sure multicast bit is set */ 1734 1735 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1736 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1737 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1738 addr[5] << 8 | addr[4]); 1739 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1740 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1741 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1742 mask[5] << 8 | mask[4]); 1743 1744 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1745 NFE_WRITE(sc, NFE_RXFILTER, filter); 1746 } 1747 1748 void 1749 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1750 { 1751 uint32_t tmp; 1752 1753 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1754 addr[0] = (tmp >> 8) & 0xff; 1755 addr[1] = (tmp & 0xff); 1756 1757 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1758 addr[2] = (tmp >> 24) & 0xff; 1759 addr[3] = (tmp >> 16) & 0xff; 1760 addr[4] = (tmp >> 8) & 0xff; 1761 addr[5] = (tmp & 0xff); 1762 } 1763 1764 void 1765 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1766 { 1767 NFE_WRITE(sc, NFE_MACADDR_LO, 1768 addr[5] << 8 | addr[4]); 1769 NFE_WRITE(sc, NFE_MACADDR_HI, 1770 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1771 } 1772 1773 void 1774 nfe_tick(void *arg) 1775 { 1776 struct nfe_softc *sc = arg; 1777 int s; 1778 1779 s = splnet(); 1780 mii_tick(&sc->sc_mii); 1781 splx(s); 1782 1783 callout_schedule(&sc->sc_tick_ch, hz); 1784 } 1785
Indexes created Tue Sep 30 20:09:53 GMT 2025