if_nfe.c revision 1.30
1 /* $NetBSD: if_nfe.c,v 1.30 2008/03/26 14:46:21 cube Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.52 2006/03/02 09:04:00 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.30 2008/03/26 14:46:21 cube Exp $"); 25 26 #include "opt_inet.h" 27 #include "bpfilter.h" 28 #include "vlan.h" 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/types.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/queue.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/socket.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/pci/if_nfereg.h> 74 #include <dev/pci/if_nfevar.h> 75 76 int nfe_match(device_t, cfdata_t, void *); 77 void nfe_attach(device_t, device_t, void *); 78 void nfe_power(int, void *); 79 void nfe_miibus_statchg(device_t); 80 int nfe_miibus_readreg(device_t, int, int); 81 void nfe_miibus_writereg(device_t, int, int, int); 82 int nfe_intr(void *); 83 int nfe_ioctl(struct ifnet *, u_long, void *); 84 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 85 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 86 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 87 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 88 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 89 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 90 void nfe_rxeof(struct nfe_softc *); 91 void nfe_txeof(struct nfe_softc *); 92 int nfe_encap(struct nfe_softc *, struct mbuf *); 93 void nfe_start(struct ifnet *); 94 void nfe_watchdog(struct ifnet *); 95 int nfe_init(struct ifnet *); 96 void nfe_stop(struct ifnet *, int); 97 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 98 void nfe_jfree(struct mbuf *, void *, size_t, void *); 99 int nfe_jpool_alloc(struct nfe_softc *); 100 void nfe_jpool_free(struct nfe_softc *); 101 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 102 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 105 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 void nfe_setmulti(struct nfe_softc *); 108 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 109 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 110 void nfe_tick(void *); 111 112 CFATTACH_DECL_NEW(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, 113 NULL, NULL); 114 115 /*#define NFE_NO_JUMBO*/ 116 117 #ifdef NFE_DEBUG 118 int nfedebug = 0; 119 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 120 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 121 #else 122 #define DPRINTF(x) 123 #define DPRINTFN(n,x) 124 #endif 125 126 /* deal with naming differences */ 127 128 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 129 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 130 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 131 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 132 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 133 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 134 135 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 136 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 137 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 138 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 139 140 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 141 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 142 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 143 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 144 145 #ifdef _LP64 146 #define __LP64__ 1 147 #endif 148 149 const struct nfe_product { 150 pci_vendor_id_t vendor; 151 pci_product_id_t product; 152 } nfe_devices[] = { 153 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 155 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 183 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 }, 184 }; 185 186 int 187 nfe_match(device_t dev, cfdata_t match, void *aux) 188 { 189 struct pci_attach_args *pa = aux; 190 const struct nfe_product *np; 191 int i; 192 193 for (i = 0; i < sizeof(nfe_devices) / sizeof(nfe_devices[0]); i++) { 194 np = &nfe_devices[i]; 195 if (PCI_VENDOR(pa->pa_id) == np->vendor && 196 PCI_PRODUCT(pa->pa_id) == np->product) 197 return 1; 198 } 199 return 0; 200 } 201 202 void 203 nfe_attach(device_t parent, device_t self, void *aux) 204 { 205 struct nfe_softc *sc = device_private(self); 206 struct pci_attach_args *pa = aux; 207 pci_chipset_tag_t pc = pa->pa_pc; 208 pci_intr_handle_t ih; 209 const char *intrstr; 210 struct ifnet *ifp; 211 bus_size_t memsize; 212 pcireg_t memtype; 213 char devinfo[256]; 214 215 sc->sc_dev = self; 216 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 217 aprint_normal(": %s (rev. 0x%02x)\n", 218 devinfo, PCI_REVISION(pa->pa_class)); 219 220 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 221 switch (memtype) { 222 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 223 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 224 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 225 &sc->sc_memh, NULL, &memsize) == 0) 226 break; 227 /* FALLTHROUGH */ 228 default: 229 aprint_error_dev(self, "could not map mem space\n"); 230 return; 231 } 232 233 if (pci_intr_map(pa, &ih) != 0) { 234 aprint_error_dev(self, "could not map interrupt\n"); 235 return; 236 } 237 238 intrstr = pci_intr_string(pc, ih); 239 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 240 if (sc->sc_ih == NULL) { 241 aprint_error_dev(self, "could not establish interrupt"); 242 if (intrstr != NULL) 243 aprint_normal(" at %s", intrstr); 244 aprint_normal("\n"); 245 return; 246 } 247 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 248 249 sc->sc_dmat = pa->pa_dmat; 250 251 /* Check for reversed ethernet address */ 252 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 253 sc->sc_flags |= NFE_CORRECT_MACADDR; 254 255 nfe_get_macaddr(sc, sc->sc_enaddr); 256 aprint_normal_dev(self, "Ethernet address %s\n", 257 ether_sprintf(sc->sc_enaddr)); 258 259 sc->sc_flags = 0; 260 261 switch (PCI_PRODUCT(pa->pa_id)) { 262 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 263 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 264 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 265 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 266 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 267 break; 268 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 269 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 270 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 271 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 272 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 273 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 274 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 275 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 276 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 277 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 278 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 279 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 280 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 281 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 282 sc->sc_flags |= NFE_40BIT_ADDR |NFE_PWR_MGMT; 283 break; 284 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 285 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 286 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 287 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 288 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 289 break; 290 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 291 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 292 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 293 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 294 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 295 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 296 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 297 NFE_HW_VLAN | NFE_PWR_MGMT; 298 break; 299 } 300 301 if ((sc->sc_flags & NFE_PWR_MGMT) != 0) { 302 /* wakeup some newer chips from powerdown mode */ 303 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 304 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 305 DELAY(100); 306 NFE_WRITE(sc, NFE_MAC_RESET, 0); 307 DELAY(100); 308 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 309 NFE_WRITE(sc, NFE_PWR2_CTL, 310 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_WAKEUP_MASK); 311 } 312 313 #ifndef NFE_NO_JUMBO 314 /* enable jumbo frames for adapters that support it */ 315 if (sc->sc_flags & NFE_JUMBO_SUP) 316 sc->sc_flags |= NFE_USE_JUMBO; 317 #endif 318 319 /* 320 * Allocate Tx and Rx rings. 321 */ 322 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 323 aprint_error_dev(self, "could not allocate Tx ring\n"); 324 return; 325 } 326 327 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 328 aprint_error_dev(self, "could not allocate Rx ring\n"); 329 nfe_free_tx_ring(sc, &sc->txq); 330 return; 331 } 332 333 ifp = &sc->sc_ethercom.ec_if; 334 ifp->if_softc = sc; 335 ifp->if_mtu = ETHERMTU; 336 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 337 ifp->if_ioctl = nfe_ioctl; 338 ifp->if_start = nfe_start; 339 ifp->if_stop = nfe_stop; 340 ifp->if_watchdog = nfe_watchdog; 341 ifp->if_init = nfe_init; 342 ifp->if_baudrate = IF_Gbps(1); 343 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 344 IFQ_SET_READY(&ifp->if_snd); 345 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 346 347 #if NVLAN > 0 348 if (sc->sc_flags & NFE_HW_VLAN) 349 sc->sc_ethercom.ec_capabilities |= 350 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 351 #endif 352 if (sc->sc_flags & NFE_HW_CSUM) { 353 ifp->if_capabilities |= 354 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 355 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 356 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 357 } 358 359 sc->sc_mii.mii_ifp = ifp; 360 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 361 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 362 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 363 364 sc->sc_ethercom.ec_mii = &sc->sc_mii; 365 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 366 ether_mediastatus); 367 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 368 MII_OFFSET_ANY, 0); 369 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 370 aprint_error_dev(self, "no PHY found!\n"); 371 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 372 0, NULL); 373 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 374 } else 375 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 376 377 if_attach(ifp); 378 ether_ifattach(ifp, sc->sc_enaddr); 379 380 callout_init(&sc->sc_tick_ch, 0); 381 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 382 383 if (!pmf_device_register(self, NULL, NULL)) 384 aprint_error_dev(self, "couldn't establish power handler\n"); 385 else 386 pmf_class_network_register(self, ifp); 387 } 388 389 void 390 nfe_miibus_statchg(device_t dev) 391 { 392 struct nfe_softc *sc = device_private(dev); 393 struct mii_data *mii = &sc->sc_mii; 394 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 395 396 phy = NFE_READ(sc, NFE_PHY_IFACE); 397 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 398 399 seed = NFE_READ(sc, NFE_RNDSEED); 400 seed &= ~NFE_SEED_MASK; 401 402 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 403 phy |= NFE_PHY_HDX; /* half-duplex */ 404 misc |= NFE_MISC1_HDX; 405 } 406 407 switch (IFM_SUBTYPE(mii->mii_media_active)) { 408 case IFM_1000_T: /* full-duplex only */ 409 link |= NFE_MEDIA_1000T; 410 seed |= NFE_SEED_1000T; 411 phy |= NFE_PHY_1000T; 412 break; 413 case IFM_100_TX: 414 link |= NFE_MEDIA_100TX; 415 seed |= NFE_SEED_100TX; 416 phy |= NFE_PHY_100TX; 417 break; 418 case IFM_10_T: 419 link |= NFE_MEDIA_10T; 420 seed |= NFE_SEED_10T; 421 break; 422 } 423 424 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 425 426 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 427 NFE_WRITE(sc, NFE_MISC1, misc); 428 NFE_WRITE(sc, NFE_LINKSPEED, link); 429 } 430 431 int 432 nfe_miibus_readreg(device_t dev, int phy, int reg) 433 { 434 struct nfe_softc *sc = device_private(dev); 435 uint32_t val; 436 int ntries; 437 438 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 439 440 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 441 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 442 DELAY(100); 443 } 444 445 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 446 447 for (ntries = 0; ntries < 1000; ntries++) { 448 DELAY(100); 449 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 450 break; 451 } 452 if (ntries == 1000) { 453 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 454 device_xname(sc->sc_dev))); 455 return 0; 456 } 457 458 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 459 DPRINTFN(2, ("%s: could not read PHY\n", 460 device_xname(sc->sc_dev))); 461 return 0; 462 } 463 464 val = NFE_READ(sc, NFE_PHY_DATA); 465 if (val != 0xffffffff && val != 0) 466 sc->mii_phyaddr = phy; 467 468 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 469 device_xname(sc->sc_dev), phy, reg, val)); 470 471 return val; 472 } 473 474 void 475 nfe_miibus_writereg(device_t dev, int phy, int reg, int val) 476 { 477 struct nfe_softc *sc = device_private(dev); 478 uint32_t ctl; 479 int ntries; 480 481 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 482 483 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 484 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 485 DELAY(100); 486 } 487 488 NFE_WRITE(sc, NFE_PHY_DATA, val); 489 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 490 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 491 492 for (ntries = 0; ntries < 1000; ntries++) { 493 DELAY(100); 494 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 495 break; 496 } 497 #ifdef NFE_DEBUG 498 if (nfedebug >= 2 && ntries == 1000) 499 printf("could not write to PHY\n"); 500 #endif 501 } 502 503 int 504 nfe_intr(void *arg) 505 { 506 struct nfe_softc *sc = arg; 507 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 508 uint32_t r; 509 int handled; 510 511 if ((ifp->if_flags & IFF_UP) == 0) 512 return 0; 513 514 handled = 0; 515 516 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 517 518 for (;;) { 519 r = NFE_READ(sc, NFE_IRQ_STATUS); 520 if ((r & NFE_IRQ_WANTED) == 0) 521 break; 522 523 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 524 handled = 1; 525 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 526 527 if ((r & (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX)) 528 != 0) { 529 /* check Rx ring */ 530 nfe_rxeof(sc); 531 } 532 533 if ((r & (NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE)) 534 != 0) { 535 /* check Tx ring */ 536 nfe_txeof(sc); 537 } 538 539 if ((r & NFE_IRQ_LINK) != 0) { 540 NFE_READ(sc, NFE_PHY_STATUS); 541 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 542 DPRINTF(("%s: link state changed\n", 543 device_xname(sc->sc_dev))); 544 } 545 } 546 547 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 548 549 if (handled && !IF_IS_EMPTY(&ifp->if_snd)) 550 nfe_start(ifp); 551 552 return handled; 553 } 554 555 int 556 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 557 { 558 struct nfe_softc *sc = ifp->if_softc; 559 struct ifreq *ifr = (struct ifreq *)data; 560 struct ifaddr *ifa = (struct ifaddr *)data; 561 int s, error = 0; 562 563 s = splnet(); 564 565 switch (cmd) { 566 case SIOCSIFADDR: 567 ifp->if_flags |= IFF_UP; 568 nfe_init(ifp); 569 switch (ifa->ifa_addr->sa_family) { 570 #ifdef INET 571 case AF_INET: 572 arp_ifinit(ifp, ifa); 573 break; 574 #endif 575 default: 576 break; 577 } 578 break; 579 case SIOCSIFMTU: 580 if (ifr->ifr_mtu < ETHERMIN || 581 ((sc->sc_flags & NFE_USE_JUMBO) && 582 ifr->ifr_mtu > ETHERMTU_JUMBO) || 583 (!(sc->sc_flags & NFE_USE_JUMBO) && 584 ifr->ifr_mtu > ETHERMTU)) 585 error = EINVAL; 586 else if ((error = ifioctl_common(ifp, cmd, data)) == ENETRESET) 587 error = 0; 588 break; 589 case SIOCSIFFLAGS: 590 if (ifp->if_flags & IFF_UP) { 591 /* 592 * If only the PROMISC or ALLMULTI flag changes, then 593 * don't do a full re-init of the chip, just update 594 * the Rx filter. 595 */ 596 if ((ifp->if_flags & IFF_RUNNING) && 597 ((ifp->if_flags ^ sc->sc_if_flags) & 598 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 599 nfe_setmulti(sc); 600 else 601 nfe_init(ifp); 602 } else { 603 if (ifp->if_flags & IFF_RUNNING) 604 nfe_stop(ifp, 1); 605 } 606 sc->sc_if_flags = ifp->if_flags; 607 break; 608 default: 609 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 610 break; 611 612 error = 0; 613 614 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 615 ; 616 else if (ifp->if_flags & IFF_RUNNING) 617 nfe_setmulti(sc); 618 break; 619 } 620 621 splx(s); 622 623 return error; 624 } 625 626 void 627 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 628 { 629 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 630 (char *)desc32 - (char *)sc->txq.desc32, 631 sizeof (struct nfe_desc32), ops); 632 } 633 634 void 635 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 636 { 637 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 638 (char *)desc64 - (char *)sc->txq.desc64, 639 sizeof (struct nfe_desc64), ops); 640 } 641 642 void 643 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 644 { 645 if (end > start) { 646 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 647 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 648 (char *)&sc->txq.desc32[end] - 649 (char *)&sc->txq.desc32[start], ops); 650 return; 651 } 652 /* sync from 'start' to end of ring */ 653 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 654 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 655 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 656 (char *)&sc->txq.desc32[start], ops); 657 658 /* sync from start of ring to 'end' */ 659 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 660 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 661 } 662 663 void 664 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 665 { 666 if (end > start) { 667 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 668 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 669 (char *)&sc->txq.desc64[end] - 670 (char *)&sc->txq.desc64[start], ops); 671 return; 672 } 673 /* sync from 'start' to end of ring */ 674 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 675 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 676 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 677 (char *)&sc->txq.desc64[start], ops); 678 679 /* sync from start of ring to 'end' */ 680 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 681 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 682 } 683 684 void 685 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 686 { 687 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 688 (char *)desc32 - (char *)sc->rxq.desc32, 689 sizeof (struct nfe_desc32), ops); 690 } 691 692 void 693 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 694 { 695 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 696 (char *)desc64 - (char *)sc->rxq.desc64, 697 sizeof (struct nfe_desc64), ops); 698 } 699 700 void 701 nfe_rxeof(struct nfe_softc *sc) 702 { 703 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 704 struct nfe_desc32 *desc32; 705 struct nfe_desc64 *desc64; 706 struct nfe_rx_data *data; 707 struct nfe_jbuf *jbuf; 708 struct mbuf *m, *mnew; 709 bus_addr_t physaddr; 710 uint16_t flags; 711 int error, len, i; 712 713 desc32 = NULL; 714 desc64 = NULL; 715 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 716 data = &sc->rxq.data[i]; 717 718 if (sc->sc_flags & NFE_40BIT_ADDR) { 719 desc64 = &sc->rxq.desc64[i]; 720 nfe_rxdesc64_sync(sc, desc64, 721 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 722 723 flags = le16toh(desc64->flags); 724 len = le16toh(desc64->length) & 0x3fff; 725 } else { 726 desc32 = &sc->rxq.desc32[i]; 727 nfe_rxdesc32_sync(sc, desc32, 728 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 729 730 flags = le16toh(desc32->flags); 731 len = le16toh(desc32->length) & 0x3fff; 732 } 733 734 if ((flags & NFE_RX_READY) != 0) 735 break; 736 737 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 738 if ((flags & NFE_RX_VALID_V1) == 0) 739 goto skip; 740 741 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 742 flags &= ~NFE_RX_ERROR; 743 len--; /* fix buffer length */ 744 } 745 } else { 746 if ((flags & NFE_RX_VALID_V2) == 0) 747 goto skip; 748 749 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 750 flags &= ~NFE_RX_ERROR; 751 len--; /* fix buffer length */ 752 } 753 } 754 755 if (flags & NFE_RX_ERROR) { 756 ifp->if_ierrors++; 757 goto skip; 758 } 759 760 /* 761 * Try to allocate a new mbuf for this ring element and load 762 * it before processing the current mbuf. If the ring element 763 * cannot be loaded, drop the received packet and reuse the 764 * old mbuf. In the unlikely case that the old mbuf can't be 765 * reloaded either, explicitly panic. 766 */ 767 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 768 if (mnew == NULL) { 769 ifp->if_ierrors++; 770 goto skip; 771 } 772 773 if (sc->sc_flags & NFE_USE_JUMBO) { 774 physaddr = 775 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 776 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 777 if (len > MCLBYTES) { 778 m_freem(mnew); 779 ifp->if_ierrors++; 780 goto skip1; 781 } 782 MCLGET(mnew, M_DONTWAIT); 783 if ((mnew->m_flags & M_EXT) == 0) { 784 m_freem(mnew); 785 ifp->if_ierrors++; 786 goto skip1; 787 } 788 789 memcpy(mtod(mnew, void *), 790 mtod(data->m, const void *), len); 791 m = mnew; 792 goto mbufcopied; 793 } else { 794 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 795 796 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 797 mtod(data->m, char *) - (char *)sc->rxq.jpool, 798 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 799 800 physaddr = jbuf->physaddr; 801 } 802 } else { 803 MCLGET(mnew, M_DONTWAIT); 804 if ((mnew->m_flags & M_EXT) == 0) { 805 m_freem(mnew); 806 ifp->if_ierrors++; 807 goto skip; 808 } 809 810 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 811 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 812 bus_dmamap_unload(sc->sc_dmat, data->map); 813 814 error = bus_dmamap_load(sc->sc_dmat, data->map, 815 mtod(mnew, void *), MCLBYTES, NULL, 816 BUS_DMA_READ | BUS_DMA_NOWAIT); 817 if (error != 0) { 818 m_freem(mnew); 819 820 /* try to reload the old mbuf */ 821 error = bus_dmamap_load(sc->sc_dmat, data->map, 822 mtod(data->m, void *), MCLBYTES, NULL, 823 BUS_DMA_READ | BUS_DMA_NOWAIT); 824 if (error != 0) { 825 /* very unlikely that it will fail.. */ 826 panic("%s: could not load old rx mbuf", 827 device_xname(sc->sc_dev)); 828 } 829 ifp->if_ierrors++; 830 goto skip; 831 } 832 physaddr = data->map->dm_segs[0].ds_addr; 833 } 834 835 /* 836 * New mbuf successfully loaded, update Rx ring and continue 837 * processing. 838 */ 839 m = data->m; 840 data->m = mnew; 841 842 mbufcopied: 843 /* finalize mbuf */ 844 m->m_pkthdr.len = m->m_len = len; 845 m->m_pkthdr.rcvif = ifp; 846 847 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 848 /* 849 * XXX 850 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 851 */ 852 if (flags & NFE_RX_IP_CSUMOK) { 853 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 854 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 855 device_xname(sc->sc_dev))); 856 } 857 /* 858 * XXX 859 * no way to check M_CSUM_TCP_UDP_BAD or 860 * other protocols? 861 */ 862 if (flags & NFE_RX_UDP_CSUMOK) { 863 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 864 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 865 device_xname(sc->sc_dev))); 866 } else if (flags & NFE_RX_TCP_CSUMOK) { 867 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 868 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 869 device_xname(sc->sc_dev))); 870 } 871 } 872 873 #if NBPFILTER > 0 874 if (ifp->if_bpf) 875 bpf_mtap(ifp->if_bpf, m); 876 #endif 877 ifp->if_ipackets++; 878 (*ifp->if_input)(ifp, m); 879 880 skip1: 881 /* update mapping address in h/w descriptor */ 882 if (sc->sc_flags & NFE_40BIT_ADDR) { 883 #if defined(__LP64__) 884 desc64->physaddr[0] = htole32(physaddr >> 32); 885 #endif 886 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 887 } else { 888 desc32->physaddr = htole32(physaddr); 889 } 890 891 skip: 892 if (sc->sc_flags & NFE_40BIT_ADDR) { 893 desc64->length = htole16(sc->rxq.bufsz); 894 desc64->flags = htole16(NFE_RX_READY); 895 896 nfe_rxdesc64_sync(sc, desc64, 897 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 898 } else { 899 desc32->length = htole16(sc->rxq.bufsz); 900 desc32->flags = htole16(NFE_RX_READY); 901 902 nfe_rxdesc32_sync(sc, desc32, 903 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 904 } 905 } 906 /* update current RX pointer */ 907 sc->rxq.cur = i; 908 } 909 910 void 911 nfe_txeof(struct nfe_softc *sc) 912 { 913 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 914 struct nfe_desc32 *desc32; 915 struct nfe_desc64 *desc64; 916 struct nfe_tx_data *data = NULL; 917 int i; 918 uint16_t flags; 919 920 for (i = sc->txq.next; 921 sc->txq.queued > 0; 922 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 923 if (sc->sc_flags & NFE_40BIT_ADDR) { 924 desc64 = &sc->txq.desc64[i]; 925 nfe_txdesc64_sync(sc, desc64, 926 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 927 928 flags = le16toh(desc64->flags); 929 } else { 930 desc32 = &sc->txq.desc32[i]; 931 nfe_txdesc32_sync(sc, desc32, 932 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 933 934 flags = le16toh(desc32->flags); 935 } 936 937 if ((flags & NFE_TX_VALID) != 0) 938 break; 939 940 data = &sc->txq.data[i]; 941 942 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 943 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 944 data->m == NULL) 945 continue; 946 947 if ((flags & NFE_TX_ERROR_V1) != 0) { 948 aprint_error_dev(sc->sc_dev, 949 "tx v1 error 0x%04x\n", flags); 950 ifp->if_oerrors++; 951 } else 952 ifp->if_opackets++; 953 } else { 954 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 955 data->m == NULL) 956 continue; 957 958 if ((flags & NFE_TX_ERROR_V2) != 0) { 959 aprint_error_dev(sc->sc_dev, 960 "tx v2 error 0x%04x\n", flags); 961 ifp->if_oerrors++; 962 } else 963 ifp->if_opackets++; 964 } 965 966 if (data->m == NULL) { /* should not get there */ 967 aprint_error_dev(sc->sc_dev, 968 "last fragment bit w/o associated mbuf!\n"); 969 continue; 970 } 971 972 /* last fragment of the mbuf chain transmitted */ 973 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 974 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 975 bus_dmamap_unload(sc->sc_dmat, data->active); 976 m_freem(data->m); 977 data->m = NULL; 978 } 979 980 sc->txq.next = i; 981 982 if (sc->txq.queued < NFE_TX_RING_COUNT) { 983 /* at least one slot freed */ 984 ifp->if_flags &= ~IFF_OACTIVE; 985 } 986 987 if (sc->txq.queued == 0) { 988 /* all queued packets are sent */ 989 ifp->if_timer = 0; 990 } 991 } 992 993 int 994 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 995 { 996 struct nfe_desc32 *desc32; 997 struct nfe_desc64 *desc64; 998 struct nfe_tx_data *data; 999 bus_dmamap_t map; 1000 uint16_t flags, csumflags; 1001 #if NVLAN > 0 1002 struct m_tag *mtag; 1003 uint32_t vtag = 0; 1004 #endif 1005 int error, i, first; 1006 1007 desc32 = NULL; 1008 desc64 = NULL; 1009 data = NULL; 1010 1011 flags = 0; 1012 csumflags = 0; 1013 first = sc->txq.cur; 1014 1015 map = sc->txq.data[first].map; 1016 1017 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1018 if (error != 0) { 1019 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1020 error); 1021 return error; 1022 } 1023 1024 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1025 bus_dmamap_unload(sc->sc_dmat, map); 1026 return ENOBUFS; 1027 } 1028 1029 #if NVLAN > 0 1030 /* setup h/w VLAN tagging */ 1031 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1032 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1033 #endif 1034 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1035 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1036 csumflags |= NFE_TX_IP_CSUM; 1037 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1038 csumflags |= NFE_TX_TCP_UDP_CSUM; 1039 } 1040 1041 for (i = 0; i < map->dm_nsegs; i++) { 1042 data = &sc->txq.data[sc->txq.cur]; 1043 1044 if (sc->sc_flags & NFE_40BIT_ADDR) { 1045 desc64 = &sc->txq.desc64[sc->txq.cur]; 1046 #if defined(__LP64__) 1047 desc64->physaddr[0] = 1048 htole32(map->dm_segs[i].ds_addr >> 32); 1049 #endif 1050 desc64->physaddr[1] = 1051 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1052 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1053 desc64->flags = htole16(flags); 1054 desc64->vtag = 0; 1055 } else { 1056 desc32 = &sc->txq.desc32[sc->txq.cur]; 1057 1058 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1059 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1060 desc32->flags = htole16(flags); 1061 } 1062 1063 /* 1064 * Setting of the valid bit in the first descriptor is 1065 * deferred until the whole chain is fully setup. 1066 */ 1067 flags |= NFE_TX_VALID; 1068 1069 sc->txq.queued++; 1070 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1071 } 1072 1073 /* the whole mbuf chain has been setup */ 1074 if (sc->sc_flags & NFE_40BIT_ADDR) { 1075 /* fix last descriptor */ 1076 flags |= NFE_TX_LASTFRAG_V2; 1077 desc64->flags = htole16(flags); 1078 1079 /* Checksum flags and vtag belong to the first fragment only. */ 1080 #if NVLAN > 0 1081 sc->txq.desc64[first].vtag = htole32(vtag); 1082 #endif 1083 sc->txq.desc64[first].flags |= htole16(csumflags); 1084 1085 /* finally, set the valid bit in the first descriptor */ 1086 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1087 } else { 1088 /* fix last descriptor */ 1089 if (sc->sc_flags & NFE_JUMBO_SUP) 1090 flags |= NFE_TX_LASTFRAG_V2; 1091 else 1092 flags |= NFE_TX_LASTFRAG_V1; 1093 desc32->flags = htole16(flags); 1094 1095 /* Checksum flags belong to the first fragment only. */ 1096 sc->txq.desc32[first].flags |= htole16(csumflags); 1097 1098 /* finally, set the valid bit in the first descriptor */ 1099 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1100 } 1101 1102 data->m = m0; 1103 data->active = map; 1104 1105 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1106 BUS_DMASYNC_PREWRITE); 1107 1108 return 0; 1109 } 1110 1111 void 1112 nfe_start(struct ifnet *ifp) 1113 { 1114 struct nfe_softc *sc = ifp->if_softc; 1115 int old = sc->txq.queued; 1116 struct mbuf *m0; 1117 1118 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 1119 return; 1120 1121 for (;;) { 1122 IFQ_POLL(&ifp->if_snd, m0); 1123 if (m0 == NULL) 1124 break; 1125 1126 if (nfe_encap(sc, m0) != 0) { 1127 ifp->if_flags |= IFF_OACTIVE; 1128 break; 1129 } 1130 1131 /* packet put in h/w queue, remove from s/w queue */ 1132 IFQ_DEQUEUE(&ifp->if_snd, m0); 1133 1134 #if NBPFILTER > 0 1135 if (ifp->if_bpf != NULL) 1136 bpf_mtap(ifp->if_bpf, m0); 1137 #endif 1138 } 1139 1140 if (sc->txq.queued != old) { 1141 /* packets are queued */ 1142 if (sc->sc_flags & NFE_40BIT_ADDR) 1143 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1144 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1145 else 1146 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1147 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1148 /* kick Tx */ 1149 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1150 1151 /* 1152 * Set a timeout in case the chip goes out to lunch. 1153 */ 1154 ifp->if_timer = 5; 1155 } 1156 } 1157 1158 void 1159 nfe_watchdog(struct ifnet *ifp) 1160 { 1161 struct nfe_softc *sc = ifp->if_softc; 1162 1163 aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1164 1165 ifp->if_flags &= ~IFF_RUNNING; 1166 nfe_init(ifp); 1167 1168 ifp->if_oerrors++; 1169 } 1170 1171 int 1172 nfe_init(struct ifnet *ifp) 1173 { 1174 struct nfe_softc *sc = ifp->if_softc; 1175 uint32_t tmp; 1176 int rc = 0, s; 1177 1178 if (ifp->if_flags & IFF_RUNNING) 1179 return 0; 1180 1181 nfe_stop(ifp, 0); 1182 1183 NFE_WRITE(sc, NFE_TX_UNK, 0); 1184 NFE_WRITE(sc, NFE_STATUS, 0); 1185 1186 sc->rxtxctl = NFE_RXTX_BIT2; 1187 if (sc->sc_flags & NFE_40BIT_ADDR) 1188 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1189 else if (sc->sc_flags & NFE_JUMBO_SUP) 1190 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1191 if (sc->sc_flags & NFE_HW_CSUM) 1192 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1193 #if NVLAN > 0 1194 /* 1195 * Although the adapter is capable of stripping VLAN tags from received 1196 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1197 * purpose. This will be done in software by our network stack. 1198 */ 1199 if (sc->sc_flags & NFE_HW_VLAN) 1200 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1201 #endif 1202 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1203 DELAY(10); 1204 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1205 1206 #if NVLAN 1207 if (sc->sc_flags & NFE_HW_VLAN) 1208 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1209 #endif 1210 1211 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1212 1213 /* set MAC address */ 1214 nfe_set_macaddr(sc, sc->sc_enaddr); 1215 1216 /* tell MAC where rings are in memory */ 1217 #ifdef __LP64__ 1218 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1219 #endif 1220 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1221 #ifdef __LP64__ 1222 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1223 #endif 1224 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1225 1226 NFE_WRITE(sc, NFE_RING_SIZE, 1227 (NFE_RX_RING_COUNT - 1) << 16 | 1228 (NFE_TX_RING_COUNT - 1)); 1229 1230 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1231 1232 /* force MAC to wakeup */ 1233 tmp = NFE_READ(sc, NFE_PWR_STATE); 1234 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1235 DELAY(10); 1236 tmp = NFE_READ(sc, NFE_PWR_STATE); 1237 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1238 1239 s = splnet(); 1240 nfe_intr(sc); /* XXX clear IRQ status registers */ 1241 splx(s); 1242 1243 #if 1 1244 /* configure interrupts coalescing/mitigation */ 1245 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1246 #else 1247 /* no interrupt mitigation: one interrupt per packet */ 1248 NFE_WRITE(sc, NFE_IMTIMER, 970); 1249 #endif 1250 1251 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1252 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1253 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1254 1255 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1256 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1257 1258 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1259 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC); 1260 1261 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1262 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1263 DELAY(10); 1264 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1265 1266 /* set Rx filter */ 1267 nfe_setmulti(sc); 1268 1269 if ((rc = ether_mediachange(ifp)) != 0) 1270 goto out; 1271 1272 nfe_tick(sc); 1273 1274 /* enable Rx */ 1275 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1276 1277 /* enable Tx */ 1278 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1279 1280 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1281 1282 /* enable interrupts */ 1283 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1284 1285 callout_schedule(&sc->sc_tick_ch, hz); 1286 1287 ifp->if_flags |= IFF_RUNNING; 1288 ifp->if_flags &= ~IFF_OACTIVE; 1289 1290 out: 1291 return rc; 1292 } 1293 1294 void 1295 nfe_stop(struct ifnet *ifp, int disable) 1296 { 1297 struct nfe_softc *sc = ifp->if_softc; 1298 1299 callout_stop(&sc->sc_tick_ch); 1300 1301 ifp->if_timer = 0; 1302 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1303 1304 mii_down(&sc->sc_mii); 1305 1306 /* abort Tx */ 1307 NFE_WRITE(sc, NFE_TX_CTL, 0); 1308 1309 /* disable Rx */ 1310 NFE_WRITE(sc, NFE_RX_CTL, 0); 1311 1312 /* disable interrupts */ 1313 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1314 1315 /* reset Tx and Rx rings */ 1316 nfe_reset_tx_ring(sc, &sc->txq); 1317 nfe_reset_rx_ring(sc, &sc->rxq); 1318 } 1319 1320 int 1321 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1322 { 1323 struct nfe_desc32 *desc32; 1324 struct nfe_desc64 *desc64; 1325 struct nfe_rx_data *data; 1326 struct nfe_jbuf *jbuf; 1327 void **desc; 1328 bus_addr_t physaddr; 1329 int i, nsegs, error, descsize; 1330 1331 if (sc->sc_flags & NFE_40BIT_ADDR) { 1332 desc = (void **)&ring->desc64; 1333 descsize = sizeof (struct nfe_desc64); 1334 } else { 1335 desc = (void **)&ring->desc32; 1336 descsize = sizeof (struct nfe_desc32); 1337 } 1338 1339 ring->cur = ring->next = 0; 1340 ring->bufsz = MCLBYTES; 1341 1342 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1343 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1344 if (error != 0) { 1345 aprint_error_dev(sc->sc_dev, 1346 "could not create desc DMA map\n"); 1347 goto fail; 1348 } 1349 1350 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1351 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1352 if (error != 0) { 1353 aprint_error_dev(sc->sc_dev, 1354 "could not allocate DMA memory\n"); 1355 goto fail; 1356 } 1357 1358 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1359 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1360 if (error != 0) { 1361 aprint_error_dev(sc->sc_dev, 1362 "could not map desc DMA memory\n"); 1363 goto fail; 1364 } 1365 1366 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1367 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1368 if (error != 0) { 1369 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1370 goto fail; 1371 } 1372 1373 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1374 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1375 1376 if (sc->sc_flags & NFE_USE_JUMBO) { 1377 ring->bufsz = NFE_JBYTES; 1378 if ((error = nfe_jpool_alloc(sc)) != 0) { 1379 aprint_error_dev(sc->sc_dev, 1380 "could not allocate jumbo frames\n"); 1381 goto fail; 1382 } 1383 } 1384 1385 /* 1386 * Pre-allocate Rx buffers and populate Rx ring. 1387 */ 1388 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1389 data = &sc->rxq.data[i]; 1390 1391 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1392 if (data->m == NULL) { 1393 aprint_error_dev(sc->sc_dev, 1394 "could not allocate rx mbuf\n"); 1395 error = ENOMEM; 1396 goto fail; 1397 } 1398 1399 if (sc->sc_flags & NFE_USE_JUMBO) { 1400 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1401 aprint_error_dev(sc->sc_dev, 1402 "could not allocate jumbo buffer\n"); 1403 goto fail; 1404 } 1405 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1406 sc); 1407 1408 physaddr = jbuf->physaddr; 1409 } else { 1410 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1411 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1412 if (error != 0) { 1413 aprint_error_dev(sc->sc_dev, 1414 "could not create DMA map\n"); 1415 goto fail; 1416 } 1417 MCLGET(data->m, M_DONTWAIT); 1418 if (!(data->m->m_flags & M_EXT)) { 1419 aprint_error_dev(sc->sc_dev, 1420 "could not allocate mbuf cluster\n"); 1421 error = ENOMEM; 1422 goto fail; 1423 } 1424 1425 error = bus_dmamap_load(sc->sc_dmat, data->map, 1426 mtod(data->m, void *), MCLBYTES, NULL, 1427 BUS_DMA_READ | BUS_DMA_NOWAIT); 1428 if (error != 0) { 1429 aprint_error_dev(sc->sc_dev, 1430 "could not load rx buf DMA map"); 1431 goto fail; 1432 } 1433 physaddr = data->map->dm_segs[0].ds_addr; 1434 } 1435 1436 if (sc->sc_flags & NFE_40BIT_ADDR) { 1437 desc64 = &sc->rxq.desc64[i]; 1438 #if defined(__LP64__) 1439 desc64->physaddr[0] = htole32(physaddr >> 32); 1440 #endif 1441 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1442 desc64->length = htole16(sc->rxq.bufsz); 1443 desc64->flags = htole16(NFE_RX_READY); 1444 } else { 1445 desc32 = &sc->rxq.desc32[i]; 1446 desc32->physaddr = htole32(physaddr); 1447 desc32->length = htole16(sc->rxq.bufsz); 1448 desc32->flags = htole16(NFE_RX_READY); 1449 } 1450 } 1451 1452 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1453 BUS_DMASYNC_PREWRITE); 1454 1455 return 0; 1456 1457 fail: nfe_free_rx_ring(sc, ring); 1458 return error; 1459 } 1460 1461 void 1462 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1463 { 1464 int i; 1465 1466 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1467 if (sc->sc_flags & NFE_40BIT_ADDR) { 1468 ring->desc64[i].length = htole16(ring->bufsz); 1469 ring->desc64[i].flags = htole16(NFE_RX_READY); 1470 } else { 1471 ring->desc32[i].length = htole16(ring->bufsz); 1472 ring->desc32[i].flags = htole16(NFE_RX_READY); 1473 } 1474 } 1475 1476 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1477 BUS_DMASYNC_PREWRITE); 1478 1479 ring->cur = ring->next = 0; 1480 } 1481 1482 void 1483 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1484 { 1485 struct nfe_rx_data *data; 1486 void *desc; 1487 int i, descsize; 1488 1489 if (sc->sc_flags & NFE_40BIT_ADDR) { 1490 desc = ring->desc64; 1491 descsize = sizeof (struct nfe_desc64); 1492 } else { 1493 desc = ring->desc32; 1494 descsize = sizeof (struct nfe_desc32); 1495 } 1496 1497 if (desc != NULL) { 1498 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1499 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1500 bus_dmamap_unload(sc->sc_dmat, ring->map); 1501 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1502 NFE_RX_RING_COUNT * descsize); 1503 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1504 } 1505 1506 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1507 data = &ring->data[i]; 1508 1509 if (data->map != NULL) { 1510 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1511 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1512 bus_dmamap_unload(sc->sc_dmat, data->map); 1513 bus_dmamap_destroy(sc->sc_dmat, data->map); 1514 } 1515 if (data->m != NULL) 1516 m_freem(data->m); 1517 } 1518 } 1519 1520 struct nfe_jbuf * 1521 nfe_jalloc(struct nfe_softc *sc, int i) 1522 { 1523 struct nfe_jbuf *jbuf; 1524 1525 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1526 if (jbuf == NULL) 1527 return NULL; 1528 sc->rxq.jbufmap[i] = 1529 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1530 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1531 return jbuf; 1532 } 1533 1534 /* 1535 * This is called automatically by the network stack when the mbuf is freed. 1536 * Caution must be taken that the NIC might be reset by the time the mbuf is 1537 * freed. 1538 */ 1539 void 1540 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1541 { 1542 struct nfe_softc *sc = arg; 1543 struct nfe_jbuf *jbuf; 1544 int i; 1545 1546 /* find the jbuf from the base pointer */ 1547 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1548 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1549 aprint_error_dev(sc->sc_dev, 1550 "request to free a buffer (%p) not managed by us\n", buf); 1551 return; 1552 } 1553 jbuf = &sc->rxq.jbuf[i]; 1554 1555 /* ..and put it back in the free list */ 1556 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1557 1558 if (m != NULL) 1559 pool_cache_put(mb_cache, m); 1560 } 1561 1562 int 1563 nfe_jpool_alloc(struct nfe_softc *sc) 1564 { 1565 struct nfe_rx_ring *ring = &sc->rxq; 1566 struct nfe_jbuf *jbuf; 1567 bus_addr_t physaddr; 1568 char *buf; 1569 int i, nsegs, error; 1570 1571 /* 1572 * Allocate a big chunk of DMA'able memory. 1573 */ 1574 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1575 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1576 if (error != 0) { 1577 aprint_error_dev(sc->sc_dev, 1578 "could not create jumbo DMA map\n"); 1579 goto fail; 1580 } 1581 1582 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1583 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1584 if (error != 0) { 1585 aprint_error_dev(sc->sc_dev, 1586 "could not allocate jumbo DMA memory\n"); 1587 goto fail; 1588 } 1589 1590 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1591 &ring->jpool, BUS_DMA_NOWAIT); 1592 if (error != 0) { 1593 aprint_error_dev(sc->sc_dev, 1594 "could not map jumbo DMA memory\n"); 1595 goto fail; 1596 } 1597 1598 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1599 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1600 if (error != 0) { 1601 aprint_error_dev(sc->sc_dev, 1602 "could not load jumbo DMA map\n"); 1603 goto fail; 1604 } 1605 1606 /* ..and split it into 9KB chunks */ 1607 SLIST_INIT(&ring->jfreelist); 1608 1609 buf = ring->jpool; 1610 physaddr = ring->jmap->dm_segs[0].ds_addr; 1611 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1612 jbuf = &ring->jbuf[i]; 1613 1614 jbuf->buf = buf; 1615 jbuf->physaddr = physaddr; 1616 1617 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1618 1619 buf += NFE_JBYTES; 1620 physaddr += NFE_JBYTES; 1621 } 1622 1623 return 0; 1624 1625 fail: nfe_jpool_free(sc); 1626 return error; 1627 } 1628 1629 void 1630 nfe_jpool_free(struct nfe_softc *sc) 1631 { 1632 struct nfe_rx_ring *ring = &sc->rxq; 1633 1634 if (ring->jmap != NULL) { 1635 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1636 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1637 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1638 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1639 } 1640 if (ring->jpool != NULL) { 1641 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1642 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1643 } 1644 } 1645 1646 int 1647 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1648 { 1649 int i, nsegs, error; 1650 void **desc; 1651 int descsize; 1652 1653 if (sc->sc_flags & NFE_40BIT_ADDR) { 1654 desc = (void **)&ring->desc64; 1655 descsize = sizeof (struct nfe_desc64); 1656 } else { 1657 desc = (void **)&ring->desc32; 1658 descsize = sizeof (struct nfe_desc32); 1659 } 1660 1661 ring->queued = 0; 1662 ring->cur = ring->next = 0; 1663 1664 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1665 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1666 1667 if (error != 0) { 1668 aprint_error_dev(sc->sc_dev, 1669 "could not create desc DMA map\n"); 1670 goto fail; 1671 } 1672 1673 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1674 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1675 if (error != 0) { 1676 aprint_error_dev(sc->sc_dev, 1677 "could not allocate DMA memory\n"); 1678 goto fail; 1679 } 1680 1681 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1682 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1683 if (error != 0) { 1684 aprint_error_dev(sc->sc_dev, 1685 "could not map desc DMA memory\n"); 1686 goto fail; 1687 } 1688 1689 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1690 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1691 if (error != 0) { 1692 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1693 goto fail; 1694 } 1695 1696 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1697 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1698 1699 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1700 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1701 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1702 &ring->data[i].map); 1703 if (error != 0) { 1704 aprint_error_dev(sc->sc_dev, 1705 "could not create DMA map\n"); 1706 goto fail; 1707 } 1708 } 1709 1710 return 0; 1711 1712 fail: nfe_free_tx_ring(sc, ring); 1713 return error; 1714 } 1715 1716 void 1717 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1718 { 1719 struct nfe_tx_data *data; 1720 int i; 1721 1722 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1723 if (sc->sc_flags & NFE_40BIT_ADDR) 1724 ring->desc64[i].flags = 0; 1725 else 1726 ring->desc32[i].flags = 0; 1727 1728 data = &ring->data[i]; 1729 1730 if (data->m != NULL) { 1731 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1732 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1733 bus_dmamap_unload(sc->sc_dmat, data->active); 1734 m_freem(data->m); 1735 data->m = NULL; 1736 } 1737 } 1738 1739 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1740 BUS_DMASYNC_PREWRITE); 1741 1742 ring->queued = 0; 1743 ring->cur = ring->next = 0; 1744 } 1745 1746 void 1747 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1748 { 1749 struct nfe_tx_data *data; 1750 void *desc; 1751 int i, descsize; 1752 1753 if (sc->sc_flags & NFE_40BIT_ADDR) { 1754 desc = ring->desc64; 1755 descsize = sizeof (struct nfe_desc64); 1756 } else { 1757 desc = ring->desc32; 1758 descsize = sizeof (struct nfe_desc32); 1759 } 1760 1761 if (desc != NULL) { 1762 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1763 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1764 bus_dmamap_unload(sc->sc_dmat, ring->map); 1765 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1766 NFE_TX_RING_COUNT * descsize); 1767 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1768 } 1769 1770 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1771 data = &ring->data[i]; 1772 1773 if (data->m != NULL) { 1774 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1775 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1776 bus_dmamap_unload(sc->sc_dmat, data->active); 1777 m_freem(data->m); 1778 } 1779 } 1780 1781 /* ..and now actually destroy the DMA mappings */ 1782 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1783 data = &ring->data[i]; 1784 if (data->map == NULL) 1785 continue; 1786 bus_dmamap_destroy(sc->sc_dmat, data->map); 1787 } 1788 } 1789 1790 void 1791 nfe_setmulti(struct nfe_softc *sc) 1792 { 1793 struct ethercom *ec = &sc->sc_ethercom; 1794 struct ifnet *ifp = &ec->ec_if; 1795 struct ether_multi *enm; 1796 struct ether_multistep step; 1797 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1798 uint32_t filter = NFE_RXFILTER_MAGIC; 1799 int i; 1800 1801 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1802 bzero(addr, ETHER_ADDR_LEN); 1803 bzero(mask, ETHER_ADDR_LEN); 1804 goto done; 1805 } 1806 1807 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1808 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1809 1810 ETHER_FIRST_MULTI(step, ec, enm); 1811 while (enm != NULL) { 1812 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1813 ifp->if_flags |= IFF_ALLMULTI; 1814 bzero(addr, ETHER_ADDR_LEN); 1815 bzero(mask, ETHER_ADDR_LEN); 1816 goto done; 1817 } 1818 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1819 addr[i] &= enm->enm_addrlo[i]; 1820 mask[i] &= ~enm->enm_addrlo[i]; 1821 } 1822 ETHER_NEXT_MULTI(step, enm); 1823 } 1824 for (i = 0; i < ETHER_ADDR_LEN; i++) 1825 mask[i] |= addr[i]; 1826 1827 done: 1828 addr[0] |= 0x01; /* make sure multicast bit is set */ 1829 1830 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1831 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1832 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1833 addr[5] << 8 | addr[4]); 1834 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1835 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1836 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1837 mask[5] << 8 | mask[4]); 1838 1839 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1840 NFE_WRITE(sc, NFE_RXFILTER, filter); 1841 } 1842 1843 void 1844 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1845 { 1846 uint32_t tmp; 1847 1848 if ((sc->sc_flags & NFE_CORRECT_MACADDR) == 0) { 1849 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1850 addr[0] = (tmp >> 8) & 0xff; 1851 addr[1] = (tmp & 0xff); 1852 1853 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1854 addr[2] = (tmp >> 24) & 0xff; 1855 addr[3] = (tmp >> 16) & 0xff; 1856 addr[4] = (tmp >> 8) & 0xff; 1857 addr[5] = (tmp & 0xff); 1858 } else { 1859 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1860 addr[5] = (tmp >> 8) & 0xff; 1861 addr[4] = (tmp & 0xff); 1862 1863 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1864 addr[3] = (tmp >> 24) & 0xff; 1865 addr[2] = (tmp >> 16) & 0xff; 1866 addr[1] = (tmp >> 8) & 0xff; 1867 addr[0] = (tmp & 0xff); 1868 } 1869 } 1870 1871 void 1872 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1873 { 1874 NFE_WRITE(sc, NFE_MACADDR_LO, 1875 addr[5] << 8 | addr[4]); 1876 NFE_WRITE(sc, NFE_MACADDR_HI, 1877 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1878 } 1879 1880 void 1881 nfe_tick(void *arg) 1882 { 1883 struct nfe_softc *sc = arg; 1884 int s; 1885 1886 s = splnet(); 1887 mii_tick(&sc->sc_mii); 1888 splx(s); 1889 1890 callout_schedule(&sc->sc_tick_ch, hz); 1891 } 1892
Indexes created Tue Sep 30 10:09:55 GMT 2025