if_nfe.c revision 1.33
1 /* $NetBSD: if_nfe.c,v 1.33 2008/04/17 20:16:46 christos Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.77 2008/02/05 16:52:50 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006, 2007 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.33 2008/04/17 20:16:46 christos Exp $"); 25 26 #include "opt_inet.h" 27 #include "bpfilter.h" 28 #include "vlan.h" 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/types.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/queue.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/callout.h> 40 #include <sys/socket.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/pci/if_nfereg.h> 74 #include <dev/pci/if_nfevar.h> 75 76 int nfe_match(device_t, cfdata_t, void *); 77 void nfe_attach(device_t, device_t, void *); 78 void nfe_power(int, void *); 79 void nfe_miibus_statchg(device_t); 80 int nfe_miibus_readreg(device_t, int, int); 81 void nfe_miibus_writereg(device_t, int, int, int); 82 int nfe_intr(void *); 83 int nfe_ioctl(struct ifnet *, u_long, void *); 84 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 85 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 86 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 87 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 88 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 89 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 90 void nfe_rxeof(struct nfe_softc *); 91 void nfe_txeof(struct nfe_softc *); 92 int nfe_encap(struct nfe_softc *, struct mbuf *); 93 void nfe_start(struct ifnet *); 94 void nfe_watchdog(struct ifnet *); 95 int nfe_init(struct ifnet *); 96 void nfe_stop(struct ifnet *, int); 97 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 98 void nfe_jfree(struct mbuf *, void *, size_t, void *); 99 int nfe_jpool_alloc(struct nfe_softc *); 100 void nfe_jpool_free(struct nfe_softc *); 101 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 102 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 105 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 void nfe_setmulti(struct nfe_softc *); 108 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 109 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 110 void nfe_tick(void *); 111 112 CFATTACH_DECL_NEW(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, 113 NULL, NULL); 114 115 #ifdef NFE_DEBUG 116 int nfedebug = 0; 117 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 118 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 119 #else 120 #define DPRINTF(x) 121 #define DPRINTFN(n,x) 122 #endif 123 124 /* deal with naming differences */ 125 126 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 127 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 128 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 129 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 130 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 131 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 132 133 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 134 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 135 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 136 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 137 138 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 139 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 140 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 141 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 142 143 #ifdef _LP64 144 #define __LP64__ 1 145 #endif 146 147 const struct nfe_product { 148 pci_vendor_id_t vendor; 149 pci_product_id_t product; 150 } nfe_devices[] = { 151 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 152 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 153 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 155 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1 }, 183 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2 }, 184 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3 }, 185 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4 }, 186 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1 }, 187 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2 }, 188 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3 }, 189 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4 } 190 }; 191 192 int 193 nfe_match(device_t dev, cfdata_t match, void *aux) 194 { 195 struct pci_attach_args *pa = aux; 196 const struct nfe_product *np; 197 int i; 198 199 for (i = 0; i < sizeof(nfe_devices) / sizeof(nfe_devices[0]); i++) { 200 np = &nfe_devices[i]; 201 if (PCI_VENDOR(pa->pa_id) == np->vendor && 202 PCI_PRODUCT(pa->pa_id) == np->product) 203 return 1; 204 } 205 return 0; 206 } 207 208 void 209 nfe_attach(device_t parent, device_t self, void *aux) 210 { 211 struct nfe_softc *sc = device_private(self); 212 struct pci_attach_args *pa = aux; 213 pci_chipset_tag_t pc = pa->pa_pc; 214 pci_intr_handle_t ih; 215 const char *intrstr; 216 struct ifnet *ifp; 217 bus_size_t memsize; 218 pcireg_t memtype; 219 char devinfo[256]; 220 221 sc->sc_dev = self; 222 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 223 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 224 225 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 226 switch (memtype) { 227 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 228 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 229 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 230 &sc->sc_memh, NULL, &memsize) == 0) 231 break; 232 /* FALLTHROUGH */ 233 default: 234 aprint_error_dev(self, "could not map mem space\n"); 235 return; 236 } 237 238 if (pci_intr_map(pa, &ih) != 0) { 239 aprint_error_dev(self, "could not map interrupt\n"); 240 return; 241 } 242 243 intrstr = pci_intr_string(pc, ih); 244 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 245 if (sc->sc_ih == NULL) { 246 aprint_error_dev(self, "could not establish interrupt"); 247 if (intrstr != NULL) 248 aprint_normal(" at %s", intrstr); 249 aprint_normal("\n"); 250 return; 251 } 252 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 253 254 sc->sc_dmat = pa->pa_dmat; 255 256 sc->sc_flags = 0; 257 258 switch (PCI_PRODUCT(pa->pa_id)) { 259 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 260 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 261 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 262 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 263 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 264 break; 265 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 266 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 267 sc->sc_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT; 268 break; 269 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 270 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 271 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 272 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 273 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 274 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 275 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 276 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 277 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 278 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 279 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 280 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 281 sc->sc_flags |= NFE_40BIT_ADDR | NFE_CORRECT_MACADDR | 282 NFE_PWR_MGMT; 283 break; 284 case PCI_PRODUCT_NVIDIA_MCP77_LAN1: 285 case PCI_PRODUCT_NVIDIA_MCP77_LAN2: 286 case PCI_PRODUCT_NVIDIA_MCP77_LAN3: 287 case PCI_PRODUCT_NVIDIA_MCP77_LAN4: 288 case PCI_PRODUCT_NVIDIA_MCP79_LAN1: 289 case PCI_PRODUCT_NVIDIA_MCP79_LAN2: 290 case PCI_PRODUCT_NVIDIA_MCP79_LAN3: 291 case PCI_PRODUCT_NVIDIA_MCP79_LAN4: 292 sc->sc_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | 293 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 294 break; 295 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 296 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 297 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 298 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 299 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 300 break; 301 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 302 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 303 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 304 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 305 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 306 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 307 break; 308 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 309 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 310 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 311 NFE_HW_VLAN | NFE_PWR_MGMT; 312 break; 313 } 314 315 if ((sc->sc_flags & NFE_PWR_MGMT) != 0) { 316 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 317 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 318 DELAY(100); 319 NFE_WRITE(sc, NFE_MAC_RESET, 0); 320 DELAY(100); 321 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 322 NFE_WRITE(sc, NFE_PWR2_CTL, 323 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_WAKEUP_MASK); 324 } 325 326 #ifdef notyet 327 /* enable jumbo frames for adapters that support it */ 328 if (sc->sc_flags & NFE_JUMBO_SUP) 329 sc->sc_flags |= NFE_USE_JUMBO; 330 #endif 331 332 /* Check for reversed ethernet address */ 333 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 334 sc->sc_flags |= NFE_CORRECT_MACADDR; 335 336 nfe_get_macaddr(sc, sc->sc_enaddr); 337 aprint_normal_dev(self, "Ethernet address %s\n", 338 ether_sprintf(sc->sc_enaddr)); 339 340 /* 341 * Allocate Tx and Rx rings. 342 */ 343 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 344 aprint_error_dev(self, "could not allocate Tx ring\n"); 345 return; 346 } 347 348 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 349 aprint_error_dev(self, "could not allocate Rx ring\n"); 350 nfe_free_tx_ring(sc, &sc->txq); 351 return; 352 } 353 354 ifp = &sc->sc_ethercom.ec_if; 355 ifp->if_softc = sc; 356 ifp->if_mtu = ETHERMTU; 357 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 358 ifp->if_ioctl = nfe_ioctl; 359 ifp->if_start = nfe_start; 360 ifp->if_stop = nfe_stop; 361 ifp->if_watchdog = nfe_watchdog; 362 ifp->if_init = nfe_init; 363 ifp->if_baudrate = IF_Gbps(1); 364 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 365 IFQ_SET_READY(&ifp->if_snd); 366 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 367 368 #ifdef notyet 369 if (sc->sc_flags & NFE_USE_JUMBO) 370 ifp->if_hardmtu = NFE_JUMBO_MTU; 371 #endif 372 373 #if NVLAN > 0 374 if (sc->sc_flags & NFE_HW_VLAN) 375 sc->sc_ethercom.ec_capabilities |= 376 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 377 #endif 378 if (sc->sc_flags & NFE_HW_CSUM) { 379 ifp->if_capabilities |= 380 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 381 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 382 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 383 } 384 385 sc->sc_mii.mii_ifp = ifp; 386 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 387 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 388 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 389 390 sc->sc_ethercom.ec_mii = &sc->sc_mii; 391 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 392 ether_mediastatus); 393 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 394 MII_OFFSET_ANY, 0); 395 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 396 aprint_error_dev(self, "no PHY found!\n"); 397 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 398 0, NULL); 399 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 400 } else 401 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 402 403 if_attach(ifp); 404 ether_ifattach(ifp, sc->sc_enaddr); 405 406 callout_init(&sc->sc_tick_ch, 0); 407 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 408 409 if (!pmf_device_register(self, NULL, NULL)) 410 aprint_error_dev(self, "couldn't establish power handler\n"); 411 else 412 pmf_class_network_register(self, ifp); 413 } 414 415 void 416 nfe_miibus_statchg(device_t dev) 417 { 418 struct nfe_softc *sc = device_private(dev); 419 struct mii_data *mii = &sc->sc_mii; 420 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 421 422 phy = NFE_READ(sc, NFE_PHY_IFACE); 423 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 424 425 seed = NFE_READ(sc, NFE_RNDSEED); 426 seed &= ~NFE_SEED_MASK; 427 428 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 429 phy |= NFE_PHY_HDX; /* half-duplex */ 430 misc |= NFE_MISC1_HDX; 431 } 432 433 switch (IFM_SUBTYPE(mii->mii_media_active)) { 434 case IFM_1000_T: /* full-duplex only */ 435 link |= NFE_MEDIA_1000T; 436 seed |= NFE_SEED_1000T; 437 phy |= NFE_PHY_1000T; 438 break; 439 case IFM_100_TX: 440 link |= NFE_MEDIA_100TX; 441 seed |= NFE_SEED_100TX; 442 phy |= NFE_PHY_100TX; 443 break; 444 case IFM_10_T: 445 link |= NFE_MEDIA_10T; 446 seed |= NFE_SEED_10T; 447 break; 448 } 449 450 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 451 452 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 453 NFE_WRITE(sc, NFE_MISC1, misc); 454 NFE_WRITE(sc, NFE_LINKSPEED, link); 455 } 456 457 int 458 nfe_miibus_readreg(device_t dev, int phy, int reg) 459 { 460 struct nfe_softc *sc = device_private(dev); 461 uint32_t val; 462 int ntries; 463 464 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 465 466 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 467 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 468 DELAY(100); 469 } 470 471 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 472 473 for (ntries = 0; ntries < 1000; ntries++) { 474 DELAY(100); 475 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 476 break; 477 } 478 if (ntries == 1000) { 479 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 480 device_xname(sc->sc_dev))); 481 return 0; 482 } 483 484 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 485 DPRINTFN(2, ("%s: could not read PHY\n", 486 device_xname(sc->sc_dev))); 487 return 0; 488 } 489 490 val = NFE_READ(sc, NFE_PHY_DATA); 491 if (val != 0xffffffff && val != 0) 492 sc->mii_phyaddr = phy; 493 494 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 495 device_xname(sc->sc_dev), phy, reg, val)); 496 497 return val; 498 } 499 500 void 501 nfe_miibus_writereg(device_t dev, int phy, int reg, int val) 502 { 503 struct nfe_softc *sc = device_private(dev); 504 uint32_t ctl; 505 int ntries; 506 507 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 508 509 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 510 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 511 DELAY(100); 512 } 513 514 NFE_WRITE(sc, NFE_PHY_DATA, val); 515 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 516 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 517 518 for (ntries = 0; ntries < 1000; ntries++) { 519 DELAY(100); 520 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 521 break; 522 } 523 #ifdef NFE_DEBUG 524 if (nfedebug >= 2 && ntries == 1000) 525 printf("could not write to PHY\n"); 526 #endif 527 } 528 529 int 530 nfe_intr(void *arg) 531 { 532 struct nfe_softc *sc = arg; 533 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 534 uint32_t r; 535 int handled; 536 537 if ((ifp->if_flags & IFF_UP) == 0) 538 return 0; 539 540 handled = 0; 541 542 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 543 544 for (;;) { 545 r = NFE_READ(sc, NFE_IRQ_STATUS); 546 if ((r & NFE_IRQ_WANTED) == 0) 547 break; 548 549 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 550 handled = 1; 551 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 552 553 if ((r & (NFE_IRQ_RXERR|NFE_IRQ_RX_NOBUF|NFE_IRQ_RX)) != 0) { 554 /* check Rx ring */ 555 nfe_rxeof(sc); 556 } 557 if ((r & (NFE_IRQ_TXERR|NFE_IRQ_TXERR2|NFE_IRQ_TX_DONE)) != 0) { 558 /* check Tx ring */ 559 nfe_txeof(sc); 560 } 561 if ((r & NFE_IRQ_LINK) != 0) { 562 NFE_READ(sc, NFE_PHY_STATUS); 563 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 564 DPRINTF(("%s: link state changed\n", 565 device_xname(sc->sc_dev))); 566 } 567 } 568 569 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 570 571 if (handled && !IF_IS_EMPTY(&ifp->if_snd)) 572 nfe_start(ifp); 573 574 return handled; 575 } 576 577 int 578 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 579 { 580 struct nfe_softc *sc = ifp->if_softc; 581 struct ifreq *ifr = (struct ifreq *)data; 582 struct ifaddr *ifa = (struct ifaddr *)data; 583 int s, error = 0; 584 585 s = splnet(); 586 587 switch (cmd) { 588 case SIOCSIFADDR: 589 ifp->if_flags |= IFF_UP; 590 nfe_init(ifp); 591 switch (ifa->ifa_addr->sa_family) { 592 #ifdef INET 593 case AF_INET: 594 arp_ifinit(ifp, ifa); 595 break; 596 #endif 597 default: 598 break; 599 } 600 break; 601 case SIOCSIFMTU: 602 if (ifr->ifr_mtu < ETHERMIN || 603 ((sc->sc_flags & NFE_USE_JUMBO) && 604 ifr->ifr_mtu > ETHERMTU_JUMBO) || 605 (!(sc->sc_flags & NFE_USE_JUMBO) && 606 ifr->ifr_mtu > ETHERMTU)) 607 error = EINVAL; 608 else if ((error = ifioctl_common(ifp, cmd, data)) == ENETRESET) 609 error = 0; 610 break; 611 case SIOCSIFFLAGS: 612 if (ifp->if_flags & IFF_UP) { 613 /* 614 * If only the PROMISC or ALLMULTI flag changes, then 615 * don't do a full re-init of the chip, just update 616 * the Rx filter. 617 */ 618 if ((ifp->if_flags & IFF_RUNNING) && 619 ((ifp->if_flags ^ sc->sc_if_flags) & 620 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 621 nfe_setmulti(sc); 622 } else 623 nfe_init(ifp); 624 } else { 625 if (ifp->if_flags & IFF_RUNNING) 626 nfe_stop(ifp, 1); 627 } 628 sc->sc_if_flags = ifp->if_flags; 629 break; 630 default: 631 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 632 break; 633 634 error = 0; 635 636 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 637 ; 638 else if (ifp->if_flags & IFF_RUNNING) 639 nfe_setmulti(sc); 640 break; 641 } 642 643 splx(s); 644 645 return error; 646 } 647 648 void 649 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 650 { 651 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 652 (char *)desc32 - (char *)sc->txq.desc32, 653 sizeof (struct nfe_desc32), ops); 654 } 655 656 void 657 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 658 { 659 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 660 (char *)desc64 - (char *)sc->txq.desc64, 661 sizeof (struct nfe_desc64), ops); 662 } 663 664 void 665 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 666 { 667 if (end > start) { 668 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 669 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 670 (char *)&sc->txq.desc32[end] - 671 (char *)&sc->txq.desc32[start], ops); 672 return; 673 } 674 /* sync from 'start' to end of ring */ 675 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 676 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 677 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 678 (char *)&sc->txq.desc32[start], ops); 679 680 /* sync from start of ring to 'end' */ 681 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 682 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 683 } 684 685 void 686 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 687 { 688 if (end > start) { 689 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 690 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 691 (char *)&sc->txq.desc64[end] - 692 (char *)&sc->txq.desc64[start], ops); 693 return; 694 } 695 /* sync from 'start' to end of ring */ 696 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 697 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 698 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 699 (char *)&sc->txq.desc64[start], ops); 700 701 /* sync from start of ring to 'end' */ 702 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 703 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 704 } 705 706 void 707 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 708 { 709 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 710 (char *)desc32 - (char *)sc->rxq.desc32, 711 sizeof (struct nfe_desc32), ops); 712 } 713 714 void 715 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 716 { 717 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 718 (char *)desc64 - (char *)sc->rxq.desc64, 719 sizeof (struct nfe_desc64), ops); 720 } 721 722 void 723 nfe_rxeof(struct nfe_softc *sc) 724 { 725 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 726 struct nfe_desc32 *desc32; 727 struct nfe_desc64 *desc64; 728 struct nfe_rx_data *data; 729 struct nfe_jbuf *jbuf; 730 struct mbuf *m, *mnew; 731 bus_addr_t physaddr; 732 uint16_t flags; 733 int error, len, i; 734 735 desc32 = NULL; 736 desc64 = NULL; 737 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 738 data = &sc->rxq.data[i]; 739 740 if (sc->sc_flags & NFE_40BIT_ADDR) { 741 desc64 = &sc->rxq.desc64[i]; 742 nfe_rxdesc64_sync(sc, desc64, 743 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 744 745 flags = le16toh(desc64->flags); 746 len = le16toh(desc64->length) & 0x3fff; 747 } else { 748 desc32 = &sc->rxq.desc32[i]; 749 nfe_rxdesc32_sync(sc, desc32, 750 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 751 752 flags = le16toh(desc32->flags); 753 len = le16toh(desc32->length) & 0x3fff; 754 } 755 756 if ((flags & NFE_RX_READY) != 0) 757 break; 758 759 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 760 if ((flags & NFE_RX_VALID_V1) == 0) 761 goto skip; 762 763 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 764 flags &= ~NFE_RX_ERROR; 765 len--; /* fix buffer length */ 766 } 767 } else { 768 if ((flags & NFE_RX_VALID_V2) == 0) 769 goto skip; 770 771 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 772 flags &= ~NFE_RX_ERROR; 773 len--; /* fix buffer length */ 774 } 775 } 776 777 if (flags & NFE_RX_ERROR) { 778 ifp->if_ierrors++; 779 goto skip; 780 } 781 782 /* 783 * Try to allocate a new mbuf for this ring element and load 784 * it before processing the current mbuf. If the ring element 785 * cannot be loaded, drop the received packet and reuse the 786 * old mbuf. In the unlikely case that the old mbuf can't be 787 * reloaded either, explicitly panic. 788 */ 789 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 790 if (mnew == NULL) { 791 ifp->if_ierrors++; 792 goto skip; 793 } 794 795 if (sc->sc_flags & NFE_USE_JUMBO) { 796 physaddr = 797 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 798 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 799 if (len > MCLBYTES) { 800 m_freem(mnew); 801 ifp->if_ierrors++; 802 goto skip1; 803 } 804 MCLGET(mnew, M_DONTWAIT); 805 if ((mnew->m_flags & M_EXT) == 0) { 806 m_freem(mnew); 807 ifp->if_ierrors++; 808 goto skip1; 809 } 810 811 (void)memcpy(mtod(mnew, void *), 812 mtod(data->m, const void *), len); 813 m = mnew; 814 goto mbufcopied; 815 } else { 816 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 817 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 818 mtod(data->m, char *) - (char *)sc->rxq.jpool, 819 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 820 821 physaddr = jbuf->physaddr; 822 } 823 } else { 824 MCLGET(mnew, M_DONTWAIT); 825 if ((mnew->m_flags & M_EXT) == 0) { 826 m_freem(mnew); 827 ifp->if_ierrors++; 828 goto skip; 829 } 830 831 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 832 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 833 bus_dmamap_unload(sc->sc_dmat, data->map); 834 835 error = bus_dmamap_load(sc->sc_dmat, data->map, 836 mtod(mnew, void *), MCLBYTES, NULL, 837 BUS_DMA_READ | BUS_DMA_NOWAIT); 838 if (error != 0) { 839 m_freem(mnew); 840 841 /* try to reload the old mbuf */ 842 error = bus_dmamap_load(sc->sc_dmat, data->map, 843 mtod(data->m, void *), MCLBYTES, NULL, 844 BUS_DMA_READ | BUS_DMA_NOWAIT); 845 if (error != 0) { 846 /* very unlikely that it will fail.. */ 847 panic("%s: could not load old rx mbuf", 848 device_xname(sc->sc_dev)); 849 } 850 ifp->if_ierrors++; 851 goto skip; 852 } 853 physaddr = data->map->dm_segs[0].ds_addr; 854 } 855 856 /* 857 * New mbuf successfully loaded, update Rx ring and continue 858 * processing. 859 */ 860 m = data->m; 861 data->m = mnew; 862 863 mbufcopied: 864 /* finalize mbuf */ 865 m->m_pkthdr.len = m->m_len = len; 866 m->m_pkthdr.rcvif = ifp; 867 868 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 869 /* 870 * XXX 871 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 872 */ 873 if (flags & NFE_RX_IP_CSUMOK) { 874 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 875 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 876 device_xname(sc->sc_dev))); 877 } 878 /* 879 * XXX 880 * no way to check M_CSUM_TCP_UDP_BAD or 881 * other protocols? 882 */ 883 if (flags & NFE_RX_UDP_CSUMOK) { 884 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 885 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 886 device_xname(sc->sc_dev))); 887 } else if (flags & NFE_RX_TCP_CSUMOK) { 888 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 889 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 890 device_xname(sc->sc_dev))); 891 } 892 } 893 #if NBPFILTER > 0 894 if (ifp->if_bpf) 895 bpf_mtap(ifp->if_bpf, m); 896 #endif 897 ifp->if_ipackets++; 898 (*ifp->if_input)(ifp, m); 899 900 skip1: 901 /* update mapping address in h/w descriptor */ 902 if (sc->sc_flags & NFE_40BIT_ADDR) { 903 #if defined(__LP64__) 904 desc64->physaddr[0] = htole32(physaddr >> 32); 905 #endif 906 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 907 } else { 908 desc32->physaddr = htole32(physaddr); 909 } 910 911 skip: 912 if (sc->sc_flags & NFE_40BIT_ADDR) { 913 desc64->length = htole16(sc->rxq.bufsz); 914 desc64->flags = htole16(NFE_RX_READY); 915 916 nfe_rxdesc64_sync(sc, desc64, 917 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 918 } else { 919 desc32->length = htole16(sc->rxq.bufsz); 920 desc32->flags = htole16(NFE_RX_READY); 921 922 nfe_rxdesc32_sync(sc, desc32, 923 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 924 } 925 } 926 /* update current RX pointer */ 927 sc->rxq.cur = i; 928 } 929 930 void 931 nfe_txeof(struct nfe_softc *sc) 932 { 933 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 934 struct nfe_desc32 *desc32; 935 struct nfe_desc64 *desc64; 936 struct nfe_tx_data *data = NULL; 937 int i; 938 uint16_t flags; 939 char buf[128]; 940 941 for (i = sc->txq.next; 942 sc->txq.queued > 0; 943 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 944 if (sc->sc_flags & NFE_40BIT_ADDR) { 945 desc64 = &sc->txq.desc64[i]; 946 nfe_txdesc64_sync(sc, desc64, 947 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 948 949 flags = le16toh(desc64->flags); 950 } else { 951 desc32 = &sc->txq.desc32[i]; 952 nfe_txdesc32_sync(sc, desc32, 953 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 954 955 flags = le16toh(desc32->flags); 956 } 957 958 if ((flags & NFE_TX_VALID) != 0) 959 break; 960 961 data = &sc->txq.data[i]; 962 963 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 964 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 965 data->m == NULL) 966 continue; 967 968 if ((flags & NFE_TX_ERROR_V1) != 0) { 969 aprint_error_dev(sc->sc_dev, "tx v1 error %s\n", 970 bitmask_snprintf(flags, NFE_V1_TXERR, 971 buf, sizeof(buf))); 972 ifp->if_oerrors++; 973 } else 974 ifp->if_opackets++; 975 } else { 976 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 977 data->m == NULL) 978 continue; 979 980 if ((flags & NFE_TX_ERROR_V2) != 0) { 981 aprint_error_dev(sc->sc_dev, "tx v2 error %s\n", 982 bitmask_snprintf(flags, NFE_V2_TXERR, 983 buf, sizeof(buf))); 984 ifp->if_oerrors++; 985 } else 986 ifp->if_opackets++; 987 } 988 989 if (data->m == NULL) { /* should not get there */ 990 aprint_error_dev(sc->sc_dev, 991 "last fragment bit w/o associated mbuf!\n"); 992 continue; 993 } 994 995 /* last fragment of the mbuf chain transmitted */ 996 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 997 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 998 bus_dmamap_unload(sc->sc_dmat, data->active); 999 m_freem(data->m); 1000 data->m = NULL; 1001 } 1002 1003 sc->txq.next = i; 1004 1005 if (sc->txq.queued < NFE_TX_RING_COUNT) { 1006 /* at least one slot freed */ 1007 ifp->if_flags &= ~IFF_OACTIVE; 1008 } 1009 1010 if (sc->txq.queued == 0) { 1011 /* all queued packets are sent */ 1012 ifp->if_timer = 0; 1013 } 1014 } 1015 1016 int 1017 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 1018 { 1019 struct nfe_desc32 *desc32; 1020 struct nfe_desc64 *desc64; 1021 struct nfe_tx_data *data; 1022 bus_dmamap_t map; 1023 uint16_t flags, csumflags; 1024 #if NVLAN > 0 1025 struct m_tag *mtag; 1026 uint32_t vtag = 0; 1027 #endif 1028 int error, i, first; 1029 1030 desc32 = NULL; 1031 desc64 = NULL; 1032 data = NULL; 1033 1034 flags = 0; 1035 csumflags = 0; 1036 first = sc->txq.cur; 1037 1038 map = sc->txq.data[first].map; 1039 1040 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1041 if (error != 0) { 1042 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1043 error); 1044 return error; 1045 } 1046 1047 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1048 bus_dmamap_unload(sc->sc_dmat, map); 1049 return ENOBUFS; 1050 } 1051 1052 #if NVLAN > 0 1053 /* setup h/w VLAN tagging */ 1054 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1055 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1056 #endif 1057 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1058 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1059 csumflags |= NFE_TX_IP_CSUM; 1060 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1061 csumflags |= NFE_TX_TCP_UDP_CSUM; 1062 } 1063 1064 for (i = 0; i < map->dm_nsegs; i++) { 1065 data = &sc->txq.data[sc->txq.cur]; 1066 1067 if (sc->sc_flags & NFE_40BIT_ADDR) { 1068 desc64 = &sc->txq.desc64[sc->txq.cur]; 1069 #if defined(__LP64__) 1070 desc64->physaddr[0] = 1071 htole32(map->dm_segs[i].ds_addr >> 32); 1072 #endif 1073 desc64->physaddr[1] = 1074 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1075 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1076 desc64->flags = htole16(flags); 1077 desc64->vtag = 0; 1078 } else { 1079 desc32 = &sc->txq.desc32[sc->txq.cur]; 1080 1081 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1082 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1083 desc32->flags = htole16(flags); 1084 } 1085 1086 /* 1087 * Setting of the valid bit in the first descriptor is 1088 * deferred until the whole chain is fully setup. 1089 */ 1090 flags |= NFE_TX_VALID; 1091 1092 sc->txq.queued++; 1093 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1094 } 1095 1096 /* the whole mbuf chain has been setup */ 1097 if (sc->sc_flags & NFE_40BIT_ADDR) { 1098 /* fix last descriptor */ 1099 flags |= NFE_TX_LASTFRAG_V2; 1100 desc64->flags = htole16(flags); 1101 1102 /* Checksum flags and vtag belong to the first fragment only. */ 1103 #if NVLAN > 0 1104 sc->txq.desc64[first].vtag = htole32(vtag); 1105 #endif 1106 sc->txq.desc64[first].flags |= htole16(csumflags); 1107 1108 /* finally, set the valid bit in the first descriptor */ 1109 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1110 } else { 1111 /* fix last descriptor */ 1112 if (sc->sc_flags & NFE_JUMBO_SUP) 1113 flags |= NFE_TX_LASTFRAG_V2; 1114 else 1115 flags |= NFE_TX_LASTFRAG_V1; 1116 desc32->flags = htole16(flags); 1117 1118 /* Checksum flags belong to the first fragment only. */ 1119 sc->txq.desc32[first].flags |= htole16(csumflags); 1120 1121 /* finally, set the valid bit in the first descriptor */ 1122 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1123 } 1124 1125 data->m = m0; 1126 data->active = map; 1127 1128 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1129 BUS_DMASYNC_PREWRITE); 1130 1131 return 0; 1132 } 1133 1134 void 1135 nfe_start(struct ifnet *ifp) 1136 { 1137 struct nfe_softc *sc = ifp->if_softc; 1138 int old = sc->txq.queued; 1139 struct mbuf *m0; 1140 1141 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1142 return; 1143 1144 for (;;) { 1145 IFQ_POLL(&ifp->if_snd, m0); 1146 if (m0 == NULL) 1147 break; 1148 1149 if (nfe_encap(sc, m0) != 0) { 1150 ifp->if_flags |= IFF_OACTIVE; 1151 break; 1152 } 1153 1154 /* packet put in h/w queue, remove from s/w queue */ 1155 IFQ_DEQUEUE(&ifp->if_snd, m0); 1156 1157 #if NBPFILTER > 0 1158 if (ifp->if_bpf != NULL) 1159 bpf_mtap(ifp->if_bpf, m0); 1160 #endif 1161 } 1162 1163 if (sc->txq.queued != old) { 1164 /* packets are queued */ 1165 if (sc->sc_flags & NFE_40BIT_ADDR) 1166 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1167 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1168 else 1169 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1170 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1171 /* kick Tx */ 1172 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1173 1174 /* 1175 * Set a timeout in case the chip goes out to lunch. 1176 */ 1177 ifp->if_timer = 5; 1178 } 1179 } 1180 1181 void 1182 nfe_watchdog(struct ifnet *ifp) 1183 { 1184 struct nfe_softc *sc = ifp->if_softc; 1185 1186 aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1187 1188 ifp->if_flags &= ~IFF_RUNNING; 1189 nfe_init(ifp); 1190 1191 ifp->if_oerrors++; 1192 } 1193 1194 int 1195 nfe_init(struct ifnet *ifp) 1196 { 1197 struct nfe_softc *sc = ifp->if_softc; 1198 uint32_t tmp; 1199 int rc = 0, s; 1200 1201 if (ifp->if_flags & IFF_RUNNING) 1202 return 0; 1203 1204 nfe_stop(ifp, 0); 1205 1206 NFE_WRITE(sc, NFE_TX_UNK, 0); 1207 NFE_WRITE(sc, NFE_STATUS, 0); 1208 1209 sc->rxtxctl = NFE_RXTX_BIT2; 1210 if (sc->sc_flags & NFE_40BIT_ADDR) 1211 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1212 else if (sc->sc_flags & NFE_JUMBO_SUP) 1213 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1214 if (sc->sc_flags & NFE_HW_CSUM) 1215 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1216 #if NVLAN > 0 1217 /* 1218 * Although the adapter is capable of stripping VLAN tags from received 1219 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1220 * purpose. This will be done in software by our network stack. 1221 */ 1222 if (sc->sc_flags & NFE_HW_VLAN) 1223 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1224 #endif 1225 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1226 DELAY(10); 1227 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1228 1229 #if NVLAN 1230 if (sc->sc_flags & NFE_HW_VLAN) 1231 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1232 #endif 1233 1234 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1235 1236 /* set MAC address */ 1237 nfe_set_macaddr(sc, sc->sc_enaddr); 1238 1239 /* tell MAC where rings are in memory */ 1240 #ifdef __LP64__ 1241 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1242 #endif 1243 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1244 #ifdef __LP64__ 1245 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1246 #endif 1247 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1248 1249 NFE_WRITE(sc, NFE_RING_SIZE, 1250 (NFE_RX_RING_COUNT - 1) << 16 | 1251 (NFE_TX_RING_COUNT - 1)); 1252 1253 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1254 1255 /* force MAC to wakeup */ 1256 tmp = NFE_READ(sc, NFE_PWR_STATE); 1257 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1258 DELAY(10); 1259 tmp = NFE_READ(sc, NFE_PWR_STATE); 1260 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1261 1262 s = splnet(); 1263 nfe_intr(sc); /* XXX clear IRQ status registers */ 1264 splx(s); 1265 1266 #if 1 1267 /* configure interrupts coalescing/mitigation */ 1268 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1269 #else 1270 /* no interrupt mitigation: one interrupt per packet */ 1271 NFE_WRITE(sc, NFE_IMTIMER, 970); 1272 #endif 1273 1274 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1275 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1276 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1277 1278 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1279 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1280 1281 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1282 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_ENABLE); 1283 1284 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1285 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1286 DELAY(10); 1287 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1288 1289 /* set Rx filter */ 1290 nfe_setmulti(sc); 1291 1292 if ((rc = ether_mediachange(ifp)) != 0) 1293 goto out; 1294 1295 nfe_tick(sc); 1296 1297 /* enable Rx */ 1298 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1299 1300 /* enable Tx */ 1301 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1302 1303 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1304 1305 /* enable interrupts */ 1306 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1307 1308 callout_schedule(&sc->sc_tick_ch, hz); 1309 1310 ifp->if_flags |= IFF_RUNNING; 1311 ifp->if_flags &= ~IFF_OACTIVE; 1312 1313 out: 1314 return rc; 1315 } 1316 1317 void 1318 nfe_stop(struct ifnet *ifp, int disable) 1319 { 1320 struct nfe_softc *sc = ifp->if_softc; 1321 1322 callout_stop(&sc->sc_tick_ch); 1323 1324 ifp->if_timer = 0; 1325 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1326 1327 mii_down(&sc->sc_mii); 1328 1329 /* abort Tx */ 1330 NFE_WRITE(sc, NFE_TX_CTL, 0); 1331 1332 /* disable Rx */ 1333 NFE_WRITE(sc, NFE_RX_CTL, 0); 1334 1335 /* disable interrupts */ 1336 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1337 1338 /* reset Tx and Rx rings */ 1339 nfe_reset_tx_ring(sc, &sc->txq); 1340 nfe_reset_rx_ring(sc, &sc->rxq); 1341 } 1342 1343 int 1344 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1345 { 1346 struct nfe_desc32 *desc32; 1347 struct nfe_desc64 *desc64; 1348 struct nfe_rx_data *data; 1349 struct nfe_jbuf *jbuf; 1350 void **desc; 1351 bus_addr_t physaddr; 1352 int i, nsegs, error, descsize; 1353 1354 if (sc->sc_flags & NFE_40BIT_ADDR) { 1355 desc = (void **)&ring->desc64; 1356 descsize = sizeof (struct nfe_desc64); 1357 } else { 1358 desc = (void **)&ring->desc32; 1359 descsize = sizeof (struct nfe_desc32); 1360 } 1361 1362 ring->cur = ring->next = 0; 1363 ring->bufsz = MCLBYTES; 1364 1365 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1366 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1367 if (error != 0) { 1368 aprint_error_dev(sc->sc_dev, 1369 "could not create desc DMA map\n"); 1370 goto fail; 1371 } 1372 1373 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1374 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1375 if (error != 0) { 1376 aprint_error_dev(sc->sc_dev, 1377 "could not allocate DMA memory\n"); 1378 goto fail; 1379 } 1380 1381 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1382 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1383 if (error != 0) { 1384 aprint_error_dev(sc->sc_dev, 1385 "could not map desc DMA memory\n"); 1386 goto fail; 1387 } 1388 1389 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1390 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1391 if (error != 0) { 1392 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1393 goto fail; 1394 } 1395 1396 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1397 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1398 1399 if (sc->sc_flags & NFE_USE_JUMBO) { 1400 ring->bufsz = NFE_JBYTES; 1401 if ((error = nfe_jpool_alloc(sc)) != 0) { 1402 aprint_error_dev(sc->sc_dev, 1403 "could not allocate jumbo frames\n"); 1404 goto fail; 1405 } 1406 } 1407 1408 /* 1409 * Pre-allocate Rx buffers and populate Rx ring. 1410 */ 1411 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1412 data = &sc->rxq.data[i]; 1413 1414 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1415 if (data->m == NULL) { 1416 aprint_error_dev(sc->sc_dev, 1417 "could not allocate rx mbuf\n"); 1418 error = ENOMEM; 1419 goto fail; 1420 } 1421 1422 if (sc->sc_flags & NFE_USE_JUMBO) { 1423 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1424 aprint_error_dev(sc->sc_dev, 1425 "could not allocate jumbo buffer\n"); 1426 goto fail; 1427 } 1428 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1429 sc); 1430 1431 physaddr = jbuf->physaddr; 1432 } else { 1433 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1434 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1435 if (error != 0) { 1436 aprint_error_dev(sc->sc_dev, 1437 "could not create DMA map\n"); 1438 goto fail; 1439 } 1440 MCLGET(data->m, M_DONTWAIT); 1441 if (!(data->m->m_flags & M_EXT)) { 1442 aprint_error_dev(sc->sc_dev, 1443 "could not allocate mbuf cluster\n"); 1444 error = ENOMEM; 1445 goto fail; 1446 } 1447 1448 error = bus_dmamap_load(sc->sc_dmat, data->map, 1449 mtod(data->m, void *), MCLBYTES, NULL, 1450 BUS_DMA_READ | BUS_DMA_NOWAIT); 1451 if (error != 0) { 1452 aprint_error_dev(sc->sc_dev, 1453 "could not load rx buf DMA map"); 1454 goto fail; 1455 } 1456 physaddr = data->map->dm_segs[0].ds_addr; 1457 } 1458 1459 if (sc->sc_flags & NFE_40BIT_ADDR) { 1460 desc64 = &sc->rxq.desc64[i]; 1461 #if defined(__LP64__) 1462 desc64->physaddr[0] = htole32(physaddr >> 32); 1463 #endif 1464 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1465 desc64->length = htole16(sc->rxq.bufsz); 1466 desc64->flags = htole16(NFE_RX_READY); 1467 } else { 1468 desc32 = &sc->rxq.desc32[i]; 1469 desc32->physaddr = htole32(physaddr); 1470 desc32->length = htole16(sc->rxq.bufsz); 1471 desc32->flags = htole16(NFE_RX_READY); 1472 } 1473 } 1474 1475 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1476 BUS_DMASYNC_PREWRITE); 1477 1478 return 0; 1479 1480 fail: nfe_free_rx_ring(sc, ring); 1481 return error; 1482 } 1483 1484 void 1485 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1486 { 1487 int i; 1488 1489 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1490 if (sc->sc_flags & NFE_40BIT_ADDR) { 1491 ring->desc64[i].length = htole16(ring->bufsz); 1492 ring->desc64[i].flags = htole16(NFE_RX_READY); 1493 } else { 1494 ring->desc32[i].length = htole16(ring->bufsz); 1495 ring->desc32[i].flags = htole16(NFE_RX_READY); 1496 } 1497 } 1498 1499 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1500 BUS_DMASYNC_PREWRITE); 1501 1502 ring->cur = ring->next = 0; 1503 } 1504 1505 void 1506 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1507 { 1508 struct nfe_rx_data *data; 1509 void *desc; 1510 int i, descsize; 1511 1512 if (sc->sc_flags & NFE_40BIT_ADDR) { 1513 desc = ring->desc64; 1514 descsize = sizeof (struct nfe_desc64); 1515 } else { 1516 desc = ring->desc32; 1517 descsize = sizeof (struct nfe_desc32); 1518 } 1519 1520 if (desc != NULL) { 1521 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1522 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1523 bus_dmamap_unload(sc->sc_dmat, ring->map); 1524 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1525 NFE_RX_RING_COUNT * descsize); 1526 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1527 } 1528 1529 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1530 data = &ring->data[i]; 1531 1532 if (data->map != NULL) { 1533 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1534 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1535 bus_dmamap_unload(sc->sc_dmat, data->map); 1536 bus_dmamap_destroy(sc->sc_dmat, data->map); 1537 } 1538 if (data->m != NULL) 1539 m_freem(data->m); 1540 } 1541 } 1542 1543 struct nfe_jbuf * 1544 nfe_jalloc(struct nfe_softc *sc, int i) 1545 { 1546 struct nfe_jbuf *jbuf; 1547 1548 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1549 if (jbuf == NULL) 1550 return NULL; 1551 sc->rxq.jbufmap[i] = 1552 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1553 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1554 return jbuf; 1555 } 1556 1557 /* 1558 * This is called automatically by the network stack when the mbuf is freed. 1559 * Caution must be taken that the NIC might be reset by the time the mbuf is 1560 * freed. 1561 */ 1562 void 1563 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1564 { 1565 struct nfe_softc *sc = arg; 1566 struct nfe_jbuf *jbuf; 1567 int i; 1568 1569 /* find the jbuf from the base pointer */ 1570 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1571 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1572 aprint_error_dev(sc->sc_dev, 1573 "request to free a buffer (%p) not managed by us\n", buf); 1574 return; 1575 } 1576 jbuf = &sc->rxq.jbuf[i]; 1577 1578 /* ..and put it back in the free list */ 1579 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1580 1581 if (m != NULL) 1582 pool_cache_put(mb_cache, m); 1583 } 1584 1585 int 1586 nfe_jpool_alloc(struct nfe_softc *sc) 1587 { 1588 struct nfe_rx_ring *ring = &sc->rxq; 1589 struct nfe_jbuf *jbuf; 1590 bus_addr_t physaddr; 1591 char *buf; 1592 int i, nsegs, error; 1593 1594 /* 1595 * Allocate a big chunk of DMA'able memory. 1596 */ 1597 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1598 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1599 if (error != 0) { 1600 aprint_error_dev(sc->sc_dev, 1601 "could not create jumbo DMA map\n"); 1602 goto fail; 1603 } 1604 1605 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1606 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1607 if (error != 0) { 1608 aprint_error_dev(sc->sc_dev, 1609 "could not allocate jumbo DMA memory\n"); 1610 goto fail; 1611 } 1612 1613 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1614 &ring->jpool, BUS_DMA_NOWAIT); 1615 if (error != 0) { 1616 aprint_error_dev(sc->sc_dev, 1617 "could not map jumbo DMA memory\n"); 1618 goto fail; 1619 } 1620 1621 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1622 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1623 if (error != 0) { 1624 aprint_error_dev(sc->sc_dev, 1625 "could not load jumbo DMA map\n"); 1626 goto fail; 1627 } 1628 1629 /* ..and split it into 9KB chunks */ 1630 SLIST_INIT(&ring->jfreelist); 1631 1632 buf = ring->jpool; 1633 physaddr = ring->jmap->dm_segs[0].ds_addr; 1634 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1635 jbuf = &ring->jbuf[i]; 1636 1637 jbuf->buf = buf; 1638 jbuf->physaddr = physaddr; 1639 1640 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1641 1642 buf += NFE_JBYTES; 1643 physaddr += NFE_JBYTES; 1644 } 1645 1646 return 0; 1647 1648 fail: nfe_jpool_free(sc); 1649 return error; 1650 } 1651 1652 void 1653 nfe_jpool_free(struct nfe_softc *sc) 1654 { 1655 struct nfe_rx_ring *ring = &sc->rxq; 1656 1657 if (ring->jmap != NULL) { 1658 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1659 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1660 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1661 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1662 } 1663 if (ring->jpool != NULL) { 1664 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1665 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1666 } 1667 } 1668 1669 int 1670 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1671 { 1672 int i, nsegs, error; 1673 void **desc; 1674 int descsize; 1675 1676 if (sc->sc_flags & NFE_40BIT_ADDR) { 1677 desc = (void **)&ring->desc64; 1678 descsize = sizeof (struct nfe_desc64); 1679 } else { 1680 desc = (void **)&ring->desc32; 1681 descsize = sizeof (struct nfe_desc32); 1682 } 1683 1684 ring->queued = 0; 1685 ring->cur = ring->next = 0; 1686 1687 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1688 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1689 1690 if (error != 0) { 1691 aprint_error_dev(sc->sc_dev, 1692 "could not create desc DMA map\n"); 1693 goto fail; 1694 } 1695 1696 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1697 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1698 if (error != 0) { 1699 aprint_error_dev(sc->sc_dev, 1700 "could not allocate DMA memory\n"); 1701 goto fail; 1702 } 1703 1704 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1705 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1706 if (error != 0) { 1707 aprint_error_dev(sc->sc_dev, 1708 "could not map desc DMA memory\n"); 1709 goto fail; 1710 } 1711 1712 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1713 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1714 if (error != 0) { 1715 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1716 goto fail; 1717 } 1718 1719 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1720 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1721 1722 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1723 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1724 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1725 &ring->data[i].map); 1726 if (error != 0) { 1727 aprint_error_dev(sc->sc_dev, 1728 "could not create DMA map\n"); 1729 goto fail; 1730 } 1731 } 1732 1733 return 0; 1734 1735 fail: nfe_free_tx_ring(sc, ring); 1736 return error; 1737 } 1738 1739 void 1740 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1741 { 1742 struct nfe_tx_data *data; 1743 int i; 1744 1745 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1746 if (sc->sc_flags & NFE_40BIT_ADDR) 1747 ring->desc64[i].flags = 0; 1748 else 1749 ring->desc32[i].flags = 0; 1750 1751 data = &ring->data[i]; 1752 1753 if (data->m != NULL) { 1754 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1755 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1756 bus_dmamap_unload(sc->sc_dmat, data->active); 1757 m_freem(data->m); 1758 data->m = NULL; 1759 } 1760 } 1761 1762 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1763 BUS_DMASYNC_PREWRITE); 1764 1765 ring->queued = 0; 1766 ring->cur = ring->next = 0; 1767 } 1768 1769 void 1770 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1771 { 1772 struct nfe_tx_data *data; 1773 void *desc; 1774 int i, descsize; 1775 1776 if (sc->sc_flags & NFE_40BIT_ADDR) { 1777 desc = ring->desc64; 1778 descsize = sizeof (struct nfe_desc64); 1779 } else { 1780 desc = ring->desc32; 1781 descsize = sizeof (struct nfe_desc32); 1782 } 1783 1784 if (desc != NULL) { 1785 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1786 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1787 bus_dmamap_unload(sc->sc_dmat, ring->map); 1788 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1789 NFE_TX_RING_COUNT * descsize); 1790 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1791 } 1792 1793 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1794 data = &ring->data[i]; 1795 1796 if (data->m != NULL) { 1797 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1798 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1799 bus_dmamap_unload(sc->sc_dmat, data->active); 1800 m_freem(data->m); 1801 } 1802 } 1803 1804 /* ..and now actually destroy the DMA mappings */ 1805 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1806 data = &ring->data[i]; 1807 if (data->map == NULL) 1808 continue; 1809 bus_dmamap_destroy(sc->sc_dmat, data->map); 1810 } 1811 } 1812 1813 void 1814 nfe_setmulti(struct nfe_softc *sc) 1815 { 1816 struct ethercom *ec = &sc->sc_ethercom; 1817 struct ifnet *ifp = &ec->ec_if; 1818 struct ether_multi *enm; 1819 struct ether_multistep step; 1820 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1821 uint32_t filter = NFE_RXFILTER_MAGIC; 1822 int i; 1823 1824 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1825 bzero(addr, ETHER_ADDR_LEN); 1826 bzero(mask, ETHER_ADDR_LEN); 1827 goto done; 1828 } 1829 1830 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1831 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1832 1833 ETHER_FIRST_MULTI(step, ec, enm); 1834 while (enm != NULL) { 1835 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1836 ifp->if_flags |= IFF_ALLMULTI; 1837 bzero(addr, ETHER_ADDR_LEN); 1838 bzero(mask, ETHER_ADDR_LEN); 1839 goto done; 1840 } 1841 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1842 addr[i] &= enm->enm_addrlo[i]; 1843 mask[i] &= ~enm->enm_addrlo[i]; 1844 } 1845 ETHER_NEXT_MULTI(step, enm); 1846 } 1847 for (i = 0; i < ETHER_ADDR_LEN; i++) 1848 mask[i] |= addr[i]; 1849 1850 done: 1851 addr[0] |= 0x01; /* make sure multicast bit is set */ 1852 1853 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1854 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1855 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1856 addr[5] << 8 | addr[4]); 1857 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1858 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1859 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1860 mask[5] << 8 | mask[4]); 1861 1862 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1863 NFE_WRITE(sc, NFE_RXFILTER, filter); 1864 } 1865 1866 void 1867 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1868 { 1869 uint32_t tmp; 1870 1871 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 1872 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1873 addr[0] = (tmp & 0xff); 1874 addr[1] = (tmp >> 8) & 0xff; 1875 addr[2] = (tmp >> 16) & 0xff; 1876 addr[3] = (tmp >> 24) & 0xff; 1877 1878 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1879 addr[4] = (tmp & 0xff); 1880 addr[5] = (tmp >> 8) & 0xff; 1881 1882 } else { 1883 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1884 addr[0] = (tmp >> 8) & 0xff; 1885 addr[1] = (tmp & 0xff); 1886 1887 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1888 addr[2] = (tmp >> 24) & 0xff; 1889 addr[3] = (tmp >> 16) & 0xff; 1890 addr[4] = (tmp >> 8) & 0xff; 1891 addr[5] = (tmp & 0xff); 1892 } 1893 } 1894 1895 void 1896 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1897 { 1898 NFE_WRITE(sc, NFE_MACADDR_LO, 1899 addr[5] << 8 | addr[4]); 1900 NFE_WRITE(sc, NFE_MACADDR_HI, 1901 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1902 } 1903 1904 void 1905 nfe_tick(void *arg) 1906 { 1907 struct nfe_softc *sc = arg; 1908 int s; 1909 1910 s = splnet(); 1911 mii_tick(&sc->sc_mii); 1912 splx(s); 1913 1914 callout_schedule(&sc->sc_tick_ch, hz); 1915 } 1916
Indexes created Tue Sep 30 11:09:46 GMT 2025