if_nfe.c revision 1.35
1 /* $NetBSD: if_nfe.c,v 1.35 2008/05/25 22:57:35 jmcneill Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.77 2008/02/05 16:52:50 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006, 2007 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.35 2008/05/25 22:57:35 jmcneill Exp $"); 25 26 #include "opt_inet.h" 27 #include "bpfilter.h" 28 #include "vlan.h" 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/types.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/mutex.h> 37 #include <sys/queue.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/callout.h> 41 #include <sys/socket.h> 42 43 #include <sys/bus.h> 44 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 #include <net/if_ether.h> 49 #include <net/if_arp.h> 50 51 #ifdef INET 52 #include <netinet/in.h> 53 #include <netinet/in_systm.h> 54 #include <netinet/in_var.h> 55 #include <netinet/ip.h> 56 #include <netinet/if_inarp.h> 57 #endif 58 59 #if NVLAN > 0 60 #include <net/if_types.h> 61 #endif 62 63 #if NBPFILTER > 0 64 #include <net/bpf.h> 65 #endif 66 67 #include <dev/mii/mii.h> 68 #include <dev/mii/miivar.h> 69 70 #include <dev/pci/pcireg.h> 71 #include <dev/pci/pcivar.h> 72 #include <dev/pci/pcidevs.h> 73 74 #include <dev/pci/if_nfereg.h> 75 #include <dev/pci/if_nfevar.h> 76 77 int nfe_match(device_t, cfdata_t, void *); 78 void nfe_attach(device_t, device_t, void *); 79 void nfe_power(int, void *); 80 void nfe_miibus_statchg(device_t); 81 int nfe_miibus_readreg(device_t, int, int); 82 void nfe_miibus_writereg(device_t, int, int, int); 83 int nfe_intr(void *); 84 int nfe_ioctl(struct ifnet *, u_long, void *); 85 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 86 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 87 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 88 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 89 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 90 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 91 void nfe_rxeof(struct nfe_softc *); 92 void nfe_txeof(struct nfe_softc *); 93 int nfe_encap(struct nfe_softc *, struct mbuf *); 94 void nfe_start(struct ifnet *); 95 void nfe_watchdog(struct ifnet *); 96 int nfe_init(struct ifnet *); 97 void nfe_stop(struct ifnet *, int); 98 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 99 void nfe_jfree(struct mbuf *, void *, size_t, void *); 100 int nfe_jpool_alloc(struct nfe_softc *); 101 void nfe_jpool_free(struct nfe_softc *); 102 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 105 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 108 void nfe_setmulti(struct nfe_softc *); 109 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 110 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 111 void nfe_tick(void *); 112 void nfe_poweron(device_t); 113 bool nfe_resume(device_t PMF_FN_PROTO); 114 115 CFATTACH_DECL_NEW(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, 116 NULL, NULL); 117 118 /* #define NFE_NO_JUMBO */ 119 120 #ifdef NFE_DEBUG 121 int nfedebug = 0; 122 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 123 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 124 #else 125 #define DPRINTF(x) 126 #define DPRINTFN(n,x) 127 #endif 128 129 /* deal with naming differences */ 130 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 134 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 135 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 136 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 137 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 140 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 141 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 142 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 145 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 146 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 147 148 #ifdef _LP64 149 #define __LP64__ 1 150 #endif 151 152 const struct nfe_product { 153 pci_vendor_id_t vendor; 154 pci_product_id_t product; 155 } nfe_devices[] = { 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 183 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 184 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 185 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 186 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 }, 187 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1 }, 188 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2 }, 189 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3 }, 190 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4 }, 191 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1 }, 192 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2 }, 193 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3 }, 194 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4 } 195 }; 196 197 int 198 nfe_match(device_t dev, cfdata_t match, void *aux) 199 { 200 struct pci_attach_args *pa = aux; 201 const struct nfe_product *np; 202 int i; 203 204 for (i = 0; i < sizeof(nfe_devices) / sizeof(nfe_devices[0]); i++) { 205 np = &nfe_devices[i]; 206 if (PCI_VENDOR(pa->pa_id) == np->vendor && 207 PCI_PRODUCT(pa->pa_id) == np->product) 208 return 1; 209 } 210 return 0; 211 } 212 213 void 214 nfe_attach(device_t parent, device_t self, void *aux) 215 { 216 struct nfe_softc *sc = device_private(self); 217 struct pci_attach_args *pa = aux; 218 pci_chipset_tag_t pc = pa->pa_pc; 219 pci_intr_handle_t ih; 220 const char *intrstr; 221 struct ifnet *ifp; 222 bus_size_t memsize; 223 pcireg_t memtype; 224 char devinfo[256]; 225 226 sc->sc_dev = self; 227 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 228 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 229 230 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 231 switch (memtype) { 232 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 233 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 234 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 235 &sc->sc_memh, NULL, &memsize) == 0) 236 break; 237 /* FALLTHROUGH */ 238 default: 239 aprint_error_dev(self, "could not map mem space\n"); 240 return; 241 } 242 243 if (pci_intr_map(pa, &ih) != 0) { 244 aprint_error_dev(self, "could not map interrupt\n"); 245 return; 246 } 247 248 intrstr = pci_intr_string(pc, ih); 249 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 250 if (sc->sc_ih == NULL) { 251 aprint_error_dev(self, "could not establish interrupt"); 252 if (intrstr != NULL) 253 aprint_normal(" at %s", intrstr); 254 aprint_normal("\n"); 255 return; 256 } 257 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 258 259 sc->sc_dmat = pa->pa_dmat; 260 261 sc->sc_flags = 0; 262 263 switch (PCI_PRODUCT(pa->pa_id)) { 264 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 265 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 266 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 267 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 268 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 269 break; 270 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 271 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 272 sc->sc_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT; 273 break; 274 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 275 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 276 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 277 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 278 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 279 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 280 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 281 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 282 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 283 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 284 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 285 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 286 sc->sc_flags |= NFE_40BIT_ADDR | NFE_CORRECT_MACADDR | 287 NFE_PWR_MGMT; 288 break; 289 case PCI_PRODUCT_NVIDIA_MCP77_LAN1: 290 case PCI_PRODUCT_NVIDIA_MCP77_LAN2: 291 case PCI_PRODUCT_NVIDIA_MCP77_LAN3: 292 case PCI_PRODUCT_NVIDIA_MCP77_LAN4: 293 case PCI_PRODUCT_NVIDIA_MCP79_LAN1: 294 case PCI_PRODUCT_NVIDIA_MCP79_LAN2: 295 case PCI_PRODUCT_NVIDIA_MCP79_LAN3: 296 case PCI_PRODUCT_NVIDIA_MCP79_LAN4: 297 sc->sc_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | 298 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 299 break; 300 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 301 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 302 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 303 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 304 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 305 break; 306 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 307 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 308 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 309 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 310 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 311 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 312 break; 313 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 314 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 315 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 316 NFE_HW_VLAN | NFE_PWR_MGMT; 317 break; 318 } 319 320 nfe_poweron(self); 321 322 #ifndef NFE_NO_JUMBO 323 /* enable jumbo frames for adapters that support it */ 324 if (sc->sc_flags & NFE_JUMBO_SUP) 325 sc->sc_flags |= NFE_USE_JUMBO; 326 #endif 327 328 /* Check for reversed ethernet address */ 329 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 330 sc->sc_flags |= NFE_CORRECT_MACADDR; 331 332 nfe_get_macaddr(sc, sc->sc_enaddr); 333 aprint_normal_dev(self, "Ethernet address %s\n", 334 ether_sprintf(sc->sc_enaddr)); 335 336 /* 337 * Allocate Tx and Rx rings. 338 */ 339 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 340 aprint_error_dev(self, "could not allocate Tx ring\n"); 341 return; 342 } 343 344 mutex_init(&sc->rxq.mtx, MUTEX_SPIN, IPL_NET); 345 346 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 347 aprint_error_dev(self, "could not allocate Rx ring\n"); 348 nfe_free_tx_ring(sc, &sc->txq); 349 return; 350 } 351 352 ifp = &sc->sc_ethercom.ec_if; 353 ifp->if_softc = sc; 354 ifp->if_mtu = ETHERMTU; 355 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 356 ifp->if_ioctl = nfe_ioctl; 357 ifp->if_start = nfe_start; 358 ifp->if_stop = nfe_stop; 359 ifp->if_watchdog = nfe_watchdog; 360 ifp->if_init = nfe_init; 361 ifp->if_baudrate = IF_Gbps(1); 362 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 363 IFQ_SET_READY(&ifp->if_snd); 364 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 365 366 #ifdef notyet 367 if (sc->sc_flags & NFE_USE_JUMBO) 368 ifp->if_hardmtu = NFE_JUMBO_MTU; 369 #endif 370 371 #if NVLAN > 0 372 if (sc->sc_flags & NFE_HW_VLAN) 373 sc->sc_ethercom.ec_capabilities |= 374 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 375 #endif 376 if (sc->sc_flags & NFE_HW_CSUM) { 377 ifp->if_capabilities |= 378 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 379 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 380 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 381 } 382 383 sc->sc_mii.mii_ifp = ifp; 384 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 385 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 386 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 387 388 sc->sc_ethercom.ec_mii = &sc->sc_mii; 389 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 390 ether_mediastatus); 391 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 392 MII_OFFSET_ANY, 0); 393 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 394 aprint_error_dev(self, "no PHY found!\n"); 395 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 396 0, NULL); 397 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 398 } else 399 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 400 401 if_attach(ifp); 402 ether_ifattach(ifp, sc->sc_enaddr); 403 404 callout_init(&sc->sc_tick_ch, 0); 405 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 406 407 if (!pmf_device_register(self, NULL, nfe_resume)) 408 aprint_error_dev(self, "couldn't establish power handler\n"); 409 else 410 pmf_class_network_register(self, ifp); 411 } 412 413 void 414 nfe_miibus_statchg(device_t dev) 415 { 416 struct nfe_softc *sc = device_private(dev); 417 struct mii_data *mii = &sc->sc_mii; 418 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 419 420 phy = NFE_READ(sc, NFE_PHY_IFACE); 421 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 422 423 seed = NFE_READ(sc, NFE_RNDSEED); 424 seed &= ~NFE_SEED_MASK; 425 426 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 427 phy |= NFE_PHY_HDX; /* half-duplex */ 428 misc |= NFE_MISC1_HDX; 429 } 430 431 switch (IFM_SUBTYPE(mii->mii_media_active)) { 432 case IFM_1000_T: /* full-duplex only */ 433 link |= NFE_MEDIA_1000T; 434 seed |= NFE_SEED_1000T; 435 phy |= NFE_PHY_1000T; 436 break; 437 case IFM_100_TX: 438 link |= NFE_MEDIA_100TX; 439 seed |= NFE_SEED_100TX; 440 phy |= NFE_PHY_100TX; 441 break; 442 case IFM_10_T: 443 link |= NFE_MEDIA_10T; 444 seed |= NFE_SEED_10T; 445 break; 446 } 447 448 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 449 450 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 451 NFE_WRITE(sc, NFE_MISC1, misc); 452 NFE_WRITE(sc, NFE_LINKSPEED, link); 453 } 454 455 int 456 nfe_miibus_readreg(device_t dev, int phy, int reg) 457 { 458 struct nfe_softc *sc = device_private(dev); 459 uint32_t val; 460 int ntries; 461 462 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 463 464 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 465 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 466 DELAY(100); 467 } 468 469 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 470 471 for (ntries = 0; ntries < 1000; ntries++) { 472 DELAY(100); 473 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 474 break; 475 } 476 if (ntries == 1000) { 477 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 478 device_xname(sc->sc_dev))); 479 return 0; 480 } 481 482 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 483 DPRINTFN(2, ("%s: could not read PHY\n", 484 device_xname(sc->sc_dev))); 485 return 0; 486 } 487 488 val = NFE_READ(sc, NFE_PHY_DATA); 489 if (val != 0xffffffff && val != 0) 490 sc->mii_phyaddr = phy; 491 492 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 493 device_xname(sc->sc_dev), phy, reg, val)); 494 495 return val; 496 } 497 498 void 499 nfe_miibus_writereg(device_t dev, int phy, int reg, int val) 500 { 501 struct nfe_softc *sc = device_private(dev); 502 uint32_t ctl; 503 int ntries; 504 505 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 506 507 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 508 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 509 DELAY(100); 510 } 511 512 NFE_WRITE(sc, NFE_PHY_DATA, val); 513 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 514 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 515 516 for (ntries = 0; ntries < 1000; ntries++) { 517 DELAY(100); 518 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 519 break; 520 } 521 #ifdef NFE_DEBUG 522 if (nfedebug >= 2 && ntries == 1000) 523 printf("could not write to PHY\n"); 524 #endif 525 } 526 527 int 528 nfe_intr(void *arg) 529 { 530 struct nfe_softc *sc = arg; 531 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 532 uint32_t r; 533 int handled; 534 535 if ((ifp->if_flags & IFF_UP) == 0) 536 return 0; 537 538 handled = 0; 539 540 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 541 542 for (;;) { 543 r = NFE_READ(sc, NFE_IRQ_STATUS); 544 if ((r & NFE_IRQ_WANTED) == 0) 545 break; 546 547 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 548 handled = 1; 549 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 550 551 if ((r & (NFE_IRQ_RXERR|NFE_IRQ_RX_NOBUF|NFE_IRQ_RX)) != 0) { 552 /* check Rx ring */ 553 nfe_rxeof(sc); 554 } 555 if ((r & (NFE_IRQ_TXERR|NFE_IRQ_TXERR2|NFE_IRQ_TX_DONE)) != 0) { 556 /* check Tx ring */ 557 nfe_txeof(sc); 558 } 559 if ((r & NFE_IRQ_LINK) != 0) { 560 NFE_READ(sc, NFE_PHY_STATUS); 561 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 562 DPRINTF(("%s: link state changed\n", 563 device_xname(sc->sc_dev))); 564 } 565 } 566 567 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 568 569 if (handled && !IF_IS_EMPTY(&ifp->if_snd)) 570 nfe_start(ifp); 571 572 return handled; 573 } 574 575 int 576 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 577 { 578 struct nfe_softc *sc = ifp->if_softc; 579 struct ifreq *ifr = (struct ifreq *)data; 580 struct ifaddr *ifa = (struct ifaddr *)data; 581 int s, error = 0; 582 583 s = splnet(); 584 585 switch (cmd) { 586 case SIOCSIFADDR: 587 ifp->if_flags |= IFF_UP; 588 nfe_init(ifp); 589 switch (ifa->ifa_addr->sa_family) { 590 #ifdef INET 591 case AF_INET: 592 arp_ifinit(ifp, ifa); 593 break; 594 #endif 595 default: 596 break; 597 } 598 break; 599 case SIOCSIFMTU: 600 if (ifr->ifr_mtu < ETHERMIN || 601 ((sc->sc_flags & NFE_USE_JUMBO) && 602 ifr->ifr_mtu > ETHERMTU_JUMBO) || 603 (!(sc->sc_flags & NFE_USE_JUMBO) && 604 ifr->ifr_mtu > ETHERMTU)) 605 error = EINVAL; 606 else if ((error = ifioctl_common(ifp, cmd, data)) == ENETRESET) 607 error = 0; 608 break; 609 case SIOCSIFFLAGS: 610 if (ifp->if_flags & IFF_UP) { 611 /* 612 * If only the PROMISC or ALLMULTI flag changes, then 613 * don't do a full re-init of the chip, just update 614 * the Rx filter. 615 */ 616 if ((ifp->if_flags & IFF_RUNNING) && 617 ((ifp->if_flags ^ sc->sc_if_flags) & 618 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 619 nfe_setmulti(sc); 620 } else 621 nfe_init(ifp); 622 } else { 623 if (ifp->if_flags & IFF_RUNNING) 624 nfe_stop(ifp, 1); 625 } 626 sc->sc_if_flags = ifp->if_flags; 627 break; 628 default: 629 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 630 break; 631 632 error = 0; 633 634 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 635 ; 636 else if (ifp->if_flags & IFF_RUNNING) 637 nfe_setmulti(sc); 638 break; 639 } 640 641 splx(s); 642 643 return error; 644 } 645 646 void 647 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 648 { 649 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 650 (char *)desc32 - (char *)sc->txq.desc32, 651 sizeof (struct nfe_desc32), ops); 652 } 653 654 void 655 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 656 { 657 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 658 (char *)desc64 - (char *)sc->txq.desc64, 659 sizeof (struct nfe_desc64), ops); 660 } 661 662 void 663 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 664 { 665 if (end > start) { 666 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 667 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 668 (char *)&sc->txq.desc32[end] - 669 (char *)&sc->txq.desc32[start], ops); 670 return; 671 } 672 /* sync from 'start' to end of ring */ 673 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 674 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 675 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 676 (char *)&sc->txq.desc32[start], ops); 677 678 /* sync from start of ring to 'end' */ 679 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 680 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 681 } 682 683 void 684 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 685 { 686 if (end > start) { 687 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 688 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 689 (char *)&sc->txq.desc64[end] - 690 (char *)&sc->txq.desc64[start], ops); 691 return; 692 } 693 /* sync from 'start' to end of ring */ 694 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 695 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 696 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 697 (char *)&sc->txq.desc64[start], ops); 698 699 /* sync from start of ring to 'end' */ 700 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 701 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 702 } 703 704 void 705 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 706 { 707 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 708 (char *)desc32 - (char *)sc->rxq.desc32, 709 sizeof (struct nfe_desc32), ops); 710 } 711 712 void 713 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 714 { 715 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 716 (char *)desc64 - (char *)sc->rxq.desc64, 717 sizeof (struct nfe_desc64), ops); 718 } 719 720 void 721 nfe_rxeof(struct nfe_softc *sc) 722 { 723 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 724 struct nfe_desc32 *desc32; 725 struct nfe_desc64 *desc64; 726 struct nfe_rx_data *data; 727 struct nfe_jbuf *jbuf; 728 struct mbuf *m, *mnew; 729 bus_addr_t physaddr; 730 uint16_t flags; 731 int error, len, i; 732 733 desc32 = NULL; 734 desc64 = NULL; 735 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 736 data = &sc->rxq.data[i]; 737 738 if (sc->sc_flags & NFE_40BIT_ADDR) { 739 desc64 = &sc->rxq.desc64[i]; 740 nfe_rxdesc64_sync(sc, desc64, 741 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 742 743 flags = le16toh(desc64->flags); 744 len = le16toh(desc64->length) & 0x3fff; 745 } else { 746 desc32 = &sc->rxq.desc32[i]; 747 nfe_rxdesc32_sync(sc, desc32, 748 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 749 750 flags = le16toh(desc32->flags); 751 len = le16toh(desc32->length) & 0x3fff; 752 } 753 754 if ((flags & NFE_RX_READY) != 0) 755 break; 756 757 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 758 if ((flags & NFE_RX_VALID_V1) == 0) 759 goto skip; 760 761 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 762 flags &= ~NFE_RX_ERROR; 763 len--; /* fix buffer length */ 764 } 765 } else { 766 if ((flags & NFE_RX_VALID_V2) == 0) 767 goto skip; 768 769 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 770 flags &= ~NFE_RX_ERROR; 771 len--; /* fix buffer length */ 772 } 773 } 774 775 if (flags & NFE_RX_ERROR) { 776 ifp->if_ierrors++; 777 goto skip; 778 } 779 780 /* 781 * Try to allocate a new mbuf for this ring element and load 782 * it before processing the current mbuf. If the ring element 783 * cannot be loaded, drop the received packet and reuse the 784 * old mbuf. In the unlikely case that the old mbuf can't be 785 * reloaded either, explicitly panic. 786 */ 787 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 788 if (mnew == NULL) { 789 ifp->if_ierrors++; 790 goto skip; 791 } 792 793 if (sc->sc_flags & NFE_USE_JUMBO) { 794 physaddr = 795 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 796 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 797 if (len > MCLBYTES) { 798 m_freem(mnew); 799 ifp->if_ierrors++; 800 goto skip1; 801 } 802 MCLGET(mnew, M_DONTWAIT); 803 if ((mnew->m_flags & M_EXT) == 0) { 804 m_freem(mnew); 805 ifp->if_ierrors++; 806 goto skip1; 807 } 808 809 (void)memcpy(mtod(mnew, void *), 810 mtod(data->m, const void *), len); 811 m = mnew; 812 goto mbufcopied; 813 } else { 814 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 815 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 816 mtod(data->m, char *) - (char *)sc->rxq.jpool, 817 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 818 819 physaddr = jbuf->physaddr; 820 } 821 } else { 822 MCLGET(mnew, M_DONTWAIT); 823 if ((mnew->m_flags & M_EXT) == 0) { 824 m_freem(mnew); 825 ifp->if_ierrors++; 826 goto skip; 827 } 828 829 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 830 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 831 bus_dmamap_unload(sc->sc_dmat, data->map); 832 833 error = bus_dmamap_load(sc->sc_dmat, data->map, 834 mtod(mnew, void *), MCLBYTES, NULL, 835 BUS_DMA_READ | BUS_DMA_NOWAIT); 836 if (error != 0) { 837 m_freem(mnew); 838 839 /* try to reload the old mbuf */ 840 error = bus_dmamap_load(sc->sc_dmat, data->map, 841 mtod(data->m, void *), MCLBYTES, NULL, 842 BUS_DMA_READ | BUS_DMA_NOWAIT); 843 if (error != 0) { 844 /* very unlikely that it will fail.. */ 845 panic("%s: could not load old rx mbuf", 846 device_xname(sc->sc_dev)); 847 } 848 ifp->if_ierrors++; 849 goto skip; 850 } 851 physaddr = data->map->dm_segs[0].ds_addr; 852 } 853 854 /* 855 * New mbuf successfully loaded, update Rx ring and continue 856 * processing. 857 */ 858 m = data->m; 859 data->m = mnew; 860 861 mbufcopied: 862 /* finalize mbuf */ 863 m->m_pkthdr.len = m->m_len = len; 864 m->m_pkthdr.rcvif = ifp; 865 866 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 867 /* 868 * XXX 869 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 870 */ 871 if (flags & NFE_RX_IP_CSUMOK) { 872 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 873 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 874 device_xname(sc->sc_dev))); 875 } 876 /* 877 * XXX 878 * no way to check M_CSUM_TCP_UDP_BAD or 879 * other protocols? 880 */ 881 if (flags & NFE_RX_UDP_CSUMOK) { 882 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 883 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 884 device_xname(sc->sc_dev))); 885 } else if (flags & NFE_RX_TCP_CSUMOK) { 886 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 887 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 888 device_xname(sc->sc_dev))); 889 } 890 } 891 #if NBPFILTER > 0 892 if (ifp->if_bpf) 893 bpf_mtap(ifp->if_bpf, m); 894 #endif 895 ifp->if_ipackets++; 896 (*ifp->if_input)(ifp, m); 897 898 skip1: 899 /* update mapping address in h/w descriptor */ 900 if (sc->sc_flags & NFE_40BIT_ADDR) { 901 #if defined(__LP64__) 902 desc64->physaddr[0] = htole32(physaddr >> 32); 903 #endif 904 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 905 } else { 906 desc32->physaddr = htole32(physaddr); 907 } 908 909 skip: 910 if (sc->sc_flags & NFE_40BIT_ADDR) { 911 desc64->length = htole16(sc->rxq.bufsz); 912 desc64->flags = htole16(NFE_RX_READY); 913 914 nfe_rxdesc64_sync(sc, desc64, 915 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 916 } else { 917 desc32->length = htole16(sc->rxq.bufsz); 918 desc32->flags = htole16(NFE_RX_READY); 919 920 nfe_rxdesc32_sync(sc, desc32, 921 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 922 } 923 } 924 /* update current RX pointer */ 925 sc->rxq.cur = i; 926 } 927 928 void 929 nfe_txeof(struct nfe_softc *sc) 930 { 931 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 932 struct nfe_desc32 *desc32; 933 struct nfe_desc64 *desc64; 934 struct nfe_tx_data *data = NULL; 935 int i; 936 uint16_t flags; 937 char buf[128]; 938 939 for (i = sc->txq.next; 940 sc->txq.queued > 0; 941 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 942 if (sc->sc_flags & NFE_40BIT_ADDR) { 943 desc64 = &sc->txq.desc64[i]; 944 nfe_txdesc64_sync(sc, desc64, 945 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 946 947 flags = le16toh(desc64->flags); 948 } else { 949 desc32 = &sc->txq.desc32[i]; 950 nfe_txdesc32_sync(sc, desc32, 951 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 952 953 flags = le16toh(desc32->flags); 954 } 955 956 if ((flags & NFE_TX_VALID) != 0) 957 break; 958 959 data = &sc->txq.data[i]; 960 961 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 962 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 963 data->m == NULL) 964 continue; 965 966 if ((flags & NFE_TX_ERROR_V1) != 0) { 967 aprint_error_dev(sc->sc_dev, "tx v1 error %s\n", 968 bitmask_snprintf(flags, NFE_V1_TXERR, 969 buf, sizeof(buf))); 970 ifp->if_oerrors++; 971 } else 972 ifp->if_opackets++; 973 } else { 974 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 975 data->m == NULL) 976 continue; 977 978 if ((flags & NFE_TX_ERROR_V2) != 0) { 979 aprint_error_dev(sc->sc_dev, "tx v2 error %s\n", 980 bitmask_snprintf(flags, NFE_V2_TXERR, 981 buf, sizeof(buf))); 982 ifp->if_oerrors++; 983 } else 984 ifp->if_opackets++; 985 } 986 987 if (data->m == NULL) { /* should not get there */ 988 aprint_error_dev(sc->sc_dev, 989 "last fragment bit w/o associated mbuf!\n"); 990 continue; 991 } 992 993 /* last fragment of the mbuf chain transmitted */ 994 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 995 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 996 bus_dmamap_unload(sc->sc_dmat, data->active); 997 m_freem(data->m); 998 data->m = NULL; 999 } 1000 1001 sc->txq.next = i; 1002 1003 if (sc->txq.queued < NFE_TX_RING_COUNT) { 1004 /* at least one slot freed */ 1005 ifp->if_flags &= ~IFF_OACTIVE; 1006 } 1007 1008 if (sc->txq.queued == 0) { 1009 /* all queued packets are sent */ 1010 ifp->if_timer = 0; 1011 } 1012 } 1013 1014 int 1015 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 1016 { 1017 struct nfe_desc32 *desc32; 1018 struct nfe_desc64 *desc64; 1019 struct nfe_tx_data *data; 1020 bus_dmamap_t map; 1021 uint16_t flags, csumflags; 1022 #if NVLAN > 0 1023 struct m_tag *mtag; 1024 uint32_t vtag = 0; 1025 #endif 1026 int error, i, first; 1027 1028 desc32 = NULL; 1029 desc64 = NULL; 1030 data = NULL; 1031 1032 flags = 0; 1033 csumflags = 0; 1034 first = sc->txq.cur; 1035 1036 map = sc->txq.data[first].map; 1037 1038 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1039 if (error != 0) { 1040 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1041 error); 1042 return error; 1043 } 1044 1045 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1046 bus_dmamap_unload(sc->sc_dmat, map); 1047 return ENOBUFS; 1048 } 1049 1050 #if NVLAN > 0 1051 /* setup h/w VLAN tagging */ 1052 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1053 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1054 #endif 1055 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1056 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1057 csumflags |= NFE_TX_IP_CSUM; 1058 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1059 csumflags |= NFE_TX_TCP_UDP_CSUM; 1060 } 1061 1062 for (i = 0; i < map->dm_nsegs; i++) { 1063 data = &sc->txq.data[sc->txq.cur]; 1064 1065 if (sc->sc_flags & NFE_40BIT_ADDR) { 1066 desc64 = &sc->txq.desc64[sc->txq.cur]; 1067 #if defined(__LP64__) 1068 desc64->physaddr[0] = 1069 htole32(map->dm_segs[i].ds_addr >> 32); 1070 #endif 1071 desc64->physaddr[1] = 1072 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1073 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1074 desc64->flags = htole16(flags); 1075 desc64->vtag = 0; 1076 } else { 1077 desc32 = &sc->txq.desc32[sc->txq.cur]; 1078 1079 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1080 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1081 desc32->flags = htole16(flags); 1082 } 1083 1084 /* 1085 * Setting of the valid bit in the first descriptor is 1086 * deferred until the whole chain is fully setup. 1087 */ 1088 flags |= NFE_TX_VALID; 1089 1090 sc->txq.queued++; 1091 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1092 } 1093 1094 /* the whole mbuf chain has been setup */ 1095 if (sc->sc_flags & NFE_40BIT_ADDR) { 1096 /* fix last descriptor */ 1097 flags |= NFE_TX_LASTFRAG_V2; 1098 desc64->flags = htole16(flags); 1099 1100 /* Checksum flags and vtag belong to the first fragment only. */ 1101 #if NVLAN > 0 1102 sc->txq.desc64[first].vtag = htole32(vtag); 1103 #endif 1104 sc->txq.desc64[first].flags |= htole16(csumflags); 1105 1106 /* finally, set the valid bit in the first descriptor */ 1107 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1108 } else { 1109 /* fix last descriptor */ 1110 if (sc->sc_flags & NFE_JUMBO_SUP) 1111 flags |= NFE_TX_LASTFRAG_V2; 1112 else 1113 flags |= NFE_TX_LASTFRAG_V1; 1114 desc32->flags = htole16(flags); 1115 1116 /* Checksum flags belong to the first fragment only. */ 1117 sc->txq.desc32[first].flags |= htole16(csumflags); 1118 1119 /* finally, set the valid bit in the first descriptor */ 1120 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1121 } 1122 1123 data->m = m0; 1124 data->active = map; 1125 1126 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1127 BUS_DMASYNC_PREWRITE); 1128 1129 return 0; 1130 } 1131 1132 void 1133 nfe_start(struct ifnet *ifp) 1134 { 1135 struct nfe_softc *sc = ifp->if_softc; 1136 int old = sc->txq.queued; 1137 struct mbuf *m0; 1138 1139 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1140 return; 1141 1142 for (;;) { 1143 IFQ_POLL(&ifp->if_snd, m0); 1144 if (m0 == NULL) 1145 break; 1146 1147 if (nfe_encap(sc, m0) != 0) { 1148 ifp->if_flags |= IFF_OACTIVE; 1149 break; 1150 } 1151 1152 /* packet put in h/w queue, remove from s/w queue */ 1153 IFQ_DEQUEUE(&ifp->if_snd, m0); 1154 1155 #if NBPFILTER > 0 1156 if (ifp->if_bpf != NULL) 1157 bpf_mtap(ifp->if_bpf, m0); 1158 #endif 1159 } 1160 1161 if (sc->txq.queued != old) { 1162 /* packets are queued */ 1163 if (sc->sc_flags & NFE_40BIT_ADDR) 1164 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1165 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1166 else 1167 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1168 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1169 /* kick Tx */ 1170 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1171 1172 /* 1173 * Set a timeout in case the chip goes out to lunch. 1174 */ 1175 ifp->if_timer = 5; 1176 } 1177 } 1178 1179 void 1180 nfe_watchdog(struct ifnet *ifp) 1181 { 1182 struct nfe_softc *sc = ifp->if_softc; 1183 1184 aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1185 1186 ifp->if_flags &= ~IFF_RUNNING; 1187 nfe_init(ifp); 1188 1189 ifp->if_oerrors++; 1190 } 1191 1192 int 1193 nfe_init(struct ifnet *ifp) 1194 { 1195 struct nfe_softc *sc = ifp->if_softc; 1196 uint32_t tmp; 1197 int rc = 0, s; 1198 1199 if (ifp->if_flags & IFF_RUNNING) 1200 return 0; 1201 1202 nfe_stop(ifp, 0); 1203 1204 NFE_WRITE(sc, NFE_TX_UNK, 0); 1205 NFE_WRITE(sc, NFE_STATUS, 0); 1206 1207 sc->rxtxctl = NFE_RXTX_BIT2; 1208 if (sc->sc_flags & NFE_40BIT_ADDR) 1209 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1210 else if (sc->sc_flags & NFE_JUMBO_SUP) 1211 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1212 if (sc->sc_flags & NFE_HW_CSUM) 1213 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1214 #if NVLAN > 0 1215 /* 1216 * Although the adapter is capable of stripping VLAN tags from received 1217 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1218 * purpose. This will be done in software by our network stack. 1219 */ 1220 if (sc->sc_flags & NFE_HW_VLAN) 1221 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1222 #endif 1223 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1224 DELAY(10); 1225 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1226 1227 #if NVLAN 1228 if (sc->sc_flags & NFE_HW_VLAN) 1229 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1230 #endif 1231 1232 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1233 1234 /* set MAC address */ 1235 nfe_set_macaddr(sc, sc->sc_enaddr); 1236 1237 /* tell MAC where rings are in memory */ 1238 #ifdef __LP64__ 1239 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1240 #endif 1241 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1242 #ifdef __LP64__ 1243 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1244 #endif 1245 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1246 1247 NFE_WRITE(sc, NFE_RING_SIZE, 1248 (NFE_RX_RING_COUNT - 1) << 16 | 1249 (NFE_TX_RING_COUNT - 1)); 1250 1251 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1252 1253 /* force MAC to wakeup */ 1254 tmp = NFE_READ(sc, NFE_PWR_STATE); 1255 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1256 DELAY(10); 1257 tmp = NFE_READ(sc, NFE_PWR_STATE); 1258 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1259 1260 s = splnet(); 1261 nfe_intr(sc); /* XXX clear IRQ status registers */ 1262 splx(s); 1263 1264 #if 1 1265 /* configure interrupts coalescing/mitigation */ 1266 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1267 #else 1268 /* no interrupt mitigation: one interrupt per packet */ 1269 NFE_WRITE(sc, NFE_IMTIMER, 970); 1270 #endif 1271 1272 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1273 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1274 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1275 1276 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1277 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1278 1279 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1280 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_ENABLE); 1281 1282 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1283 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1284 DELAY(10); 1285 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1286 1287 /* set Rx filter */ 1288 nfe_setmulti(sc); 1289 1290 if ((rc = ether_mediachange(ifp)) != 0) 1291 goto out; 1292 1293 nfe_tick(sc); 1294 1295 /* enable Rx */ 1296 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1297 1298 /* enable Tx */ 1299 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1300 1301 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1302 1303 /* enable interrupts */ 1304 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1305 1306 callout_schedule(&sc->sc_tick_ch, hz); 1307 1308 ifp->if_flags |= IFF_RUNNING; 1309 ifp->if_flags &= ~IFF_OACTIVE; 1310 1311 out: 1312 return rc; 1313 } 1314 1315 void 1316 nfe_stop(struct ifnet *ifp, int disable) 1317 { 1318 struct nfe_softc *sc = ifp->if_softc; 1319 1320 callout_stop(&sc->sc_tick_ch); 1321 1322 ifp->if_timer = 0; 1323 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1324 1325 mii_down(&sc->sc_mii); 1326 1327 /* abort Tx */ 1328 NFE_WRITE(sc, NFE_TX_CTL, 0); 1329 1330 /* disable Rx */ 1331 NFE_WRITE(sc, NFE_RX_CTL, 0); 1332 1333 /* disable interrupts */ 1334 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1335 1336 /* reset Tx and Rx rings */ 1337 nfe_reset_tx_ring(sc, &sc->txq); 1338 nfe_reset_rx_ring(sc, &sc->rxq); 1339 } 1340 1341 int 1342 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1343 { 1344 struct nfe_desc32 *desc32; 1345 struct nfe_desc64 *desc64; 1346 struct nfe_rx_data *data; 1347 struct nfe_jbuf *jbuf; 1348 void **desc; 1349 bus_addr_t physaddr; 1350 int i, nsegs, error, descsize; 1351 1352 if (sc->sc_flags & NFE_40BIT_ADDR) { 1353 desc = (void **)&ring->desc64; 1354 descsize = sizeof (struct nfe_desc64); 1355 } else { 1356 desc = (void **)&ring->desc32; 1357 descsize = sizeof (struct nfe_desc32); 1358 } 1359 1360 ring->cur = ring->next = 0; 1361 ring->bufsz = MCLBYTES; 1362 1363 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1364 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1365 if (error != 0) { 1366 aprint_error_dev(sc->sc_dev, 1367 "could not create desc DMA map\n"); 1368 goto fail; 1369 } 1370 1371 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1372 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1373 if (error != 0) { 1374 aprint_error_dev(sc->sc_dev, 1375 "could not allocate DMA memory\n"); 1376 goto fail; 1377 } 1378 1379 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1380 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1381 if (error != 0) { 1382 aprint_error_dev(sc->sc_dev, 1383 "could not map desc DMA memory\n"); 1384 goto fail; 1385 } 1386 1387 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1388 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1389 if (error != 0) { 1390 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1391 goto fail; 1392 } 1393 1394 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1395 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1396 1397 if (sc->sc_flags & NFE_USE_JUMBO) { 1398 ring->bufsz = NFE_JBYTES; 1399 if ((error = nfe_jpool_alloc(sc)) != 0) { 1400 aprint_error_dev(sc->sc_dev, 1401 "could not allocate jumbo frames\n"); 1402 goto fail; 1403 } 1404 } 1405 1406 /* 1407 * Pre-allocate Rx buffers and populate Rx ring. 1408 */ 1409 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1410 data = &sc->rxq.data[i]; 1411 1412 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1413 if (data->m == NULL) { 1414 aprint_error_dev(sc->sc_dev, 1415 "could not allocate rx mbuf\n"); 1416 error = ENOMEM; 1417 goto fail; 1418 } 1419 1420 if (sc->sc_flags & NFE_USE_JUMBO) { 1421 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1422 aprint_error_dev(sc->sc_dev, 1423 "could not allocate jumbo buffer\n"); 1424 goto fail; 1425 } 1426 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1427 sc); 1428 1429 physaddr = jbuf->physaddr; 1430 } else { 1431 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1432 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1433 if (error != 0) { 1434 aprint_error_dev(sc->sc_dev, 1435 "could not create DMA map\n"); 1436 goto fail; 1437 } 1438 MCLGET(data->m, M_DONTWAIT); 1439 if (!(data->m->m_flags & M_EXT)) { 1440 aprint_error_dev(sc->sc_dev, 1441 "could not allocate mbuf cluster\n"); 1442 error = ENOMEM; 1443 goto fail; 1444 } 1445 1446 error = bus_dmamap_load(sc->sc_dmat, data->map, 1447 mtod(data->m, void *), MCLBYTES, NULL, 1448 BUS_DMA_READ | BUS_DMA_NOWAIT); 1449 if (error != 0) { 1450 aprint_error_dev(sc->sc_dev, 1451 "could not load rx buf DMA map"); 1452 goto fail; 1453 } 1454 physaddr = data->map->dm_segs[0].ds_addr; 1455 } 1456 1457 if (sc->sc_flags & NFE_40BIT_ADDR) { 1458 desc64 = &sc->rxq.desc64[i]; 1459 #if defined(__LP64__) 1460 desc64->physaddr[0] = htole32(physaddr >> 32); 1461 #endif 1462 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1463 desc64->length = htole16(sc->rxq.bufsz); 1464 desc64->flags = htole16(NFE_RX_READY); 1465 } else { 1466 desc32 = &sc->rxq.desc32[i]; 1467 desc32->physaddr = htole32(physaddr); 1468 desc32->length = htole16(sc->rxq.bufsz); 1469 desc32->flags = htole16(NFE_RX_READY); 1470 } 1471 } 1472 1473 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1474 BUS_DMASYNC_PREWRITE); 1475 1476 return 0; 1477 1478 fail: nfe_free_rx_ring(sc, ring); 1479 return error; 1480 } 1481 1482 void 1483 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1484 { 1485 int i; 1486 1487 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1488 if (sc->sc_flags & NFE_40BIT_ADDR) { 1489 ring->desc64[i].length = htole16(ring->bufsz); 1490 ring->desc64[i].flags = htole16(NFE_RX_READY); 1491 } else { 1492 ring->desc32[i].length = htole16(ring->bufsz); 1493 ring->desc32[i].flags = htole16(NFE_RX_READY); 1494 } 1495 } 1496 1497 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1498 BUS_DMASYNC_PREWRITE); 1499 1500 ring->cur = ring->next = 0; 1501 } 1502 1503 void 1504 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1505 { 1506 struct nfe_rx_data *data; 1507 void *desc; 1508 int i, descsize; 1509 1510 if (sc->sc_flags & NFE_40BIT_ADDR) { 1511 desc = ring->desc64; 1512 descsize = sizeof (struct nfe_desc64); 1513 } else { 1514 desc = ring->desc32; 1515 descsize = sizeof (struct nfe_desc32); 1516 } 1517 1518 if (desc != NULL) { 1519 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1520 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1521 bus_dmamap_unload(sc->sc_dmat, ring->map); 1522 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1523 NFE_RX_RING_COUNT * descsize); 1524 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1525 } 1526 1527 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1528 data = &ring->data[i]; 1529 1530 if (data->map != NULL) { 1531 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1532 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1533 bus_dmamap_unload(sc->sc_dmat, data->map); 1534 bus_dmamap_destroy(sc->sc_dmat, data->map); 1535 } 1536 if (data->m != NULL) 1537 m_freem(data->m); 1538 } 1539 } 1540 1541 struct nfe_jbuf * 1542 nfe_jalloc(struct nfe_softc *sc, int i) 1543 { 1544 struct nfe_jbuf *jbuf; 1545 1546 mutex_enter(&sc->rxq.mtx); 1547 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1548 if (jbuf != NULL) 1549 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1550 mutex_exit(&sc->rxq.mtx); 1551 if (jbuf == NULL) 1552 return NULL; 1553 sc->rxq.jbufmap[i] = 1554 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1555 return jbuf; 1556 } 1557 1558 /* 1559 * This is called automatically by the network stack when the mbuf is freed. 1560 * Caution must be taken that the NIC might be reset by the time the mbuf is 1561 * freed. 1562 */ 1563 void 1564 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1565 { 1566 struct nfe_softc *sc = arg; 1567 struct nfe_jbuf *jbuf; 1568 int i; 1569 1570 /* find the jbuf from the base pointer */ 1571 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1572 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1573 aprint_error_dev(sc->sc_dev, 1574 "request to free a buffer (%p) not managed by us\n", buf); 1575 return; 1576 } 1577 jbuf = &sc->rxq.jbuf[i]; 1578 1579 /* ..and put it back in the free list */ 1580 mutex_enter(&sc->rxq.mtx); 1581 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1582 mutex_exit(&sc->rxq.mtx); 1583 1584 if (m != NULL) 1585 pool_cache_put(mb_cache, m); 1586 } 1587 1588 int 1589 nfe_jpool_alloc(struct nfe_softc *sc) 1590 { 1591 struct nfe_rx_ring *ring = &sc->rxq; 1592 struct nfe_jbuf *jbuf; 1593 bus_addr_t physaddr; 1594 char *buf; 1595 int i, nsegs, error; 1596 1597 /* 1598 * Allocate a big chunk of DMA'able memory. 1599 */ 1600 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1601 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1602 if (error != 0) { 1603 aprint_error_dev(sc->sc_dev, 1604 "could not create jumbo DMA map\n"); 1605 goto fail; 1606 } 1607 1608 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1609 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1610 if (error != 0) { 1611 aprint_error_dev(sc->sc_dev, 1612 "could not allocate jumbo DMA memory\n"); 1613 goto fail; 1614 } 1615 1616 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1617 &ring->jpool, BUS_DMA_NOWAIT); 1618 if (error != 0) { 1619 aprint_error_dev(sc->sc_dev, 1620 "could not map jumbo DMA memory\n"); 1621 goto fail; 1622 } 1623 1624 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1625 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1626 if (error != 0) { 1627 aprint_error_dev(sc->sc_dev, 1628 "could not load jumbo DMA map\n"); 1629 goto fail; 1630 } 1631 1632 /* ..and split it into 9KB chunks */ 1633 SLIST_INIT(&ring->jfreelist); 1634 1635 buf = ring->jpool; 1636 physaddr = ring->jmap->dm_segs[0].ds_addr; 1637 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1638 jbuf = &ring->jbuf[i]; 1639 1640 jbuf->buf = buf; 1641 jbuf->physaddr = physaddr; 1642 1643 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1644 1645 buf += NFE_JBYTES; 1646 physaddr += NFE_JBYTES; 1647 } 1648 1649 return 0; 1650 1651 fail: nfe_jpool_free(sc); 1652 return error; 1653 } 1654 1655 void 1656 nfe_jpool_free(struct nfe_softc *sc) 1657 { 1658 struct nfe_rx_ring *ring = &sc->rxq; 1659 1660 if (ring->jmap != NULL) { 1661 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1662 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1663 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1664 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1665 } 1666 if (ring->jpool != NULL) { 1667 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1668 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1669 } 1670 } 1671 1672 int 1673 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1674 { 1675 int i, nsegs, error; 1676 void **desc; 1677 int descsize; 1678 1679 if (sc->sc_flags & NFE_40BIT_ADDR) { 1680 desc = (void **)&ring->desc64; 1681 descsize = sizeof (struct nfe_desc64); 1682 } else { 1683 desc = (void **)&ring->desc32; 1684 descsize = sizeof (struct nfe_desc32); 1685 } 1686 1687 ring->queued = 0; 1688 ring->cur = ring->next = 0; 1689 1690 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1691 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1692 1693 if (error != 0) { 1694 aprint_error_dev(sc->sc_dev, 1695 "could not create desc DMA map\n"); 1696 goto fail; 1697 } 1698 1699 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1700 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1701 if (error != 0) { 1702 aprint_error_dev(sc->sc_dev, 1703 "could not allocate DMA memory\n"); 1704 goto fail; 1705 } 1706 1707 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1708 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1709 if (error != 0) { 1710 aprint_error_dev(sc->sc_dev, 1711 "could not map desc DMA memory\n"); 1712 goto fail; 1713 } 1714 1715 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1716 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1717 if (error != 0) { 1718 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1719 goto fail; 1720 } 1721 1722 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1723 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1724 1725 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1726 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1727 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1728 &ring->data[i].map); 1729 if (error != 0) { 1730 aprint_error_dev(sc->sc_dev, 1731 "could not create DMA map\n"); 1732 goto fail; 1733 } 1734 } 1735 1736 return 0; 1737 1738 fail: nfe_free_tx_ring(sc, ring); 1739 return error; 1740 } 1741 1742 void 1743 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1744 { 1745 struct nfe_tx_data *data; 1746 int i; 1747 1748 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1749 if (sc->sc_flags & NFE_40BIT_ADDR) 1750 ring->desc64[i].flags = 0; 1751 else 1752 ring->desc32[i].flags = 0; 1753 1754 data = &ring->data[i]; 1755 1756 if (data->m != NULL) { 1757 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1758 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1759 bus_dmamap_unload(sc->sc_dmat, data->active); 1760 m_freem(data->m); 1761 data->m = NULL; 1762 } 1763 } 1764 1765 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1766 BUS_DMASYNC_PREWRITE); 1767 1768 ring->queued = 0; 1769 ring->cur = ring->next = 0; 1770 } 1771 1772 void 1773 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1774 { 1775 struct nfe_tx_data *data; 1776 void *desc; 1777 int i, descsize; 1778 1779 if (sc->sc_flags & NFE_40BIT_ADDR) { 1780 desc = ring->desc64; 1781 descsize = sizeof (struct nfe_desc64); 1782 } else { 1783 desc = ring->desc32; 1784 descsize = sizeof (struct nfe_desc32); 1785 } 1786 1787 if (desc != NULL) { 1788 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1789 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1790 bus_dmamap_unload(sc->sc_dmat, ring->map); 1791 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1792 NFE_TX_RING_COUNT * descsize); 1793 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1794 } 1795 1796 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1797 data = &ring->data[i]; 1798 1799 if (data->m != NULL) { 1800 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1801 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1802 bus_dmamap_unload(sc->sc_dmat, data->active); 1803 m_freem(data->m); 1804 } 1805 } 1806 1807 /* ..and now actually destroy the DMA mappings */ 1808 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1809 data = &ring->data[i]; 1810 if (data->map == NULL) 1811 continue; 1812 bus_dmamap_destroy(sc->sc_dmat, data->map); 1813 } 1814 } 1815 1816 void 1817 nfe_setmulti(struct nfe_softc *sc) 1818 { 1819 struct ethercom *ec = &sc->sc_ethercom; 1820 struct ifnet *ifp = &ec->ec_if; 1821 struct ether_multi *enm; 1822 struct ether_multistep step; 1823 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1824 uint32_t filter = NFE_RXFILTER_MAGIC; 1825 int i; 1826 1827 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1828 bzero(addr, ETHER_ADDR_LEN); 1829 bzero(mask, ETHER_ADDR_LEN); 1830 goto done; 1831 } 1832 1833 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1834 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1835 1836 ETHER_FIRST_MULTI(step, ec, enm); 1837 while (enm != NULL) { 1838 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1839 ifp->if_flags |= IFF_ALLMULTI; 1840 bzero(addr, ETHER_ADDR_LEN); 1841 bzero(mask, ETHER_ADDR_LEN); 1842 goto done; 1843 } 1844 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1845 addr[i] &= enm->enm_addrlo[i]; 1846 mask[i] &= ~enm->enm_addrlo[i]; 1847 } 1848 ETHER_NEXT_MULTI(step, enm); 1849 } 1850 for (i = 0; i < ETHER_ADDR_LEN; i++) 1851 mask[i] |= addr[i]; 1852 1853 done: 1854 addr[0] |= 0x01; /* make sure multicast bit is set */ 1855 1856 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1857 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1858 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1859 addr[5] << 8 | addr[4]); 1860 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1861 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1862 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1863 mask[5] << 8 | mask[4]); 1864 1865 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1866 NFE_WRITE(sc, NFE_RXFILTER, filter); 1867 } 1868 1869 void 1870 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1871 { 1872 uint32_t tmp; 1873 1874 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 1875 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1876 addr[0] = (tmp & 0xff); 1877 addr[1] = (tmp >> 8) & 0xff; 1878 addr[2] = (tmp >> 16) & 0xff; 1879 addr[3] = (tmp >> 24) & 0xff; 1880 1881 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1882 addr[4] = (tmp & 0xff); 1883 addr[5] = (tmp >> 8) & 0xff; 1884 1885 } else { 1886 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1887 addr[0] = (tmp >> 8) & 0xff; 1888 addr[1] = (tmp & 0xff); 1889 1890 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1891 addr[2] = (tmp >> 24) & 0xff; 1892 addr[3] = (tmp >> 16) & 0xff; 1893 addr[4] = (tmp >> 8) & 0xff; 1894 addr[5] = (tmp & 0xff); 1895 } 1896 } 1897 1898 void 1899 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1900 { 1901 NFE_WRITE(sc, NFE_MACADDR_LO, 1902 addr[5] << 8 | addr[4]); 1903 NFE_WRITE(sc, NFE_MACADDR_HI, 1904 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1905 } 1906 1907 void 1908 nfe_tick(void *arg) 1909 { 1910 struct nfe_softc *sc = arg; 1911 int s; 1912 1913 s = splnet(); 1914 mii_tick(&sc->sc_mii); 1915 splx(s); 1916 1917 callout_schedule(&sc->sc_tick_ch, hz); 1918 } 1919 1920 void 1921 nfe_poweron(device_t self) 1922 { 1923 struct nfe_softc *sc = device_private(self); 1924 1925 if ((sc->sc_flags & NFE_PWR_MGMT) != 0) { 1926 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 1927 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 1928 DELAY(100); 1929 NFE_WRITE(sc, NFE_MAC_RESET, 0); 1930 DELAY(100); 1931 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 1932 NFE_WRITE(sc, NFE_PWR2_CTL, 1933 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_WAKEUP_MASK); 1934 } 1935 } 1936 1937 bool 1938 nfe_resume(device_t dv PMF_FN_ARGS) 1939 { 1940 nfe_poweron(dv); 1941 1942 return true; 1943 } 1944
Indexes created Tue Sep 30 07:10:03 GMT 2025