if_nfe.c revision 1.36.6.1
1 /* $NetBSD: if_nfe.c,v 1.36.6.1 2009/03/02 20:46:03 snj Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.77 2008/02/05 16:52:50 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006, 2007 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.36.6.1 2009/03/02 20:46:03 snj Exp $"); 25 26 #include "opt_inet.h" 27 #include "bpfilter.h" 28 #include "vlan.h" 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/types.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/mutex.h> 37 #include <sys/queue.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/callout.h> 41 #include <sys/socket.h> 42 43 #include <sys/bus.h> 44 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 #include <net/if_ether.h> 49 #include <net/if_arp.h> 50 51 #ifdef INET 52 #include <netinet/in.h> 53 #include <netinet/in_systm.h> 54 #include <netinet/in_var.h> 55 #include <netinet/ip.h> 56 #include <netinet/if_inarp.h> 57 #endif 58 59 #if NVLAN > 0 60 #include <net/if_types.h> 61 #endif 62 63 #if NBPFILTER > 0 64 #include <net/bpf.h> 65 #endif 66 67 #include <dev/mii/mii.h> 68 #include <dev/mii/miivar.h> 69 70 #include <dev/pci/pcireg.h> 71 #include <dev/pci/pcivar.h> 72 #include <dev/pci/pcidevs.h> 73 74 #include <dev/pci/if_nfereg.h> 75 #include <dev/pci/if_nfevar.h> 76 77 int nfe_match(device_t, cfdata_t, void *); 78 void nfe_attach(device_t, device_t, void *); 79 void nfe_power(int, void *); 80 void nfe_miibus_statchg(device_t); 81 int nfe_miibus_readreg(device_t, int, int); 82 void nfe_miibus_writereg(device_t, int, int, int); 83 int nfe_intr(void *); 84 int nfe_ioctl(struct ifnet *, u_long, void *); 85 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 86 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 87 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 88 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 89 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 90 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 91 void nfe_rxeof(struct nfe_softc *); 92 void nfe_txeof(struct nfe_softc *); 93 int nfe_encap(struct nfe_softc *, struct mbuf *); 94 void nfe_start(struct ifnet *); 95 void nfe_watchdog(struct ifnet *); 96 int nfe_init(struct ifnet *); 97 void nfe_stop(struct ifnet *, int); 98 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 99 void nfe_jfree(struct mbuf *, void *, size_t, void *); 100 int nfe_jpool_alloc(struct nfe_softc *); 101 void nfe_jpool_free(struct nfe_softc *); 102 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 105 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 108 void nfe_setmulti(struct nfe_softc *); 109 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 110 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 111 void nfe_tick(void *); 112 void nfe_poweron(device_t); 113 bool nfe_resume(device_t PMF_FN_PROTO); 114 115 CFATTACH_DECL_NEW(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, 116 NULL, NULL); 117 118 /* #define NFE_NO_JUMBO */ 119 120 #ifdef NFE_DEBUG 121 int nfedebug = 0; 122 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 123 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 124 #else 125 #define DPRINTF(x) 126 #define DPRINTFN(n,x) 127 #endif 128 129 /* deal with naming differences */ 130 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 134 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 135 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 136 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 137 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 140 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 141 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 142 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 145 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 146 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 147 148 #ifdef _LP64 149 #define __LP64__ 1 150 #endif 151 152 const struct nfe_product { 153 pci_vendor_id_t vendor; 154 pci_product_id_t product; 155 } nfe_devices[] = { 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 183 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 184 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 185 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 186 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 }, 187 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1 }, 188 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2 }, 189 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3 }, 190 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4 }, 191 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1 }, 192 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2 }, 193 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3 }, 194 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4 } 195 }; 196 197 int 198 nfe_match(device_t dev, cfdata_t match, void *aux) 199 { 200 struct pci_attach_args *pa = aux; 201 const struct nfe_product *np; 202 int i; 203 204 for (i = 0; i < sizeof(nfe_devices) / sizeof(nfe_devices[0]); i++) { 205 np = &nfe_devices[i]; 206 if (PCI_VENDOR(pa->pa_id) == np->vendor && 207 PCI_PRODUCT(pa->pa_id) == np->product) 208 return 1; 209 } 210 return 0; 211 } 212 213 void 214 nfe_attach(device_t parent, device_t self, void *aux) 215 { 216 struct nfe_softc *sc = device_private(self); 217 struct pci_attach_args *pa = aux; 218 pci_chipset_tag_t pc = pa->pa_pc; 219 pci_intr_handle_t ih; 220 const char *intrstr; 221 struct ifnet *ifp; 222 bus_size_t memsize; 223 pcireg_t memtype; 224 char devinfo[256]; 225 226 sc->sc_dev = self; 227 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 228 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 229 230 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 231 switch (memtype) { 232 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 233 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 234 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 235 &sc->sc_memh, NULL, &memsize) == 0) 236 break; 237 /* FALLTHROUGH */ 238 default: 239 aprint_error_dev(self, "could not map mem space\n"); 240 return; 241 } 242 243 if (pci_intr_map(pa, &ih) != 0) { 244 aprint_error_dev(self, "could not map interrupt\n"); 245 goto fail; 246 } 247 248 intrstr = pci_intr_string(pc, ih); 249 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 250 if (sc->sc_ih == NULL) { 251 aprint_error_dev(self, "could not establish interrupt"); 252 if (intrstr != NULL) 253 aprint_normal(" at %s", intrstr); 254 aprint_normal("\n"); 255 goto fail; 256 } 257 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 258 259 sc->sc_dmat = pa->pa_dmat; 260 261 sc->sc_flags = 0; 262 263 switch (PCI_PRODUCT(pa->pa_id)) { 264 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 265 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 266 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 267 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 268 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 269 break; 270 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 271 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 272 sc->sc_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT; 273 break; 274 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 275 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 276 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 277 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 278 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 279 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 280 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 281 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 282 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 283 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 284 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 285 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 286 sc->sc_flags |= NFE_40BIT_ADDR | NFE_CORRECT_MACADDR | 287 NFE_PWR_MGMT; 288 break; 289 case PCI_PRODUCT_NVIDIA_MCP77_LAN1: 290 case PCI_PRODUCT_NVIDIA_MCP77_LAN2: 291 case PCI_PRODUCT_NVIDIA_MCP77_LAN3: 292 case PCI_PRODUCT_NVIDIA_MCP77_LAN4: 293 case PCI_PRODUCT_NVIDIA_MCP79_LAN1: 294 case PCI_PRODUCT_NVIDIA_MCP79_LAN2: 295 case PCI_PRODUCT_NVIDIA_MCP79_LAN3: 296 case PCI_PRODUCT_NVIDIA_MCP79_LAN4: 297 sc->sc_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | 298 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 299 break; 300 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 301 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 302 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 303 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 304 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 305 break; 306 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 307 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 308 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 309 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 310 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 311 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 312 break; 313 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 314 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 315 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 316 NFE_HW_VLAN | NFE_PWR_MGMT; 317 break; 318 } 319 320 nfe_poweron(self); 321 322 #ifndef NFE_NO_JUMBO 323 /* enable jumbo frames for adapters that support it */ 324 if (sc->sc_flags & NFE_JUMBO_SUP) 325 sc->sc_flags |= NFE_USE_JUMBO; 326 #endif 327 328 /* Check for reversed ethernet address */ 329 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 330 sc->sc_flags |= NFE_CORRECT_MACADDR; 331 332 nfe_get_macaddr(sc, sc->sc_enaddr); 333 aprint_normal_dev(self, "Ethernet address %s\n", 334 ether_sprintf(sc->sc_enaddr)); 335 336 /* 337 * Allocate Tx and Rx rings. 338 */ 339 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 340 aprint_error_dev(self, "could not allocate Tx ring\n"); 341 goto fail; 342 } 343 344 mutex_init(&sc->rxq.mtx, MUTEX_DEFAULT, IPL_NET); 345 346 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 347 aprint_error_dev(self, "could not allocate Rx ring\n"); 348 nfe_free_tx_ring(sc, &sc->txq); 349 goto fail; 350 } 351 352 ifp = &sc->sc_ethercom.ec_if; 353 ifp->if_softc = sc; 354 ifp->if_mtu = ETHERMTU; 355 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 356 ifp->if_ioctl = nfe_ioctl; 357 ifp->if_start = nfe_start; 358 ifp->if_stop = nfe_stop; 359 ifp->if_watchdog = nfe_watchdog; 360 ifp->if_init = nfe_init; 361 ifp->if_baudrate = IF_Gbps(1); 362 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 363 IFQ_SET_READY(&ifp->if_snd); 364 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 365 366 #ifdef notyet 367 if (sc->sc_flags & NFE_USE_JUMBO) 368 ifp->if_hardmtu = NFE_JUMBO_MTU; 369 #endif 370 371 #if NVLAN > 0 372 if (sc->sc_flags & NFE_HW_VLAN) 373 sc->sc_ethercom.ec_capabilities |= 374 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 375 #endif 376 if (sc->sc_flags & NFE_HW_CSUM) { 377 ifp->if_capabilities |= 378 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 379 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 380 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 381 } 382 383 sc->sc_mii.mii_ifp = ifp; 384 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 385 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 386 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 387 388 sc->sc_ethercom.ec_mii = &sc->sc_mii; 389 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 390 ether_mediastatus); 391 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 392 MII_OFFSET_ANY, 0); 393 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 394 aprint_error_dev(self, "no PHY found!\n"); 395 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 396 0, NULL); 397 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 398 } else 399 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 400 401 if_attach(ifp); 402 ether_ifattach(ifp, sc->sc_enaddr); 403 404 callout_init(&sc->sc_tick_ch, 0); 405 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 406 407 if (!pmf_device_register(self, NULL, nfe_resume)) 408 aprint_error_dev(self, "couldn't establish power handler\n"); 409 else 410 pmf_class_network_register(self, ifp); 411 412 return; 413 414 fail: 415 if (sc->sc_ih != NULL) { 416 pci_intr_disestablish(pc, sc->sc_ih); 417 sc->sc_ih = NULL; 418 } 419 if (memsize) 420 bus_space_unmap(sc->sc_memt, sc->sc_memh, memsize); 421 } 422 423 void 424 nfe_miibus_statchg(device_t dev) 425 { 426 struct nfe_softc *sc = device_private(dev); 427 struct mii_data *mii = &sc->sc_mii; 428 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 429 430 phy = NFE_READ(sc, NFE_PHY_IFACE); 431 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 432 433 seed = NFE_READ(sc, NFE_RNDSEED); 434 seed &= ~NFE_SEED_MASK; 435 436 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 437 phy |= NFE_PHY_HDX; /* half-duplex */ 438 misc |= NFE_MISC1_HDX; 439 } 440 441 switch (IFM_SUBTYPE(mii->mii_media_active)) { 442 case IFM_1000_T: /* full-duplex only */ 443 link |= NFE_MEDIA_1000T; 444 seed |= NFE_SEED_1000T; 445 phy |= NFE_PHY_1000T; 446 break; 447 case IFM_100_TX: 448 link |= NFE_MEDIA_100TX; 449 seed |= NFE_SEED_100TX; 450 phy |= NFE_PHY_100TX; 451 break; 452 case IFM_10_T: 453 link |= NFE_MEDIA_10T; 454 seed |= NFE_SEED_10T; 455 break; 456 } 457 458 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 459 460 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 461 NFE_WRITE(sc, NFE_MISC1, misc); 462 NFE_WRITE(sc, NFE_LINKSPEED, link); 463 } 464 465 int 466 nfe_miibus_readreg(device_t dev, int phy, int reg) 467 { 468 struct nfe_softc *sc = device_private(dev); 469 uint32_t val; 470 int ntries; 471 472 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 473 474 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 475 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 476 DELAY(100); 477 } 478 479 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 480 481 for (ntries = 0; ntries < 1000; ntries++) { 482 DELAY(100); 483 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 484 break; 485 } 486 if (ntries == 1000) { 487 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 488 device_xname(sc->sc_dev))); 489 return 0; 490 } 491 492 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 493 DPRINTFN(2, ("%s: could not read PHY\n", 494 device_xname(sc->sc_dev))); 495 return 0; 496 } 497 498 val = NFE_READ(sc, NFE_PHY_DATA); 499 if (val != 0xffffffff && val != 0) 500 sc->mii_phyaddr = phy; 501 502 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 503 device_xname(sc->sc_dev), phy, reg, val)); 504 505 return val; 506 } 507 508 void 509 nfe_miibus_writereg(device_t dev, int phy, int reg, int val) 510 { 511 struct nfe_softc *sc = device_private(dev); 512 uint32_t ctl; 513 int ntries; 514 515 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 516 517 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 518 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 519 DELAY(100); 520 } 521 522 NFE_WRITE(sc, NFE_PHY_DATA, val); 523 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 524 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 525 526 for (ntries = 0; ntries < 1000; ntries++) { 527 DELAY(100); 528 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 529 break; 530 } 531 #ifdef NFE_DEBUG 532 if (nfedebug >= 2 && ntries == 1000) 533 printf("could not write to PHY\n"); 534 #endif 535 } 536 537 int 538 nfe_intr(void *arg) 539 { 540 struct nfe_softc *sc = arg; 541 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 542 uint32_t r; 543 int handled; 544 545 if ((ifp->if_flags & IFF_UP) == 0) 546 return 0; 547 548 handled = 0; 549 550 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 551 552 for (;;) { 553 r = NFE_READ(sc, NFE_IRQ_STATUS); 554 if ((r & NFE_IRQ_WANTED) == 0) 555 break; 556 557 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 558 handled = 1; 559 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 560 561 if ((r & (NFE_IRQ_RXERR|NFE_IRQ_RX_NOBUF|NFE_IRQ_RX)) != 0) { 562 /* check Rx ring */ 563 nfe_rxeof(sc); 564 } 565 if ((r & (NFE_IRQ_TXERR|NFE_IRQ_TXERR2|NFE_IRQ_TX_DONE)) != 0) { 566 /* check Tx ring */ 567 nfe_txeof(sc); 568 } 569 if ((r & NFE_IRQ_LINK) != 0) { 570 NFE_READ(sc, NFE_PHY_STATUS); 571 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 572 DPRINTF(("%s: link state changed\n", 573 device_xname(sc->sc_dev))); 574 } 575 } 576 577 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 578 579 if (handled && !IF_IS_EMPTY(&ifp->if_snd)) 580 nfe_start(ifp); 581 582 return handled; 583 } 584 585 int 586 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 587 { 588 struct nfe_softc *sc = ifp->if_softc; 589 struct ifreq *ifr = (struct ifreq *)data; 590 struct ifaddr *ifa = (struct ifaddr *)data; 591 int s, error = 0; 592 593 s = splnet(); 594 595 switch (cmd) { 596 case SIOCSIFADDR: 597 ifp->if_flags |= IFF_UP; 598 nfe_init(ifp); 599 switch (ifa->ifa_addr->sa_family) { 600 #ifdef INET 601 case AF_INET: 602 arp_ifinit(ifp, ifa); 603 break; 604 #endif 605 default: 606 break; 607 } 608 break; 609 case SIOCSIFMTU: 610 if (ifr->ifr_mtu < ETHERMIN || 611 ((sc->sc_flags & NFE_USE_JUMBO) && 612 ifr->ifr_mtu > ETHERMTU_JUMBO) || 613 (!(sc->sc_flags & NFE_USE_JUMBO) && 614 ifr->ifr_mtu > ETHERMTU)) 615 error = EINVAL; 616 else if ((error = ifioctl_common(ifp, cmd, data)) == ENETRESET) 617 error = 0; 618 break; 619 case SIOCSIFFLAGS: 620 if (ifp->if_flags & IFF_UP) { 621 /* 622 * If only the PROMISC or ALLMULTI flag changes, then 623 * don't do a full re-init of the chip, just update 624 * the Rx filter. 625 */ 626 if ((ifp->if_flags & IFF_RUNNING) && 627 ((ifp->if_flags ^ sc->sc_if_flags) & 628 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 629 nfe_setmulti(sc); 630 } else 631 nfe_init(ifp); 632 } else { 633 if (ifp->if_flags & IFF_RUNNING) 634 nfe_stop(ifp, 1); 635 } 636 sc->sc_if_flags = ifp->if_flags; 637 break; 638 default: 639 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 640 break; 641 642 error = 0; 643 644 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 645 ; 646 else if (ifp->if_flags & IFF_RUNNING) 647 nfe_setmulti(sc); 648 break; 649 } 650 651 splx(s); 652 653 return error; 654 } 655 656 void 657 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 658 { 659 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 660 (char *)desc32 - (char *)sc->txq.desc32, 661 sizeof (struct nfe_desc32), ops); 662 } 663 664 void 665 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 666 { 667 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 668 (char *)desc64 - (char *)sc->txq.desc64, 669 sizeof (struct nfe_desc64), ops); 670 } 671 672 void 673 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 674 { 675 if (end > start) { 676 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 677 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 678 (char *)&sc->txq.desc32[end] - 679 (char *)&sc->txq.desc32[start], ops); 680 return; 681 } 682 /* sync from 'start' to end of ring */ 683 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 684 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 685 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 686 (char *)&sc->txq.desc32[start], ops); 687 688 /* sync from start of ring to 'end' */ 689 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 690 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 691 } 692 693 void 694 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 695 { 696 if (end > start) { 697 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 698 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 699 (char *)&sc->txq.desc64[end] - 700 (char *)&sc->txq.desc64[start], ops); 701 return; 702 } 703 /* sync from 'start' to end of ring */ 704 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 705 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 706 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 707 (char *)&sc->txq.desc64[start], ops); 708 709 /* sync from start of ring to 'end' */ 710 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 711 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 712 } 713 714 void 715 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 716 { 717 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 718 (char *)desc32 - (char *)sc->rxq.desc32, 719 sizeof (struct nfe_desc32), ops); 720 } 721 722 void 723 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 724 { 725 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 726 (char *)desc64 - (char *)sc->rxq.desc64, 727 sizeof (struct nfe_desc64), ops); 728 } 729 730 void 731 nfe_rxeof(struct nfe_softc *sc) 732 { 733 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 734 struct nfe_desc32 *desc32; 735 struct nfe_desc64 *desc64; 736 struct nfe_rx_data *data; 737 struct nfe_jbuf *jbuf; 738 struct mbuf *m, *mnew; 739 bus_addr_t physaddr; 740 uint16_t flags; 741 int error, len, i; 742 743 desc32 = NULL; 744 desc64 = NULL; 745 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 746 data = &sc->rxq.data[i]; 747 748 if (sc->sc_flags & NFE_40BIT_ADDR) { 749 desc64 = &sc->rxq.desc64[i]; 750 nfe_rxdesc64_sync(sc, desc64, 751 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 752 753 flags = le16toh(desc64->flags); 754 len = le16toh(desc64->length) & 0x3fff; 755 } else { 756 desc32 = &sc->rxq.desc32[i]; 757 nfe_rxdesc32_sync(sc, desc32, 758 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 759 760 flags = le16toh(desc32->flags); 761 len = le16toh(desc32->length) & 0x3fff; 762 } 763 764 if ((flags & NFE_RX_READY) != 0) 765 break; 766 767 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 768 if ((flags & NFE_RX_VALID_V1) == 0) 769 goto skip; 770 771 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 772 flags &= ~NFE_RX_ERROR; 773 len--; /* fix buffer length */ 774 } 775 } else { 776 if ((flags & NFE_RX_VALID_V2) == 0) 777 goto skip; 778 779 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 780 flags &= ~NFE_RX_ERROR; 781 len--; /* fix buffer length */ 782 } 783 } 784 785 if (flags & NFE_RX_ERROR) { 786 ifp->if_ierrors++; 787 goto skip; 788 } 789 790 /* 791 * Try to allocate a new mbuf for this ring element and load 792 * it before processing the current mbuf. If the ring element 793 * cannot be loaded, drop the received packet and reuse the 794 * old mbuf. In the unlikely case that the old mbuf can't be 795 * reloaded either, explicitly panic. 796 */ 797 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 798 if (mnew == NULL) { 799 ifp->if_ierrors++; 800 goto skip; 801 } 802 803 if (sc->sc_flags & NFE_USE_JUMBO) { 804 physaddr = 805 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 806 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 807 if (len > MCLBYTES) { 808 m_freem(mnew); 809 ifp->if_ierrors++; 810 goto skip1; 811 } 812 MCLGET(mnew, M_DONTWAIT); 813 if ((mnew->m_flags & M_EXT) == 0) { 814 m_freem(mnew); 815 ifp->if_ierrors++; 816 goto skip1; 817 } 818 819 (void)memcpy(mtod(mnew, void *), 820 mtod(data->m, const void *), len); 821 m = mnew; 822 goto mbufcopied; 823 } else { 824 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 825 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 826 mtod(data->m, char *) - (char *)sc->rxq.jpool, 827 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 828 829 physaddr = jbuf->physaddr; 830 } 831 } else { 832 MCLGET(mnew, M_DONTWAIT); 833 if ((mnew->m_flags & M_EXT) == 0) { 834 m_freem(mnew); 835 ifp->if_ierrors++; 836 goto skip; 837 } 838 839 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 840 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 841 bus_dmamap_unload(sc->sc_dmat, data->map); 842 843 error = bus_dmamap_load(sc->sc_dmat, data->map, 844 mtod(mnew, void *), MCLBYTES, NULL, 845 BUS_DMA_READ | BUS_DMA_NOWAIT); 846 if (error != 0) { 847 m_freem(mnew); 848 849 /* try to reload the old mbuf */ 850 error = bus_dmamap_load(sc->sc_dmat, data->map, 851 mtod(data->m, void *), MCLBYTES, NULL, 852 BUS_DMA_READ | BUS_DMA_NOWAIT); 853 if (error != 0) { 854 /* very unlikely that it will fail.. */ 855 panic("%s: could not load old rx mbuf", 856 device_xname(sc->sc_dev)); 857 } 858 ifp->if_ierrors++; 859 goto skip; 860 } 861 physaddr = data->map->dm_segs[0].ds_addr; 862 } 863 864 /* 865 * New mbuf successfully loaded, update Rx ring and continue 866 * processing. 867 */ 868 m = data->m; 869 data->m = mnew; 870 871 mbufcopied: 872 /* finalize mbuf */ 873 m->m_pkthdr.len = m->m_len = len; 874 m->m_pkthdr.rcvif = ifp; 875 876 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 877 /* 878 * XXX 879 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 880 */ 881 if (flags & NFE_RX_IP_CSUMOK) { 882 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 883 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 884 device_xname(sc->sc_dev))); 885 } 886 /* 887 * XXX 888 * no way to check M_CSUM_TCP_UDP_BAD or 889 * other protocols? 890 */ 891 if (flags & NFE_RX_UDP_CSUMOK) { 892 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 893 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 894 device_xname(sc->sc_dev))); 895 } else if (flags & NFE_RX_TCP_CSUMOK) { 896 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 897 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 898 device_xname(sc->sc_dev))); 899 } 900 } 901 #if NBPFILTER > 0 902 if (ifp->if_bpf) 903 bpf_mtap(ifp->if_bpf, m); 904 #endif 905 ifp->if_ipackets++; 906 (*ifp->if_input)(ifp, m); 907 908 skip1: 909 /* update mapping address in h/w descriptor */ 910 if (sc->sc_flags & NFE_40BIT_ADDR) { 911 #if defined(__LP64__) 912 desc64->physaddr[0] = htole32(physaddr >> 32); 913 #endif 914 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 915 } else { 916 desc32->physaddr = htole32(physaddr); 917 } 918 919 skip: 920 if (sc->sc_flags & NFE_40BIT_ADDR) { 921 desc64->length = htole16(sc->rxq.bufsz); 922 desc64->flags = htole16(NFE_RX_READY); 923 924 nfe_rxdesc64_sync(sc, desc64, 925 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 926 } else { 927 desc32->length = htole16(sc->rxq.bufsz); 928 desc32->flags = htole16(NFE_RX_READY); 929 930 nfe_rxdesc32_sync(sc, desc32, 931 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 932 } 933 } 934 /* update current RX pointer */ 935 sc->rxq.cur = i; 936 } 937 938 void 939 nfe_txeof(struct nfe_softc *sc) 940 { 941 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 942 struct nfe_desc32 *desc32; 943 struct nfe_desc64 *desc64; 944 struct nfe_tx_data *data = NULL; 945 int i; 946 uint16_t flags; 947 char buf[128]; 948 949 for (i = sc->txq.next; 950 sc->txq.queued > 0; 951 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 952 if (sc->sc_flags & NFE_40BIT_ADDR) { 953 desc64 = &sc->txq.desc64[i]; 954 nfe_txdesc64_sync(sc, desc64, 955 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 956 957 flags = le16toh(desc64->flags); 958 } else { 959 desc32 = &sc->txq.desc32[i]; 960 nfe_txdesc32_sync(sc, desc32, 961 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 962 963 flags = le16toh(desc32->flags); 964 } 965 966 if ((flags & NFE_TX_VALID) != 0) 967 break; 968 969 data = &sc->txq.data[i]; 970 971 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 972 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 973 data->m == NULL) 974 continue; 975 976 if ((flags & NFE_TX_ERROR_V1) != 0) { 977 aprint_error_dev(sc->sc_dev, "tx v1 error %s\n", 978 bitmask_snprintf(flags, NFE_V1_TXERR, 979 buf, sizeof(buf))); 980 ifp->if_oerrors++; 981 } else 982 ifp->if_opackets++; 983 } else { 984 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 985 data->m == NULL) 986 continue; 987 988 if ((flags & NFE_TX_ERROR_V2) != 0) { 989 aprint_error_dev(sc->sc_dev, "tx v2 error %s\n", 990 bitmask_snprintf(flags, NFE_V2_TXERR, 991 buf, sizeof(buf))); 992 ifp->if_oerrors++; 993 } else 994 ifp->if_opackets++; 995 } 996 997 if (data->m == NULL) { /* should not get there */ 998 aprint_error_dev(sc->sc_dev, 999 "last fragment bit w/o associated mbuf!\n"); 1000 continue; 1001 } 1002 1003 /* last fragment of the mbuf chain transmitted */ 1004 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1005 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1006 bus_dmamap_unload(sc->sc_dmat, data->active); 1007 m_freem(data->m); 1008 data->m = NULL; 1009 } 1010 1011 sc->txq.next = i; 1012 1013 if (sc->txq.queued < NFE_TX_RING_COUNT) { 1014 /* at least one slot freed */ 1015 ifp->if_flags &= ~IFF_OACTIVE; 1016 } 1017 1018 if (sc->txq.queued == 0) { 1019 /* all queued packets are sent */ 1020 ifp->if_timer = 0; 1021 } 1022 } 1023 1024 int 1025 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 1026 { 1027 struct nfe_desc32 *desc32; 1028 struct nfe_desc64 *desc64; 1029 struct nfe_tx_data *data; 1030 bus_dmamap_t map; 1031 uint16_t flags, csumflags; 1032 #if NVLAN > 0 1033 struct m_tag *mtag; 1034 uint32_t vtag = 0; 1035 #endif 1036 int error, i, first; 1037 1038 desc32 = NULL; 1039 desc64 = NULL; 1040 data = NULL; 1041 1042 flags = 0; 1043 csumflags = 0; 1044 first = sc->txq.cur; 1045 1046 map = sc->txq.data[first].map; 1047 1048 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1049 if (error != 0) { 1050 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1051 error); 1052 return error; 1053 } 1054 1055 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1056 bus_dmamap_unload(sc->sc_dmat, map); 1057 return ENOBUFS; 1058 } 1059 1060 #if NVLAN > 0 1061 /* setup h/w VLAN tagging */ 1062 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1063 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1064 #endif 1065 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1066 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1067 csumflags |= NFE_TX_IP_CSUM; 1068 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1069 csumflags |= NFE_TX_TCP_UDP_CSUM; 1070 } 1071 1072 for (i = 0; i < map->dm_nsegs; i++) { 1073 data = &sc->txq.data[sc->txq.cur]; 1074 1075 if (sc->sc_flags & NFE_40BIT_ADDR) { 1076 desc64 = &sc->txq.desc64[sc->txq.cur]; 1077 #if defined(__LP64__) 1078 desc64->physaddr[0] = 1079 htole32(map->dm_segs[i].ds_addr >> 32); 1080 #endif 1081 desc64->physaddr[1] = 1082 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1083 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1084 desc64->flags = htole16(flags); 1085 desc64->vtag = 0; 1086 } else { 1087 desc32 = &sc->txq.desc32[sc->txq.cur]; 1088 1089 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1090 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1091 desc32->flags = htole16(flags); 1092 } 1093 1094 /* 1095 * Setting of the valid bit in the first descriptor is 1096 * deferred until the whole chain is fully setup. 1097 */ 1098 flags |= NFE_TX_VALID; 1099 1100 sc->txq.queued++; 1101 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1102 } 1103 1104 /* the whole mbuf chain has been setup */ 1105 if (sc->sc_flags & NFE_40BIT_ADDR) { 1106 /* fix last descriptor */ 1107 flags |= NFE_TX_LASTFRAG_V2; 1108 desc64->flags = htole16(flags); 1109 1110 /* Checksum flags and vtag belong to the first fragment only. */ 1111 #if NVLAN > 0 1112 sc->txq.desc64[first].vtag = htole32(vtag); 1113 #endif 1114 sc->txq.desc64[first].flags |= htole16(csumflags); 1115 1116 /* finally, set the valid bit in the first descriptor */ 1117 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1118 } else { 1119 /* fix last descriptor */ 1120 if (sc->sc_flags & NFE_JUMBO_SUP) 1121 flags |= NFE_TX_LASTFRAG_V2; 1122 else 1123 flags |= NFE_TX_LASTFRAG_V1; 1124 desc32->flags = htole16(flags); 1125 1126 /* Checksum flags belong to the first fragment only. */ 1127 sc->txq.desc32[first].flags |= htole16(csumflags); 1128 1129 /* finally, set the valid bit in the first descriptor */ 1130 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1131 } 1132 1133 data->m = m0; 1134 data->active = map; 1135 1136 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1137 BUS_DMASYNC_PREWRITE); 1138 1139 return 0; 1140 } 1141 1142 void 1143 nfe_start(struct ifnet *ifp) 1144 { 1145 struct nfe_softc *sc = ifp->if_softc; 1146 int old = sc->txq.queued; 1147 struct mbuf *m0; 1148 1149 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1150 return; 1151 1152 for (;;) { 1153 IFQ_POLL(&ifp->if_snd, m0); 1154 if (m0 == NULL) 1155 break; 1156 1157 if (nfe_encap(sc, m0) != 0) { 1158 ifp->if_flags |= IFF_OACTIVE; 1159 break; 1160 } 1161 1162 /* packet put in h/w queue, remove from s/w queue */ 1163 IFQ_DEQUEUE(&ifp->if_snd, m0); 1164 1165 #if NBPFILTER > 0 1166 if (ifp->if_bpf != NULL) 1167 bpf_mtap(ifp->if_bpf, m0); 1168 #endif 1169 } 1170 1171 if (sc->txq.queued != old) { 1172 /* packets are queued */ 1173 if (sc->sc_flags & NFE_40BIT_ADDR) 1174 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1175 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1176 else 1177 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1178 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1179 /* kick Tx */ 1180 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1181 1182 /* 1183 * Set a timeout in case the chip goes out to lunch. 1184 */ 1185 ifp->if_timer = 5; 1186 } 1187 } 1188 1189 void 1190 nfe_watchdog(struct ifnet *ifp) 1191 { 1192 struct nfe_softc *sc = ifp->if_softc; 1193 1194 aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1195 1196 ifp->if_flags &= ~IFF_RUNNING; 1197 nfe_init(ifp); 1198 1199 ifp->if_oerrors++; 1200 } 1201 1202 int 1203 nfe_init(struct ifnet *ifp) 1204 { 1205 struct nfe_softc *sc = ifp->if_softc; 1206 uint32_t tmp; 1207 int rc = 0, s; 1208 1209 if (ifp->if_flags & IFF_RUNNING) 1210 return 0; 1211 1212 nfe_stop(ifp, 0); 1213 1214 NFE_WRITE(sc, NFE_TX_UNK, 0); 1215 NFE_WRITE(sc, NFE_STATUS, 0); 1216 1217 sc->rxtxctl = NFE_RXTX_BIT2; 1218 if (sc->sc_flags & NFE_40BIT_ADDR) 1219 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1220 else if (sc->sc_flags & NFE_JUMBO_SUP) 1221 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1222 if (sc->sc_flags & NFE_HW_CSUM) 1223 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1224 #if NVLAN > 0 1225 /* 1226 * Although the adapter is capable of stripping VLAN tags from received 1227 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1228 * purpose. This will be done in software by our network stack. 1229 */ 1230 if (sc->sc_flags & NFE_HW_VLAN) 1231 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1232 #endif 1233 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1234 DELAY(10); 1235 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1236 1237 #if NVLAN 1238 if (sc->sc_flags & NFE_HW_VLAN) 1239 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1240 #endif 1241 1242 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1243 1244 /* set MAC address */ 1245 nfe_set_macaddr(sc, sc->sc_enaddr); 1246 1247 /* tell MAC where rings are in memory */ 1248 #ifdef __LP64__ 1249 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1250 #endif 1251 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1252 #ifdef __LP64__ 1253 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1254 #endif 1255 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1256 1257 NFE_WRITE(sc, NFE_RING_SIZE, 1258 (NFE_RX_RING_COUNT - 1) << 16 | 1259 (NFE_TX_RING_COUNT - 1)); 1260 1261 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1262 1263 /* force MAC to wakeup */ 1264 tmp = NFE_READ(sc, NFE_PWR_STATE); 1265 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1266 DELAY(10); 1267 tmp = NFE_READ(sc, NFE_PWR_STATE); 1268 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1269 1270 s = splnet(); 1271 nfe_intr(sc); /* XXX clear IRQ status registers */ 1272 splx(s); 1273 1274 #if 1 1275 /* configure interrupts coalescing/mitigation */ 1276 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1277 #else 1278 /* no interrupt mitigation: one interrupt per packet */ 1279 NFE_WRITE(sc, NFE_IMTIMER, 970); 1280 #endif 1281 1282 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1283 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1284 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1285 1286 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1287 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1288 1289 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1290 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_ENABLE); 1291 1292 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1293 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1294 DELAY(10); 1295 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1296 1297 /* set Rx filter */ 1298 nfe_setmulti(sc); 1299 1300 if ((rc = ether_mediachange(ifp)) != 0) 1301 goto out; 1302 1303 nfe_tick(sc); 1304 1305 /* enable Rx */ 1306 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1307 1308 /* enable Tx */ 1309 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1310 1311 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1312 1313 /* enable interrupts */ 1314 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1315 1316 callout_schedule(&sc->sc_tick_ch, hz); 1317 1318 ifp->if_flags |= IFF_RUNNING; 1319 ifp->if_flags &= ~IFF_OACTIVE; 1320 1321 out: 1322 return rc; 1323 } 1324 1325 void 1326 nfe_stop(struct ifnet *ifp, int disable) 1327 { 1328 struct nfe_softc *sc = ifp->if_softc; 1329 1330 callout_stop(&sc->sc_tick_ch); 1331 1332 ifp->if_timer = 0; 1333 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1334 1335 mii_down(&sc->sc_mii); 1336 1337 /* abort Tx */ 1338 NFE_WRITE(sc, NFE_TX_CTL, 0); 1339 1340 /* disable Rx */ 1341 NFE_WRITE(sc, NFE_RX_CTL, 0); 1342 1343 /* disable interrupts */ 1344 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1345 1346 /* reset Tx and Rx rings */ 1347 nfe_reset_tx_ring(sc, &sc->txq); 1348 nfe_reset_rx_ring(sc, &sc->rxq); 1349 } 1350 1351 int 1352 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1353 { 1354 struct nfe_desc32 *desc32; 1355 struct nfe_desc64 *desc64; 1356 struct nfe_rx_data *data; 1357 struct nfe_jbuf *jbuf; 1358 void **desc; 1359 bus_addr_t physaddr; 1360 int i, nsegs, error, descsize; 1361 1362 if (sc->sc_flags & NFE_40BIT_ADDR) { 1363 desc = (void **)&ring->desc64; 1364 descsize = sizeof (struct nfe_desc64); 1365 } else { 1366 desc = (void **)&ring->desc32; 1367 descsize = sizeof (struct nfe_desc32); 1368 } 1369 1370 ring->cur = ring->next = 0; 1371 ring->bufsz = MCLBYTES; 1372 1373 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1374 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1375 if (error != 0) { 1376 aprint_error_dev(sc->sc_dev, 1377 "could not create desc DMA map\n"); 1378 ring->map = NULL; 1379 goto fail; 1380 } 1381 1382 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1383 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1384 if (error != 0) { 1385 aprint_error_dev(sc->sc_dev, 1386 "could not allocate DMA memory\n"); 1387 goto fail; 1388 } 1389 1390 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1391 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1392 if (error != 0) { 1393 aprint_error_dev(sc->sc_dev, 1394 "could not map desc DMA memory\n"); 1395 goto fail; 1396 } 1397 1398 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1399 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1400 if (error != 0) { 1401 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1402 goto fail; 1403 } 1404 1405 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1406 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1407 1408 if (sc->sc_flags & NFE_USE_JUMBO) { 1409 ring->bufsz = NFE_JBYTES; 1410 if ((error = nfe_jpool_alloc(sc)) != 0) { 1411 aprint_error_dev(sc->sc_dev, 1412 "could not allocate jumbo frames\n"); 1413 goto fail; 1414 } 1415 } 1416 1417 /* 1418 * Pre-allocate Rx buffers and populate Rx ring. 1419 */ 1420 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1421 data = &sc->rxq.data[i]; 1422 1423 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1424 if (data->m == NULL) { 1425 aprint_error_dev(sc->sc_dev, 1426 "could not allocate rx mbuf\n"); 1427 error = ENOMEM; 1428 goto fail; 1429 } 1430 1431 if (sc->sc_flags & NFE_USE_JUMBO) { 1432 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1433 aprint_error_dev(sc->sc_dev, 1434 "could not allocate jumbo buffer\n"); 1435 goto fail; 1436 } 1437 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1438 sc); 1439 1440 physaddr = jbuf->physaddr; 1441 } else { 1442 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1443 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1444 if (error != 0) { 1445 aprint_error_dev(sc->sc_dev, 1446 "could not create DMA map\n"); 1447 data->map = NULL; 1448 goto fail; 1449 } 1450 MCLGET(data->m, M_DONTWAIT); 1451 if (!(data->m->m_flags & M_EXT)) { 1452 aprint_error_dev(sc->sc_dev, 1453 "could not allocate mbuf cluster\n"); 1454 error = ENOMEM; 1455 goto fail; 1456 } 1457 1458 error = bus_dmamap_load(sc->sc_dmat, data->map, 1459 mtod(data->m, void *), MCLBYTES, NULL, 1460 BUS_DMA_READ | BUS_DMA_NOWAIT); 1461 if (error != 0) { 1462 aprint_error_dev(sc->sc_dev, 1463 "could not load rx buf DMA map"); 1464 goto fail; 1465 } 1466 physaddr = data->map->dm_segs[0].ds_addr; 1467 } 1468 1469 if (sc->sc_flags & NFE_40BIT_ADDR) { 1470 desc64 = &sc->rxq.desc64[i]; 1471 #if defined(__LP64__) 1472 desc64->physaddr[0] = htole32(physaddr >> 32); 1473 #endif 1474 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1475 desc64->length = htole16(sc->rxq.bufsz); 1476 desc64->flags = htole16(NFE_RX_READY); 1477 } else { 1478 desc32 = &sc->rxq.desc32[i]; 1479 desc32->physaddr = htole32(physaddr); 1480 desc32->length = htole16(sc->rxq.bufsz); 1481 desc32->flags = htole16(NFE_RX_READY); 1482 } 1483 } 1484 1485 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1486 BUS_DMASYNC_PREWRITE); 1487 1488 return 0; 1489 1490 fail: nfe_free_rx_ring(sc, ring); 1491 return error; 1492 } 1493 1494 void 1495 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1496 { 1497 int i; 1498 1499 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1500 if (sc->sc_flags & NFE_40BIT_ADDR) { 1501 ring->desc64[i].length = htole16(ring->bufsz); 1502 ring->desc64[i].flags = htole16(NFE_RX_READY); 1503 } else { 1504 ring->desc32[i].length = htole16(ring->bufsz); 1505 ring->desc32[i].flags = htole16(NFE_RX_READY); 1506 } 1507 } 1508 1509 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1510 BUS_DMASYNC_PREWRITE); 1511 1512 ring->cur = ring->next = 0; 1513 } 1514 1515 void 1516 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1517 { 1518 struct nfe_rx_data *data; 1519 void *desc; 1520 int i, descsize; 1521 1522 if (sc->sc_flags & NFE_40BIT_ADDR) { 1523 desc = ring->desc64; 1524 descsize = sizeof (struct nfe_desc64); 1525 } else { 1526 desc = ring->desc32; 1527 descsize = sizeof (struct nfe_desc32); 1528 } 1529 1530 if (desc != NULL) { 1531 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1532 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1533 bus_dmamap_unload(sc->sc_dmat, ring->map); 1534 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1535 NFE_RX_RING_COUNT * descsize); 1536 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1537 } 1538 1539 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1540 data = &ring->data[i]; 1541 1542 if (data->map != NULL) { 1543 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1544 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1545 bus_dmamap_unload(sc->sc_dmat, data->map); 1546 bus_dmamap_destroy(sc->sc_dmat, data->map); 1547 } 1548 if (data->m != NULL) 1549 m_freem(data->m); 1550 } 1551 } 1552 1553 struct nfe_jbuf * 1554 nfe_jalloc(struct nfe_softc *sc, int i) 1555 { 1556 struct nfe_jbuf *jbuf; 1557 1558 mutex_enter(&sc->rxq.mtx); 1559 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1560 if (jbuf != NULL) 1561 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1562 mutex_exit(&sc->rxq.mtx); 1563 if (jbuf == NULL) 1564 return NULL; 1565 sc->rxq.jbufmap[i] = 1566 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1567 return jbuf; 1568 } 1569 1570 /* 1571 * This is called automatically by the network stack when the mbuf is freed. 1572 * Caution must be taken that the NIC might be reset by the time the mbuf is 1573 * freed. 1574 */ 1575 void 1576 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1577 { 1578 struct nfe_softc *sc = arg; 1579 struct nfe_jbuf *jbuf; 1580 int i; 1581 1582 /* find the jbuf from the base pointer */ 1583 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1584 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1585 aprint_error_dev(sc->sc_dev, 1586 "request to free a buffer (%p) not managed by us\n", buf); 1587 return; 1588 } 1589 jbuf = &sc->rxq.jbuf[i]; 1590 1591 /* ..and put it back in the free list */ 1592 mutex_enter(&sc->rxq.mtx); 1593 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1594 mutex_exit(&sc->rxq.mtx); 1595 1596 if (m != NULL) 1597 pool_cache_put(mb_cache, m); 1598 } 1599 1600 int 1601 nfe_jpool_alloc(struct nfe_softc *sc) 1602 { 1603 struct nfe_rx_ring *ring = &sc->rxq; 1604 struct nfe_jbuf *jbuf; 1605 bus_addr_t physaddr; 1606 char *buf; 1607 int i, nsegs, error; 1608 1609 /* 1610 * Allocate a big chunk of DMA'able memory. 1611 */ 1612 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1613 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1614 if (error != 0) { 1615 aprint_error_dev(sc->sc_dev, 1616 "could not create jumbo DMA map\n"); 1617 ring->jmap = NULL; 1618 goto fail; 1619 } 1620 1621 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1622 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1623 if (error != 0) { 1624 aprint_error_dev(sc->sc_dev, 1625 "could not allocate jumbo DMA memory\n"); 1626 goto fail; 1627 } 1628 1629 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1630 &ring->jpool, BUS_DMA_NOWAIT); 1631 if (error != 0) { 1632 aprint_error_dev(sc->sc_dev, 1633 "could not map jumbo DMA memory\n"); 1634 goto fail; 1635 } 1636 1637 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1638 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1639 if (error != 0) { 1640 aprint_error_dev(sc->sc_dev, 1641 "could not load jumbo DMA map\n"); 1642 goto fail; 1643 } 1644 1645 /* ..and split it into 9KB chunks */ 1646 SLIST_INIT(&ring->jfreelist); 1647 1648 buf = ring->jpool; 1649 physaddr = ring->jmap->dm_segs[0].ds_addr; 1650 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1651 jbuf = &ring->jbuf[i]; 1652 1653 jbuf->buf = buf; 1654 jbuf->physaddr = physaddr; 1655 1656 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1657 1658 buf += NFE_JBYTES; 1659 physaddr += NFE_JBYTES; 1660 } 1661 1662 return 0; 1663 1664 fail: nfe_jpool_free(sc); 1665 return error; 1666 } 1667 1668 void 1669 nfe_jpool_free(struct nfe_softc *sc) 1670 { 1671 struct nfe_rx_ring *ring = &sc->rxq; 1672 1673 if (ring->jmap != NULL) { 1674 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1675 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1676 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1677 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1678 } 1679 if (ring->jpool != NULL) { 1680 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1681 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1682 } 1683 } 1684 1685 int 1686 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1687 { 1688 int i, nsegs, error; 1689 void **desc; 1690 int descsize; 1691 1692 if (sc->sc_flags & NFE_40BIT_ADDR) { 1693 desc = (void **)&ring->desc64; 1694 descsize = sizeof (struct nfe_desc64); 1695 } else { 1696 desc = (void **)&ring->desc32; 1697 descsize = sizeof (struct nfe_desc32); 1698 } 1699 1700 ring->queued = 0; 1701 ring->cur = ring->next = 0; 1702 1703 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1704 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1705 1706 if (error != 0) { 1707 aprint_error_dev(sc->sc_dev, 1708 "could not create desc DMA map\n"); 1709 ring->map = NULL; 1710 goto fail; 1711 } 1712 1713 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1714 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1715 if (error != 0) { 1716 aprint_error_dev(sc->sc_dev, 1717 "could not allocate DMA memory\n"); 1718 goto fail; 1719 } 1720 1721 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1722 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1723 if (error != 0) { 1724 aprint_error_dev(sc->sc_dev, 1725 "could not map desc DMA memory\n"); 1726 goto fail; 1727 } 1728 1729 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1730 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1731 if (error != 0) { 1732 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1733 goto fail; 1734 } 1735 1736 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1737 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1738 1739 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1740 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1741 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1742 &ring->data[i].map); 1743 if (error != 0) { 1744 aprint_error_dev(sc->sc_dev, 1745 "could not create DMA map\n"); 1746 ring->data[i].map = NULL; 1747 goto fail; 1748 } 1749 } 1750 1751 return 0; 1752 1753 fail: nfe_free_tx_ring(sc, ring); 1754 return error; 1755 } 1756 1757 void 1758 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1759 { 1760 struct nfe_tx_data *data; 1761 int i; 1762 1763 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1764 if (sc->sc_flags & NFE_40BIT_ADDR) 1765 ring->desc64[i].flags = 0; 1766 else 1767 ring->desc32[i].flags = 0; 1768 1769 data = &ring->data[i]; 1770 1771 if (data->m != NULL) { 1772 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1773 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1774 bus_dmamap_unload(sc->sc_dmat, data->active); 1775 m_freem(data->m); 1776 data->m = NULL; 1777 } 1778 } 1779 1780 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1781 BUS_DMASYNC_PREWRITE); 1782 1783 ring->queued = 0; 1784 ring->cur = ring->next = 0; 1785 } 1786 1787 void 1788 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1789 { 1790 struct nfe_tx_data *data; 1791 void *desc; 1792 int i, descsize; 1793 1794 if (sc->sc_flags & NFE_40BIT_ADDR) { 1795 desc = ring->desc64; 1796 descsize = sizeof (struct nfe_desc64); 1797 } else { 1798 desc = ring->desc32; 1799 descsize = sizeof (struct nfe_desc32); 1800 } 1801 1802 if (desc != NULL) { 1803 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1804 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1805 bus_dmamap_unload(sc->sc_dmat, ring->map); 1806 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1807 NFE_TX_RING_COUNT * descsize); 1808 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1809 } 1810 1811 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1812 data = &ring->data[i]; 1813 1814 if (data->m != NULL) { 1815 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1816 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1817 bus_dmamap_unload(sc->sc_dmat, data->active); 1818 m_freem(data->m); 1819 } 1820 } 1821 1822 /* ..and now actually destroy the DMA mappings */ 1823 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1824 data = &ring->data[i]; 1825 if (data->map == NULL) 1826 continue; 1827 bus_dmamap_destroy(sc->sc_dmat, data->map); 1828 } 1829 } 1830 1831 void 1832 nfe_setmulti(struct nfe_softc *sc) 1833 { 1834 struct ethercom *ec = &sc->sc_ethercom; 1835 struct ifnet *ifp = &ec->ec_if; 1836 struct ether_multi *enm; 1837 struct ether_multistep step; 1838 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1839 uint32_t filter = NFE_RXFILTER_MAGIC; 1840 int i; 1841 1842 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1843 bzero(addr, ETHER_ADDR_LEN); 1844 bzero(mask, ETHER_ADDR_LEN); 1845 goto done; 1846 } 1847 1848 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1849 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1850 1851 ETHER_FIRST_MULTI(step, ec, enm); 1852 while (enm != NULL) { 1853 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1854 ifp->if_flags |= IFF_ALLMULTI; 1855 bzero(addr, ETHER_ADDR_LEN); 1856 bzero(mask, ETHER_ADDR_LEN); 1857 goto done; 1858 } 1859 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1860 addr[i] &= enm->enm_addrlo[i]; 1861 mask[i] &= ~enm->enm_addrlo[i]; 1862 } 1863 ETHER_NEXT_MULTI(step, enm); 1864 } 1865 for (i = 0; i < ETHER_ADDR_LEN; i++) 1866 mask[i] |= addr[i]; 1867 1868 done: 1869 addr[0] |= 0x01; /* make sure multicast bit is set */ 1870 1871 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1872 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1873 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1874 addr[5] << 8 | addr[4]); 1875 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1876 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1877 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1878 mask[5] << 8 | mask[4]); 1879 1880 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1881 NFE_WRITE(sc, NFE_RXFILTER, filter); 1882 } 1883 1884 void 1885 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1886 { 1887 uint32_t tmp; 1888 1889 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 1890 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1891 addr[0] = (tmp & 0xff); 1892 addr[1] = (tmp >> 8) & 0xff; 1893 addr[2] = (tmp >> 16) & 0xff; 1894 addr[3] = (tmp >> 24) & 0xff; 1895 1896 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1897 addr[4] = (tmp & 0xff); 1898 addr[5] = (tmp >> 8) & 0xff; 1899 1900 } else { 1901 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1902 addr[0] = (tmp >> 8) & 0xff; 1903 addr[1] = (tmp & 0xff); 1904 1905 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1906 addr[2] = (tmp >> 24) & 0xff; 1907 addr[3] = (tmp >> 16) & 0xff; 1908 addr[4] = (tmp >> 8) & 0xff; 1909 addr[5] = (tmp & 0xff); 1910 } 1911 } 1912 1913 void 1914 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1915 { 1916 NFE_WRITE(sc, NFE_MACADDR_LO, 1917 addr[5] << 8 | addr[4]); 1918 NFE_WRITE(sc, NFE_MACADDR_HI, 1919 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1920 } 1921 1922 void 1923 nfe_tick(void *arg) 1924 { 1925 struct nfe_softc *sc = arg; 1926 int s; 1927 1928 s = splnet(); 1929 mii_tick(&sc->sc_mii); 1930 splx(s); 1931 1932 callout_schedule(&sc->sc_tick_ch, hz); 1933 } 1934 1935 void 1936 nfe_poweron(device_t self) 1937 { 1938 struct nfe_softc *sc = device_private(self); 1939 1940 if ((sc->sc_flags & NFE_PWR_MGMT) != 0) { 1941 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 1942 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 1943 DELAY(100); 1944 NFE_WRITE(sc, NFE_MAC_RESET, 0); 1945 DELAY(100); 1946 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 1947 NFE_WRITE(sc, NFE_PWR2_CTL, 1948 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_WAKEUP_MASK); 1949 } 1950 } 1951 1952 bool 1953 nfe_resume(device_t dv PMF_FN_ARGS) 1954 { 1955 nfe_poweron(dv); 1956 1957 return true; 1958 } 1959
Indexes created Tue Oct 14 00:09:49 GMT 2025