if_nfe.c revision 1.39
1 /* $NetBSD: if_nfe.c,v 1.39 2009/01/18 11:21:06 cegger Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.77 2008/02/05 16:52:50 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006, 2007 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.39 2009/01/18 11:21:06 cegger Exp $"); 25 26 #include "opt_inet.h" 27 #include "bpfilter.h" 28 #include "vlan.h" 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/types.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/mutex.h> 37 #include <sys/queue.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/callout.h> 41 #include <sys/socket.h> 42 43 #include <sys/bus.h> 44 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 #include <net/if_ether.h> 49 #include <net/if_arp.h> 50 51 #ifdef INET 52 #include <netinet/in.h> 53 #include <netinet/in_systm.h> 54 #include <netinet/in_var.h> 55 #include <netinet/ip.h> 56 #include <netinet/if_inarp.h> 57 #endif 58 59 #if NVLAN > 0 60 #include <net/if_types.h> 61 #endif 62 63 #if NBPFILTER > 0 64 #include <net/bpf.h> 65 #endif 66 67 #include <dev/mii/mii.h> 68 #include <dev/mii/miivar.h> 69 70 #include <dev/pci/pcireg.h> 71 #include <dev/pci/pcivar.h> 72 #include <dev/pci/pcidevs.h> 73 74 #include <dev/pci/if_nfereg.h> 75 #include <dev/pci/if_nfevar.h> 76 77 static int nfe_ifflags_cb(struct ethercom *); 78 79 int nfe_match(device_t, cfdata_t, void *); 80 void nfe_attach(device_t, device_t, void *); 81 void nfe_power(int, void *); 82 void nfe_miibus_statchg(device_t); 83 int nfe_miibus_readreg(device_t, int, int); 84 void nfe_miibus_writereg(device_t, int, int, int); 85 int nfe_intr(void *); 86 int nfe_ioctl(struct ifnet *, u_long, void *); 87 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 88 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 89 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 90 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 91 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 92 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 93 void nfe_rxeof(struct nfe_softc *); 94 void nfe_txeof(struct nfe_softc *); 95 int nfe_encap(struct nfe_softc *, struct mbuf *); 96 void nfe_start(struct ifnet *); 97 void nfe_watchdog(struct ifnet *); 98 int nfe_init(struct ifnet *); 99 void nfe_stop(struct ifnet *, int); 100 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 101 void nfe_jfree(struct mbuf *, void *, size_t, void *); 102 int nfe_jpool_alloc(struct nfe_softc *); 103 void nfe_jpool_free(struct nfe_softc *); 104 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 105 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 106 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 107 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 108 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 109 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 110 void nfe_setmulti(struct nfe_softc *); 111 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 112 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 113 void nfe_tick(void *); 114 void nfe_poweron(device_t); 115 bool nfe_resume(device_t PMF_FN_PROTO); 116 117 CFATTACH_DECL_NEW(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, 118 NULL, NULL); 119 120 /* #define NFE_NO_JUMBO */ 121 122 #ifdef NFE_DEBUG 123 int nfedebug = 0; 124 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 125 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 126 #else 127 #define DPRINTF(x) 128 #define DPRINTFN(n,x) 129 #endif 130 131 /* deal with naming differences */ 132 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 134 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 135 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 136 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 137 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 138 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 139 140 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 141 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 142 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 143 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 144 145 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 146 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 147 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 148 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 149 150 #ifdef _LP64 151 #define __LP64__ 1 152 #endif 153 154 const struct nfe_product { 155 pci_vendor_id_t vendor; 156 pci_product_id_t product; 157 } nfe_devices[] = { 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 183 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 184 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 185 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 186 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 187 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 188 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 }, 189 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1 }, 190 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2 }, 191 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3 }, 192 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4 }, 193 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1 }, 194 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2 }, 195 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3 }, 196 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4 } 197 }; 198 199 int 200 nfe_match(device_t dev, cfdata_t match, void *aux) 201 { 202 struct pci_attach_args *pa = aux; 203 const struct nfe_product *np; 204 int i; 205 206 for (i = 0; i < sizeof(nfe_devices) / sizeof(nfe_devices[0]); i++) { 207 np = &nfe_devices[i]; 208 if (PCI_VENDOR(pa->pa_id) == np->vendor && 209 PCI_PRODUCT(pa->pa_id) == np->product) 210 return 1; 211 } 212 return 0; 213 } 214 215 void 216 nfe_attach(device_t parent, device_t self, void *aux) 217 { 218 struct nfe_softc *sc = device_private(self); 219 struct pci_attach_args *pa = aux; 220 pci_chipset_tag_t pc = pa->pa_pc; 221 pci_intr_handle_t ih; 222 const char *intrstr; 223 struct ifnet *ifp; 224 bus_size_t memsize; 225 pcireg_t memtype; 226 char devinfo[256]; 227 228 sc->sc_dev = self; 229 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 230 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 231 232 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 233 switch (memtype) { 234 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 235 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 236 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 237 &sc->sc_memh, NULL, &memsize) == 0) 238 break; 239 /* FALLTHROUGH */ 240 default: 241 aprint_error_dev(self, "could not map mem space\n"); 242 return; 243 } 244 245 if (pci_intr_map(pa, &ih) != 0) { 246 aprint_error_dev(self, "could not map interrupt\n"); 247 return; 248 } 249 250 intrstr = pci_intr_string(pc, ih); 251 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 252 if (sc->sc_ih == NULL) { 253 aprint_error_dev(self, "could not establish interrupt"); 254 if (intrstr != NULL) 255 aprint_normal(" at %s", intrstr); 256 aprint_normal("\n"); 257 return; 258 } 259 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 260 261 sc->sc_dmat = pa->pa_dmat; 262 263 sc->sc_flags = 0; 264 265 switch (PCI_PRODUCT(pa->pa_id)) { 266 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 267 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 268 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 269 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 270 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 271 break; 272 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 273 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 274 sc->sc_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT; 275 break; 276 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 277 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 278 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 279 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 280 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 281 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 282 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 283 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 284 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 285 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 286 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 287 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 288 sc->sc_flags |= NFE_40BIT_ADDR | NFE_CORRECT_MACADDR | 289 NFE_PWR_MGMT; 290 break; 291 case PCI_PRODUCT_NVIDIA_MCP77_LAN1: 292 case PCI_PRODUCT_NVIDIA_MCP77_LAN2: 293 case PCI_PRODUCT_NVIDIA_MCP77_LAN3: 294 case PCI_PRODUCT_NVIDIA_MCP77_LAN4: 295 case PCI_PRODUCT_NVIDIA_MCP79_LAN1: 296 case PCI_PRODUCT_NVIDIA_MCP79_LAN2: 297 case PCI_PRODUCT_NVIDIA_MCP79_LAN3: 298 case PCI_PRODUCT_NVIDIA_MCP79_LAN4: 299 sc->sc_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | 300 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 301 break; 302 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 303 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 304 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 305 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 306 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 307 break; 308 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 309 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 310 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 311 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 312 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 313 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 314 break; 315 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 316 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 317 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 318 NFE_HW_VLAN | NFE_PWR_MGMT; 319 break; 320 } 321 322 nfe_poweron(self); 323 324 #ifndef NFE_NO_JUMBO 325 /* enable jumbo frames for adapters that support it */ 326 if (sc->sc_flags & NFE_JUMBO_SUP) 327 sc->sc_flags |= NFE_USE_JUMBO; 328 #endif 329 330 /* Check for reversed ethernet address */ 331 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 332 sc->sc_flags |= NFE_CORRECT_MACADDR; 333 334 nfe_get_macaddr(sc, sc->sc_enaddr); 335 aprint_normal_dev(self, "Ethernet address %s\n", 336 ether_sprintf(sc->sc_enaddr)); 337 338 /* 339 * Allocate Tx and Rx rings. 340 */ 341 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 342 aprint_error_dev(self, "could not allocate Tx ring\n"); 343 return; 344 } 345 346 mutex_init(&sc->rxq.mtx, MUTEX_DEFAULT, IPL_NET); 347 348 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 349 aprint_error_dev(self, "could not allocate Rx ring\n"); 350 nfe_free_tx_ring(sc, &sc->txq); 351 return; 352 } 353 354 ifp = &sc->sc_ethercom.ec_if; 355 ifp->if_softc = sc; 356 ifp->if_mtu = ETHERMTU; 357 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 358 ifp->if_ioctl = nfe_ioctl; 359 ifp->if_start = nfe_start; 360 ifp->if_stop = nfe_stop; 361 ifp->if_watchdog = nfe_watchdog; 362 ifp->if_init = nfe_init; 363 ifp->if_baudrate = IF_Gbps(1); 364 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 365 IFQ_SET_READY(&ifp->if_snd); 366 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 367 368 if (sc->sc_flags & NFE_USE_JUMBO) 369 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 370 371 #if NVLAN > 0 372 if (sc->sc_flags & NFE_HW_VLAN) 373 sc->sc_ethercom.ec_capabilities |= 374 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 375 #endif 376 if (sc->sc_flags & NFE_HW_CSUM) { 377 ifp->if_capabilities |= 378 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 379 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 380 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 381 } 382 383 sc->sc_mii.mii_ifp = ifp; 384 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 385 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 386 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 387 388 sc->sc_ethercom.ec_mii = &sc->sc_mii; 389 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 390 ether_mediastatus); 391 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 392 MII_OFFSET_ANY, 0); 393 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 394 aprint_error_dev(self, "no PHY found!\n"); 395 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 396 0, NULL); 397 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 398 } else 399 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 400 401 if_attach(ifp); 402 ether_ifattach(ifp, sc->sc_enaddr); 403 ether_set_ifflags_cb(&sc->sc_ethercom, nfe_ifflags_cb); 404 405 callout_init(&sc->sc_tick_ch, 0); 406 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 407 408 if (!pmf_device_register(self, NULL, nfe_resume)) 409 aprint_error_dev(self, "couldn't establish power handler\n"); 410 else 411 pmf_class_network_register(self, ifp); 412 } 413 414 void 415 nfe_miibus_statchg(device_t dev) 416 { 417 struct nfe_softc *sc = device_private(dev); 418 struct mii_data *mii = &sc->sc_mii; 419 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 420 421 phy = NFE_READ(sc, NFE_PHY_IFACE); 422 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 423 424 seed = NFE_READ(sc, NFE_RNDSEED); 425 seed &= ~NFE_SEED_MASK; 426 427 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 428 phy |= NFE_PHY_HDX; /* half-duplex */ 429 misc |= NFE_MISC1_HDX; 430 } 431 432 switch (IFM_SUBTYPE(mii->mii_media_active)) { 433 case IFM_1000_T: /* full-duplex only */ 434 link |= NFE_MEDIA_1000T; 435 seed |= NFE_SEED_1000T; 436 phy |= NFE_PHY_1000T; 437 break; 438 case IFM_100_TX: 439 link |= NFE_MEDIA_100TX; 440 seed |= NFE_SEED_100TX; 441 phy |= NFE_PHY_100TX; 442 break; 443 case IFM_10_T: 444 link |= NFE_MEDIA_10T; 445 seed |= NFE_SEED_10T; 446 break; 447 } 448 449 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 450 451 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 452 NFE_WRITE(sc, NFE_MISC1, misc); 453 NFE_WRITE(sc, NFE_LINKSPEED, link); 454 } 455 456 int 457 nfe_miibus_readreg(device_t dev, int phy, int reg) 458 { 459 struct nfe_softc *sc = device_private(dev); 460 uint32_t val; 461 int ntries; 462 463 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 464 465 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 466 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 467 DELAY(100); 468 } 469 470 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 471 472 for (ntries = 0; ntries < 1000; ntries++) { 473 DELAY(100); 474 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 475 break; 476 } 477 if (ntries == 1000) { 478 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 479 device_xname(sc->sc_dev))); 480 return 0; 481 } 482 483 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 484 DPRINTFN(2, ("%s: could not read PHY\n", 485 device_xname(sc->sc_dev))); 486 return 0; 487 } 488 489 val = NFE_READ(sc, NFE_PHY_DATA); 490 if (val != 0xffffffff && val != 0) 491 sc->mii_phyaddr = phy; 492 493 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 494 device_xname(sc->sc_dev), phy, reg, val)); 495 496 return val; 497 } 498 499 void 500 nfe_miibus_writereg(device_t dev, int phy, int reg, int val) 501 { 502 struct nfe_softc *sc = device_private(dev); 503 uint32_t ctl; 504 int ntries; 505 506 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 507 508 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 509 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 510 DELAY(100); 511 } 512 513 NFE_WRITE(sc, NFE_PHY_DATA, val); 514 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 515 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 516 517 for (ntries = 0; ntries < 1000; ntries++) { 518 DELAY(100); 519 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 520 break; 521 } 522 #ifdef NFE_DEBUG 523 if (nfedebug >= 2 && ntries == 1000) 524 printf("could not write to PHY\n"); 525 #endif 526 } 527 528 int 529 nfe_intr(void *arg) 530 { 531 struct nfe_softc *sc = arg; 532 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 533 uint32_t r; 534 int handled; 535 536 if ((ifp->if_flags & IFF_UP) == 0) 537 return 0; 538 539 handled = 0; 540 541 for (;;) { 542 r = NFE_READ(sc, NFE_IRQ_STATUS); 543 if ((r & NFE_IRQ_WANTED) == 0) 544 break; 545 546 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 547 handled = 1; 548 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 549 550 if ((r & (NFE_IRQ_RXERR|NFE_IRQ_RX_NOBUF|NFE_IRQ_RX)) != 0) { 551 /* check Rx ring */ 552 nfe_rxeof(sc); 553 } 554 if ((r & (NFE_IRQ_TXERR|NFE_IRQ_TXERR2|NFE_IRQ_TX_DONE)) != 0) { 555 /* check Tx ring */ 556 nfe_txeof(sc); 557 } 558 if ((r & NFE_IRQ_LINK) != 0) { 559 NFE_READ(sc, NFE_PHY_STATUS); 560 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 561 DPRINTF(("%s: link state changed\n", 562 device_xname(sc->sc_dev))); 563 } 564 } 565 566 if (handled && !IF_IS_EMPTY(&ifp->if_snd)) 567 nfe_start(ifp); 568 569 return handled; 570 } 571 572 static int 573 nfe_ifflags_cb(struct ethercom *ec) 574 { 575 struct ifnet *ifp = &ec->ec_if; 576 struct nfe_softc *sc = ifp->if_softc; 577 int change = ifp->if_flags ^ sc->sc_if_flags; 578 579 /* 580 * If only the PROMISC flag changes, then 581 * don't do a full re-init of the chip, just update 582 * the Rx filter. 583 */ 584 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 585 return ENETRESET; 586 else if ((change & IFF_PROMISC) != 0) 587 nfe_setmulti(sc); 588 589 return 0; 590 } 591 592 int 593 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 594 { 595 struct nfe_softc *sc = ifp->if_softc; 596 struct ifaddr *ifa = (struct ifaddr *)data; 597 int s, error = 0; 598 599 s = splnet(); 600 601 switch (cmd) { 602 case SIOCINITIFADDR: 603 ifp->if_flags |= IFF_UP; 604 nfe_init(ifp); 605 switch (ifa->ifa_addr->sa_family) { 606 #ifdef INET 607 case AF_INET: 608 arp_ifinit(ifp, ifa); 609 break; 610 #endif 611 default: 612 break; 613 } 614 break; 615 default: 616 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 617 break; 618 619 error = 0; 620 621 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 622 ; 623 else if (ifp->if_flags & IFF_RUNNING) 624 nfe_setmulti(sc); 625 break; 626 } 627 sc->sc_if_flags = ifp->if_flags; 628 629 splx(s); 630 631 return error; 632 } 633 634 void 635 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 636 { 637 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 638 (char *)desc32 - (char *)sc->txq.desc32, 639 sizeof (struct nfe_desc32), ops); 640 } 641 642 void 643 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 644 { 645 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 646 (char *)desc64 - (char *)sc->txq.desc64, 647 sizeof (struct nfe_desc64), ops); 648 } 649 650 void 651 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 652 { 653 if (end > start) { 654 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 655 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 656 (char *)&sc->txq.desc32[end] - 657 (char *)&sc->txq.desc32[start], ops); 658 return; 659 } 660 /* sync from 'start' to end of ring */ 661 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 662 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 663 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 664 (char *)&sc->txq.desc32[start], ops); 665 666 /* sync from start of ring to 'end' */ 667 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 668 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 669 } 670 671 void 672 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 673 { 674 if (end > start) { 675 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 676 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 677 (char *)&sc->txq.desc64[end] - 678 (char *)&sc->txq.desc64[start], ops); 679 return; 680 } 681 /* sync from 'start' to end of ring */ 682 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 683 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 684 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 685 (char *)&sc->txq.desc64[start], ops); 686 687 /* sync from start of ring to 'end' */ 688 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 689 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 690 } 691 692 void 693 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 694 { 695 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 696 (char *)desc32 - (char *)sc->rxq.desc32, 697 sizeof (struct nfe_desc32), ops); 698 } 699 700 void 701 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 702 { 703 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 704 (char *)desc64 - (char *)sc->rxq.desc64, 705 sizeof (struct nfe_desc64), ops); 706 } 707 708 void 709 nfe_rxeof(struct nfe_softc *sc) 710 { 711 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 712 struct nfe_desc32 *desc32; 713 struct nfe_desc64 *desc64; 714 struct nfe_rx_data *data; 715 struct nfe_jbuf *jbuf; 716 struct mbuf *m, *mnew; 717 bus_addr_t physaddr; 718 uint16_t flags; 719 int error, len, i; 720 721 desc32 = NULL; 722 desc64 = NULL; 723 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 724 data = &sc->rxq.data[i]; 725 726 if (sc->sc_flags & NFE_40BIT_ADDR) { 727 desc64 = &sc->rxq.desc64[i]; 728 nfe_rxdesc64_sync(sc, desc64, 729 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 730 731 flags = le16toh(desc64->flags); 732 len = le16toh(desc64->length) & 0x3fff; 733 } else { 734 desc32 = &sc->rxq.desc32[i]; 735 nfe_rxdesc32_sync(sc, desc32, 736 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 737 738 flags = le16toh(desc32->flags); 739 len = le16toh(desc32->length) & 0x3fff; 740 } 741 742 if ((flags & NFE_RX_READY) != 0) 743 break; 744 745 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 746 if ((flags & NFE_RX_VALID_V1) == 0) 747 goto skip; 748 749 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 750 flags &= ~NFE_RX_ERROR; 751 len--; /* fix buffer length */ 752 } 753 } else { 754 if ((flags & NFE_RX_VALID_V2) == 0) 755 goto skip; 756 757 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 758 flags &= ~NFE_RX_ERROR; 759 len--; /* fix buffer length */ 760 } 761 } 762 763 if (flags & NFE_RX_ERROR) { 764 ifp->if_ierrors++; 765 goto skip; 766 } 767 768 /* 769 * Try to allocate a new mbuf for this ring element and load 770 * it before processing the current mbuf. If the ring element 771 * cannot be loaded, drop the received packet and reuse the 772 * old mbuf. In the unlikely case that the old mbuf can't be 773 * reloaded either, explicitly panic. 774 */ 775 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 776 if (mnew == NULL) { 777 ifp->if_ierrors++; 778 goto skip; 779 } 780 781 if (sc->sc_flags & NFE_USE_JUMBO) { 782 physaddr = 783 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 784 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 785 if (len > MCLBYTES) { 786 m_freem(mnew); 787 ifp->if_ierrors++; 788 goto skip1; 789 } 790 MCLGET(mnew, M_DONTWAIT); 791 if ((mnew->m_flags & M_EXT) == 0) { 792 m_freem(mnew); 793 ifp->if_ierrors++; 794 goto skip1; 795 } 796 797 (void)memcpy(mtod(mnew, void *), 798 mtod(data->m, const void *), len); 799 m = mnew; 800 goto mbufcopied; 801 } else { 802 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 803 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 804 mtod(data->m, char *) - (char *)sc->rxq.jpool, 805 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 806 807 physaddr = jbuf->physaddr; 808 } 809 } else { 810 MCLGET(mnew, M_DONTWAIT); 811 if ((mnew->m_flags & M_EXT) == 0) { 812 m_freem(mnew); 813 ifp->if_ierrors++; 814 goto skip; 815 } 816 817 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 818 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 819 bus_dmamap_unload(sc->sc_dmat, data->map); 820 821 error = bus_dmamap_load(sc->sc_dmat, data->map, 822 mtod(mnew, void *), MCLBYTES, NULL, 823 BUS_DMA_READ | BUS_DMA_NOWAIT); 824 if (error != 0) { 825 m_freem(mnew); 826 827 /* try to reload the old mbuf */ 828 error = bus_dmamap_load(sc->sc_dmat, data->map, 829 mtod(data->m, void *), MCLBYTES, NULL, 830 BUS_DMA_READ | BUS_DMA_NOWAIT); 831 if (error != 0) { 832 /* very unlikely that it will fail.. */ 833 panic("%s: could not load old rx mbuf", 834 device_xname(sc->sc_dev)); 835 } 836 ifp->if_ierrors++; 837 goto skip; 838 } 839 physaddr = data->map->dm_segs[0].ds_addr; 840 } 841 842 /* 843 * New mbuf successfully loaded, update Rx ring and continue 844 * processing. 845 */ 846 m = data->m; 847 data->m = mnew; 848 849 mbufcopied: 850 /* finalize mbuf */ 851 m->m_pkthdr.len = m->m_len = len; 852 m->m_pkthdr.rcvif = ifp; 853 854 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 855 /* 856 * XXX 857 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 858 */ 859 if (flags & NFE_RX_IP_CSUMOK) { 860 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 861 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 862 device_xname(sc->sc_dev))); 863 } 864 /* 865 * XXX 866 * no way to check M_CSUM_TCP_UDP_BAD or 867 * other protocols? 868 */ 869 if (flags & NFE_RX_UDP_CSUMOK) { 870 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 871 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 872 device_xname(sc->sc_dev))); 873 } else if (flags & NFE_RX_TCP_CSUMOK) { 874 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 875 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 876 device_xname(sc->sc_dev))); 877 } 878 } 879 #if NBPFILTER > 0 880 if (ifp->if_bpf) 881 bpf_mtap(ifp->if_bpf, m); 882 #endif 883 ifp->if_ipackets++; 884 (*ifp->if_input)(ifp, m); 885 886 skip1: 887 /* update mapping address in h/w descriptor */ 888 if (sc->sc_flags & NFE_40BIT_ADDR) { 889 #if defined(__LP64__) 890 desc64->physaddr[0] = htole32(physaddr >> 32); 891 #endif 892 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 893 } else { 894 desc32->physaddr = htole32(physaddr); 895 } 896 897 skip: 898 if (sc->sc_flags & NFE_40BIT_ADDR) { 899 desc64->length = htole16(sc->rxq.bufsz); 900 desc64->flags = htole16(NFE_RX_READY); 901 902 nfe_rxdesc64_sync(sc, desc64, 903 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 904 } else { 905 desc32->length = htole16(sc->rxq.bufsz); 906 desc32->flags = htole16(NFE_RX_READY); 907 908 nfe_rxdesc32_sync(sc, desc32, 909 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 910 } 911 } 912 /* update current RX pointer */ 913 sc->rxq.cur = i; 914 } 915 916 void 917 nfe_txeof(struct nfe_softc *sc) 918 { 919 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 920 struct nfe_desc32 *desc32; 921 struct nfe_desc64 *desc64; 922 struct nfe_tx_data *data = NULL; 923 int i; 924 uint16_t flags; 925 char buf[128]; 926 927 for (i = sc->txq.next; 928 sc->txq.queued > 0; 929 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 930 if (sc->sc_flags & NFE_40BIT_ADDR) { 931 desc64 = &sc->txq.desc64[i]; 932 nfe_txdesc64_sync(sc, desc64, 933 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 934 935 flags = le16toh(desc64->flags); 936 } else { 937 desc32 = &sc->txq.desc32[i]; 938 nfe_txdesc32_sync(sc, desc32, 939 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 940 941 flags = le16toh(desc32->flags); 942 } 943 944 if ((flags & NFE_TX_VALID) != 0) 945 break; 946 947 data = &sc->txq.data[i]; 948 949 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 950 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 951 data->m == NULL) 952 continue; 953 954 if ((flags & NFE_TX_ERROR_V1) != 0) { 955 snprintb(buf, sizeof(buf), NFE_V1_TXERR, flags); 956 aprint_error_dev(sc->sc_dev, "tx v1 error %s\n", 957 buf); 958 ifp->if_oerrors++; 959 } else 960 ifp->if_opackets++; 961 } else { 962 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 963 data->m == NULL) 964 continue; 965 966 if ((flags & NFE_TX_ERROR_V2) != 0) { 967 snprintb(buf, sizeof(buf), NFE_V2_TXERR, flags); 968 aprint_error_dev(sc->sc_dev, "tx v2 error %s\n", 969 buf); 970 ifp->if_oerrors++; 971 } else 972 ifp->if_opackets++; 973 } 974 975 if (data->m == NULL) { /* should not get there */ 976 aprint_error_dev(sc->sc_dev, 977 "last fragment bit w/o associated mbuf!\n"); 978 continue; 979 } 980 981 /* last fragment of the mbuf chain transmitted */ 982 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 983 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 984 bus_dmamap_unload(sc->sc_dmat, data->active); 985 m_freem(data->m); 986 data->m = NULL; 987 } 988 989 sc->txq.next = i; 990 991 if (sc->txq.queued < NFE_TX_RING_COUNT) { 992 /* at least one slot freed */ 993 ifp->if_flags &= ~IFF_OACTIVE; 994 } 995 996 if (sc->txq.queued == 0) { 997 /* all queued packets are sent */ 998 ifp->if_timer = 0; 999 } 1000 } 1001 1002 int 1003 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 1004 { 1005 struct nfe_desc32 *desc32; 1006 struct nfe_desc64 *desc64; 1007 struct nfe_tx_data *data; 1008 bus_dmamap_t map; 1009 uint16_t flags, csumflags; 1010 #if NVLAN > 0 1011 struct m_tag *mtag; 1012 uint32_t vtag = 0; 1013 #endif 1014 int error, i, first; 1015 1016 desc32 = NULL; 1017 desc64 = NULL; 1018 data = NULL; 1019 1020 flags = 0; 1021 csumflags = 0; 1022 first = sc->txq.cur; 1023 1024 map = sc->txq.data[first].map; 1025 1026 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1027 if (error != 0) { 1028 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1029 error); 1030 return error; 1031 } 1032 1033 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1034 bus_dmamap_unload(sc->sc_dmat, map); 1035 return ENOBUFS; 1036 } 1037 1038 #if NVLAN > 0 1039 /* setup h/w VLAN tagging */ 1040 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1041 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1042 #endif 1043 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1044 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1045 csumflags |= NFE_TX_IP_CSUM; 1046 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1047 csumflags |= NFE_TX_TCP_UDP_CSUM; 1048 } 1049 1050 for (i = 0; i < map->dm_nsegs; i++) { 1051 data = &sc->txq.data[sc->txq.cur]; 1052 1053 if (sc->sc_flags & NFE_40BIT_ADDR) { 1054 desc64 = &sc->txq.desc64[sc->txq.cur]; 1055 #if defined(__LP64__) 1056 desc64->physaddr[0] = 1057 htole32(map->dm_segs[i].ds_addr >> 32); 1058 #endif 1059 desc64->physaddr[1] = 1060 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1061 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1062 desc64->flags = htole16(flags); 1063 desc64->vtag = 0; 1064 } else { 1065 desc32 = &sc->txq.desc32[sc->txq.cur]; 1066 1067 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1068 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1069 desc32->flags = htole16(flags); 1070 } 1071 1072 /* 1073 * Setting of the valid bit in the first descriptor is 1074 * deferred until the whole chain is fully setup. 1075 */ 1076 flags |= NFE_TX_VALID; 1077 1078 sc->txq.queued++; 1079 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1080 } 1081 1082 /* the whole mbuf chain has been setup */ 1083 if (sc->sc_flags & NFE_40BIT_ADDR) { 1084 /* fix last descriptor */ 1085 flags |= NFE_TX_LASTFRAG_V2; 1086 desc64->flags = htole16(flags); 1087 1088 /* Checksum flags and vtag belong to the first fragment only. */ 1089 #if NVLAN > 0 1090 sc->txq.desc64[first].vtag = htole32(vtag); 1091 #endif 1092 sc->txq.desc64[first].flags |= htole16(csumflags); 1093 1094 /* finally, set the valid bit in the first descriptor */ 1095 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1096 } else { 1097 /* fix last descriptor */ 1098 if (sc->sc_flags & NFE_JUMBO_SUP) 1099 flags |= NFE_TX_LASTFRAG_V2; 1100 else 1101 flags |= NFE_TX_LASTFRAG_V1; 1102 desc32->flags = htole16(flags); 1103 1104 /* Checksum flags belong to the first fragment only. */ 1105 sc->txq.desc32[first].flags |= htole16(csumflags); 1106 1107 /* finally, set the valid bit in the first descriptor */ 1108 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1109 } 1110 1111 data->m = m0; 1112 data->active = map; 1113 1114 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1115 BUS_DMASYNC_PREWRITE); 1116 1117 return 0; 1118 } 1119 1120 void 1121 nfe_start(struct ifnet *ifp) 1122 { 1123 struct nfe_softc *sc = ifp->if_softc; 1124 int old = sc->txq.queued; 1125 struct mbuf *m0; 1126 1127 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1128 return; 1129 1130 for (;;) { 1131 IFQ_POLL(&ifp->if_snd, m0); 1132 if (m0 == NULL) 1133 break; 1134 1135 if (nfe_encap(sc, m0) != 0) { 1136 ifp->if_flags |= IFF_OACTIVE; 1137 break; 1138 } 1139 1140 /* packet put in h/w queue, remove from s/w queue */ 1141 IFQ_DEQUEUE(&ifp->if_snd, m0); 1142 1143 #if NBPFILTER > 0 1144 if (ifp->if_bpf != NULL) 1145 bpf_mtap(ifp->if_bpf, m0); 1146 #endif 1147 } 1148 1149 if (sc->txq.queued != old) { 1150 /* packets are queued */ 1151 if (sc->sc_flags & NFE_40BIT_ADDR) 1152 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1153 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1154 else 1155 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1156 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1157 /* kick Tx */ 1158 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1159 1160 /* 1161 * Set a timeout in case the chip goes out to lunch. 1162 */ 1163 ifp->if_timer = 5; 1164 } 1165 } 1166 1167 void 1168 nfe_watchdog(struct ifnet *ifp) 1169 { 1170 struct nfe_softc *sc = ifp->if_softc; 1171 1172 aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1173 1174 ifp->if_flags &= ~IFF_RUNNING; 1175 nfe_init(ifp); 1176 1177 ifp->if_oerrors++; 1178 } 1179 1180 int 1181 nfe_init(struct ifnet *ifp) 1182 { 1183 struct nfe_softc *sc = ifp->if_softc; 1184 uint32_t tmp; 1185 int rc = 0, s; 1186 1187 if (ifp->if_flags & IFF_RUNNING) 1188 return 0; 1189 1190 nfe_stop(ifp, 0); 1191 1192 NFE_WRITE(sc, NFE_TX_UNK, 0); 1193 NFE_WRITE(sc, NFE_STATUS, 0); 1194 1195 sc->rxtxctl = NFE_RXTX_BIT2; 1196 if (sc->sc_flags & NFE_40BIT_ADDR) 1197 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1198 else if (sc->sc_flags & NFE_JUMBO_SUP) 1199 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1200 if (sc->sc_flags & NFE_HW_CSUM) 1201 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1202 #if NVLAN > 0 1203 /* 1204 * Although the adapter is capable of stripping VLAN tags from received 1205 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1206 * purpose. This will be done in software by our network stack. 1207 */ 1208 if (sc->sc_flags & NFE_HW_VLAN) 1209 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1210 #endif 1211 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1212 DELAY(10); 1213 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1214 1215 #if NVLAN 1216 if (sc->sc_flags & NFE_HW_VLAN) 1217 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1218 #endif 1219 1220 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1221 1222 /* set MAC address */ 1223 nfe_set_macaddr(sc, sc->sc_enaddr); 1224 1225 /* tell MAC where rings are in memory */ 1226 #ifdef __LP64__ 1227 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1228 #endif 1229 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1230 #ifdef __LP64__ 1231 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1232 #endif 1233 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1234 1235 NFE_WRITE(sc, NFE_RING_SIZE, 1236 (NFE_RX_RING_COUNT - 1) << 16 | 1237 (NFE_TX_RING_COUNT - 1)); 1238 1239 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1240 1241 /* force MAC to wakeup */ 1242 tmp = NFE_READ(sc, NFE_PWR_STATE); 1243 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1244 DELAY(10); 1245 tmp = NFE_READ(sc, NFE_PWR_STATE); 1246 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1247 1248 s = splnet(); 1249 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1250 nfe_intr(sc); /* XXX clear IRQ status registers */ 1251 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1252 splx(s); 1253 1254 #if 1 1255 /* configure interrupts coalescing/mitigation */ 1256 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1257 #else 1258 /* no interrupt mitigation: one interrupt per packet */ 1259 NFE_WRITE(sc, NFE_IMTIMER, 970); 1260 #endif 1261 1262 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1263 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1264 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1265 1266 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1267 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1268 1269 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1270 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_ENABLE); 1271 1272 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1273 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1274 DELAY(10); 1275 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1276 1277 /* set Rx filter */ 1278 nfe_setmulti(sc); 1279 1280 if ((rc = ether_mediachange(ifp)) != 0) 1281 goto out; 1282 1283 nfe_tick(sc); 1284 1285 /* enable Rx */ 1286 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1287 1288 /* enable Tx */ 1289 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1290 1291 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1292 1293 /* enable interrupts */ 1294 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1295 1296 callout_schedule(&sc->sc_tick_ch, hz); 1297 1298 ifp->if_flags |= IFF_RUNNING; 1299 ifp->if_flags &= ~IFF_OACTIVE; 1300 1301 out: 1302 return rc; 1303 } 1304 1305 void 1306 nfe_stop(struct ifnet *ifp, int disable) 1307 { 1308 struct nfe_softc *sc = ifp->if_softc; 1309 1310 callout_stop(&sc->sc_tick_ch); 1311 1312 ifp->if_timer = 0; 1313 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1314 1315 mii_down(&sc->sc_mii); 1316 1317 /* abort Tx */ 1318 NFE_WRITE(sc, NFE_TX_CTL, 0); 1319 1320 /* disable Rx */ 1321 NFE_WRITE(sc, NFE_RX_CTL, 0); 1322 1323 /* disable interrupts */ 1324 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1325 1326 /* reset Tx and Rx rings */ 1327 nfe_reset_tx_ring(sc, &sc->txq); 1328 nfe_reset_rx_ring(sc, &sc->rxq); 1329 } 1330 1331 int 1332 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1333 { 1334 struct nfe_desc32 *desc32; 1335 struct nfe_desc64 *desc64; 1336 struct nfe_rx_data *data; 1337 struct nfe_jbuf *jbuf; 1338 void **desc; 1339 bus_addr_t physaddr; 1340 int i, nsegs, error, descsize; 1341 1342 if (sc->sc_flags & NFE_40BIT_ADDR) { 1343 desc = (void **)&ring->desc64; 1344 descsize = sizeof (struct nfe_desc64); 1345 } else { 1346 desc = (void **)&ring->desc32; 1347 descsize = sizeof (struct nfe_desc32); 1348 } 1349 1350 ring->cur = ring->next = 0; 1351 ring->bufsz = MCLBYTES; 1352 1353 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1354 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1355 if (error != 0) { 1356 aprint_error_dev(sc->sc_dev, 1357 "could not create desc DMA map\n"); 1358 goto fail; 1359 } 1360 1361 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1362 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1363 if (error != 0) { 1364 aprint_error_dev(sc->sc_dev, 1365 "could not allocate DMA memory\n"); 1366 goto fail; 1367 } 1368 1369 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1370 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1371 if (error != 0) { 1372 aprint_error_dev(sc->sc_dev, 1373 "could not map desc DMA memory\n"); 1374 goto fail; 1375 } 1376 1377 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1378 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1379 if (error != 0) { 1380 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1381 goto fail; 1382 } 1383 1384 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1385 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1386 1387 if (sc->sc_flags & NFE_USE_JUMBO) { 1388 ring->bufsz = NFE_JBYTES; 1389 if ((error = nfe_jpool_alloc(sc)) != 0) { 1390 aprint_error_dev(sc->sc_dev, 1391 "could not allocate jumbo frames\n"); 1392 goto fail; 1393 } 1394 } 1395 1396 /* 1397 * Pre-allocate Rx buffers and populate Rx ring. 1398 */ 1399 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1400 data = &sc->rxq.data[i]; 1401 1402 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1403 if (data->m == NULL) { 1404 aprint_error_dev(sc->sc_dev, 1405 "could not allocate rx mbuf\n"); 1406 error = ENOMEM; 1407 goto fail; 1408 } 1409 1410 if (sc->sc_flags & NFE_USE_JUMBO) { 1411 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1412 aprint_error_dev(sc->sc_dev, 1413 "could not allocate jumbo buffer\n"); 1414 goto fail; 1415 } 1416 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1417 sc); 1418 1419 physaddr = jbuf->physaddr; 1420 } else { 1421 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1422 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1423 if (error != 0) { 1424 aprint_error_dev(sc->sc_dev, 1425 "could not create DMA map\n"); 1426 goto fail; 1427 } 1428 MCLGET(data->m, M_DONTWAIT); 1429 if (!(data->m->m_flags & M_EXT)) { 1430 aprint_error_dev(sc->sc_dev, 1431 "could not allocate mbuf cluster\n"); 1432 error = ENOMEM; 1433 goto fail; 1434 } 1435 1436 error = bus_dmamap_load(sc->sc_dmat, data->map, 1437 mtod(data->m, void *), MCLBYTES, NULL, 1438 BUS_DMA_READ | BUS_DMA_NOWAIT); 1439 if (error != 0) { 1440 aprint_error_dev(sc->sc_dev, 1441 "could not load rx buf DMA map"); 1442 goto fail; 1443 } 1444 physaddr = data->map->dm_segs[0].ds_addr; 1445 } 1446 1447 if (sc->sc_flags & NFE_40BIT_ADDR) { 1448 desc64 = &sc->rxq.desc64[i]; 1449 #if defined(__LP64__) 1450 desc64->physaddr[0] = htole32(physaddr >> 32); 1451 #endif 1452 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1453 desc64->length = htole16(sc->rxq.bufsz); 1454 desc64->flags = htole16(NFE_RX_READY); 1455 } else { 1456 desc32 = &sc->rxq.desc32[i]; 1457 desc32->physaddr = htole32(physaddr); 1458 desc32->length = htole16(sc->rxq.bufsz); 1459 desc32->flags = htole16(NFE_RX_READY); 1460 } 1461 } 1462 1463 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1464 BUS_DMASYNC_PREWRITE); 1465 1466 return 0; 1467 1468 fail: nfe_free_rx_ring(sc, ring); 1469 return error; 1470 } 1471 1472 void 1473 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1474 { 1475 int i; 1476 1477 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1478 if (sc->sc_flags & NFE_40BIT_ADDR) { 1479 ring->desc64[i].length = htole16(ring->bufsz); 1480 ring->desc64[i].flags = htole16(NFE_RX_READY); 1481 } else { 1482 ring->desc32[i].length = htole16(ring->bufsz); 1483 ring->desc32[i].flags = htole16(NFE_RX_READY); 1484 } 1485 } 1486 1487 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1488 BUS_DMASYNC_PREWRITE); 1489 1490 ring->cur = ring->next = 0; 1491 } 1492 1493 void 1494 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1495 { 1496 struct nfe_rx_data *data; 1497 void *desc; 1498 int i, descsize; 1499 1500 if (sc->sc_flags & NFE_40BIT_ADDR) { 1501 desc = ring->desc64; 1502 descsize = sizeof (struct nfe_desc64); 1503 } else { 1504 desc = ring->desc32; 1505 descsize = sizeof (struct nfe_desc32); 1506 } 1507 1508 if (desc != NULL) { 1509 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1510 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1511 bus_dmamap_unload(sc->sc_dmat, ring->map); 1512 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1513 NFE_RX_RING_COUNT * descsize); 1514 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1515 } 1516 1517 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1518 data = &ring->data[i]; 1519 1520 if (data->map != NULL) { 1521 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1522 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1523 bus_dmamap_unload(sc->sc_dmat, data->map); 1524 bus_dmamap_destroy(sc->sc_dmat, data->map); 1525 } 1526 if (data->m != NULL) 1527 m_freem(data->m); 1528 } 1529 } 1530 1531 struct nfe_jbuf * 1532 nfe_jalloc(struct nfe_softc *sc, int i) 1533 { 1534 struct nfe_jbuf *jbuf; 1535 1536 mutex_enter(&sc->rxq.mtx); 1537 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1538 if (jbuf != NULL) 1539 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1540 mutex_exit(&sc->rxq.mtx); 1541 if (jbuf == NULL) 1542 return NULL; 1543 sc->rxq.jbufmap[i] = 1544 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1545 return jbuf; 1546 } 1547 1548 /* 1549 * This is called automatically by the network stack when the mbuf is freed. 1550 * Caution must be taken that the NIC might be reset by the time the mbuf is 1551 * freed. 1552 */ 1553 void 1554 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1555 { 1556 struct nfe_softc *sc = arg; 1557 struct nfe_jbuf *jbuf; 1558 int i; 1559 1560 /* find the jbuf from the base pointer */ 1561 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1562 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1563 aprint_error_dev(sc->sc_dev, 1564 "request to free a buffer (%p) not managed by us\n", buf); 1565 return; 1566 } 1567 jbuf = &sc->rxq.jbuf[i]; 1568 1569 /* ..and put it back in the free list */ 1570 mutex_enter(&sc->rxq.mtx); 1571 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1572 mutex_exit(&sc->rxq.mtx); 1573 1574 if (m != NULL) 1575 pool_cache_put(mb_cache, m); 1576 } 1577 1578 int 1579 nfe_jpool_alloc(struct nfe_softc *sc) 1580 { 1581 struct nfe_rx_ring *ring = &sc->rxq; 1582 struct nfe_jbuf *jbuf; 1583 bus_addr_t physaddr; 1584 char *buf; 1585 int i, nsegs, error; 1586 1587 /* 1588 * Allocate a big chunk of DMA'able memory. 1589 */ 1590 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1591 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1592 if (error != 0) { 1593 aprint_error_dev(sc->sc_dev, 1594 "could not create jumbo DMA map\n"); 1595 goto fail; 1596 } 1597 1598 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1599 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1600 if (error != 0) { 1601 aprint_error_dev(sc->sc_dev, 1602 "could not allocate jumbo DMA memory\n"); 1603 goto fail; 1604 } 1605 1606 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1607 &ring->jpool, BUS_DMA_NOWAIT); 1608 if (error != 0) { 1609 aprint_error_dev(sc->sc_dev, 1610 "could not map jumbo DMA memory\n"); 1611 goto fail; 1612 } 1613 1614 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1615 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1616 if (error != 0) { 1617 aprint_error_dev(sc->sc_dev, 1618 "could not load jumbo DMA map\n"); 1619 goto fail; 1620 } 1621 1622 /* ..and split it into 9KB chunks */ 1623 SLIST_INIT(&ring->jfreelist); 1624 1625 buf = ring->jpool; 1626 physaddr = ring->jmap->dm_segs[0].ds_addr; 1627 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1628 jbuf = &ring->jbuf[i]; 1629 1630 jbuf->buf = buf; 1631 jbuf->physaddr = physaddr; 1632 1633 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1634 1635 buf += NFE_JBYTES; 1636 physaddr += NFE_JBYTES; 1637 } 1638 1639 return 0; 1640 1641 fail: nfe_jpool_free(sc); 1642 return error; 1643 } 1644 1645 void 1646 nfe_jpool_free(struct nfe_softc *sc) 1647 { 1648 struct nfe_rx_ring *ring = &sc->rxq; 1649 1650 if (ring->jmap != NULL) { 1651 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1652 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1653 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1654 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1655 } 1656 if (ring->jpool != NULL) { 1657 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1658 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1659 } 1660 } 1661 1662 int 1663 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1664 { 1665 int i, nsegs, error; 1666 void **desc; 1667 int descsize; 1668 1669 if (sc->sc_flags & NFE_40BIT_ADDR) { 1670 desc = (void **)&ring->desc64; 1671 descsize = sizeof (struct nfe_desc64); 1672 } else { 1673 desc = (void **)&ring->desc32; 1674 descsize = sizeof (struct nfe_desc32); 1675 } 1676 1677 ring->queued = 0; 1678 ring->cur = ring->next = 0; 1679 1680 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1681 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1682 1683 if (error != 0) { 1684 aprint_error_dev(sc->sc_dev, 1685 "could not create desc DMA map\n"); 1686 goto fail; 1687 } 1688 1689 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1690 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1691 if (error != 0) { 1692 aprint_error_dev(sc->sc_dev, 1693 "could not allocate DMA memory\n"); 1694 goto fail; 1695 } 1696 1697 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1698 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1699 if (error != 0) { 1700 aprint_error_dev(sc->sc_dev, 1701 "could not map desc DMA memory\n"); 1702 goto fail; 1703 } 1704 1705 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1706 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1707 if (error != 0) { 1708 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1709 goto fail; 1710 } 1711 1712 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1713 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1714 1715 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1716 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1717 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1718 &ring->data[i].map); 1719 if (error != 0) { 1720 aprint_error_dev(sc->sc_dev, 1721 "could not create DMA map\n"); 1722 goto fail; 1723 } 1724 } 1725 1726 return 0; 1727 1728 fail: nfe_free_tx_ring(sc, ring); 1729 return error; 1730 } 1731 1732 void 1733 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1734 { 1735 struct nfe_tx_data *data; 1736 int i; 1737 1738 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1739 if (sc->sc_flags & NFE_40BIT_ADDR) 1740 ring->desc64[i].flags = 0; 1741 else 1742 ring->desc32[i].flags = 0; 1743 1744 data = &ring->data[i]; 1745 1746 if (data->m != NULL) { 1747 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1748 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1749 bus_dmamap_unload(sc->sc_dmat, data->active); 1750 m_freem(data->m); 1751 data->m = NULL; 1752 } 1753 } 1754 1755 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1756 BUS_DMASYNC_PREWRITE); 1757 1758 ring->queued = 0; 1759 ring->cur = ring->next = 0; 1760 } 1761 1762 void 1763 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1764 { 1765 struct nfe_tx_data *data; 1766 void *desc; 1767 int i, descsize; 1768 1769 if (sc->sc_flags & NFE_40BIT_ADDR) { 1770 desc = ring->desc64; 1771 descsize = sizeof (struct nfe_desc64); 1772 } else { 1773 desc = ring->desc32; 1774 descsize = sizeof (struct nfe_desc32); 1775 } 1776 1777 if (desc != NULL) { 1778 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1779 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1780 bus_dmamap_unload(sc->sc_dmat, ring->map); 1781 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1782 NFE_TX_RING_COUNT * descsize); 1783 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1784 } 1785 1786 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1787 data = &ring->data[i]; 1788 1789 if (data->m != NULL) { 1790 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1791 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1792 bus_dmamap_unload(sc->sc_dmat, data->active); 1793 m_freem(data->m); 1794 } 1795 } 1796 1797 /* ..and now actually destroy the DMA mappings */ 1798 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1799 data = &ring->data[i]; 1800 if (data->map == NULL) 1801 continue; 1802 bus_dmamap_destroy(sc->sc_dmat, data->map); 1803 } 1804 } 1805 1806 void 1807 nfe_setmulti(struct nfe_softc *sc) 1808 { 1809 struct ethercom *ec = &sc->sc_ethercom; 1810 struct ifnet *ifp = &ec->ec_if; 1811 struct ether_multi *enm; 1812 struct ether_multistep step; 1813 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1814 uint32_t filter = NFE_RXFILTER_MAGIC; 1815 int i; 1816 1817 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1818 bzero(addr, ETHER_ADDR_LEN); 1819 bzero(mask, ETHER_ADDR_LEN); 1820 goto done; 1821 } 1822 1823 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1824 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1825 1826 ETHER_FIRST_MULTI(step, ec, enm); 1827 while (enm != NULL) { 1828 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1829 ifp->if_flags |= IFF_ALLMULTI; 1830 bzero(addr, ETHER_ADDR_LEN); 1831 bzero(mask, ETHER_ADDR_LEN); 1832 goto done; 1833 } 1834 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1835 addr[i] &= enm->enm_addrlo[i]; 1836 mask[i] &= ~enm->enm_addrlo[i]; 1837 } 1838 ETHER_NEXT_MULTI(step, enm); 1839 } 1840 for (i = 0; i < ETHER_ADDR_LEN; i++) 1841 mask[i] |= addr[i]; 1842 1843 done: 1844 addr[0] |= 0x01; /* make sure multicast bit is set */ 1845 1846 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1847 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1848 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1849 addr[5] << 8 | addr[4]); 1850 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1851 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1852 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1853 mask[5] << 8 | mask[4]); 1854 1855 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1856 NFE_WRITE(sc, NFE_RXFILTER, filter); 1857 } 1858 1859 void 1860 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1861 { 1862 uint32_t tmp; 1863 1864 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 1865 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1866 addr[0] = (tmp & 0xff); 1867 addr[1] = (tmp >> 8) & 0xff; 1868 addr[2] = (tmp >> 16) & 0xff; 1869 addr[3] = (tmp >> 24) & 0xff; 1870 1871 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1872 addr[4] = (tmp & 0xff); 1873 addr[5] = (tmp >> 8) & 0xff; 1874 1875 } else { 1876 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1877 addr[0] = (tmp >> 8) & 0xff; 1878 addr[1] = (tmp & 0xff); 1879 1880 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1881 addr[2] = (tmp >> 24) & 0xff; 1882 addr[3] = (tmp >> 16) & 0xff; 1883 addr[4] = (tmp >> 8) & 0xff; 1884 addr[5] = (tmp & 0xff); 1885 } 1886 } 1887 1888 void 1889 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1890 { 1891 NFE_WRITE(sc, NFE_MACADDR_LO, 1892 addr[5] << 8 | addr[4]); 1893 NFE_WRITE(sc, NFE_MACADDR_HI, 1894 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1895 } 1896 1897 void 1898 nfe_tick(void *arg) 1899 { 1900 struct nfe_softc *sc = arg; 1901 int s; 1902 1903 s = splnet(); 1904 mii_tick(&sc->sc_mii); 1905 splx(s); 1906 1907 callout_schedule(&sc->sc_tick_ch, hz); 1908 } 1909 1910 void 1911 nfe_poweron(device_t self) 1912 { 1913 struct nfe_softc *sc = device_private(self); 1914 1915 if ((sc->sc_flags & NFE_PWR_MGMT) != 0) { 1916 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 1917 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 1918 DELAY(100); 1919 NFE_WRITE(sc, NFE_MAC_RESET, 0); 1920 DELAY(100); 1921 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 1922 NFE_WRITE(sc, NFE_PWR2_CTL, 1923 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_WAKEUP_MASK); 1924 } 1925 } 1926 1927 bool 1928 nfe_resume(device_t dv PMF_FN_ARGS) 1929 { 1930 nfe_poweron(dv); 1931 1932 return true; 1933 } 1934
Indexes created Tue Sep 30 11:09:46 GMT 2025