if_nfe.c revision 1.4
1 /* $NetBSD: if_nfe.c,v 1.4 2006/09/03 07:42:04 xtraeme Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.52 2006/03/02 09:04:00 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.4 2006/09/03 07:42:04 xtraeme Exp $"); 25 26 #include "opt_inet.h" 27 #include "bpfilter.h" 28 #include "vlan.h" 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/types.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/queue.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/socket.h> 41 42 #include <machine/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/pci/if_nfereg.h> 74 #include <dev/pci/if_nfevar.h> 75 76 int nfe_match(struct device *, struct cfdata *, void *); 77 void nfe_attach(struct device *, struct device *, void *); 78 void nfe_power(int, void *); 79 void nfe_miibus_statchg(struct device *); 80 int nfe_miibus_readreg(struct device *, int, int); 81 void nfe_miibus_writereg(struct device *, int, int, int); 82 int nfe_intr(void *); 83 int nfe_ioctl(struct ifnet *, u_long, caddr_t); 84 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 85 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 86 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 87 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 88 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 89 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 90 void nfe_rxeof(struct nfe_softc *); 91 void nfe_txeof(struct nfe_softc *); 92 int nfe_encap(struct nfe_softc *, struct mbuf *); 93 void nfe_start(struct ifnet *); 94 void nfe_watchdog(struct ifnet *); 95 int nfe_init(struct ifnet *); 96 void nfe_stop(struct ifnet *, int); 97 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *); 98 void nfe_jfree(struct mbuf *, caddr_t, size_t, void *); 99 int nfe_jpool_alloc(struct nfe_softc *); 100 void nfe_jpool_free(struct nfe_softc *); 101 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 102 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 105 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 int nfe_ifmedia_upd(struct ifnet *); 108 void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 109 void nfe_setmulti(struct nfe_softc *); 110 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 111 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 112 void nfe_tick(void *); 113 114 CFATTACH_DECL(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, NULL, NULL); 115 116 /*#define NFE_NO_JUMBO*/ 117 118 #ifdef NFE_DEBUG 119 int nfedebug = 0; 120 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 121 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 122 #else 123 #define DPRINTF(x) 124 #define DPRINTFN(n,x) 125 #endif 126 127 /* deal with naming differences */ 128 129 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 130 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 134 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 135 136 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 137 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 140 141 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 142 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 145 146 #ifdef _LP64 147 #define __LP64__ 1 148 #endif 149 150 const struct nfe_product { 151 pci_vendor_id_t vendor; 152 pci_product_id_t product; 153 } nfe_devices[] = { 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 155 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 } 177 }; 178 179 int 180 nfe_match(struct device *dev, struct cfdata *match, void *aux) 181 { 182 struct pci_attach_args *pa = aux; 183 const struct nfe_product *np; 184 int i; 185 186 for (i = 0; i < sizeof(nfe_devices) / sizeof(nfe_devices[0]); i++) { 187 np = &nfe_devices[i]; 188 if (PCI_VENDOR(pa->pa_id) == np->vendor && 189 PCI_PRODUCT(pa->pa_id) == np->product) 190 return 1; 191 } 192 return 0; 193 } 194 195 void 196 nfe_attach(struct device *parent, struct device *self, void *aux) 197 { 198 struct nfe_softc *sc = (struct nfe_softc *)self; 199 struct pci_attach_args *pa = aux; 200 pci_chipset_tag_t pc = pa->pa_pc; 201 pci_intr_handle_t ih; 202 const char *intrstr; 203 struct ifnet *ifp; 204 bus_size_t memsize; 205 pcireg_t memtype; 206 207 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 208 switch (memtype) { 209 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 210 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 211 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 212 &sc->sc_memh, NULL, &memsize) == 0) 213 break; 214 /* FALLTHROUGH */ 215 default: 216 printf(": could not map mem space\n"); 217 return; 218 } 219 220 if (pci_intr_map(pa, &ih) != 0) { 221 printf(": could not map interrupt\n"); 222 return; 223 } 224 225 intrstr = pci_intr_string(pc, ih); 226 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 227 if (sc->sc_ih == NULL) { 228 printf(": could not establish interrupt"); 229 if (intrstr != NULL) 230 printf(" at %s", intrstr); 231 printf("\n"); 232 return; 233 } 234 printf(": %s", intrstr); 235 236 sc->sc_dmat = pa->pa_dmat; 237 238 nfe_get_macaddr(sc, sc->sc_enaddr); 239 printf(", address %s\n", ether_sprintf(sc->sc_enaddr)); 240 241 sc->sc_flags = 0; 242 243 switch (PCI_PRODUCT(pa->pa_id)) { 244 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 245 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 246 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 247 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 248 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 249 break; 250 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 251 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 252 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 253 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 254 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 255 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 256 sc->sc_flags |= NFE_40BIT_ADDR; 257 break; 258 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 259 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 260 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 261 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 262 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 263 break; 264 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 265 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 266 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 267 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 268 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 269 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 270 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 271 NFE_HW_VLAN; 272 break; 273 } 274 275 #ifndef NFE_NO_JUMBO 276 /* enable jumbo frames for adapters that support it */ 277 if (sc->sc_flags & NFE_JUMBO_SUP) 278 sc->sc_flags |= NFE_USE_JUMBO; 279 #endif 280 281 /* 282 * Allocate Tx and Rx rings. 283 */ 284 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 285 printf("%s: could not allocate Tx ring\n", 286 sc->sc_dev.dv_xname); 287 return; 288 } 289 290 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 291 printf("%s: could not allocate Rx ring\n", 292 sc->sc_dev.dv_xname); 293 nfe_free_tx_ring(sc, &sc->txq); 294 return; 295 } 296 297 ifp = &sc->sc_ethercom.ec_if; 298 ifp->if_softc = sc; 299 ifp->if_mtu = ETHERMTU; 300 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 301 ifp->if_ioctl = nfe_ioctl; 302 ifp->if_start = nfe_start; 303 ifp->if_watchdog = nfe_watchdog; 304 ifp->if_init = nfe_init; 305 ifp->if_baudrate = IF_Gbps(1); 306 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 307 IFQ_SET_READY(&ifp->if_snd); 308 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 309 310 #if NVLAN > 0 311 if (sc->sc_flags & NFE_HW_VLAN) 312 sc->sc_ethercom.ec_capabilities |= 313 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 314 #endif 315 #ifdef NFE_CSUM 316 if (sc->sc_flags & NFE_HW_CSUM) { 317 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 318 IFCAP_CSUM_UDPv4; 319 } 320 #endif 321 322 sc->sc_mii.mii_ifp = ifp; 323 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 324 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 325 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 326 327 ifmedia_init(&sc->sc_mii.mii_media, 0, nfe_ifmedia_upd, 328 nfe_ifmedia_sts); 329 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 330 MII_OFFSET_ANY, 0); 331 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 332 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 333 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 334 0, NULL); 335 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 336 } else 337 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 338 339 if_attach(ifp); 340 ether_ifattach(ifp, sc->sc_enaddr); 341 342 callout_init(&sc->sc_tick_ch); 343 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 344 345 sc->sc_powerhook = powerhook_establish(nfe_power, sc); 346 } 347 348 void 349 nfe_power(int why, void *arg) 350 { 351 struct nfe_softc *sc = arg; 352 struct ifnet *ifp; 353 354 if (why == PWR_RESUME) { 355 ifp = &sc->sc_ethercom.ec_if; 356 if (ifp->if_flags & IFF_UP) { 357 ifp->if_flags &= ~IFF_RUNNING; 358 nfe_init(ifp); 359 if (ifp->if_flags & IFF_RUNNING) 360 nfe_start(ifp); 361 } 362 } 363 } 364 365 void 366 nfe_miibus_statchg(struct device *dev) 367 { 368 struct nfe_softc *sc = (struct nfe_softc *)dev; 369 struct mii_data *mii = &sc->sc_mii; 370 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 371 372 phy = NFE_READ(sc, NFE_PHY_IFACE); 373 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 374 375 seed = NFE_READ(sc, NFE_RNDSEED); 376 seed &= ~NFE_SEED_MASK; 377 378 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 379 phy |= NFE_PHY_HDX; /* half-duplex */ 380 misc |= NFE_MISC1_HDX; 381 } 382 383 switch (IFM_SUBTYPE(mii->mii_media_active)) { 384 case IFM_1000_T: /* full-duplex only */ 385 link |= NFE_MEDIA_1000T; 386 seed |= NFE_SEED_1000T; 387 phy |= NFE_PHY_1000T; 388 break; 389 case IFM_100_TX: 390 link |= NFE_MEDIA_100TX; 391 seed |= NFE_SEED_100TX; 392 phy |= NFE_PHY_100TX; 393 break; 394 case IFM_10_T: 395 link |= NFE_MEDIA_10T; 396 seed |= NFE_SEED_10T; 397 break; 398 } 399 400 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 401 402 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 403 NFE_WRITE(sc, NFE_MISC1, misc); 404 NFE_WRITE(sc, NFE_LINKSPEED, link); 405 } 406 407 int 408 nfe_miibus_readreg(struct device *dev, int phy, int reg) 409 { 410 struct nfe_softc *sc = (struct nfe_softc *)dev; 411 uint32_t val; 412 int ntries; 413 414 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 415 416 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 417 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 418 DELAY(100); 419 } 420 421 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 422 423 for (ntries = 0; ntries < 1000; ntries++) { 424 DELAY(100); 425 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 426 break; 427 } 428 if (ntries == 1000) { 429 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 430 sc->sc_dev.dv_xname)); 431 return 0; 432 } 433 434 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 435 DPRINTFN(2, ("%s: could not read PHY\n", 436 sc->sc_dev.dv_xname)); 437 return 0; 438 } 439 440 val = NFE_READ(sc, NFE_PHY_DATA); 441 if (val != 0xffffffff && val != 0) 442 sc->mii_phyaddr = phy; 443 444 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 445 sc->sc_dev.dv_xname, phy, reg, val)); 446 447 return val; 448 } 449 450 void 451 nfe_miibus_writereg(struct device *dev, int phy, int reg, int val) 452 { 453 struct nfe_softc *sc = (struct nfe_softc *)dev; 454 uint32_t ctl; 455 int ntries; 456 457 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 458 459 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 460 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 461 DELAY(100); 462 } 463 464 NFE_WRITE(sc, NFE_PHY_DATA, val); 465 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 466 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 467 468 for (ntries = 0; ntries < 1000; ntries++) { 469 DELAY(100); 470 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 471 break; 472 } 473 #ifdef NFE_DEBUG 474 if (nfedebug >= 2 && ntries == 1000) 475 printf("could not write to PHY\n"); 476 #endif 477 } 478 479 int 480 nfe_intr(void *arg) 481 { 482 struct nfe_softc *sc = arg; 483 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 484 uint32_t r; 485 486 if ((r = NFE_READ(sc, NFE_IRQ_STATUS)) == 0) 487 return 0; /* not for us */ 488 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 489 490 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 491 492 if (r & NFE_IRQ_LINK) { 493 NFE_READ(sc, NFE_PHY_STATUS); 494 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 495 DPRINTF(("%s: link state changed\n", sc->sc_dev.dv_xname)); 496 } 497 498 if (ifp->if_flags & IFF_RUNNING) { 499 /* check Rx ring */ 500 nfe_rxeof(sc); 501 502 /* check Tx ring */ 503 nfe_txeof(sc); 504 } 505 506 return 1; 507 } 508 509 int 510 nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 511 { 512 struct nfe_softc *sc = ifp->if_softc; 513 struct ifreq *ifr = (struct ifreq *)data; 514 struct ifaddr *ifa = (struct ifaddr *)data; 515 int s, error = 0; 516 517 s = splnet(); 518 519 switch (cmd) { 520 case SIOCSIFADDR: 521 ifp->if_flags |= IFF_UP; 522 nfe_init(ifp); 523 switch (ifa->ifa_addr->sa_family) { 524 #ifdef INET 525 case AF_INET: 526 arp_ifinit(ifp, ifa); 527 break; 528 #endif 529 default: 530 break; 531 } 532 break; 533 case SIOCSIFMTU: 534 if (ifr->ifr_mtu < ETHERMIN || 535 ((sc->sc_flags & NFE_USE_JUMBO) && 536 ifr->ifr_mtu > ETHERMTU_JUMBO) || 537 (!(sc->sc_flags & NFE_USE_JUMBO) && 538 ifr->ifr_mtu > ETHERMTU)) 539 error = EINVAL; 540 else if (ifp->if_mtu != ifr->ifr_mtu) 541 ifp->if_mtu = ifr->ifr_mtu; 542 break; 543 case SIOCSIFFLAGS: 544 if (ifp->if_flags & IFF_UP) { 545 /* 546 * If only the PROMISC or ALLMULTI flag changes, then 547 * don't do a full re-init of the chip, just update 548 * the Rx filter. 549 */ 550 if ((ifp->if_flags & IFF_RUNNING) && 551 ((ifp->if_flags ^ sc->sc_if_flags) & 552 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 553 nfe_setmulti(sc); 554 else 555 nfe_init(ifp); 556 } else { 557 if (ifp->if_flags & IFF_RUNNING) 558 nfe_stop(ifp, 1); 559 } 560 sc->sc_if_flags = ifp->if_flags; 561 break; 562 case SIOCADDMULTI: 563 case SIOCDELMULTI: 564 error = (cmd == SIOCADDMULTI) ? 565 ether_addmulti(ifr, &sc->sc_ethercom) : 566 ether_delmulti(ifr, &sc->sc_ethercom); 567 568 if (error == ENETRESET) { 569 if (ifp->if_flags & IFF_RUNNING) 570 nfe_setmulti(sc); 571 error = 0; 572 } 573 break; 574 case SIOCSIFMEDIA: 575 case SIOCGIFMEDIA: 576 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 577 break; 578 default: 579 error = ether_ioctl(ifp, cmd, data); 580 if (error == ENETRESET) { 581 if (ifp->if_flags & IFF_RUNNING) 582 nfe_setmulti(sc); 583 error = 0; 584 } 585 break; 586 587 } 588 589 splx(s); 590 591 return error; 592 } 593 594 void 595 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 596 { 597 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 598 (caddr_t)desc32 - (caddr_t)sc->txq.desc32, 599 sizeof (struct nfe_desc32), ops); 600 } 601 602 void 603 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 604 { 605 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 606 (caddr_t)desc64 - (caddr_t)sc->txq.desc64, 607 sizeof (struct nfe_desc64), ops); 608 } 609 610 void 611 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 612 { 613 if (end > start) { 614 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 615 (caddr_t)&sc->txq.desc32[start] - (caddr_t)sc->txq.desc32, 616 (caddr_t)&sc->txq.desc32[end] - 617 (caddr_t)&sc->txq.desc32[start], ops); 618 return; 619 } 620 /* sync from 'start' to end of ring */ 621 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 622 (caddr_t)&sc->txq.desc32[start] - (caddr_t)sc->txq.desc32, 623 (caddr_t)&sc->txq.desc32[NFE_TX_RING_COUNT] - 624 (caddr_t)&sc->txq.desc32[start], ops); 625 626 /* sync from start of ring to 'end' */ 627 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 628 (caddr_t)&sc->txq.desc32[end] - (caddr_t)sc->txq.desc32, ops); 629 } 630 631 void 632 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 633 { 634 if (end > start) { 635 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 636 (caddr_t)&sc->txq.desc64[start] - (caddr_t)sc->txq.desc64, 637 (caddr_t)&sc->txq.desc64[end] - 638 (caddr_t)&sc->txq.desc64[start], ops); 639 return; 640 } 641 /* sync from 'start' to end of ring */ 642 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 643 (caddr_t)&sc->txq.desc64[start] - (caddr_t)sc->txq.desc64, 644 (caddr_t)&sc->txq.desc64[NFE_TX_RING_COUNT] - 645 (caddr_t)&sc->txq.desc64[start], ops); 646 647 /* sync from start of ring to 'end' */ 648 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 649 (caddr_t)&sc->txq.desc64[end] - (caddr_t)sc->txq.desc64, ops); 650 } 651 652 void 653 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 654 { 655 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 656 (caddr_t)desc32 - (caddr_t)sc->rxq.desc32, 657 sizeof (struct nfe_desc32), ops); 658 } 659 660 void 661 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 662 { 663 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 664 (caddr_t)desc64 - (caddr_t)sc->rxq.desc64, 665 sizeof (struct nfe_desc64), ops); 666 } 667 668 void 669 nfe_rxeof(struct nfe_softc *sc) 670 { 671 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 672 struct nfe_desc32 *desc32; 673 struct nfe_desc64 *desc64; 674 struct nfe_rx_data *data; 675 struct nfe_jbuf *jbuf; 676 struct mbuf *m, *mnew; 677 bus_addr_t physaddr; 678 uint16_t flags; 679 int error, len; 680 681 desc32 = NULL; 682 desc64 = NULL; 683 for (;;) { 684 data = &sc->rxq.data[sc->rxq.cur]; 685 686 if (sc->sc_flags & NFE_40BIT_ADDR) { 687 desc64 = &sc->rxq.desc64[sc->rxq.cur]; 688 nfe_rxdesc64_sync(sc, desc64, BUS_DMASYNC_POSTREAD); 689 690 flags = le16toh(desc64->flags); 691 len = le16toh(desc64->length) & 0x3fff; 692 } else { 693 desc32 = &sc->rxq.desc32[sc->rxq.cur]; 694 nfe_rxdesc32_sync(sc, desc32, BUS_DMASYNC_POSTREAD); 695 696 flags = le16toh(desc32->flags); 697 len = le16toh(desc32->length) & 0x3fff; 698 } 699 700 if (flags & NFE_RX_READY) 701 break; 702 703 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 704 if (!(flags & NFE_RX_VALID_V1)) 705 goto skip; 706 707 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 708 flags &= ~NFE_RX_ERROR; 709 len--; /* fix buffer length */ 710 } 711 } else { 712 if (!(flags & NFE_RX_VALID_V2)) 713 goto skip; 714 715 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 716 flags &= ~NFE_RX_ERROR; 717 len--; /* fix buffer length */ 718 } 719 } 720 721 if (flags & NFE_RX_ERROR) { 722 ifp->if_ierrors++; 723 goto skip; 724 } 725 726 /* 727 * Try to allocate a new mbuf for this ring element and load 728 * it before processing the current mbuf. If the ring element 729 * cannot be loaded, drop the received packet and reuse the 730 * old mbuf. In the unlikely case that the old mbuf can't be 731 * reloaded either, explicitly panic. 732 */ 733 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 734 if (mnew == NULL) { 735 ifp->if_ierrors++; 736 goto skip; 737 } 738 739 if (sc->sc_flags & NFE_USE_JUMBO) { 740 if ((jbuf = nfe_jalloc(sc)) == NULL) { 741 m_freem(mnew); 742 ifp->if_ierrors++; 743 goto skip; 744 } 745 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 746 747 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 748 mtod(data->m, caddr_t) - sc->rxq.jpool, NFE_JBYTES, 749 BUS_DMASYNC_POSTREAD); 750 751 physaddr = jbuf->physaddr; 752 } else { 753 MCLGET(mnew, M_DONTWAIT); 754 if (!(mnew->m_flags & M_EXT)) { 755 m_freem(mnew); 756 ifp->if_ierrors++; 757 goto skip; 758 } 759 760 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 761 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 762 bus_dmamap_unload(sc->sc_dmat, data->map); 763 764 error = bus_dmamap_load(sc->sc_dmat, data->map, 765 mtod(mnew, void *), MCLBYTES, NULL, 766 BUS_DMA_READ | BUS_DMA_NOWAIT); 767 if (error != 0) { 768 m_freem(mnew); 769 770 /* try to reload the old mbuf */ 771 error = bus_dmamap_load(sc->sc_dmat, data->map, 772 mtod(data->m, void *), MCLBYTES, NULL, 773 BUS_DMA_READ | BUS_DMA_NOWAIT); 774 if (error != 0) { 775 /* very unlikely that it will fail.. */ 776 panic("%s: could not load old rx mbuf", 777 sc->sc_dev.dv_xname); 778 } 779 ifp->if_ierrors++; 780 goto skip; 781 } 782 physaddr = data->map->dm_segs[0].ds_addr; 783 } 784 785 /* 786 * New mbuf successfully loaded, update Rx ring and continue 787 * processing. 788 */ 789 m = data->m; 790 data->m = mnew; 791 792 /* finalize mbuf */ 793 m->m_pkthdr.len = m->m_len = len; 794 m->m_pkthdr.rcvif = ifp; 795 796 #ifdef notyet 797 if (sc->sc_flags & NFE_HW_CSUM) { 798 if (flags & NFE_RX_IP_CSUMOK) 799 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 800 if (flags & NFE_RX_UDP_CSUMOK) 801 m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK; 802 if (flags & NFE_RX_TCP_CSUMOK) 803 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK; 804 } 805 #elif defined(NFE_CSUM) 806 if ((sc->sc_flags & NFE_HW_CSUM) && (flags & NFE_RX_CSUMOK)) 807 m->m_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK; 808 #endif 809 810 #if NBPFILTER > 0 811 if (ifp->if_bpf) 812 bpf_mtap(ifp->if_bpf, m); 813 #endif 814 ifp->if_ipackets++; 815 (*ifp->if_input)(ifp, m); 816 817 /* update mapping address in h/w descriptor */ 818 if (sc->sc_flags & NFE_40BIT_ADDR) { 819 #if defined(__LP64__) 820 desc64->physaddr[0] = htole32(physaddr >> 32); 821 #endif 822 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 823 } else { 824 desc32->physaddr = htole32(physaddr); 825 } 826 827 skip: if (sc->sc_flags & NFE_40BIT_ADDR) { 828 desc64->length = htole16(sc->rxq.bufsz); 829 desc64->flags = htole16(NFE_RX_READY); 830 831 nfe_rxdesc64_sync(sc, desc64, BUS_DMASYNC_PREWRITE); 832 } else { 833 desc32->length = htole16(sc->rxq.bufsz); 834 desc32->flags = htole16(NFE_RX_READY); 835 836 nfe_rxdesc32_sync(sc, desc32, BUS_DMASYNC_PREWRITE); 837 } 838 839 sc->rxq.cur = (sc->rxq.cur + 1) % NFE_RX_RING_COUNT; 840 } 841 } 842 843 void 844 nfe_txeof(struct nfe_softc *sc) 845 { 846 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 847 struct nfe_desc32 *desc32; 848 struct nfe_desc64 *desc64; 849 struct nfe_tx_data *data = NULL; 850 uint16_t flags; 851 852 while (sc->txq.next != sc->txq.cur) { 853 if (sc->sc_flags & NFE_40BIT_ADDR) { 854 desc64 = &sc->txq.desc64[sc->txq.next]; 855 nfe_txdesc64_sync(sc, desc64, BUS_DMASYNC_POSTREAD); 856 857 flags = le16toh(desc64->flags); 858 } else { 859 desc32 = &sc->txq.desc32[sc->txq.next]; 860 nfe_txdesc32_sync(sc, desc32, BUS_DMASYNC_POSTREAD); 861 862 flags = le16toh(desc32->flags); 863 } 864 865 if (flags & NFE_TX_VALID) 866 break; 867 868 data = &sc->txq.data[sc->txq.next]; 869 870 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 871 if (!(flags & NFE_TX_LASTFRAG_V1) && data->m == NULL) 872 goto skip; 873 874 if ((flags & NFE_TX_ERROR_V1) != 0) { 875 printf("%s: tx v1 error 0x%04x\n", 876 sc->sc_dev.dv_xname, flags); 877 ifp->if_oerrors++; 878 } else 879 ifp->if_opackets++; 880 } else { 881 if (!(flags & NFE_TX_LASTFRAG_V2) && data->m == NULL) 882 goto skip; 883 884 if ((flags & NFE_TX_ERROR_V2) != 0) { 885 printf("%s: tx v2 error 0x%04x\n", 886 sc->sc_dev.dv_xname, flags); 887 ifp->if_oerrors++; 888 } else 889 ifp->if_opackets++; 890 } 891 892 if (data->m == NULL) { /* should not get there */ 893 printf("%s: last fragment bit w/o associated mbuf!\n", 894 sc->sc_dev.dv_xname); 895 goto skip; 896 } 897 898 /* last fragment of the mbuf chain transmitted */ 899 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 900 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 901 bus_dmamap_unload(sc->sc_dmat, data->active); 902 m_freem(data->m); 903 data->m = NULL; 904 905 ifp->if_timer = 0; 906 907 skip: sc->txq.queued--; 908 sc->txq.next = (sc->txq.next + 1) % NFE_TX_RING_COUNT; 909 } 910 911 if (data != NULL) { /* at least one slot freed */ 912 ifp->if_flags &= ~IFF_OACTIVE; 913 nfe_start(ifp); 914 } 915 } 916 917 int 918 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 919 { 920 struct nfe_desc32 *desc32; 921 struct nfe_desc64 *desc64; 922 struct nfe_tx_data *data; 923 bus_dmamap_t map; 924 uint16_t flags = NFE_TX_VALID; 925 #if NVLAN > 0 926 struct m_tag *mtag; 927 uint32_t vtag = 0; 928 #endif 929 int error, i; 930 931 desc32 = NULL; 932 desc64 = NULL; 933 data = NULL; 934 map = sc->txq.data[sc->txq.cur].map; 935 936 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 937 if (error != 0) { 938 printf("%s: could not map mbuf (error %d)\n", 939 sc->sc_dev.dv_xname, error); 940 return error; 941 } 942 943 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 944 bus_dmamap_unload(sc->sc_dmat, map); 945 return ENOBUFS; 946 } 947 948 #if NVLAN > 0 949 /* setup h/w VLAN tagging */ 950 if (sc->sc_ethercom.ec_nvlans) { 951 mtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL); 952 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 953 } 954 #endif 955 #ifdef NFE_CSUM 956 if (m0->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 957 flags |= NFE_TX_IP_CSUM; 958 if (m0->m_pkthdr.csum_flags & (M_TCPV4_CSUM_OUT | M_UDPV4_CSUM_OUT)) 959 flags |= NFE_TX_TCP_CSUM; 960 #endif 961 962 for (i = 0; i < map->dm_nsegs; i++) { 963 data = &sc->txq.data[sc->txq.cur]; 964 965 if (sc->sc_flags & NFE_40BIT_ADDR) { 966 desc64 = &sc->txq.desc64[sc->txq.cur]; 967 #if defined(__LP64__) 968 desc64->physaddr[0] = 969 htole32(map->dm_segs[i].ds_addr >> 32); 970 #endif 971 desc64->physaddr[1] = 972 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 973 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 974 desc64->flags = htole16(flags); 975 #if NVLAN > 0 976 desc64->vtag = htole32(vtag); 977 #endif 978 } else { 979 desc32 = &sc->txq.desc32[sc->txq.cur]; 980 981 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 982 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 983 desc32->flags = htole16(flags); 984 } 985 986 /* csum flags and vtag belong to the first fragment only */ 987 if (map->dm_nsegs > 1) { 988 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_CSUM); 989 #if NVLAN > 0 990 vtag = 0; 991 #endif 992 } 993 994 sc->txq.queued++; 995 sc->txq.cur = (sc->txq.cur + 1) % NFE_TX_RING_COUNT; 996 } 997 998 /* the whole mbuf chain has been DMA mapped, fix last descriptor */ 999 if (sc->sc_flags & NFE_40BIT_ADDR) { 1000 flags |= NFE_TX_LASTFRAG_V2; 1001 desc64->flags = htole16(flags); 1002 } else { 1003 if (sc->sc_flags & NFE_JUMBO_SUP) 1004 flags |= NFE_TX_LASTFRAG_V2; 1005 else 1006 flags |= NFE_TX_LASTFRAG_V1; 1007 desc32->flags = htole16(flags); 1008 } 1009 1010 data->m = m0; 1011 data->active = map; 1012 1013 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1014 BUS_DMASYNC_PREWRITE); 1015 1016 return 0; 1017 } 1018 1019 void 1020 nfe_start(struct ifnet *ifp) 1021 { 1022 struct nfe_softc *sc = ifp->if_softc; 1023 int old = sc->txq.cur; 1024 struct mbuf *m0; 1025 1026 for (;;) { 1027 IFQ_POLL(&ifp->if_snd, m0); 1028 if (m0 == NULL) 1029 break; 1030 1031 if (nfe_encap(sc, m0) != 0) { 1032 ifp->if_flags |= IFF_OACTIVE; 1033 break; 1034 } 1035 1036 /* packet put in h/w queue, remove from s/w queue */ 1037 IFQ_DEQUEUE(&ifp->if_snd, m0); 1038 1039 #if NBPFILTER > 0 1040 if (ifp->if_bpf != NULL) 1041 bpf_mtap(ifp->if_bpf, m0); 1042 #endif 1043 } 1044 if (sc->txq.cur == old) /* nothing sent */ 1045 return; 1046 1047 if (sc->sc_flags & NFE_40BIT_ADDR) 1048 nfe_txdesc64_rsync(sc, old, sc->txq.cur, BUS_DMASYNC_PREWRITE); 1049 else 1050 nfe_txdesc32_rsync(sc, old, sc->txq.cur, BUS_DMASYNC_PREWRITE); 1051 1052 /* kick Tx */ 1053 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1054 1055 /* 1056 * Set a timeout in case the chip goes out to lunch. 1057 */ 1058 ifp->if_timer = 5; 1059 } 1060 1061 void 1062 nfe_watchdog(struct ifnet *ifp) 1063 { 1064 struct nfe_softc *sc = ifp->if_softc; 1065 1066 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1067 1068 ifp->if_flags &= ~IFF_RUNNING; 1069 nfe_init(ifp); 1070 1071 ifp->if_oerrors++; 1072 } 1073 1074 int 1075 nfe_init(struct ifnet *ifp) 1076 { 1077 struct nfe_softc *sc = ifp->if_softc; 1078 uint32_t tmp; 1079 1080 if (ifp->if_flags & IFF_RUNNING) 1081 return 0; 1082 1083 nfe_stop(ifp, 0); 1084 1085 NFE_WRITE(sc, NFE_TX_UNK, 0); 1086 NFE_WRITE(sc, NFE_STATUS, 0); 1087 1088 sc->rxtxctl = NFE_RXTX_BIT2; 1089 if (sc->sc_flags & NFE_40BIT_ADDR) 1090 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1091 else if (sc->sc_flags & NFE_JUMBO_SUP) 1092 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1093 #ifdef NFE_CSUM 1094 if (sc->sc_flags & NFE_HW_CSUM) 1095 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1096 #endif 1097 #if NVLAN > 0 1098 /* 1099 * Although the adapter is capable of stripping VLAN tags from received 1100 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1101 * purpose. This will be done in software by our network stack. 1102 */ 1103 if (sc->sc_flags & NFE_HW_VLAN) 1104 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1105 #endif 1106 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1107 DELAY(10); 1108 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1109 1110 #if NVLAN 1111 if (sc->sc_flags & NFE_HW_VLAN) 1112 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1113 #endif 1114 1115 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1116 1117 /* set MAC address */ 1118 nfe_set_macaddr(sc, sc->sc_enaddr); 1119 1120 /* tell MAC where rings are in memory */ 1121 #ifdef __LP64__ 1122 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1123 #endif 1124 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1125 #ifdef __LP64__ 1126 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1127 #endif 1128 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1129 1130 NFE_WRITE(sc, NFE_RING_SIZE, 1131 (NFE_RX_RING_COUNT - 1) << 16 | 1132 (NFE_TX_RING_COUNT - 1)); 1133 1134 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1135 1136 /* force MAC to wakeup */ 1137 tmp = NFE_READ(sc, NFE_PWR_STATE); 1138 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1139 DELAY(10); 1140 tmp = NFE_READ(sc, NFE_PWR_STATE); 1141 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1142 1143 #if 1 1144 /* configure interrupts coalescing/mitigation */ 1145 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1146 #else 1147 /* no interrupt mitigation: one interrupt per packet */ 1148 NFE_WRITE(sc, NFE_IMTIMER, 970); 1149 #endif 1150 1151 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1152 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1153 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1154 1155 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1156 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1157 1158 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1159 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC); 1160 1161 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1162 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1163 DELAY(10); 1164 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1165 1166 /* set Rx filter */ 1167 nfe_setmulti(sc); 1168 1169 nfe_ifmedia_upd(ifp); 1170 1171 /* enable Rx */ 1172 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1173 1174 /* enable Tx */ 1175 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1176 1177 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1178 1179 /* enable interrupts */ 1180 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1181 1182 callout_schedule(&sc->sc_tick_ch, hz); 1183 1184 ifp->if_flags |= IFF_RUNNING; 1185 ifp->if_flags &= ~IFF_OACTIVE; 1186 1187 return 0; 1188 } 1189 1190 void 1191 nfe_stop(struct ifnet *ifp, int disable) 1192 { 1193 struct nfe_softc *sc = ifp->if_softc; 1194 1195 callout_stop(&sc->sc_tick_ch); 1196 1197 ifp->if_timer = 0; 1198 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1199 1200 mii_down(&sc->sc_mii); 1201 1202 /* abort Tx */ 1203 NFE_WRITE(sc, NFE_TX_CTL, 0); 1204 1205 /* disable Rx */ 1206 NFE_WRITE(sc, NFE_RX_CTL, 0); 1207 1208 /* disable interrupts */ 1209 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1210 1211 /* reset Tx and Rx rings */ 1212 nfe_reset_tx_ring(sc, &sc->txq); 1213 nfe_reset_rx_ring(sc, &sc->rxq); 1214 } 1215 1216 int 1217 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1218 { 1219 struct nfe_desc32 *desc32; 1220 struct nfe_desc64 *desc64; 1221 struct nfe_rx_data *data; 1222 struct nfe_jbuf *jbuf; 1223 void **desc; 1224 bus_addr_t physaddr; 1225 int i, nsegs, error, descsize; 1226 1227 if (sc->sc_flags & NFE_40BIT_ADDR) { 1228 desc = (void **)&ring->desc64; 1229 descsize = sizeof (struct nfe_desc64); 1230 } else { 1231 desc = (void **)&ring->desc32; 1232 descsize = sizeof (struct nfe_desc32); 1233 } 1234 1235 ring->cur = ring->next = 0; 1236 ring->bufsz = MCLBYTES; 1237 1238 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1239 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1240 if (error != 0) { 1241 printf("%s: could not create desc DMA map\n", 1242 sc->sc_dev.dv_xname); 1243 goto fail; 1244 } 1245 1246 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1247 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1248 if (error != 0) { 1249 printf("%s: could not allocate DMA memory\n", 1250 sc->sc_dev.dv_xname); 1251 goto fail; 1252 } 1253 1254 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1255 NFE_RX_RING_COUNT * descsize, (caddr_t *)desc, BUS_DMA_NOWAIT); 1256 if (error != 0) { 1257 printf("%s: could not map desc DMA memory\n", 1258 sc->sc_dev.dv_xname); 1259 goto fail; 1260 } 1261 1262 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1263 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1264 if (error != 0) { 1265 printf("%s: could not load desc DMA map\n", 1266 sc->sc_dev.dv_xname); 1267 goto fail; 1268 } 1269 1270 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1271 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1272 1273 if (sc->sc_flags & NFE_USE_JUMBO) { 1274 ring->bufsz = NFE_JBYTES; 1275 if ((error = nfe_jpool_alloc(sc)) != 0) { 1276 printf("%s: could not allocate jumbo frames\n", 1277 sc->sc_dev.dv_xname); 1278 goto fail; 1279 } 1280 } 1281 1282 /* 1283 * Pre-allocate Rx buffers and populate Rx ring. 1284 */ 1285 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1286 data = &sc->rxq.data[i]; 1287 1288 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1289 if (data->m == NULL) { 1290 printf("%s: could not allocate rx mbuf\n", 1291 sc->sc_dev.dv_xname); 1292 error = ENOMEM; 1293 goto fail; 1294 } 1295 1296 if (sc->sc_flags & NFE_USE_JUMBO) { 1297 if ((jbuf = nfe_jalloc(sc)) == NULL) { 1298 printf("%s: could not allocate jumbo buffer\n", 1299 sc->sc_dev.dv_xname); 1300 goto fail; 1301 } 1302 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1303 sc); 1304 1305 physaddr = jbuf->physaddr; 1306 } else { 1307 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1308 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1309 if (error != 0) { 1310 printf("%s: could not create DMA map\n", 1311 sc->sc_dev.dv_xname); 1312 goto fail; 1313 } 1314 MCLGET(data->m, M_DONTWAIT); 1315 if (!(data->m->m_flags & M_EXT)) { 1316 printf("%s: could not allocate mbuf cluster\n", 1317 sc->sc_dev.dv_xname); 1318 error = ENOMEM; 1319 goto fail; 1320 } 1321 1322 error = bus_dmamap_load(sc->sc_dmat, data->map, 1323 mtod(data->m, void *), MCLBYTES, NULL, 1324 BUS_DMA_READ | BUS_DMA_NOWAIT); 1325 if (error != 0) { 1326 printf("%s: could not load rx buf DMA map", 1327 sc->sc_dev.dv_xname); 1328 goto fail; 1329 } 1330 physaddr = data->map->dm_segs[0].ds_addr; 1331 } 1332 1333 if (sc->sc_flags & NFE_40BIT_ADDR) { 1334 desc64 = &sc->rxq.desc64[i]; 1335 #if defined(__LP64__) 1336 desc64->physaddr[0] = htole32(physaddr >> 32); 1337 #endif 1338 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1339 desc64->length = htole16(sc->rxq.bufsz); 1340 desc64->flags = htole16(NFE_RX_READY); 1341 } else { 1342 desc32 = &sc->rxq.desc32[i]; 1343 desc32->physaddr = htole32(physaddr); 1344 desc32->length = htole16(sc->rxq.bufsz); 1345 desc32->flags = htole16(NFE_RX_READY); 1346 } 1347 } 1348 1349 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1350 BUS_DMASYNC_PREWRITE); 1351 1352 return 0; 1353 1354 fail: nfe_free_rx_ring(sc, ring); 1355 return error; 1356 } 1357 1358 void 1359 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1360 { 1361 int i; 1362 1363 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1364 if (sc->sc_flags & NFE_40BIT_ADDR) { 1365 ring->desc64[i].length = htole16(ring->bufsz); 1366 ring->desc64[i].flags = htole16(NFE_RX_READY); 1367 } else { 1368 ring->desc32[i].length = htole16(ring->bufsz); 1369 ring->desc32[i].flags = htole16(NFE_RX_READY); 1370 } 1371 } 1372 1373 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1374 BUS_DMASYNC_PREWRITE); 1375 1376 ring->cur = ring->next = 0; 1377 } 1378 1379 void 1380 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1381 { 1382 struct nfe_rx_data *data; 1383 void *desc; 1384 int i, descsize; 1385 1386 if (sc->sc_flags & NFE_40BIT_ADDR) { 1387 desc = ring->desc64; 1388 descsize = sizeof (struct nfe_desc64); 1389 } else { 1390 desc = ring->desc32; 1391 descsize = sizeof (struct nfe_desc32); 1392 } 1393 1394 if (desc != NULL) { 1395 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1396 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1397 bus_dmamap_unload(sc->sc_dmat, ring->map); 1398 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)desc, 1399 NFE_RX_RING_COUNT * descsize); 1400 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1401 } 1402 1403 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1404 data = &ring->data[i]; 1405 1406 if (data->map != NULL) { 1407 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1408 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1409 bus_dmamap_unload(sc->sc_dmat, data->map); 1410 bus_dmamap_destroy(sc->sc_dmat, data->map); 1411 } 1412 if (data->m != NULL) 1413 m_freem(data->m); 1414 } 1415 } 1416 1417 struct nfe_jbuf * 1418 nfe_jalloc(struct nfe_softc *sc) 1419 { 1420 struct nfe_jbuf *jbuf; 1421 1422 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1423 if (jbuf == NULL) 1424 return NULL; 1425 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1426 return jbuf; 1427 } 1428 1429 /* 1430 * This is called automatically by the network stack when the mbuf is freed. 1431 * Caution must be taken that the NIC might be reset by the time the mbuf is 1432 * freed. 1433 */ 1434 void 1435 nfe_jfree(struct mbuf *m, caddr_t buf, size_t size, void *arg) 1436 { 1437 struct nfe_softc *sc = arg; 1438 struct nfe_jbuf *jbuf; 1439 int i; 1440 1441 /* find the jbuf from the base pointer */ 1442 i = (buf - sc->rxq.jpool) / NFE_JBYTES; 1443 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1444 printf("%s: request to free a buffer (%p) not managed by us\n", 1445 sc->sc_dev.dv_xname, buf); 1446 return; 1447 } 1448 jbuf = &sc->rxq.jbuf[i]; 1449 1450 /* ..and put it back in the free list */ 1451 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1452 1453 if (m != NULL) 1454 pool_cache_put(&mbpool_cache, m); 1455 } 1456 1457 int 1458 nfe_jpool_alloc(struct nfe_softc *sc) 1459 { 1460 struct nfe_rx_ring *ring = &sc->rxq; 1461 struct nfe_jbuf *jbuf; 1462 bus_addr_t physaddr; 1463 caddr_t buf; 1464 int i, nsegs, error; 1465 1466 /* 1467 * Allocate a big chunk of DMA'able memory. 1468 */ 1469 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1470 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1471 if (error != 0) { 1472 printf("%s: could not create jumbo DMA map\n", 1473 sc->sc_dev.dv_xname); 1474 goto fail; 1475 } 1476 1477 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1478 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1479 if (error != 0) { 1480 printf("%s could not allocate jumbo DMA memory\n", 1481 sc->sc_dev.dv_xname); 1482 goto fail; 1483 } 1484 1485 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1486 &ring->jpool, BUS_DMA_NOWAIT); 1487 if (error != 0) { 1488 printf("%s: could not map jumbo DMA memory\n", 1489 sc->sc_dev.dv_xname); 1490 goto fail; 1491 } 1492 1493 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1494 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1495 if (error != 0) { 1496 printf("%s: could not load jumbo DMA map\n", 1497 sc->sc_dev.dv_xname); 1498 goto fail; 1499 } 1500 1501 /* ..and split it into 9KB chunks */ 1502 SLIST_INIT(&ring->jfreelist); 1503 1504 buf = ring->jpool; 1505 physaddr = ring->jmap->dm_segs[0].ds_addr; 1506 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1507 jbuf = &ring->jbuf[i]; 1508 1509 jbuf->buf = buf; 1510 jbuf->physaddr = physaddr; 1511 1512 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1513 1514 buf += NFE_JBYTES; 1515 physaddr += NFE_JBYTES; 1516 } 1517 1518 return 0; 1519 1520 fail: nfe_jpool_free(sc); 1521 return error; 1522 } 1523 1524 void 1525 nfe_jpool_free(struct nfe_softc *sc) 1526 { 1527 struct nfe_rx_ring *ring = &sc->rxq; 1528 1529 if (ring->jmap != NULL) { 1530 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1531 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1532 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1533 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1534 } 1535 if (ring->jpool != NULL) { 1536 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1537 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1538 } 1539 } 1540 1541 int 1542 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1543 { 1544 int i, nsegs, error; 1545 void **desc; 1546 int descsize; 1547 1548 if (sc->sc_flags & NFE_40BIT_ADDR) { 1549 desc = (void **)&ring->desc64; 1550 descsize = sizeof (struct nfe_desc64); 1551 } else { 1552 desc = (void **)&ring->desc32; 1553 descsize = sizeof (struct nfe_desc32); 1554 } 1555 1556 ring->queued = 0; 1557 ring->cur = ring->next = 0; 1558 1559 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1560 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1561 1562 if (error != 0) { 1563 printf("%s: could not create desc DMA map\n", 1564 sc->sc_dev.dv_xname); 1565 goto fail; 1566 } 1567 1568 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1569 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1570 if (error != 0) { 1571 printf("%s: could not allocate DMA memory\n", 1572 sc->sc_dev.dv_xname); 1573 goto fail; 1574 } 1575 1576 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1577 NFE_TX_RING_COUNT * descsize, (caddr_t *)desc, BUS_DMA_NOWAIT); 1578 if (error != 0) { 1579 printf("%s: could not map desc DMA memory\n", 1580 sc->sc_dev.dv_xname); 1581 goto fail; 1582 } 1583 1584 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1585 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1586 if (error != 0) { 1587 printf("%s: could not load desc DMA map\n", 1588 sc->sc_dev.dv_xname); 1589 goto fail; 1590 } 1591 1592 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1593 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1594 1595 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1596 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1597 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1598 &ring->data[i].map); 1599 if (error != 0) { 1600 printf("%s: could not create DMA map\n", 1601 sc->sc_dev.dv_xname); 1602 goto fail; 1603 } 1604 } 1605 1606 return 0; 1607 1608 fail: nfe_free_tx_ring(sc, ring); 1609 return error; 1610 } 1611 1612 void 1613 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1614 { 1615 struct nfe_tx_data *data; 1616 int i; 1617 1618 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1619 if (sc->sc_flags & NFE_40BIT_ADDR) 1620 ring->desc64[i].flags = 0; 1621 else 1622 ring->desc32[i].flags = 0; 1623 1624 data = &ring->data[i]; 1625 1626 if (data->m != NULL) { 1627 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1628 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1629 bus_dmamap_unload(sc->sc_dmat, data->active); 1630 m_freem(data->m); 1631 data->m = NULL; 1632 } 1633 } 1634 1635 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1636 BUS_DMASYNC_PREWRITE); 1637 1638 ring->queued = 0; 1639 ring->cur = ring->next = 0; 1640 } 1641 1642 void 1643 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1644 { 1645 struct nfe_tx_data *data; 1646 void *desc; 1647 int i, descsize; 1648 1649 if (sc->sc_flags & NFE_40BIT_ADDR) { 1650 desc = ring->desc64; 1651 descsize = sizeof (struct nfe_desc64); 1652 } else { 1653 desc = ring->desc32; 1654 descsize = sizeof (struct nfe_desc32); 1655 } 1656 1657 if (desc != NULL) { 1658 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1659 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1660 bus_dmamap_unload(sc->sc_dmat, ring->map); 1661 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)desc, 1662 NFE_TX_RING_COUNT * descsize); 1663 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1664 } 1665 1666 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1667 data = &ring->data[i]; 1668 1669 if (data->m != NULL) { 1670 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1671 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1672 bus_dmamap_unload(sc->sc_dmat, data->active); 1673 m_freem(data->m); 1674 } 1675 } 1676 1677 /* ..and now actually destroy the DMA mappings */ 1678 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1679 data = &ring->data[i]; 1680 if (data->map == NULL) 1681 continue; 1682 bus_dmamap_destroy(sc->sc_dmat, data->map); 1683 } 1684 } 1685 1686 int 1687 nfe_ifmedia_upd(struct ifnet *ifp) 1688 { 1689 struct nfe_softc *sc = ifp->if_softc; 1690 struct mii_data *mii = &sc->sc_mii; 1691 struct mii_softc *miisc; 1692 1693 if (mii->mii_instance != 0) { 1694 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1695 mii_phy_reset(miisc); 1696 } 1697 return mii_mediachg(mii); 1698 } 1699 1700 void 1701 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1702 { 1703 struct nfe_softc *sc = ifp->if_softc; 1704 struct mii_data *mii = &sc->sc_mii; 1705 1706 mii_pollstat(mii); 1707 ifmr->ifm_status = mii->mii_media_status; 1708 ifmr->ifm_active = mii->mii_media_active; 1709 } 1710 1711 void 1712 nfe_setmulti(struct nfe_softc *sc) 1713 { 1714 struct ethercom *ec = &sc->sc_ethercom; 1715 struct ifnet *ifp = &ec->ec_if; 1716 struct ether_multi *enm; 1717 struct ether_multistep step; 1718 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1719 uint32_t filter = NFE_RXFILTER_MAGIC; 1720 int i; 1721 1722 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1723 bzero(addr, ETHER_ADDR_LEN); 1724 bzero(mask, ETHER_ADDR_LEN); 1725 goto done; 1726 } 1727 1728 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1729 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1730 1731 ETHER_FIRST_MULTI(step, ec, enm); 1732 while (enm != NULL) { 1733 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1734 ifp->if_flags |= IFF_ALLMULTI; 1735 bzero(addr, ETHER_ADDR_LEN); 1736 bzero(mask, ETHER_ADDR_LEN); 1737 goto done; 1738 } 1739 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1740 addr[i] &= enm->enm_addrlo[i]; 1741 mask[i] &= ~enm->enm_addrlo[i]; 1742 } 1743 ETHER_NEXT_MULTI(step, enm); 1744 } 1745 for (i = 0; i < ETHER_ADDR_LEN; i++) 1746 mask[i] |= addr[i]; 1747 1748 done: 1749 addr[0] |= 0x01; /* make sure multicast bit is set */ 1750 1751 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1752 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1753 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1754 addr[5] << 8 | addr[4]); 1755 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1756 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1757 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1758 mask[5] << 8 | mask[4]); 1759 1760 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1761 NFE_WRITE(sc, NFE_RXFILTER, filter); 1762 } 1763 1764 void 1765 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1766 { 1767 uint32_t tmp; 1768 1769 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1770 addr[0] = (tmp >> 8) & 0xff; 1771 addr[1] = (tmp & 0xff); 1772 1773 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1774 addr[2] = (tmp >> 24) & 0xff; 1775 addr[3] = (tmp >> 16) & 0xff; 1776 addr[4] = (tmp >> 8) & 0xff; 1777 addr[5] = (tmp & 0xff); 1778 } 1779 1780 void 1781 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1782 { 1783 NFE_WRITE(sc, NFE_MACADDR_LO, 1784 addr[5] << 8 | addr[4]); 1785 NFE_WRITE(sc, NFE_MACADDR_HI, 1786 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1787 } 1788 1789 void 1790 nfe_tick(void *arg) 1791 { 1792 struct nfe_softc *sc = arg; 1793 int s; 1794 1795 s = splnet(); 1796 mii_tick(&sc->sc_mii); 1797 splx(s); 1798 1799 callout_schedule(&sc->sc_tick_ch, hz); 1800 } 1801
Indexes created Tue Sep 30 20:09:53 GMT 2025