if_nfe.c revision 1.40
1 /* $NetBSD: if_nfe.c,v 1.40 2009/02/12 10:33:23 cegger Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.77 2008/02/05 16:52:50 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006, 2007 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.40 2009/02/12 10:33:23 cegger Exp $"); 25 26 #include "opt_inet.h" 27 #include "bpfilter.h" 28 #include "vlan.h" 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/types.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/mutex.h> 37 #include <sys/queue.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/callout.h> 41 #include <sys/socket.h> 42 43 #include <sys/bus.h> 44 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 #include <net/if_ether.h> 49 #include <net/if_arp.h> 50 51 #ifdef INET 52 #include <netinet/in.h> 53 #include <netinet/in_systm.h> 54 #include <netinet/in_var.h> 55 #include <netinet/ip.h> 56 #include <netinet/if_inarp.h> 57 #endif 58 59 #if NVLAN > 0 60 #include <net/if_types.h> 61 #endif 62 63 #if NBPFILTER > 0 64 #include <net/bpf.h> 65 #endif 66 67 #include <dev/mii/mii.h> 68 #include <dev/mii/miivar.h> 69 70 #include <dev/pci/pcireg.h> 71 #include <dev/pci/pcivar.h> 72 #include <dev/pci/pcidevs.h> 73 74 #include <dev/pci/if_nfereg.h> 75 #include <dev/pci/if_nfevar.h> 76 77 static int nfe_ifflags_cb(struct ethercom *); 78 79 int nfe_match(device_t, cfdata_t, void *); 80 void nfe_attach(device_t, device_t, void *); 81 void nfe_power(int, void *); 82 void nfe_miibus_statchg(device_t); 83 int nfe_miibus_readreg(device_t, int, int); 84 void nfe_miibus_writereg(device_t, int, int, int); 85 int nfe_intr(void *); 86 int nfe_ioctl(struct ifnet *, u_long, void *); 87 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 88 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 89 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 90 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 91 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 92 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 93 void nfe_rxeof(struct nfe_softc *); 94 void nfe_txeof(struct nfe_softc *); 95 int nfe_encap(struct nfe_softc *, struct mbuf *); 96 void nfe_start(struct ifnet *); 97 void nfe_watchdog(struct ifnet *); 98 int nfe_init(struct ifnet *); 99 void nfe_stop(struct ifnet *, int); 100 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 101 void nfe_jfree(struct mbuf *, void *, size_t, void *); 102 int nfe_jpool_alloc(struct nfe_softc *); 103 void nfe_jpool_free(struct nfe_softc *); 104 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 105 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 106 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 107 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 108 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 109 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 110 void nfe_setmulti(struct nfe_softc *); 111 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 112 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 113 void nfe_tick(void *); 114 void nfe_poweron(device_t); 115 bool nfe_resume(device_t PMF_FN_PROTO); 116 117 CFATTACH_DECL_NEW(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, 118 NULL, NULL); 119 120 /* #define NFE_NO_JUMBO */ 121 122 #ifdef NFE_DEBUG 123 int nfedebug = 0; 124 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 125 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 126 #else 127 #define DPRINTF(x) 128 #define DPRINTFN(n,x) 129 #endif 130 131 /* deal with naming differences */ 132 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 134 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 135 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 136 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 137 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 138 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 139 140 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 141 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 142 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 143 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 144 145 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 146 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 147 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 148 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 149 150 #ifdef _LP64 151 #define __LP64__ 1 152 #endif 153 154 const struct nfe_product { 155 pci_vendor_id_t vendor; 156 pci_product_id_t product; 157 } nfe_devices[] = { 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 183 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 184 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 185 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 186 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 187 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 188 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 }, 189 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1 }, 190 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2 }, 191 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3 }, 192 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4 }, 193 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1 }, 194 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2 }, 195 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3 }, 196 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4 } 197 }; 198 199 int 200 nfe_match(device_t dev, cfdata_t match, void *aux) 201 { 202 struct pci_attach_args *pa = aux; 203 const struct nfe_product *np; 204 int i; 205 206 for (i = 0; i < sizeof(nfe_devices) / sizeof(nfe_devices[0]); i++) { 207 np = &nfe_devices[i]; 208 if (PCI_VENDOR(pa->pa_id) == np->vendor && 209 PCI_PRODUCT(pa->pa_id) == np->product) 210 return 1; 211 } 212 return 0; 213 } 214 215 void 216 nfe_attach(device_t parent, device_t self, void *aux) 217 { 218 struct nfe_softc *sc = device_private(self); 219 struct pci_attach_args *pa = aux; 220 pci_chipset_tag_t pc = pa->pa_pc; 221 pci_intr_handle_t ih; 222 const char *intrstr; 223 struct ifnet *ifp; 224 bus_size_t memsize; 225 pcireg_t memtype; 226 char devinfo[256]; 227 int mii_flags = 0; 228 229 sc->sc_dev = self; 230 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 231 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 232 233 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 234 switch (memtype) { 235 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 236 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 237 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 238 &sc->sc_memh, NULL, &memsize) == 0) 239 break; 240 /* FALLTHROUGH */ 241 default: 242 aprint_error_dev(self, "could not map mem space\n"); 243 return; 244 } 245 246 if (pci_intr_map(pa, &ih) != 0) { 247 aprint_error_dev(self, "could not map interrupt\n"); 248 return; 249 } 250 251 intrstr = pci_intr_string(pc, ih); 252 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 253 if (sc->sc_ih == NULL) { 254 aprint_error_dev(self, "could not establish interrupt"); 255 if (intrstr != NULL) 256 aprint_normal(" at %s", intrstr); 257 aprint_normal("\n"); 258 return; 259 } 260 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 261 262 sc->sc_dmat = pa->pa_dmat; 263 264 sc->sc_flags = 0; 265 266 switch (PCI_PRODUCT(pa->pa_id)) { 267 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 268 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 269 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 270 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 271 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 272 break; 273 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 274 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 275 sc->sc_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT; 276 break; 277 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 278 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 279 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 280 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 281 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 282 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 283 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 284 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 285 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 286 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 287 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 288 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 289 sc->sc_flags |= NFE_40BIT_ADDR | NFE_CORRECT_MACADDR | 290 NFE_PWR_MGMT; 291 break; 292 case PCI_PRODUCT_NVIDIA_MCP77_LAN1: 293 case PCI_PRODUCT_NVIDIA_MCP77_LAN2: 294 case PCI_PRODUCT_NVIDIA_MCP77_LAN3: 295 case PCI_PRODUCT_NVIDIA_MCP77_LAN4: 296 case PCI_PRODUCT_NVIDIA_MCP79_LAN1: 297 case PCI_PRODUCT_NVIDIA_MCP79_LAN2: 298 case PCI_PRODUCT_NVIDIA_MCP79_LAN3: 299 case PCI_PRODUCT_NVIDIA_MCP79_LAN4: 300 sc->sc_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | 301 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 302 break; 303 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 304 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 305 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 306 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 307 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 308 break; 309 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 310 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 311 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 312 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 313 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 314 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 315 mii_flags = MIIF_DOPAUSE; 316 break; 317 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 318 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 319 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 320 NFE_HW_VLAN | NFE_PWR_MGMT; 321 break; 322 } 323 324 nfe_poweron(self); 325 326 #ifndef NFE_NO_JUMBO 327 /* enable jumbo frames for adapters that support it */ 328 if (sc->sc_flags & NFE_JUMBO_SUP) 329 sc->sc_flags |= NFE_USE_JUMBO; 330 #endif 331 332 /* Check for reversed ethernet address */ 333 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 334 sc->sc_flags |= NFE_CORRECT_MACADDR; 335 336 nfe_get_macaddr(sc, sc->sc_enaddr); 337 aprint_normal_dev(self, "Ethernet address %s\n", 338 ether_sprintf(sc->sc_enaddr)); 339 340 /* 341 * Allocate Tx and Rx rings. 342 */ 343 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 344 aprint_error_dev(self, "could not allocate Tx ring\n"); 345 return; 346 } 347 348 mutex_init(&sc->rxq.mtx, MUTEX_DEFAULT, IPL_NET); 349 350 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 351 aprint_error_dev(self, "could not allocate Rx ring\n"); 352 nfe_free_tx_ring(sc, &sc->txq); 353 return; 354 } 355 356 ifp = &sc->sc_ethercom.ec_if; 357 ifp->if_softc = sc; 358 ifp->if_mtu = ETHERMTU; 359 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 360 ifp->if_ioctl = nfe_ioctl; 361 ifp->if_start = nfe_start; 362 ifp->if_stop = nfe_stop; 363 ifp->if_watchdog = nfe_watchdog; 364 ifp->if_init = nfe_init; 365 ifp->if_baudrate = IF_Gbps(1); 366 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 367 IFQ_SET_READY(&ifp->if_snd); 368 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 369 370 if (sc->sc_flags & NFE_USE_JUMBO) 371 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 372 373 #if NVLAN > 0 374 if (sc->sc_flags & NFE_HW_VLAN) 375 sc->sc_ethercom.ec_capabilities |= 376 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 377 #endif 378 if (sc->sc_flags & NFE_HW_CSUM) { 379 ifp->if_capabilities |= 380 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 381 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 382 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 383 } 384 385 sc->sc_mii.mii_ifp = ifp; 386 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 387 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 388 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 389 390 sc->sc_ethercom.ec_mii = &sc->sc_mii; 391 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 392 ether_mediastatus); 393 394 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 395 MII_OFFSET_ANY, mii_flags); 396 397 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 398 aprint_error_dev(self, "no PHY found!\n"); 399 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 400 0, NULL); 401 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 402 } else 403 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 404 405 if_attach(ifp); 406 ether_ifattach(ifp, sc->sc_enaddr); 407 ether_set_ifflags_cb(&sc->sc_ethercom, nfe_ifflags_cb); 408 409 callout_init(&sc->sc_tick_ch, 0); 410 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 411 412 if (!pmf_device_register(self, NULL, nfe_resume)) 413 aprint_error_dev(self, "couldn't establish power handler\n"); 414 else 415 pmf_class_network_register(self, ifp); 416 } 417 418 void 419 nfe_miibus_statchg(device_t dev) 420 { 421 struct nfe_softc *sc = device_private(dev); 422 struct mii_data *mii = &sc->sc_mii; 423 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 424 425 phy = NFE_READ(sc, NFE_PHY_IFACE); 426 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 427 428 seed = NFE_READ(sc, NFE_RNDSEED); 429 seed &= ~NFE_SEED_MASK; 430 431 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 432 phy |= NFE_PHY_HDX; /* half-duplex */ 433 misc |= NFE_MISC1_HDX; 434 } 435 436 switch (IFM_SUBTYPE(mii->mii_media_active)) { 437 case IFM_1000_T: /* full-duplex only */ 438 link |= NFE_MEDIA_1000T; 439 seed |= NFE_SEED_1000T; 440 phy |= NFE_PHY_1000T; 441 break; 442 case IFM_100_TX: 443 link |= NFE_MEDIA_100TX; 444 seed |= NFE_SEED_100TX; 445 phy |= NFE_PHY_100TX; 446 break; 447 case IFM_10_T: 448 link |= NFE_MEDIA_10T; 449 seed |= NFE_SEED_10T; 450 break; 451 } 452 453 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 454 455 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 456 NFE_WRITE(sc, NFE_MISC1, misc); 457 NFE_WRITE(sc, NFE_LINKSPEED, link); 458 } 459 460 int 461 nfe_miibus_readreg(device_t dev, int phy, int reg) 462 { 463 struct nfe_softc *sc = device_private(dev); 464 uint32_t val; 465 int ntries; 466 467 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 468 469 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 470 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 471 DELAY(100); 472 } 473 474 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 475 476 for (ntries = 0; ntries < 1000; ntries++) { 477 DELAY(100); 478 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 479 break; 480 } 481 if (ntries == 1000) { 482 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 483 device_xname(sc->sc_dev))); 484 return 0; 485 } 486 487 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 488 DPRINTFN(2, ("%s: could not read PHY\n", 489 device_xname(sc->sc_dev))); 490 return 0; 491 } 492 493 val = NFE_READ(sc, NFE_PHY_DATA); 494 if (val != 0xffffffff && val != 0) 495 sc->mii_phyaddr = phy; 496 497 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 498 device_xname(sc->sc_dev), phy, reg, val)); 499 500 return val; 501 } 502 503 void 504 nfe_miibus_writereg(device_t dev, int phy, int reg, int val) 505 { 506 struct nfe_softc *sc = device_private(dev); 507 uint32_t ctl; 508 int ntries; 509 510 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 511 512 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 513 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 514 DELAY(100); 515 } 516 517 NFE_WRITE(sc, NFE_PHY_DATA, val); 518 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 519 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 520 521 for (ntries = 0; ntries < 1000; ntries++) { 522 DELAY(100); 523 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 524 break; 525 } 526 #ifdef NFE_DEBUG 527 if (nfedebug >= 2 && ntries == 1000) 528 printf("could not write to PHY\n"); 529 #endif 530 } 531 532 int 533 nfe_intr(void *arg) 534 { 535 struct nfe_softc *sc = arg; 536 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 537 uint32_t r; 538 int handled; 539 540 if ((ifp->if_flags & IFF_UP) == 0) 541 return 0; 542 543 handled = 0; 544 545 for (;;) { 546 r = NFE_READ(sc, NFE_IRQ_STATUS); 547 if ((r & NFE_IRQ_WANTED) == 0) 548 break; 549 550 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 551 handled = 1; 552 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 553 554 if ((r & (NFE_IRQ_RXERR|NFE_IRQ_RX_NOBUF|NFE_IRQ_RX)) != 0) { 555 /* check Rx ring */ 556 nfe_rxeof(sc); 557 } 558 if ((r & (NFE_IRQ_TXERR|NFE_IRQ_TXERR2|NFE_IRQ_TX_DONE)) != 0) { 559 /* check Tx ring */ 560 nfe_txeof(sc); 561 } 562 if ((r & NFE_IRQ_LINK) != 0) { 563 NFE_READ(sc, NFE_PHY_STATUS); 564 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 565 DPRINTF(("%s: link state changed\n", 566 device_xname(sc->sc_dev))); 567 } 568 } 569 570 if (handled && !IF_IS_EMPTY(&ifp->if_snd)) 571 nfe_start(ifp); 572 573 return handled; 574 } 575 576 static int 577 nfe_ifflags_cb(struct ethercom *ec) 578 { 579 struct ifnet *ifp = &ec->ec_if; 580 struct nfe_softc *sc = ifp->if_softc; 581 int change = ifp->if_flags ^ sc->sc_if_flags; 582 583 /* 584 * If only the PROMISC flag changes, then 585 * don't do a full re-init of the chip, just update 586 * the Rx filter. 587 */ 588 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 589 return ENETRESET; 590 else if ((change & IFF_PROMISC) != 0) 591 nfe_setmulti(sc); 592 593 return 0; 594 } 595 596 int 597 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 598 { 599 struct nfe_softc *sc = ifp->if_softc; 600 struct ifaddr *ifa = (struct ifaddr *)data; 601 int s, error = 0; 602 603 s = splnet(); 604 605 switch (cmd) { 606 case SIOCINITIFADDR: 607 ifp->if_flags |= IFF_UP; 608 nfe_init(ifp); 609 switch (ifa->ifa_addr->sa_family) { 610 #ifdef INET 611 case AF_INET: 612 arp_ifinit(ifp, ifa); 613 break; 614 #endif 615 default: 616 break; 617 } 618 break; 619 default: 620 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 621 break; 622 623 error = 0; 624 625 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 626 ; 627 else if (ifp->if_flags & IFF_RUNNING) 628 nfe_setmulti(sc); 629 break; 630 } 631 sc->sc_if_flags = ifp->if_flags; 632 633 splx(s); 634 635 return error; 636 } 637 638 void 639 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 640 { 641 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 642 (char *)desc32 - (char *)sc->txq.desc32, 643 sizeof (struct nfe_desc32), ops); 644 } 645 646 void 647 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 648 { 649 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 650 (char *)desc64 - (char *)sc->txq.desc64, 651 sizeof (struct nfe_desc64), ops); 652 } 653 654 void 655 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 656 { 657 if (end > start) { 658 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 659 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 660 (char *)&sc->txq.desc32[end] - 661 (char *)&sc->txq.desc32[start], ops); 662 return; 663 } 664 /* sync from 'start' to end of ring */ 665 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 666 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 667 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 668 (char *)&sc->txq.desc32[start], ops); 669 670 /* sync from start of ring to 'end' */ 671 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 672 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 673 } 674 675 void 676 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 677 { 678 if (end > start) { 679 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 680 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 681 (char *)&sc->txq.desc64[end] - 682 (char *)&sc->txq.desc64[start], ops); 683 return; 684 } 685 /* sync from 'start' to end of ring */ 686 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 687 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 688 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 689 (char *)&sc->txq.desc64[start], ops); 690 691 /* sync from start of ring to 'end' */ 692 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 693 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 694 } 695 696 void 697 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 698 { 699 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 700 (char *)desc32 - (char *)sc->rxq.desc32, 701 sizeof (struct nfe_desc32), ops); 702 } 703 704 void 705 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 706 { 707 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 708 (char *)desc64 - (char *)sc->rxq.desc64, 709 sizeof (struct nfe_desc64), ops); 710 } 711 712 void 713 nfe_rxeof(struct nfe_softc *sc) 714 { 715 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 716 struct nfe_desc32 *desc32; 717 struct nfe_desc64 *desc64; 718 struct nfe_rx_data *data; 719 struct nfe_jbuf *jbuf; 720 struct mbuf *m, *mnew; 721 bus_addr_t physaddr; 722 uint16_t flags; 723 int error, len, i; 724 725 desc32 = NULL; 726 desc64 = NULL; 727 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 728 data = &sc->rxq.data[i]; 729 730 if (sc->sc_flags & NFE_40BIT_ADDR) { 731 desc64 = &sc->rxq.desc64[i]; 732 nfe_rxdesc64_sync(sc, desc64, 733 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 734 735 flags = le16toh(desc64->flags); 736 len = le16toh(desc64->length) & 0x3fff; 737 } else { 738 desc32 = &sc->rxq.desc32[i]; 739 nfe_rxdesc32_sync(sc, desc32, 740 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 741 742 flags = le16toh(desc32->flags); 743 len = le16toh(desc32->length) & 0x3fff; 744 } 745 746 if ((flags & NFE_RX_READY) != 0) 747 break; 748 749 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 750 if ((flags & NFE_RX_VALID_V1) == 0) 751 goto skip; 752 753 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 754 flags &= ~NFE_RX_ERROR; 755 len--; /* fix buffer length */ 756 } 757 } else { 758 if ((flags & NFE_RX_VALID_V2) == 0) 759 goto skip; 760 761 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 762 flags &= ~NFE_RX_ERROR; 763 len--; /* fix buffer length */ 764 } 765 } 766 767 if (flags & NFE_RX_ERROR) { 768 ifp->if_ierrors++; 769 goto skip; 770 } 771 772 /* 773 * Try to allocate a new mbuf for this ring element and load 774 * it before processing the current mbuf. If the ring element 775 * cannot be loaded, drop the received packet and reuse the 776 * old mbuf. In the unlikely case that the old mbuf can't be 777 * reloaded either, explicitly panic. 778 */ 779 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 780 if (mnew == NULL) { 781 ifp->if_ierrors++; 782 goto skip; 783 } 784 785 if (sc->sc_flags & NFE_USE_JUMBO) { 786 physaddr = 787 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 788 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 789 if (len > MCLBYTES) { 790 m_freem(mnew); 791 ifp->if_ierrors++; 792 goto skip1; 793 } 794 MCLGET(mnew, M_DONTWAIT); 795 if ((mnew->m_flags & M_EXT) == 0) { 796 m_freem(mnew); 797 ifp->if_ierrors++; 798 goto skip1; 799 } 800 801 (void)memcpy(mtod(mnew, void *), 802 mtod(data->m, const void *), len); 803 m = mnew; 804 goto mbufcopied; 805 } else { 806 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 807 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 808 mtod(data->m, char *) - (char *)sc->rxq.jpool, 809 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 810 811 physaddr = jbuf->physaddr; 812 } 813 } else { 814 MCLGET(mnew, M_DONTWAIT); 815 if ((mnew->m_flags & M_EXT) == 0) { 816 m_freem(mnew); 817 ifp->if_ierrors++; 818 goto skip; 819 } 820 821 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 822 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 823 bus_dmamap_unload(sc->sc_dmat, data->map); 824 825 error = bus_dmamap_load(sc->sc_dmat, data->map, 826 mtod(mnew, void *), MCLBYTES, NULL, 827 BUS_DMA_READ | BUS_DMA_NOWAIT); 828 if (error != 0) { 829 m_freem(mnew); 830 831 /* try to reload the old mbuf */ 832 error = bus_dmamap_load(sc->sc_dmat, data->map, 833 mtod(data->m, void *), MCLBYTES, NULL, 834 BUS_DMA_READ | BUS_DMA_NOWAIT); 835 if (error != 0) { 836 /* very unlikely that it will fail.. */ 837 panic("%s: could not load old rx mbuf", 838 device_xname(sc->sc_dev)); 839 } 840 ifp->if_ierrors++; 841 goto skip; 842 } 843 physaddr = data->map->dm_segs[0].ds_addr; 844 } 845 846 /* 847 * New mbuf successfully loaded, update Rx ring and continue 848 * processing. 849 */ 850 m = data->m; 851 data->m = mnew; 852 853 mbufcopied: 854 /* finalize mbuf */ 855 m->m_pkthdr.len = m->m_len = len; 856 m->m_pkthdr.rcvif = ifp; 857 858 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 859 /* 860 * XXX 861 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 862 */ 863 if (flags & NFE_RX_IP_CSUMOK) { 864 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 865 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 866 device_xname(sc->sc_dev))); 867 } 868 /* 869 * XXX 870 * no way to check M_CSUM_TCP_UDP_BAD or 871 * other protocols? 872 */ 873 if (flags & NFE_RX_UDP_CSUMOK) { 874 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 875 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 876 device_xname(sc->sc_dev))); 877 } else if (flags & NFE_RX_TCP_CSUMOK) { 878 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 879 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 880 device_xname(sc->sc_dev))); 881 } 882 } 883 #if NBPFILTER > 0 884 if (ifp->if_bpf) 885 bpf_mtap(ifp->if_bpf, m); 886 #endif 887 ifp->if_ipackets++; 888 (*ifp->if_input)(ifp, m); 889 890 skip1: 891 /* update mapping address in h/w descriptor */ 892 if (sc->sc_flags & NFE_40BIT_ADDR) { 893 #if defined(__LP64__) 894 desc64->physaddr[0] = htole32(physaddr >> 32); 895 #endif 896 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 897 } else { 898 desc32->physaddr = htole32(physaddr); 899 } 900 901 skip: 902 if (sc->sc_flags & NFE_40BIT_ADDR) { 903 desc64->length = htole16(sc->rxq.bufsz); 904 desc64->flags = htole16(NFE_RX_READY); 905 906 nfe_rxdesc64_sync(sc, desc64, 907 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 908 } else { 909 desc32->length = htole16(sc->rxq.bufsz); 910 desc32->flags = htole16(NFE_RX_READY); 911 912 nfe_rxdesc32_sync(sc, desc32, 913 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 914 } 915 } 916 /* update current RX pointer */ 917 sc->rxq.cur = i; 918 } 919 920 void 921 nfe_txeof(struct nfe_softc *sc) 922 { 923 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 924 struct nfe_desc32 *desc32; 925 struct nfe_desc64 *desc64; 926 struct nfe_tx_data *data = NULL; 927 int i; 928 uint16_t flags; 929 char buf[128]; 930 931 for (i = sc->txq.next; 932 sc->txq.queued > 0; 933 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 934 if (sc->sc_flags & NFE_40BIT_ADDR) { 935 desc64 = &sc->txq.desc64[i]; 936 nfe_txdesc64_sync(sc, desc64, 937 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 938 939 flags = le16toh(desc64->flags); 940 } else { 941 desc32 = &sc->txq.desc32[i]; 942 nfe_txdesc32_sync(sc, desc32, 943 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 944 945 flags = le16toh(desc32->flags); 946 } 947 948 if ((flags & NFE_TX_VALID) != 0) 949 break; 950 951 data = &sc->txq.data[i]; 952 953 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 954 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 955 data->m == NULL) 956 continue; 957 958 if ((flags & NFE_TX_ERROR_V1) != 0) { 959 snprintb(buf, sizeof(buf), NFE_V1_TXERR, flags); 960 aprint_error_dev(sc->sc_dev, "tx v1 error %s\n", 961 buf); 962 ifp->if_oerrors++; 963 } else 964 ifp->if_opackets++; 965 } else { 966 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 967 data->m == NULL) 968 continue; 969 970 if ((flags & NFE_TX_ERROR_V2) != 0) { 971 snprintb(buf, sizeof(buf), NFE_V2_TXERR, flags); 972 aprint_error_dev(sc->sc_dev, "tx v2 error %s\n", 973 buf); 974 ifp->if_oerrors++; 975 } else 976 ifp->if_opackets++; 977 } 978 979 if (data->m == NULL) { /* should not get there */ 980 aprint_error_dev(sc->sc_dev, 981 "last fragment bit w/o associated mbuf!\n"); 982 continue; 983 } 984 985 /* last fragment of the mbuf chain transmitted */ 986 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 987 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 988 bus_dmamap_unload(sc->sc_dmat, data->active); 989 m_freem(data->m); 990 data->m = NULL; 991 } 992 993 sc->txq.next = i; 994 995 if (sc->txq.queued < NFE_TX_RING_COUNT) { 996 /* at least one slot freed */ 997 ifp->if_flags &= ~IFF_OACTIVE; 998 } 999 1000 if (sc->txq.queued == 0) { 1001 /* all queued packets are sent */ 1002 ifp->if_timer = 0; 1003 } 1004 } 1005 1006 int 1007 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 1008 { 1009 struct nfe_desc32 *desc32; 1010 struct nfe_desc64 *desc64; 1011 struct nfe_tx_data *data; 1012 bus_dmamap_t map; 1013 uint16_t flags, csumflags; 1014 #if NVLAN > 0 1015 struct m_tag *mtag; 1016 uint32_t vtag = 0; 1017 #endif 1018 int error, i, first; 1019 1020 desc32 = NULL; 1021 desc64 = NULL; 1022 data = NULL; 1023 1024 flags = 0; 1025 csumflags = 0; 1026 first = sc->txq.cur; 1027 1028 map = sc->txq.data[first].map; 1029 1030 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1031 if (error != 0) { 1032 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1033 error); 1034 return error; 1035 } 1036 1037 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1038 bus_dmamap_unload(sc->sc_dmat, map); 1039 return ENOBUFS; 1040 } 1041 1042 #if NVLAN > 0 1043 /* setup h/w VLAN tagging */ 1044 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1045 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1046 #endif 1047 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1048 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1049 csumflags |= NFE_TX_IP_CSUM; 1050 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1051 csumflags |= NFE_TX_TCP_UDP_CSUM; 1052 } 1053 1054 for (i = 0; i < map->dm_nsegs; i++) { 1055 data = &sc->txq.data[sc->txq.cur]; 1056 1057 if (sc->sc_flags & NFE_40BIT_ADDR) { 1058 desc64 = &sc->txq.desc64[sc->txq.cur]; 1059 #if defined(__LP64__) 1060 desc64->physaddr[0] = 1061 htole32(map->dm_segs[i].ds_addr >> 32); 1062 #endif 1063 desc64->physaddr[1] = 1064 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1065 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1066 desc64->flags = htole16(flags); 1067 desc64->vtag = 0; 1068 } else { 1069 desc32 = &sc->txq.desc32[sc->txq.cur]; 1070 1071 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1072 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1073 desc32->flags = htole16(flags); 1074 } 1075 1076 /* 1077 * Setting of the valid bit in the first descriptor is 1078 * deferred until the whole chain is fully setup. 1079 */ 1080 flags |= NFE_TX_VALID; 1081 1082 sc->txq.queued++; 1083 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1084 } 1085 1086 /* the whole mbuf chain has been setup */ 1087 if (sc->sc_flags & NFE_40BIT_ADDR) { 1088 /* fix last descriptor */ 1089 flags |= NFE_TX_LASTFRAG_V2; 1090 desc64->flags = htole16(flags); 1091 1092 /* Checksum flags and vtag belong to the first fragment only. */ 1093 #if NVLAN > 0 1094 sc->txq.desc64[first].vtag = htole32(vtag); 1095 #endif 1096 sc->txq.desc64[first].flags |= htole16(csumflags); 1097 1098 /* finally, set the valid bit in the first descriptor */ 1099 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1100 } else { 1101 /* fix last descriptor */ 1102 if (sc->sc_flags & NFE_JUMBO_SUP) 1103 flags |= NFE_TX_LASTFRAG_V2; 1104 else 1105 flags |= NFE_TX_LASTFRAG_V1; 1106 desc32->flags = htole16(flags); 1107 1108 /* Checksum flags belong to the first fragment only. */ 1109 sc->txq.desc32[first].flags |= htole16(csumflags); 1110 1111 /* finally, set the valid bit in the first descriptor */ 1112 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1113 } 1114 1115 data->m = m0; 1116 data->active = map; 1117 1118 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1119 BUS_DMASYNC_PREWRITE); 1120 1121 return 0; 1122 } 1123 1124 void 1125 nfe_start(struct ifnet *ifp) 1126 { 1127 struct nfe_softc *sc = ifp->if_softc; 1128 int old = sc->txq.queued; 1129 struct mbuf *m0; 1130 1131 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1132 return; 1133 1134 for (;;) { 1135 IFQ_POLL(&ifp->if_snd, m0); 1136 if (m0 == NULL) 1137 break; 1138 1139 if (nfe_encap(sc, m0) != 0) { 1140 ifp->if_flags |= IFF_OACTIVE; 1141 break; 1142 } 1143 1144 /* packet put in h/w queue, remove from s/w queue */ 1145 IFQ_DEQUEUE(&ifp->if_snd, m0); 1146 1147 #if NBPFILTER > 0 1148 if (ifp->if_bpf != NULL) 1149 bpf_mtap(ifp->if_bpf, m0); 1150 #endif 1151 } 1152 1153 if (sc->txq.queued != old) { 1154 /* packets are queued */ 1155 if (sc->sc_flags & NFE_40BIT_ADDR) 1156 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1157 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1158 else 1159 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1160 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1161 /* kick Tx */ 1162 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1163 1164 /* 1165 * Set a timeout in case the chip goes out to lunch. 1166 */ 1167 ifp->if_timer = 5; 1168 } 1169 } 1170 1171 void 1172 nfe_watchdog(struct ifnet *ifp) 1173 { 1174 struct nfe_softc *sc = ifp->if_softc; 1175 1176 aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1177 1178 ifp->if_flags &= ~IFF_RUNNING; 1179 nfe_init(ifp); 1180 1181 ifp->if_oerrors++; 1182 } 1183 1184 int 1185 nfe_init(struct ifnet *ifp) 1186 { 1187 struct nfe_softc *sc = ifp->if_softc; 1188 uint32_t tmp; 1189 int rc = 0, s; 1190 1191 if (ifp->if_flags & IFF_RUNNING) 1192 return 0; 1193 1194 nfe_stop(ifp, 0); 1195 1196 NFE_WRITE(sc, NFE_TX_UNK, 0); 1197 NFE_WRITE(sc, NFE_STATUS, 0); 1198 1199 sc->rxtxctl = NFE_RXTX_BIT2; 1200 if (sc->sc_flags & NFE_40BIT_ADDR) 1201 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1202 else if (sc->sc_flags & NFE_JUMBO_SUP) 1203 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1204 if (sc->sc_flags & NFE_HW_CSUM) 1205 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1206 #if NVLAN > 0 1207 /* 1208 * Although the adapter is capable of stripping VLAN tags from received 1209 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1210 * purpose. This will be done in software by our network stack. 1211 */ 1212 if (sc->sc_flags & NFE_HW_VLAN) 1213 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1214 #endif 1215 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1216 DELAY(10); 1217 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1218 1219 #if NVLAN 1220 if (sc->sc_flags & NFE_HW_VLAN) 1221 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1222 #endif 1223 1224 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1225 1226 /* set MAC address */ 1227 nfe_set_macaddr(sc, sc->sc_enaddr); 1228 1229 /* tell MAC where rings are in memory */ 1230 #ifdef __LP64__ 1231 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1232 #endif 1233 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1234 #ifdef __LP64__ 1235 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1236 #endif 1237 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1238 1239 NFE_WRITE(sc, NFE_RING_SIZE, 1240 (NFE_RX_RING_COUNT - 1) << 16 | 1241 (NFE_TX_RING_COUNT - 1)); 1242 1243 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1244 1245 /* force MAC to wakeup */ 1246 tmp = NFE_READ(sc, NFE_PWR_STATE); 1247 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1248 DELAY(10); 1249 tmp = NFE_READ(sc, NFE_PWR_STATE); 1250 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1251 1252 s = splnet(); 1253 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1254 nfe_intr(sc); /* XXX clear IRQ status registers */ 1255 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1256 splx(s); 1257 1258 #if 1 1259 /* configure interrupts coalescing/mitigation */ 1260 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1261 #else 1262 /* no interrupt mitigation: one interrupt per packet */ 1263 NFE_WRITE(sc, NFE_IMTIMER, 970); 1264 #endif 1265 1266 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1267 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1268 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1269 1270 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1271 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1272 1273 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1274 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_ENABLE); 1275 1276 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1277 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1278 DELAY(10); 1279 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1280 1281 /* set Rx filter */ 1282 nfe_setmulti(sc); 1283 1284 if ((rc = ether_mediachange(ifp)) != 0) 1285 goto out; 1286 1287 nfe_tick(sc); 1288 1289 /* enable Rx */ 1290 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1291 1292 /* enable Tx */ 1293 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1294 1295 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1296 1297 /* enable interrupts */ 1298 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1299 1300 callout_schedule(&sc->sc_tick_ch, hz); 1301 1302 ifp->if_flags |= IFF_RUNNING; 1303 ifp->if_flags &= ~IFF_OACTIVE; 1304 1305 out: 1306 return rc; 1307 } 1308 1309 void 1310 nfe_stop(struct ifnet *ifp, int disable) 1311 { 1312 struct nfe_softc *sc = ifp->if_softc; 1313 1314 callout_stop(&sc->sc_tick_ch); 1315 1316 ifp->if_timer = 0; 1317 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1318 1319 mii_down(&sc->sc_mii); 1320 1321 /* abort Tx */ 1322 NFE_WRITE(sc, NFE_TX_CTL, 0); 1323 1324 /* disable Rx */ 1325 NFE_WRITE(sc, NFE_RX_CTL, 0); 1326 1327 /* disable interrupts */ 1328 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1329 1330 /* reset Tx and Rx rings */ 1331 nfe_reset_tx_ring(sc, &sc->txq); 1332 nfe_reset_rx_ring(sc, &sc->rxq); 1333 } 1334 1335 int 1336 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1337 { 1338 struct nfe_desc32 *desc32; 1339 struct nfe_desc64 *desc64; 1340 struct nfe_rx_data *data; 1341 struct nfe_jbuf *jbuf; 1342 void **desc; 1343 bus_addr_t physaddr; 1344 int i, nsegs, error, descsize; 1345 1346 if (sc->sc_flags & NFE_40BIT_ADDR) { 1347 desc = (void **)&ring->desc64; 1348 descsize = sizeof (struct nfe_desc64); 1349 } else { 1350 desc = (void **)&ring->desc32; 1351 descsize = sizeof (struct nfe_desc32); 1352 } 1353 1354 ring->cur = ring->next = 0; 1355 ring->bufsz = MCLBYTES; 1356 1357 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1358 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1359 if (error != 0) { 1360 aprint_error_dev(sc->sc_dev, 1361 "could not create desc DMA map\n"); 1362 goto fail; 1363 } 1364 1365 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1366 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1367 if (error != 0) { 1368 aprint_error_dev(sc->sc_dev, 1369 "could not allocate DMA memory\n"); 1370 goto fail; 1371 } 1372 1373 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1374 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1375 if (error != 0) { 1376 aprint_error_dev(sc->sc_dev, 1377 "could not map desc DMA memory\n"); 1378 goto fail; 1379 } 1380 1381 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1382 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1383 if (error != 0) { 1384 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1385 goto fail; 1386 } 1387 1388 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1389 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1390 1391 if (sc->sc_flags & NFE_USE_JUMBO) { 1392 ring->bufsz = NFE_JBYTES; 1393 if ((error = nfe_jpool_alloc(sc)) != 0) { 1394 aprint_error_dev(sc->sc_dev, 1395 "could not allocate jumbo frames\n"); 1396 goto fail; 1397 } 1398 } 1399 1400 /* 1401 * Pre-allocate Rx buffers and populate Rx ring. 1402 */ 1403 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1404 data = &sc->rxq.data[i]; 1405 1406 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1407 if (data->m == NULL) { 1408 aprint_error_dev(sc->sc_dev, 1409 "could not allocate rx mbuf\n"); 1410 error = ENOMEM; 1411 goto fail; 1412 } 1413 1414 if (sc->sc_flags & NFE_USE_JUMBO) { 1415 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1416 aprint_error_dev(sc->sc_dev, 1417 "could not allocate jumbo buffer\n"); 1418 goto fail; 1419 } 1420 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1421 sc); 1422 1423 physaddr = jbuf->physaddr; 1424 } else { 1425 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1426 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1427 if (error != 0) { 1428 aprint_error_dev(sc->sc_dev, 1429 "could not create DMA map\n"); 1430 goto fail; 1431 } 1432 MCLGET(data->m, M_DONTWAIT); 1433 if (!(data->m->m_flags & M_EXT)) { 1434 aprint_error_dev(sc->sc_dev, 1435 "could not allocate mbuf cluster\n"); 1436 error = ENOMEM; 1437 goto fail; 1438 } 1439 1440 error = bus_dmamap_load(sc->sc_dmat, data->map, 1441 mtod(data->m, void *), MCLBYTES, NULL, 1442 BUS_DMA_READ | BUS_DMA_NOWAIT); 1443 if (error != 0) { 1444 aprint_error_dev(sc->sc_dev, 1445 "could not load rx buf DMA map"); 1446 goto fail; 1447 } 1448 physaddr = data->map->dm_segs[0].ds_addr; 1449 } 1450 1451 if (sc->sc_flags & NFE_40BIT_ADDR) { 1452 desc64 = &sc->rxq.desc64[i]; 1453 #if defined(__LP64__) 1454 desc64->physaddr[0] = htole32(physaddr >> 32); 1455 #endif 1456 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1457 desc64->length = htole16(sc->rxq.bufsz); 1458 desc64->flags = htole16(NFE_RX_READY); 1459 } else { 1460 desc32 = &sc->rxq.desc32[i]; 1461 desc32->physaddr = htole32(physaddr); 1462 desc32->length = htole16(sc->rxq.bufsz); 1463 desc32->flags = htole16(NFE_RX_READY); 1464 } 1465 } 1466 1467 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1468 BUS_DMASYNC_PREWRITE); 1469 1470 return 0; 1471 1472 fail: nfe_free_rx_ring(sc, ring); 1473 return error; 1474 } 1475 1476 void 1477 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1478 { 1479 int i; 1480 1481 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1482 if (sc->sc_flags & NFE_40BIT_ADDR) { 1483 ring->desc64[i].length = htole16(ring->bufsz); 1484 ring->desc64[i].flags = htole16(NFE_RX_READY); 1485 } else { 1486 ring->desc32[i].length = htole16(ring->bufsz); 1487 ring->desc32[i].flags = htole16(NFE_RX_READY); 1488 } 1489 } 1490 1491 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1492 BUS_DMASYNC_PREWRITE); 1493 1494 ring->cur = ring->next = 0; 1495 } 1496 1497 void 1498 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1499 { 1500 struct nfe_rx_data *data; 1501 void *desc; 1502 int i, descsize; 1503 1504 if (sc->sc_flags & NFE_40BIT_ADDR) { 1505 desc = ring->desc64; 1506 descsize = sizeof (struct nfe_desc64); 1507 } else { 1508 desc = ring->desc32; 1509 descsize = sizeof (struct nfe_desc32); 1510 } 1511 1512 if (desc != NULL) { 1513 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1514 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1515 bus_dmamap_unload(sc->sc_dmat, ring->map); 1516 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1517 NFE_RX_RING_COUNT * descsize); 1518 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1519 } 1520 1521 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1522 data = &ring->data[i]; 1523 1524 if (data->map != NULL) { 1525 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1526 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1527 bus_dmamap_unload(sc->sc_dmat, data->map); 1528 bus_dmamap_destroy(sc->sc_dmat, data->map); 1529 } 1530 if (data->m != NULL) 1531 m_freem(data->m); 1532 } 1533 } 1534 1535 struct nfe_jbuf * 1536 nfe_jalloc(struct nfe_softc *sc, int i) 1537 { 1538 struct nfe_jbuf *jbuf; 1539 1540 mutex_enter(&sc->rxq.mtx); 1541 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1542 if (jbuf != NULL) 1543 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1544 mutex_exit(&sc->rxq.mtx); 1545 if (jbuf == NULL) 1546 return NULL; 1547 sc->rxq.jbufmap[i] = 1548 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1549 return jbuf; 1550 } 1551 1552 /* 1553 * This is called automatically by the network stack when the mbuf is freed. 1554 * Caution must be taken that the NIC might be reset by the time the mbuf is 1555 * freed. 1556 */ 1557 void 1558 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1559 { 1560 struct nfe_softc *sc = arg; 1561 struct nfe_jbuf *jbuf; 1562 int i; 1563 1564 /* find the jbuf from the base pointer */ 1565 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1566 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1567 aprint_error_dev(sc->sc_dev, 1568 "request to free a buffer (%p) not managed by us\n", buf); 1569 return; 1570 } 1571 jbuf = &sc->rxq.jbuf[i]; 1572 1573 /* ..and put it back in the free list */ 1574 mutex_enter(&sc->rxq.mtx); 1575 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1576 mutex_exit(&sc->rxq.mtx); 1577 1578 if (m != NULL) 1579 pool_cache_put(mb_cache, m); 1580 } 1581 1582 int 1583 nfe_jpool_alloc(struct nfe_softc *sc) 1584 { 1585 struct nfe_rx_ring *ring = &sc->rxq; 1586 struct nfe_jbuf *jbuf; 1587 bus_addr_t physaddr; 1588 char *buf; 1589 int i, nsegs, error; 1590 1591 /* 1592 * Allocate a big chunk of DMA'able memory. 1593 */ 1594 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1595 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1596 if (error != 0) { 1597 aprint_error_dev(sc->sc_dev, 1598 "could not create jumbo DMA map\n"); 1599 goto fail; 1600 } 1601 1602 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1603 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1604 if (error != 0) { 1605 aprint_error_dev(sc->sc_dev, 1606 "could not allocate jumbo DMA memory\n"); 1607 goto fail; 1608 } 1609 1610 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1611 &ring->jpool, BUS_DMA_NOWAIT); 1612 if (error != 0) { 1613 aprint_error_dev(sc->sc_dev, 1614 "could not map jumbo DMA memory\n"); 1615 goto fail; 1616 } 1617 1618 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1619 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1620 if (error != 0) { 1621 aprint_error_dev(sc->sc_dev, 1622 "could not load jumbo DMA map\n"); 1623 goto fail; 1624 } 1625 1626 /* ..and split it into 9KB chunks */ 1627 SLIST_INIT(&ring->jfreelist); 1628 1629 buf = ring->jpool; 1630 physaddr = ring->jmap->dm_segs[0].ds_addr; 1631 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1632 jbuf = &ring->jbuf[i]; 1633 1634 jbuf->buf = buf; 1635 jbuf->physaddr = physaddr; 1636 1637 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1638 1639 buf += NFE_JBYTES; 1640 physaddr += NFE_JBYTES; 1641 } 1642 1643 return 0; 1644 1645 fail: nfe_jpool_free(sc); 1646 return error; 1647 } 1648 1649 void 1650 nfe_jpool_free(struct nfe_softc *sc) 1651 { 1652 struct nfe_rx_ring *ring = &sc->rxq; 1653 1654 if (ring->jmap != NULL) { 1655 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1656 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1657 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1658 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1659 } 1660 if (ring->jpool != NULL) { 1661 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1662 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1663 } 1664 } 1665 1666 int 1667 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1668 { 1669 int i, nsegs, error; 1670 void **desc; 1671 int descsize; 1672 1673 if (sc->sc_flags & NFE_40BIT_ADDR) { 1674 desc = (void **)&ring->desc64; 1675 descsize = sizeof (struct nfe_desc64); 1676 } else { 1677 desc = (void **)&ring->desc32; 1678 descsize = sizeof (struct nfe_desc32); 1679 } 1680 1681 ring->queued = 0; 1682 ring->cur = ring->next = 0; 1683 1684 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1685 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1686 1687 if (error != 0) { 1688 aprint_error_dev(sc->sc_dev, 1689 "could not create desc DMA map\n"); 1690 goto fail; 1691 } 1692 1693 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1694 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1695 if (error != 0) { 1696 aprint_error_dev(sc->sc_dev, 1697 "could not allocate DMA memory\n"); 1698 goto fail; 1699 } 1700 1701 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1702 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1703 if (error != 0) { 1704 aprint_error_dev(sc->sc_dev, 1705 "could not map desc DMA memory\n"); 1706 goto fail; 1707 } 1708 1709 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1710 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1711 if (error != 0) { 1712 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1713 goto fail; 1714 } 1715 1716 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1717 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1718 1719 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1720 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1721 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1722 &ring->data[i].map); 1723 if (error != 0) { 1724 aprint_error_dev(sc->sc_dev, 1725 "could not create DMA map\n"); 1726 goto fail; 1727 } 1728 } 1729 1730 return 0; 1731 1732 fail: nfe_free_tx_ring(sc, ring); 1733 return error; 1734 } 1735 1736 void 1737 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1738 { 1739 struct nfe_tx_data *data; 1740 int i; 1741 1742 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1743 if (sc->sc_flags & NFE_40BIT_ADDR) 1744 ring->desc64[i].flags = 0; 1745 else 1746 ring->desc32[i].flags = 0; 1747 1748 data = &ring->data[i]; 1749 1750 if (data->m != NULL) { 1751 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1752 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1753 bus_dmamap_unload(sc->sc_dmat, data->active); 1754 m_freem(data->m); 1755 data->m = NULL; 1756 } 1757 } 1758 1759 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1760 BUS_DMASYNC_PREWRITE); 1761 1762 ring->queued = 0; 1763 ring->cur = ring->next = 0; 1764 } 1765 1766 void 1767 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1768 { 1769 struct nfe_tx_data *data; 1770 void *desc; 1771 int i, descsize; 1772 1773 if (sc->sc_flags & NFE_40BIT_ADDR) { 1774 desc = ring->desc64; 1775 descsize = sizeof (struct nfe_desc64); 1776 } else { 1777 desc = ring->desc32; 1778 descsize = sizeof (struct nfe_desc32); 1779 } 1780 1781 if (desc != NULL) { 1782 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1783 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1784 bus_dmamap_unload(sc->sc_dmat, ring->map); 1785 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1786 NFE_TX_RING_COUNT * descsize); 1787 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1788 } 1789 1790 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1791 data = &ring->data[i]; 1792 1793 if (data->m != NULL) { 1794 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1795 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1796 bus_dmamap_unload(sc->sc_dmat, data->active); 1797 m_freem(data->m); 1798 } 1799 } 1800 1801 /* ..and now actually destroy the DMA mappings */ 1802 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1803 data = &ring->data[i]; 1804 if (data->map == NULL) 1805 continue; 1806 bus_dmamap_destroy(sc->sc_dmat, data->map); 1807 } 1808 } 1809 1810 void 1811 nfe_setmulti(struct nfe_softc *sc) 1812 { 1813 struct ethercom *ec = &sc->sc_ethercom; 1814 struct ifnet *ifp = &ec->ec_if; 1815 struct ether_multi *enm; 1816 struct ether_multistep step; 1817 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1818 uint32_t filter = NFE_RXFILTER_MAGIC; 1819 int i; 1820 1821 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1822 bzero(addr, ETHER_ADDR_LEN); 1823 bzero(mask, ETHER_ADDR_LEN); 1824 goto done; 1825 } 1826 1827 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1828 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1829 1830 ETHER_FIRST_MULTI(step, ec, enm); 1831 while (enm != NULL) { 1832 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1833 ifp->if_flags |= IFF_ALLMULTI; 1834 bzero(addr, ETHER_ADDR_LEN); 1835 bzero(mask, ETHER_ADDR_LEN); 1836 goto done; 1837 } 1838 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1839 addr[i] &= enm->enm_addrlo[i]; 1840 mask[i] &= ~enm->enm_addrlo[i]; 1841 } 1842 ETHER_NEXT_MULTI(step, enm); 1843 } 1844 for (i = 0; i < ETHER_ADDR_LEN; i++) 1845 mask[i] |= addr[i]; 1846 1847 done: 1848 addr[0] |= 0x01; /* make sure multicast bit is set */ 1849 1850 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1851 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1852 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1853 addr[5] << 8 | addr[4]); 1854 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1855 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1856 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1857 mask[5] << 8 | mask[4]); 1858 1859 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1860 NFE_WRITE(sc, NFE_RXFILTER, filter); 1861 } 1862 1863 void 1864 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1865 { 1866 uint32_t tmp; 1867 1868 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 1869 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1870 addr[0] = (tmp & 0xff); 1871 addr[1] = (tmp >> 8) & 0xff; 1872 addr[2] = (tmp >> 16) & 0xff; 1873 addr[3] = (tmp >> 24) & 0xff; 1874 1875 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1876 addr[4] = (tmp & 0xff); 1877 addr[5] = (tmp >> 8) & 0xff; 1878 1879 } else { 1880 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1881 addr[0] = (tmp >> 8) & 0xff; 1882 addr[1] = (tmp & 0xff); 1883 1884 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1885 addr[2] = (tmp >> 24) & 0xff; 1886 addr[3] = (tmp >> 16) & 0xff; 1887 addr[4] = (tmp >> 8) & 0xff; 1888 addr[5] = (tmp & 0xff); 1889 } 1890 } 1891 1892 void 1893 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1894 { 1895 NFE_WRITE(sc, NFE_MACADDR_LO, 1896 addr[5] << 8 | addr[4]); 1897 NFE_WRITE(sc, NFE_MACADDR_HI, 1898 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1899 } 1900 1901 void 1902 nfe_tick(void *arg) 1903 { 1904 struct nfe_softc *sc = arg; 1905 int s; 1906 1907 s = splnet(); 1908 mii_tick(&sc->sc_mii); 1909 splx(s); 1910 1911 callout_schedule(&sc->sc_tick_ch, hz); 1912 } 1913 1914 void 1915 nfe_poweron(device_t self) 1916 { 1917 struct nfe_softc *sc = device_private(self); 1918 1919 if ((sc->sc_flags & NFE_PWR_MGMT) != 0) { 1920 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 1921 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 1922 DELAY(100); 1923 NFE_WRITE(sc, NFE_MAC_RESET, 0); 1924 DELAY(100); 1925 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 1926 NFE_WRITE(sc, NFE_PWR2_CTL, 1927 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_WAKEUP_MASK); 1928 } 1929 } 1930 1931 bool 1932 nfe_resume(device_t dv PMF_FN_ARGS) 1933 { 1934 nfe_poweron(dv); 1935 1936 return true; 1937 } 1938
Indexes created Tue Sep 30 07:10:03 GMT 2025