if_nfe.c revision 1.51
1 /* $NetBSD: if_nfe.c,v 1.51 2010/04/05 07:20:26 joerg Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.77 2008/02/05 16:52:50 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006, 2007 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.51 2010/04/05 07:20:26 joerg Exp $"); 25 26 #include "opt_inet.h" 27 #include "vlan.h" 28 29 #include <sys/param.h> 30 #include <sys/endian.h> 31 #include <sys/systm.h> 32 #include <sys/types.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/mutex.h> 36 #include <sys/queue.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/callout.h> 40 #include <sys/socket.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #include <net/bpf.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_nfereg.h> 72 #include <dev/pci/if_nfevar.h> 73 74 static int nfe_ifflags_cb(struct ethercom *); 75 76 int nfe_match(device_t, cfdata_t, void *); 77 void nfe_attach(device_t, device_t, void *); 78 void nfe_power(int, void *); 79 void nfe_miibus_statchg(device_t); 80 int nfe_miibus_readreg(device_t, int, int); 81 void nfe_miibus_writereg(device_t, int, int, int); 82 int nfe_intr(void *); 83 int nfe_ioctl(struct ifnet *, u_long, void *); 84 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 85 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 86 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 87 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 88 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 89 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 90 void nfe_rxeof(struct nfe_softc *); 91 void nfe_txeof(struct nfe_softc *); 92 int nfe_encap(struct nfe_softc *, struct mbuf *); 93 void nfe_start(struct ifnet *); 94 void nfe_watchdog(struct ifnet *); 95 int nfe_init(struct ifnet *); 96 void nfe_stop(struct ifnet *, int); 97 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 98 void nfe_jfree(struct mbuf *, void *, size_t, void *); 99 int nfe_jpool_alloc(struct nfe_softc *); 100 void nfe_jpool_free(struct nfe_softc *); 101 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 102 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 105 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 void nfe_setmulti(struct nfe_softc *); 108 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 109 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 110 void nfe_tick(void *); 111 void nfe_poweron(device_t); 112 bool nfe_resume(device_t, const pmf_qual_t *); 113 114 CFATTACH_DECL_NEW(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, 115 NULL, NULL); 116 117 /* #define NFE_NO_JUMBO */ 118 119 #ifdef NFE_DEBUG 120 int nfedebug = 0; 121 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 122 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 123 #else 124 #define DPRINTF(x) 125 #define DPRINTFN(n,x) 126 #endif 127 128 /* deal with naming differences */ 129 130 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 131 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 132 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 133 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 134 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 135 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 136 137 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 138 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 139 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 140 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 141 142 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 143 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 144 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 145 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 146 147 #ifdef _LP64 148 #define __LP64__ 1 149 #endif 150 151 const struct nfe_product { 152 pci_vendor_id_t vendor; 153 pci_product_id_t product; 154 } nfe_devices[] = { 155 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 183 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 184 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 185 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 }, 186 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1 }, 187 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2 }, 188 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3 }, 189 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4 }, 190 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1 }, 191 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2 }, 192 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3 }, 193 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4 } 194 }; 195 196 int 197 nfe_match(device_t dev, cfdata_t match, void *aux) 198 { 199 struct pci_attach_args *pa = aux; 200 const struct nfe_product *np; 201 int i; 202 203 for (i = 0; i < __arraycount(nfe_devices); i++) { 204 np = &nfe_devices[i]; 205 if (PCI_VENDOR(pa->pa_id) == np->vendor && 206 PCI_PRODUCT(pa->pa_id) == np->product) 207 return 1; 208 } 209 return 0; 210 } 211 212 void 213 nfe_attach(device_t parent, device_t self, void *aux) 214 { 215 struct nfe_softc *sc = device_private(self); 216 struct pci_attach_args *pa = aux; 217 pci_chipset_tag_t pc = pa->pa_pc; 218 pci_intr_handle_t ih; 219 const char *intrstr; 220 struct ifnet *ifp; 221 bus_size_t memsize; 222 pcireg_t memtype; 223 char devinfo[256]; 224 int mii_flags = 0; 225 226 sc->sc_dev = self; 227 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 228 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 229 230 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 231 switch (memtype) { 232 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 233 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 234 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 235 &sc->sc_memh, NULL, &memsize) == 0) 236 break; 237 /* FALLTHROUGH */ 238 default: 239 aprint_error_dev(self, "could not map mem space\n"); 240 return; 241 } 242 243 if (pci_intr_map(pa, &ih) != 0) { 244 aprint_error_dev(self, "could not map interrupt\n"); 245 goto fail; 246 } 247 248 intrstr = pci_intr_string(pc, ih); 249 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 250 if (sc->sc_ih == NULL) { 251 aprint_error_dev(self, "could not establish interrupt"); 252 if (intrstr != NULL) 253 aprint_error(" at %s", intrstr); 254 aprint_error("\n"); 255 goto fail; 256 } 257 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 258 259 sc->sc_dmat = pa->pa_dmat; 260 261 sc->sc_flags = 0; 262 263 switch (PCI_PRODUCT(pa->pa_id)) { 264 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 265 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 266 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 267 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 268 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 269 break; 270 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 271 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 272 sc->sc_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT; 273 break; 274 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 275 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 276 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 277 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 278 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 279 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 280 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 281 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 282 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 283 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 284 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 285 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 286 sc->sc_flags |= NFE_40BIT_ADDR | NFE_CORRECT_MACADDR | 287 NFE_PWR_MGMT; 288 break; 289 case PCI_PRODUCT_NVIDIA_MCP77_LAN1: 290 case PCI_PRODUCT_NVIDIA_MCP77_LAN2: 291 case PCI_PRODUCT_NVIDIA_MCP77_LAN3: 292 case PCI_PRODUCT_NVIDIA_MCP77_LAN4: 293 sc->sc_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | 294 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 295 break; 296 case PCI_PRODUCT_NVIDIA_MCP79_LAN1: 297 case PCI_PRODUCT_NVIDIA_MCP79_LAN2: 298 case PCI_PRODUCT_NVIDIA_MCP79_LAN3: 299 case PCI_PRODUCT_NVIDIA_MCP79_LAN4: 300 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 301 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 302 break; 303 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 304 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 305 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 306 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 307 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 308 break; 309 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 310 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 311 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 312 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 313 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 314 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 315 mii_flags = MIIF_DOPAUSE; 316 break; 317 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 318 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 319 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 320 NFE_HW_VLAN | NFE_PWR_MGMT; 321 break; 322 } 323 324 nfe_poweron(self); 325 326 #ifndef NFE_NO_JUMBO 327 /* enable jumbo frames for adapters that support it */ 328 if (sc->sc_flags & NFE_JUMBO_SUP) 329 sc->sc_flags |= NFE_USE_JUMBO; 330 #endif 331 332 /* Check for reversed ethernet address */ 333 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 334 sc->sc_flags |= NFE_CORRECT_MACADDR; 335 336 nfe_get_macaddr(sc, sc->sc_enaddr); 337 aprint_normal_dev(self, "Ethernet address %s\n", 338 ether_sprintf(sc->sc_enaddr)); 339 340 /* 341 * Allocate Tx and Rx rings. 342 */ 343 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 344 aprint_error_dev(self, "could not allocate Tx ring\n"); 345 goto fail; 346 } 347 348 mutex_init(&sc->rxq.mtx, MUTEX_DEFAULT, IPL_NET); 349 350 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 351 aprint_error_dev(self, "could not allocate Rx ring\n"); 352 nfe_free_tx_ring(sc, &sc->txq); 353 goto fail; 354 } 355 356 ifp = &sc->sc_ethercom.ec_if; 357 ifp->if_softc = sc; 358 ifp->if_mtu = ETHERMTU; 359 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 360 ifp->if_ioctl = nfe_ioctl; 361 ifp->if_start = nfe_start; 362 ifp->if_stop = nfe_stop; 363 ifp->if_watchdog = nfe_watchdog; 364 ifp->if_init = nfe_init; 365 ifp->if_baudrate = IF_Gbps(1); 366 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 367 IFQ_SET_READY(&ifp->if_snd); 368 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 369 370 if (sc->sc_flags & NFE_USE_JUMBO) 371 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 372 373 #if NVLAN > 0 374 if (sc->sc_flags & NFE_HW_VLAN) 375 sc->sc_ethercom.ec_capabilities |= 376 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 377 #endif 378 if (sc->sc_flags & NFE_HW_CSUM) { 379 ifp->if_capabilities |= 380 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 381 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 382 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 383 } 384 385 sc->sc_mii.mii_ifp = ifp; 386 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 387 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 388 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 389 390 sc->sc_ethercom.ec_mii = &sc->sc_mii; 391 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 392 ether_mediastatus); 393 394 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 395 MII_OFFSET_ANY, mii_flags); 396 397 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 398 aprint_error_dev(self, "no PHY found!\n"); 399 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 400 0, NULL); 401 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 402 } else 403 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 404 405 if_attach(ifp); 406 ether_ifattach(ifp, sc->sc_enaddr); 407 ether_set_ifflags_cb(&sc->sc_ethercom, nfe_ifflags_cb); 408 409 callout_init(&sc->sc_tick_ch, 0); 410 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 411 412 if (pmf_device_register(self, NULL, nfe_resume)) 413 pmf_class_network_register(self, ifp); 414 else 415 aprint_error_dev(self, "couldn't establish power handler\n"); 416 417 return; 418 419 fail: 420 if (sc->sc_ih != NULL) { 421 pci_intr_disestablish(pc, sc->sc_ih); 422 sc->sc_ih = NULL; 423 } 424 if (memsize) 425 bus_space_unmap(sc->sc_memt, sc->sc_memh, memsize); 426 } 427 428 void 429 nfe_miibus_statchg(device_t dev) 430 { 431 struct nfe_softc *sc = device_private(dev); 432 struct mii_data *mii = &sc->sc_mii; 433 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 434 435 phy = NFE_READ(sc, NFE_PHY_IFACE); 436 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 437 438 seed = NFE_READ(sc, NFE_RNDSEED); 439 seed &= ~NFE_SEED_MASK; 440 441 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 442 phy |= NFE_PHY_HDX; /* half-duplex */ 443 misc |= NFE_MISC1_HDX; 444 } 445 446 switch (IFM_SUBTYPE(mii->mii_media_active)) { 447 case IFM_1000_T: /* full-duplex only */ 448 link |= NFE_MEDIA_1000T; 449 seed |= NFE_SEED_1000T; 450 phy |= NFE_PHY_1000T; 451 break; 452 case IFM_100_TX: 453 link |= NFE_MEDIA_100TX; 454 seed |= NFE_SEED_100TX; 455 phy |= NFE_PHY_100TX; 456 break; 457 case IFM_10_T: 458 link |= NFE_MEDIA_10T; 459 seed |= NFE_SEED_10T; 460 break; 461 } 462 463 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 464 465 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 466 NFE_WRITE(sc, NFE_MISC1, misc); 467 NFE_WRITE(sc, NFE_LINKSPEED, link); 468 } 469 470 int 471 nfe_miibus_readreg(device_t dev, int phy, int reg) 472 { 473 struct nfe_softc *sc = device_private(dev); 474 uint32_t val; 475 int ntries; 476 477 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 478 479 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 480 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 481 DELAY(100); 482 } 483 484 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 485 486 for (ntries = 0; ntries < 1000; ntries++) { 487 DELAY(100); 488 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 489 break; 490 } 491 if (ntries == 1000) { 492 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 493 device_xname(sc->sc_dev))); 494 return 0; 495 } 496 497 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 498 DPRINTFN(2, ("%s: could not read PHY\n", 499 device_xname(sc->sc_dev))); 500 return 0; 501 } 502 503 val = NFE_READ(sc, NFE_PHY_DATA); 504 if (val != 0xffffffff && val != 0) 505 sc->mii_phyaddr = phy; 506 507 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 508 device_xname(sc->sc_dev), phy, reg, val)); 509 510 return val; 511 } 512 513 void 514 nfe_miibus_writereg(device_t dev, int phy, int reg, int val) 515 { 516 struct nfe_softc *sc = device_private(dev); 517 uint32_t ctl; 518 int ntries; 519 520 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 521 522 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 523 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 524 DELAY(100); 525 } 526 527 NFE_WRITE(sc, NFE_PHY_DATA, val); 528 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 529 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 530 531 for (ntries = 0; ntries < 1000; ntries++) { 532 DELAY(100); 533 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 534 break; 535 } 536 #ifdef NFE_DEBUG 537 if (nfedebug >= 2 && ntries == 1000) 538 printf("could not write to PHY\n"); 539 #endif 540 } 541 542 int 543 nfe_intr(void *arg) 544 { 545 struct nfe_softc *sc = arg; 546 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 547 uint32_t r; 548 int handled; 549 550 if ((ifp->if_flags & IFF_UP) == 0) 551 return 0; 552 553 handled = 0; 554 555 for (;;) { 556 r = NFE_READ(sc, NFE_IRQ_STATUS); 557 if ((r & NFE_IRQ_WANTED) == 0) 558 break; 559 560 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 561 handled = 1; 562 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 563 564 if ((r & (NFE_IRQ_RXERR|NFE_IRQ_RX_NOBUF|NFE_IRQ_RX)) != 0) { 565 /* check Rx ring */ 566 nfe_rxeof(sc); 567 } 568 if ((r & (NFE_IRQ_TXERR|NFE_IRQ_TXERR2|NFE_IRQ_TX_DONE)) != 0) { 569 /* check Tx ring */ 570 nfe_txeof(sc); 571 } 572 if ((r & NFE_IRQ_LINK) != 0) { 573 NFE_READ(sc, NFE_PHY_STATUS); 574 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 575 DPRINTF(("%s: link state changed\n", 576 device_xname(sc->sc_dev))); 577 } 578 } 579 580 if (handled && !IF_IS_EMPTY(&ifp->if_snd)) 581 nfe_start(ifp); 582 583 return handled; 584 } 585 586 static int 587 nfe_ifflags_cb(struct ethercom *ec) 588 { 589 struct ifnet *ifp = &ec->ec_if; 590 struct nfe_softc *sc = ifp->if_softc; 591 int change = ifp->if_flags ^ sc->sc_if_flags; 592 593 /* 594 * If only the PROMISC flag changes, then 595 * don't do a full re-init of the chip, just update 596 * the Rx filter. 597 */ 598 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 599 return ENETRESET; 600 else if ((change & IFF_PROMISC) != 0) 601 nfe_setmulti(sc); 602 603 return 0; 604 } 605 606 int 607 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 608 { 609 struct nfe_softc *sc = ifp->if_softc; 610 struct ifaddr *ifa = (struct ifaddr *)data; 611 int s, error = 0; 612 613 s = splnet(); 614 615 switch (cmd) { 616 case SIOCINITIFADDR: 617 ifp->if_flags |= IFF_UP; 618 nfe_init(ifp); 619 switch (ifa->ifa_addr->sa_family) { 620 #ifdef INET 621 case AF_INET: 622 arp_ifinit(ifp, ifa); 623 break; 624 #endif 625 default: 626 break; 627 } 628 break; 629 default: 630 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 631 break; 632 633 error = 0; 634 635 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 636 ; 637 else if (ifp->if_flags & IFF_RUNNING) 638 nfe_setmulti(sc); 639 break; 640 } 641 sc->sc_if_flags = ifp->if_flags; 642 643 splx(s); 644 645 return error; 646 } 647 648 void 649 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 650 { 651 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 652 (char *)desc32 - (char *)sc->txq.desc32, 653 sizeof (struct nfe_desc32), ops); 654 } 655 656 void 657 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 658 { 659 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 660 (char *)desc64 - (char *)sc->txq.desc64, 661 sizeof (struct nfe_desc64), ops); 662 } 663 664 void 665 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 666 { 667 if (end > start) { 668 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 669 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 670 (char *)&sc->txq.desc32[end] - 671 (char *)&sc->txq.desc32[start], ops); 672 return; 673 } 674 /* sync from 'start' to end of ring */ 675 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 676 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 677 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 678 (char *)&sc->txq.desc32[start], ops); 679 680 /* sync from start of ring to 'end' */ 681 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 682 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 683 } 684 685 void 686 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 687 { 688 if (end > start) { 689 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 690 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 691 (char *)&sc->txq.desc64[end] - 692 (char *)&sc->txq.desc64[start], ops); 693 return; 694 } 695 /* sync from 'start' to end of ring */ 696 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 697 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 698 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 699 (char *)&sc->txq.desc64[start], ops); 700 701 /* sync from start of ring to 'end' */ 702 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 703 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 704 } 705 706 void 707 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 708 { 709 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 710 (char *)desc32 - (char *)sc->rxq.desc32, 711 sizeof (struct nfe_desc32), ops); 712 } 713 714 void 715 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 716 { 717 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 718 (char *)desc64 - (char *)sc->rxq.desc64, 719 sizeof (struct nfe_desc64), ops); 720 } 721 722 void 723 nfe_rxeof(struct nfe_softc *sc) 724 { 725 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 726 struct nfe_desc32 *desc32; 727 struct nfe_desc64 *desc64; 728 struct nfe_rx_data *data; 729 struct nfe_jbuf *jbuf; 730 struct mbuf *m, *mnew; 731 bus_addr_t physaddr; 732 uint16_t flags; 733 int error, len, i; 734 735 desc32 = NULL; 736 desc64 = NULL; 737 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 738 data = &sc->rxq.data[i]; 739 740 if (sc->sc_flags & NFE_40BIT_ADDR) { 741 desc64 = &sc->rxq.desc64[i]; 742 nfe_rxdesc64_sync(sc, desc64, 743 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 744 745 flags = le16toh(desc64->flags); 746 len = le16toh(desc64->length) & 0x3fff; 747 } else { 748 desc32 = &sc->rxq.desc32[i]; 749 nfe_rxdesc32_sync(sc, desc32, 750 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 751 752 flags = le16toh(desc32->flags); 753 len = le16toh(desc32->length) & 0x3fff; 754 } 755 756 if ((flags & NFE_RX_READY) != 0) 757 break; 758 759 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 760 if ((flags & NFE_RX_VALID_V1) == 0) 761 goto skip; 762 763 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 764 flags &= ~NFE_RX_ERROR; 765 len--; /* fix buffer length */ 766 } 767 } else { 768 if ((flags & NFE_RX_VALID_V2) == 0) 769 goto skip; 770 771 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 772 flags &= ~NFE_RX_ERROR; 773 len--; /* fix buffer length */ 774 } 775 } 776 777 if (flags & NFE_RX_ERROR) { 778 ifp->if_ierrors++; 779 goto skip; 780 } 781 782 /* 783 * Try to allocate a new mbuf for this ring element and load 784 * it before processing the current mbuf. If the ring element 785 * cannot be loaded, drop the received packet and reuse the 786 * old mbuf. In the unlikely case that the old mbuf can't be 787 * reloaded either, explicitly panic. 788 */ 789 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 790 if (mnew == NULL) { 791 ifp->if_ierrors++; 792 goto skip; 793 } 794 795 if (sc->sc_flags & NFE_USE_JUMBO) { 796 physaddr = 797 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 798 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 799 if (len > MCLBYTES) { 800 m_freem(mnew); 801 ifp->if_ierrors++; 802 goto skip1; 803 } 804 MCLGET(mnew, M_DONTWAIT); 805 if ((mnew->m_flags & M_EXT) == 0) { 806 m_freem(mnew); 807 ifp->if_ierrors++; 808 goto skip1; 809 } 810 811 (void)memcpy(mtod(mnew, void *), 812 mtod(data->m, const void *), len); 813 m = mnew; 814 goto mbufcopied; 815 } else { 816 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 817 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 818 mtod(data->m, char *) - (char *)sc->rxq.jpool, 819 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 820 821 physaddr = jbuf->physaddr; 822 } 823 } else { 824 MCLGET(mnew, M_DONTWAIT); 825 if ((mnew->m_flags & M_EXT) == 0) { 826 m_freem(mnew); 827 ifp->if_ierrors++; 828 goto skip; 829 } 830 831 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 832 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 833 bus_dmamap_unload(sc->sc_dmat, data->map); 834 835 error = bus_dmamap_load(sc->sc_dmat, data->map, 836 mtod(mnew, void *), MCLBYTES, NULL, 837 BUS_DMA_READ | BUS_DMA_NOWAIT); 838 if (error != 0) { 839 m_freem(mnew); 840 841 /* try to reload the old mbuf */ 842 error = bus_dmamap_load(sc->sc_dmat, data->map, 843 mtod(data->m, void *), MCLBYTES, NULL, 844 BUS_DMA_READ | BUS_DMA_NOWAIT); 845 if (error != 0) { 846 /* very unlikely that it will fail.. */ 847 panic("%s: could not load old rx mbuf", 848 device_xname(sc->sc_dev)); 849 } 850 ifp->if_ierrors++; 851 goto skip; 852 } 853 physaddr = data->map->dm_segs[0].ds_addr; 854 } 855 856 /* 857 * New mbuf successfully loaded, update Rx ring and continue 858 * processing. 859 */ 860 m = data->m; 861 data->m = mnew; 862 863 mbufcopied: 864 /* finalize mbuf */ 865 m->m_pkthdr.len = m->m_len = len; 866 m->m_pkthdr.rcvif = ifp; 867 868 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 869 /* 870 * XXX 871 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 872 */ 873 if (flags & NFE_RX_IP_CSUMOK) { 874 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 875 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 876 device_xname(sc->sc_dev))); 877 } 878 /* 879 * XXX 880 * no way to check M_CSUM_TCP_UDP_BAD or 881 * other protocols? 882 */ 883 if (flags & NFE_RX_UDP_CSUMOK) { 884 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 885 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 886 device_xname(sc->sc_dev))); 887 } else if (flags & NFE_RX_TCP_CSUMOK) { 888 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 889 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 890 device_xname(sc->sc_dev))); 891 } 892 } 893 bpf_mtap(ifp, m); 894 ifp->if_ipackets++; 895 (*ifp->if_input)(ifp, m); 896 897 skip1: 898 /* update mapping address in h/w descriptor */ 899 if (sc->sc_flags & NFE_40BIT_ADDR) { 900 #if defined(__LP64__) 901 desc64->physaddr[0] = htole32(physaddr >> 32); 902 #endif 903 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 904 } else { 905 desc32->physaddr = htole32(physaddr); 906 } 907 908 skip: 909 if (sc->sc_flags & NFE_40BIT_ADDR) { 910 desc64->length = htole16(sc->rxq.bufsz); 911 desc64->flags = htole16(NFE_RX_READY); 912 913 nfe_rxdesc64_sync(sc, desc64, 914 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 915 } else { 916 desc32->length = htole16(sc->rxq.bufsz); 917 desc32->flags = htole16(NFE_RX_READY); 918 919 nfe_rxdesc32_sync(sc, desc32, 920 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 921 } 922 } 923 /* update current RX pointer */ 924 sc->rxq.cur = i; 925 } 926 927 void 928 nfe_txeof(struct nfe_softc *sc) 929 { 930 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 931 struct nfe_desc32 *desc32; 932 struct nfe_desc64 *desc64; 933 struct nfe_tx_data *data = NULL; 934 int i; 935 uint16_t flags; 936 char buf[128]; 937 938 for (i = sc->txq.next; 939 sc->txq.queued > 0; 940 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 941 if (sc->sc_flags & NFE_40BIT_ADDR) { 942 desc64 = &sc->txq.desc64[i]; 943 nfe_txdesc64_sync(sc, desc64, 944 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 945 946 flags = le16toh(desc64->flags); 947 } else { 948 desc32 = &sc->txq.desc32[i]; 949 nfe_txdesc32_sync(sc, desc32, 950 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 951 952 flags = le16toh(desc32->flags); 953 } 954 955 if ((flags & NFE_TX_VALID) != 0) 956 break; 957 958 data = &sc->txq.data[i]; 959 960 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 961 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 962 data->m == NULL) 963 continue; 964 965 if ((flags & NFE_TX_ERROR_V1) != 0) { 966 snprintb(buf, sizeof(buf), NFE_V1_TXERR, flags); 967 aprint_error_dev(sc->sc_dev, "tx v1 error %s\n", 968 buf); 969 ifp->if_oerrors++; 970 } else 971 ifp->if_opackets++; 972 } else { 973 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 974 data->m == NULL) 975 continue; 976 977 if ((flags & NFE_TX_ERROR_V2) != 0) { 978 snprintb(buf, sizeof(buf), NFE_V2_TXERR, flags); 979 aprint_error_dev(sc->sc_dev, "tx v2 error %s\n", 980 buf); 981 ifp->if_oerrors++; 982 } else 983 ifp->if_opackets++; 984 } 985 986 if (data->m == NULL) { /* should not get there */ 987 aprint_error_dev(sc->sc_dev, 988 "last fragment bit w/o associated mbuf!\n"); 989 continue; 990 } 991 992 /* last fragment of the mbuf chain transmitted */ 993 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 994 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 995 bus_dmamap_unload(sc->sc_dmat, data->active); 996 m_freem(data->m); 997 data->m = NULL; 998 } 999 1000 sc->txq.next = i; 1001 1002 if (sc->txq.queued < NFE_TX_RING_COUNT) { 1003 /* at least one slot freed */ 1004 ifp->if_flags &= ~IFF_OACTIVE; 1005 } 1006 1007 if (sc->txq.queued == 0) { 1008 /* all queued packets are sent */ 1009 ifp->if_timer = 0; 1010 } 1011 } 1012 1013 int 1014 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 1015 { 1016 struct nfe_desc32 *desc32; 1017 struct nfe_desc64 *desc64; 1018 struct nfe_tx_data *data; 1019 bus_dmamap_t map; 1020 uint16_t flags, csumflags; 1021 #if NVLAN > 0 1022 struct m_tag *mtag; 1023 uint32_t vtag = 0; 1024 #endif 1025 int error, i, first; 1026 1027 desc32 = NULL; 1028 desc64 = NULL; 1029 data = NULL; 1030 1031 flags = 0; 1032 csumflags = 0; 1033 first = sc->txq.cur; 1034 1035 map = sc->txq.data[first].map; 1036 1037 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1038 if (error != 0) { 1039 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1040 error); 1041 return error; 1042 } 1043 1044 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1045 bus_dmamap_unload(sc->sc_dmat, map); 1046 return ENOBUFS; 1047 } 1048 1049 #if NVLAN > 0 1050 /* setup h/w VLAN tagging */ 1051 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1052 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1053 #endif 1054 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1055 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1056 csumflags |= NFE_TX_IP_CSUM; 1057 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1058 csumflags |= NFE_TX_TCP_UDP_CSUM; 1059 } 1060 1061 for (i = 0; i < map->dm_nsegs; i++) { 1062 data = &sc->txq.data[sc->txq.cur]; 1063 1064 if (sc->sc_flags & NFE_40BIT_ADDR) { 1065 desc64 = &sc->txq.desc64[sc->txq.cur]; 1066 #if defined(__LP64__) 1067 desc64->physaddr[0] = 1068 htole32(map->dm_segs[i].ds_addr >> 32); 1069 #endif 1070 desc64->physaddr[1] = 1071 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1072 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1073 desc64->flags = htole16(flags); 1074 desc64->vtag = 0; 1075 } else { 1076 desc32 = &sc->txq.desc32[sc->txq.cur]; 1077 1078 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1079 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1080 desc32->flags = htole16(flags); 1081 } 1082 1083 /* 1084 * Setting of the valid bit in the first descriptor is 1085 * deferred until the whole chain is fully setup. 1086 */ 1087 flags |= NFE_TX_VALID; 1088 1089 sc->txq.queued++; 1090 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1091 } 1092 1093 /* the whole mbuf chain has been setup */ 1094 if (sc->sc_flags & NFE_40BIT_ADDR) { 1095 /* fix last descriptor */ 1096 flags |= NFE_TX_LASTFRAG_V2; 1097 desc64->flags = htole16(flags); 1098 1099 /* Checksum flags and vtag belong to the first fragment only. */ 1100 #if NVLAN > 0 1101 sc->txq.desc64[first].vtag = htole32(vtag); 1102 #endif 1103 sc->txq.desc64[first].flags |= htole16(csumflags); 1104 1105 /* finally, set the valid bit in the first descriptor */ 1106 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1107 } else { 1108 /* fix last descriptor */ 1109 if (sc->sc_flags & NFE_JUMBO_SUP) 1110 flags |= NFE_TX_LASTFRAG_V2; 1111 else 1112 flags |= NFE_TX_LASTFRAG_V1; 1113 desc32->flags = htole16(flags); 1114 1115 /* Checksum flags belong to the first fragment only. */ 1116 sc->txq.desc32[first].flags |= htole16(csumflags); 1117 1118 /* finally, set the valid bit in the first descriptor */ 1119 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1120 } 1121 1122 data->m = m0; 1123 data->active = map; 1124 1125 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1126 BUS_DMASYNC_PREWRITE); 1127 1128 return 0; 1129 } 1130 1131 void 1132 nfe_start(struct ifnet *ifp) 1133 { 1134 struct nfe_softc *sc = ifp->if_softc; 1135 int old = sc->txq.queued; 1136 struct mbuf *m0; 1137 1138 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1139 return; 1140 1141 for (;;) { 1142 IFQ_POLL(&ifp->if_snd, m0); 1143 if (m0 == NULL) 1144 break; 1145 1146 if (nfe_encap(sc, m0) != 0) { 1147 ifp->if_flags |= IFF_OACTIVE; 1148 break; 1149 } 1150 1151 /* packet put in h/w queue, remove from s/w queue */ 1152 IFQ_DEQUEUE(&ifp->if_snd, m0); 1153 1154 bpf_mtap(ifp, m0); 1155 } 1156 1157 if (sc->txq.queued != old) { 1158 /* packets are queued */ 1159 if (sc->sc_flags & NFE_40BIT_ADDR) 1160 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1161 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1162 else 1163 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1164 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1165 /* kick Tx */ 1166 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1167 1168 /* 1169 * Set a timeout in case the chip goes out to lunch. 1170 */ 1171 ifp->if_timer = 5; 1172 } 1173 } 1174 1175 void 1176 nfe_watchdog(struct ifnet *ifp) 1177 { 1178 struct nfe_softc *sc = ifp->if_softc; 1179 1180 aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1181 1182 ifp->if_flags &= ~IFF_RUNNING; 1183 nfe_init(ifp); 1184 1185 ifp->if_oerrors++; 1186 } 1187 1188 int 1189 nfe_init(struct ifnet *ifp) 1190 { 1191 struct nfe_softc *sc = ifp->if_softc; 1192 uint32_t tmp; 1193 int rc = 0, s; 1194 1195 if (ifp->if_flags & IFF_RUNNING) 1196 return 0; 1197 1198 nfe_stop(ifp, 0); 1199 1200 NFE_WRITE(sc, NFE_TX_UNK, 0); 1201 NFE_WRITE(sc, NFE_STATUS, 0); 1202 1203 sc->rxtxctl = NFE_RXTX_BIT2; 1204 if (sc->sc_flags & NFE_40BIT_ADDR) 1205 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1206 else if (sc->sc_flags & NFE_JUMBO_SUP) 1207 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1208 if (sc->sc_flags & NFE_HW_CSUM) 1209 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1210 #if NVLAN > 0 1211 /* 1212 * Although the adapter is capable of stripping VLAN tags from received 1213 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1214 * purpose. This will be done in software by our network stack. 1215 */ 1216 if (sc->sc_flags & NFE_HW_VLAN) 1217 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1218 #endif 1219 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1220 DELAY(10); 1221 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1222 1223 #if NVLAN 1224 if (sc->sc_flags & NFE_HW_VLAN) 1225 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1226 #endif 1227 1228 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1229 1230 /* set MAC address */ 1231 nfe_set_macaddr(sc, sc->sc_enaddr); 1232 1233 /* tell MAC where rings are in memory */ 1234 #ifdef __LP64__ 1235 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1236 #endif 1237 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1238 #ifdef __LP64__ 1239 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1240 #endif 1241 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1242 1243 NFE_WRITE(sc, NFE_RING_SIZE, 1244 (NFE_RX_RING_COUNT - 1) << 16 | 1245 (NFE_TX_RING_COUNT - 1)); 1246 1247 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1248 1249 /* force MAC to wakeup */ 1250 tmp = NFE_READ(sc, NFE_PWR_STATE); 1251 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1252 DELAY(10); 1253 tmp = NFE_READ(sc, NFE_PWR_STATE); 1254 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1255 1256 s = splnet(); 1257 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1258 nfe_intr(sc); /* XXX clear IRQ status registers */ 1259 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1260 splx(s); 1261 1262 #if 1 1263 /* configure interrupts coalescing/mitigation */ 1264 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1265 #else 1266 /* no interrupt mitigation: one interrupt per packet */ 1267 NFE_WRITE(sc, NFE_IMTIMER, 970); 1268 #endif 1269 1270 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1271 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1272 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1273 1274 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1275 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1276 1277 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1278 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_ENABLE); 1279 1280 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1281 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1282 DELAY(10); 1283 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1284 1285 /* set Rx filter */ 1286 nfe_setmulti(sc); 1287 1288 if ((rc = ether_mediachange(ifp)) != 0) 1289 goto out; 1290 1291 nfe_tick(sc); 1292 1293 /* enable Rx */ 1294 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1295 1296 /* enable Tx */ 1297 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1298 1299 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1300 1301 /* enable interrupts */ 1302 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1303 1304 callout_schedule(&sc->sc_tick_ch, hz); 1305 1306 ifp->if_flags |= IFF_RUNNING; 1307 ifp->if_flags &= ~IFF_OACTIVE; 1308 1309 out: 1310 return rc; 1311 } 1312 1313 void 1314 nfe_stop(struct ifnet *ifp, int disable) 1315 { 1316 struct nfe_softc *sc = ifp->if_softc; 1317 1318 callout_stop(&sc->sc_tick_ch); 1319 1320 ifp->if_timer = 0; 1321 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1322 1323 mii_down(&sc->sc_mii); 1324 1325 /* abort Tx */ 1326 NFE_WRITE(sc, NFE_TX_CTL, 0); 1327 1328 /* disable Rx */ 1329 NFE_WRITE(sc, NFE_RX_CTL, 0); 1330 1331 /* disable interrupts */ 1332 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1333 1334 /* reset Tx and Rx rings */ 1335 nfe_reset_tx_ring(sc, &sc->txq); 1336 nfe_reset_rx_ring(sc, &sc->rxq); 1337 } 1338 1339 int 1340 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1341 { 1342 struct nfe_desc32 *desc32; 1343 struct nfe_desc64 *desc64; 1344 struct nfe_rx_data *data; 1345 struct nfe_jbuf *jbuf; 1346 void **desc; 1347 bus_addr_t physaddr; 1348 int i, nsegs, error, descsize; 1349 1350 if (sc->sc_flags & NFE_40BIT_ADDR) { 1351 desc = (void **)&ring->desc64; 1352 descsize = sizeof (struct nfe_desc64); 1353 } else { 1354 desc = (void **)&ring->desc32; 1355 descsize = sizeof (struct nfe_desc32); 1356 } 1357 1358 ring->cur = ring->next = 0; 1359 ring->bufsz = MCLBYTES; 1360 1361 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1362 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1363 if (error != 0) { 1364 aprint_error_dev(sc->sc_dev, 1365 "could not create desc DMA map\n"); 1366 ring->map = NULL; 1367 goto fail; 1368 } 1369 1370 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1371 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1372 if (error != 0) { 1373 aprint_error_dev(sc->sc_dev, 1374 "could not allocate DMA memory\n"); 1375 goto fail; 1376 } 1377 1378 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1379 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1380 if (error != 0) { 1381 aprint_error_dev(sc->sc_dev, 1382 "could not map desc DMA memory\n"); 1383 goto fail; 1384 } 1385 1386 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1387 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1388 if (error != 0) { 1389 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1390 goto fail; 1391 } 1392 1393 memset(*desc, 0, NFE_RX_RING_COUNT * descsize); 1394 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1395 1396 if (sc->sc_flags & NFE_USE_JUMBO) { 1397 ring->bufsz = NFE_JBYTES; 1398 if ((error = nfe_jpool_alloc(sc)) != 0) { 1399 aprint_error_dev(sc->sc_dev, 1400 "could not allocate jumbo frames\n"); 1401 goto fail; 1402 } 1403 } 1404 1405 /* 1406 * Pre-allocate Rx buffers and populate Rx ring. 1407 */ 1408 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1409 data = &sc->rxq.data[i]; 1410 1411 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1412 if (data->m == NULL) { 1413 aprint_error_dev(sc->sc_dev, 1414 "could not allocate rx mbuf\n"); 1415 error = ENOMEM; 1416 goto fail; 1417 } 1418 1419 if (sc->sc_flags & NFE_USE_JUMBO) { 1420 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1421 aprint_error_dev(sc->sc_dev, 1422 "could not allocate jumbo buffer\n"); 1423 goto fail; 1424 } 1425 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1426 sc); 1427 1428 physaddr = jbuf->physaddr; 1429 } else { 1430 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1431 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1432 if (error != 0) { 1433 aprint_error_dev(sc->sc_dev, 1434 "could not create DMA map\n"); 1435 data->map = NULL; 1436 goto fail; 1437 } 1438 MCLGET(data->m, M_DONTWAIT); 1439 if (!(data->m->m_flags & M_EXT)) { 1440 aprint_error_dev(sc->sc_dev, 1441 "could not allocate mbuf cluster\n"); 1442 error = ENOMEM; 1443 goto fail; 1444 } 1445 1446 error = bus_dmamap_load(sc->sc_dmat, data->map, 1447 mtod(data->m, void *), MCLBYTES, NULL, 1448 BUS_DMA_READ | BUS_DMA_NOWAIT); 1449 if (error != 0) { 1450 aprint_error_dev(sc->sc_dev, 1451 "could not load rx buf DMA map"); 1452 goto fail; 1453 } 1454 physaddr = data->map->dm_segs[0].ds_addr; 1455 } 1456 1457 if (sc->sc_flags & NFE_40BIT_ADDR) { 1458 desc64 = &sc->rxq.desc64[i]; 1459 #if defined(__LP64__) 1460 desc64->physaddr[0] = htole32(physaddr >> 32); 1461 #endif 1462 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1463 desc64->length = htole16(sc->rxq.bufsz); 1464 desc64->flags = htole16(NFE_RX_READY); 1465 } else { 1466 desc32 = &sc->rxq.desc32[i]; 1467 desc32->physaddr = htole32(physaddr); 1468 desc32->length = htole16(sc->rxq.bufsz); 1469 desc32->flags = htole16(NFE_RX_READY); 1470 } 1471 } 1472 1473 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1474 BUS_DMASYNC_PREWRITE); 1475 1476 return 0; 1477 1478 fail: nfe_free_rx_ring(sc, ring); 1479 return error; 1480 } 1481 1482 void 1483 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1484 { 1485 int i; 1486 1487 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1488 if (sc->sc_flags & NFE_40BIT_ADDR) { 1489 ring->desc64[i].length = htole16(ring->bufsz); 1490 ring->desc64[i].flags = htole16(NFE_RX_READY); 1491 } else { 1492 ring->desc32[i].length = htole16(ring->bufsz); 1493 ring->desc32[i].flags = htole16(NFE_RX_READY); 1494 } 1495 } 1496 1497 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1498 BUS_DMASYNC_PREWRITE); 1499 1500 ring->cur = ring->next = 0; 1501 } 1502 1503 void 1504 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1505 { 1506 struct nfe_rx_data *data; 1507 void *desc; 1508 int i, descsize; 1509 1510 if (sc->sc_flags & NFE_40BIT_ADDR) { 1511 desc = ring->desc64; 1512 descsize = sizeof (struct nfe_desc64); 1513 } else { 1514 desc = ring->desc32; 1515 descsize = sizeof (struct nfe_desc32); 1516 } 1517 1518 if (desc != NULL) { 1519 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1520 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1521 bus_dmamap_unload(sc->sc_dmat, ring->map); 1522 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1523 NFE_RX_RING_COUNT * descsize); 1524 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1525 } 1526 1527 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1528 data = &ring->data[i]; 1529 1530 if (data->map != NULL) { 1531 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1532 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1533 bus_dmamap_unload(sc->sc_dmat, data->map); 1534 bus_dmamap_destroy(sc->sc_dmat, data->map); 1535 } 1536 if (data->m != NULL) 1537 m_freem(data->m); 1538 } 1539 } 1540 1541 struct nfe_jbuf * 1542 nfe_jalloc(struct nfe_softc *sc, int i) 1543 { 1544 struct nfe_jbuf *jbuf; 1545 1546 mutex_enter(&sc->rxq.mtx); 1547 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1548 if (jbuf != NULL) 1549 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1550 mutex_exit(&sc->rxq.mtx); 1551 if (jbuf == NULL) 1552 return NULL; 1553 sc->rxq.jbufmap[i] = 1554 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1555 return jbuf; 1556 } 1557 1558 /* 1559 * This is called automatically by the network stack when the mbuf is freed. 1560 * Caution must be taken that the NIC might be reset by the time the mbuf is 1561 * freed. 1562 */ 1563 void 1564 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1565 { 1566 struct nfe_softc *sc = arg; 1567 struct nfe_jbuf *jbuf; 1568 int i; 1569 1570 /* find the jbuf from the base pointer */ 1571 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1572 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1573 aprint_error_dev(sc->sc_dev, 1574 "request to free a buffer (%p) not managed by us\n", buf); 1575 return; 1576 } 1577 jbuf = &sc->rxq.jbuf[i]; 1578 1579 /* ..and put it back in the free list */ 1580 mutex_enter(&sc->rxq.mtx); 1581 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1582 mutex_exit(&sc->rxq.mtx); 1583 1584 if (m != NULL) 1585 pool_cache_put(mb_cache, m); 1586 } 1587 1588 int 1589 nfe_jpool_alloc(struct nfe_softc *sc) 1590 { 1591 struct nfe_rx_ring *ring = &sc->rxq; 1592 struct nfe_jbuf *jbuf; 1593 bus_addr_t physaddr; 1594 char *buf; 1595 int i, nsegs, error; 1596 1597 /* 1598 * Allocate a big chunk of DMA'able memory. 1599 */ 1600 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1601 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1602 if (error != 0) { 1603 aprint_error_dev(sc->sc_dev, 1604 "could not create jumbo DMA map\n"); 1605 ring->jmap = NULL; 1606 goto fail; 1607 } 1608 1609 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1610 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1611 if (error != 0) { 1612 aprint_error_dev(sc->sc_dev, 1613 "could not allocate jumbo DMA memory\n"); 1614 goto fail; 1615 } 1616 1617 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1618 &ring->jpool, BUS_DMA_NOWAIT); 1619 if (error != 0) { 1620 aprint_error_dev(sc->sc_dev, 1621 "could not map jumbo DMA memory\n"); 1622 goto fail; 1623 } 1624 1625 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1626 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1627 if (error != 0) { 1628 aprint_error_dev(sc->sc_dev, 1629 "could not load jumbo DMA map\n"); 1630 goto fail; 1631 } 1632 1633 /* ..and split it into 9KB chunks */ 1634 SLIST_INIT(&ring->jfreelist); 1635 1636 buf = ring->jpool; 1637 physaddr = ring->jmap->dm_segs[0].ds_addr; 1638 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1639 jbuf = &ring->jbuf[i]; 1640 1641 jbuf->buf = buf; 1642 jbuf->physaddr = physaddr; 1643 1644 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1645 1646 buf += NFE_JBYTES; 1647 physaddr += NFE_JBYTES; 1648 } 1649 1650 return 0; 1651 1652 fail: nfe_jpool_free(sc); 1653 return error; 1654 } 1655 1656 void 1657 nfe_jpool_free(struct nfe_softc *sc) 1658 { 1659 struct nfe_rx_ring *ring = &sc->rxq; 1660 1661 if (ring->jmap != NULL) { 1662 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1663 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1664 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1665 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1666 } 1667 if (ring->jpool != NULL) { 1668 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1669 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1670 } 1671 } 1672 1673 int 1674 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1675 { 1676 int i, nsegs, error; 1677 void **desc; 1678 int descsize; 1679 1680 if (sc->sc_flags & NFE_40BIT_ADDR) { 1681 desc = (void **)&ring->desc64; 1682 descsize = sizeof (struct nfe_desc64); 1683 } else { 1684 desc = (void **)&ring->desc32; 1685 descsize = sizeof (struct nfe_desc32); 1686 } 1687 1688 ring->queued = 0; 1689 ring->cur = ring->next = 0; 1690 1691 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1692 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1693 1694 if (error != 0) { 1695 aprint_error_dev(sc->sc_dev, 1696 "could not create desc DMA map\n"); 1697 ring->map = NULL; 1698 goto fail; 1699 } 1700 1701 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1702 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1703 if (error != 0) { 1704 aprint_error_dev(sc->sc_dev, 1705 "could not allocate DMA memory\n"); 1706 goto fail; 1707 } 1708 1709 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1710 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1711 if (error != 0) { 1712 aprint_error_dev(sc->sc_dev, 1713 "could not map desc DMA memory\n"); 1714 goto fail; 1715 } 1716 1717 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1718 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1719 if (error != 0) { 1720 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1721 goto fail; 1722 } 1723 1724 memset(*desc, 0, NFE_TX_RING_COUNT * descsize); 1725 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1726 1727 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1728 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1729 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1730 &ring->data[i].map); 1731 if (error != 0) { 1732 aprint_error_dev(sc->sc_dev, 1733 "could not create DMA map\n"); 1734 ring->data[i].map = NULL; 1735 goto fail; 1736 } 1737 } 1738 1739 return 0; 1740 1741 fail: nfe_free_tx_ring(sc, ring); 1742 return error; 1743 } 1744 1745 void 1746 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1747 { 1748 struct nfe_tx_data *data; 1749 int i; 1750 1751 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1752 if (sc->sc_flags & NFE_40BIT_ADDR) 1753 ring->desc64[i].flags = 0; 1754 else 1755 ring->desc32[i].flags = 0; 1756 1757 data = &ring->data[i]; 1758 1759 if (data->m != NULL) { 1760 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1761 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1762 bus_dmamap_unload(sc->sc_dmat, data->active); 1763 m_freem(data->m); 1764 data->m = NULL; 1765 } 1766 } 1767 1768 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1769 BUS_DMASYNC_PREWRITE); 1770 1771 ring->queued = 0; 1772 ring->cur = ring->next = 0; 1773 } 1774 1775 void 1776 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1777 { 1778 struct nfe_tx_data *data; 1779 void *desc; 1780 int i, descsize; 1781 1782 if (sc->sc_flags & NFE_40BIT_ADDR) { 1783 desc = ring->desc64; 1784 descsize = sizeof (struct nfe_desc64); 1785 } else { 1786 desc = ring->desc32; 1787 descsize = sizeof (struct nfe_desc32); 1788 } 1789 1790 if (desc != NULL) { 1791 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1792 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1793 bus_dmamap_unload(sc->sc_dmat, ring->map); 1794 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1795 NFE_TX_RING_COUNT * descsize); 1796 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1797 } 1798 1799 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1800 data = &ring->data[i]; 1801 1802 if (data->m != NULL) { 1803 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1804 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1805 bus_dmamap_unload(sc->sc_dmat, data->active); 1806 m_freem(data->m); 1807 } 1808 } 1809 1810 /* ..and now actually destroy the DMA mappings */ 1811 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1812 data = &ring->data[i]; 1813 if (data->map == NULL) 1814 continue; 1815 bus_dmamap_destroy(sc->sc_dmat, data->map); 1816 } 1817 } 1818 1819 void 1820 nfe_setmulti(struct nfe_softc *sc) 1821 { 1822 struct ethercom *ec = &sc->sc_ethercom; 1823 struct ifnet *ifp = &ec->ec_if; 1824 struct ether_multi *enm; 1825 struct ether_multistep step; 1826 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1827 uint32_t filter = NFE_RXFILTER_MAGIC; 1828 int i; 1829 1830 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1831 memset(addr, 0, ETHER_ADDR_LEN); 1832 memset(mask, 0, ETHER_ADDR_LEN); 1833 goto done; 1834 } 1835 1836 memcpy(addr, etherbroadcastaddr, ETHER_ADDR_LEN); 1837 memcpy(mask, etherbroadcastaddr, ETHER_ADDR_LEN); 1838 1839 ETHER_FIRST_MULTI(step, ec, enm); 1840 while (enm != NULL) { 1841 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1842 ifp->if_flags |= IFF_ALLMULTI; 1843 memset(addr, 0, ETHER_ADDR_LEN); 1844 memset(mask, 0, ETHER_ADDR_LEN); 1845 goto done; 1846 } 1847 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1848 addr[i] &= enm->enm_addrlo[i]; 1849 mask[i] &= ~enm->enm_addrlo[i]; 1850 } 1851 ETHER_NEXT_MULTI(step, enm); 1852 } 1853 for (i = 0; i < ETHER_ADDR_LEN; i++) 1854 mask[i] |= addr[i]; 1855 1856 done: 1857 addr[0] |= 0x01; /* make sure multicast bit is set */ 1858 1859 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1860 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1861 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1862 addr[5] << 8 | addr[4]); 1863 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1864 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1865 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1866 mask[5] << 8 | mask[4]); 1867 1868 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1869 NFE_WRITE(sc, NFE_RXFILTER, filter); 1870 } 1871 1872 void 1873 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1874 { 1875 uint32_t tmp; 1876 1877 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 1878 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1879 addr[0] = (tmp & 0xff); 1880 addr[1] = (tmp >> 8) & 0xff; 1881 addr[2] = (tmp >> 16) & 0xff; 1882 addr[3] = (tmp >> 24) & 0xff; 1883 1884 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1885 addr[4] = (tmp & 0xff); 1886 addr[5] = (tmp >> 8) & 0xff; 1887 1888 } else { 1889 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1890 addr[0] = (tmp >> 8) & 0xff; 1891 addr[1] = (tmp & 0xff); 1892 1893 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1894 addr[2] = (tmp >> 24) & 0xff; 1895 addr[3] = (tmp >> 16) & 0xff; 1896 addr[4] = (tmp >> 8) & 0xff; 1897 addr[5] = (tmp & 0xff); 1898 } 1899 } 1900 1901 void 1902 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1903 { 1904 NFE_WRITE(sc, NFE_MACADDR_LO, 1905 addr[5] << 8 | addr[4]); 1906 NFE_WRITE(sc, NFE_MACADDR_HI, 1907 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1908 } 1909 1910 void 1911 nfe_tick(void *arg) 1912 { 1913 struct nfe_softc *sc = arg; 1914 int s; 1915 1916 s = splnet(); 1917 mii_tick(&sc->sc_mii); 1918 splx(s); 1919 1920 callout_schedule(&sc->sc_tick_ch, hz); 1921 } 1922 1923 void 1924 nfe_poweron(device_t self) 1925 { 1926 struct nfe_softc *sc = device_private(self); 1927 1928 if ((sc->sc_flags & NFE_PWR_MGMT) != 0) { 1929 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 1930 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 1931 DELAY(100); 1932 NFE_WRITE(sc, NFE_MAC_RESET, 0); 1933 DELAY(100); 1934 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 1935 NFE_WRITE(sc, NFE_PWR2_CTL, 1936 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_WAKEUP_MASK); 1937 } 1938 } 1939 1940 bool 1941 nfe_resume(device_t dv, const pmf_qual_t *qual) 1942 { 1943 nfe_poweron(dv); 1944 1945 return true; 1946 } 1947
Indexes created Tue Sep 30 07:10:03 GMT 2025