if_nfe.c revision 1.52
1 /* $NetBSD: if_nfe.c,v 1.52 2010/11/02 16:56:47 jakllsch Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.77 2008/02/05 16:52:50 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006, 2007 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.52 2010/11/02 16:56:47 jakllsch Exp $"); 25 26 #include "opt_inet.h" 27 #include "vlan.h" 28 29 #include <sys/param.h> 30 #include <sys/endian.h> 31 #include <sys/systm.h> 32 #include <sys/types.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/mutex.h> 36 #include <sys/queue.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/callout.h> 40 #include <sys/socket.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #include <net/bpf.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_nfereg.h> 72 #include <dev/pci/if_nfevar.h> 73 74 static int nfe_ifflags_cb(struct ethercom *); 75 76 int nfe_match(device_t, cfdata_t, void *); 77 void nfe_attach(device_t, device_t, void *); 78 void nfe_power(int, void *); 79 void nfe_miibus_statchg(device_t); 80 int nfe_miibus_readreg(device_t, int, int); 81 void nfe_miibus_writereg(device_t, int, int, int); 82 int nfe_intr(void *); 83 int nfe_ioctl(struct ifnet *, u_long, void *); 84 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 85 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 86 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 87 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 88 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 89 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 90 void nfe_rxeof(struct nfe_softc *); 91 void nfe_txeof(struct nfe_softc *); 92 int nfe_encap(struct nfe_softc *, struct mbuf *); 93 void nfe_start(struct ifnet *); 94 void nfe_watchdog(struct ifnet *); 95 int nfe_init(struct ifnet *); 96 void nfe_stop(struct ifnet *, int); 97 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 98 void nfe_jfree(struct mbuf *, void *, size_t, void *); 99 int nfe_jpool_alloc(struct nfe_softc *); 100 void nfe_jpool_free(struct nfe_softc *); 101 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 102 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 105 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 void nfe_setmulti(struct nfe_softc *); 108 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 109 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 110 void nfe_tick(void *); 111 void nfe_poweron(device_t); 112 bool nfe_resume(device_t, const pmf_qual_t *); 113 114 CFATTACH_DECL_NEW(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, 115 NULL, NULL); 116 117 /* #define NFE_NO_JUMBO */ 118 119 #ifdef NFE_DEBUG 120 int nfedebug = 0; 121 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 122 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 123 #else 124 #define DPRINTF(x) 125 #define DPRINTFN(n,x) 126 #endif 127 128 /* deal with naming differences */ 129 130 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 131 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 132 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 133 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 134 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 135 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 136 137 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 138 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 139 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 140 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 141 142 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 143 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 144 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 145 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 146 147 #ifdef _LP64 148 #define __LP64__ 1 149 #endif 150 151 const struct nfe_product { 152 pci_vendor_id_t vendor; 153 pci_product_id_t product; 154 } nfe_devices[] = { 155 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 183 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 184 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 185 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 }, 186 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1 }, 187 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2 }, 188 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3 }, 189 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4 }, 190 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1 }, 191 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2 }, 192 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3 }, 193 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4 } 194 }; 195 196 int 197 nfe_match(device_t dev, cfdata_t match, void *aux) 198 { 199 struct pci_attach_args *pa = aux; 200 const struct nfe_product *np; 201 int i; 202 203 for (i = 0; i < __arraycount(nfe_devices); i++) { 204 np = &nfe_devices[i]; 205 if (PCI_VENDOR(pa->pa_id) == np->vendor && 206 PCI_PRODUCT(pa->pa_id) == np->product) 207 return 1; 208 } 209 return 0; 210 } 211 212 void 213 nfe_attach(device_t parent, device_t self, void *aux) 214 { 215 struct nfe_softc *sc = device_private(self); 216 struct pci_attach_args *pa = aux; 217 pci_chipset_tag_t pc = pa->pa_pc; 218 pci_intr_handle_t ih; 219 const char *intrstr; 220 struct ifnet *ifp; 221 bus_size_t memsize; 222 pcireg_t memtype, csr; 223 char devinfo[256]; 224 int mii_flags = 0; 225 226 sc->sc_dev = self; 227 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 228 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 229 230 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 231 switch (memtype) { 232 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 233 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 234 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 235 &sc->sc_memh, NULL, &memsize) == 0) 236 break; 237 /* FALLTHROUGH */ 238 default: 239 aprint_error_dev(self, "could not map mem space\n"); 240 return; 241 } 242 243 if (pci_intr_map(pa, &ih) != 0) { 244 aprint_error_dev(self, "could not map interrupt\n"); 245 goto fail; 246 } 247 248 intrstr = pci_intr_string(pc, ih); 249 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 250 if (sc->sc_ih == NULL) { 251 aprint_error_dev(self, "could not establish interrupt"); 252 if (intrstr != NULL) 253 aprint_error(" at %s", intrstr); 254 aprint_error("\n"); 255 goto fail; 256 } 257 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 258 259 sc->sc_dmat = pa->pa_dmat; 260 261 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 262 csr |= PCI_COMMAND_MASTER_ENABLE; 263 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 264 265 sc->sc_flags = 0; 266 267 switch (PCI_PRODUCT(pa->pa_id)) { 268 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 269 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 270 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 271 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 272 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 273 break; 274 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 275 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 276 sc->sc_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT; 277 break; 278 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 279 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 280 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 281 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 282 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 283 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 284 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 285 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 286 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 287 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 288 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 289 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 290 sc->sc_flags |= NFE_40BIT_ADDR | NFE_CORRECT_MACADDR | 291 NFE_PWR_MGMT; 292 break; 293 case PCI_PRODUCT_NVIDIA_MCP77_LAN1: 294 case PCI_PRODUCT_NVIDIA_MCP77_LAN2: 295 case PCI_PRODUCT_NVIDIA_MCP77_LAN3: 296 case PCI_PRODUCT_NVIDIA_MCP77_LAN4: 297 sc->sc_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | 298 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 299 break; 300 case PCI_PRODUCT_NVIDIA_MCP79_LAN1: 301 case PCI_PRODUCT_NVIDIA_MCP79_LAN2: 302 case PCI_PRODUCT_NVIDIA_MCP79_LAN3: 303 case PCI_PRODUCT_NVIDIA_MCP79_LAN4: 304 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 305 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 306 break; 307 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 308 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 309 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 310 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 311 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 312 break; 313 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 314 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 315 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 316 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 317 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 318 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 319 mii_flags = MIIF_DOPAUSE; 320 break; 321 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 322 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 323 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 324 NFE_HW_VLAN | NFE_PWR_MGMT; 325 break; 326 } 327 328 nfe_poweron(self); 329 330 #ifndef NFE_NO_JUMBO 331 /* enable jumbo frames for adapters that support it */ 332 if (sc->sc_flags & NFE_JUMBO_SUP) 333 sc->sc_flags |= NFE_USE_JUMBO; 334 #endif 335 336 /* Check for reversed ethernet address */ 337 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 338 sc->sc_flags |= NFE_CORRECT_MACADDR; 339 340 nfe_get_macaddr(sc, sc->sc_enaddr); 341 aprint_normal_dev(self, "Ethernet address %s\n", 342 ether_sprintf(sc->sc_enaddr)); 343 344 /* 345 * Allocate Tx and Rx rings. 346 */ 347 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 348 aprint_error_dev(self, "could not allocate Tx ring\n"); 349 goto fail; 350 } 351 352 mutex_init(&sc->rxq.mtx, MUTEX_DEFAULT, IPL_NET); 353 354 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 355 aprint_error_dev(self, "could not allocate Rx ring\n"); 356 nfe_free_tx_ring(sc, &sc->txq); 357 goto fail; 358 } 359 360 ifp = &sc->sc_ethercom.ec_if; 361 ifp->if_softc = sc; 362 ifp->if_mtu = ETHERMTU; 363 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 364 ifp->if_ioctl = nfe_ioctl; 365 ifp->if_start = nfe_start; 366 ifp->if_stop = nfe_stop; 367 ifp->if_watchdog = nfe_watchdog; 368 ifp->if_init = nfe_init; 369 ifp->if_baudrate = IF_Gbps(1); 370 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 371 IFQ_SET_READY(&ifp->if_snd); 372 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 373 374 if (sc->sc_flags & NFE_USE_JUMBO) 375 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 376 377 #if NVLAN > 0 378 if (sc->sc_flags & NFE_HW_VLAN) 379 sc->sc_ethercom.ec_capabilities |= 380 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 381 #endif 382 if (sc->sc_flags & NFE_HW_CSUM) { 383 ifp->if_capabilities |= 384 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 385 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 386 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 387 } 388 389 sc->sc_mii.mii_ifp = ifp; 390 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 391 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 392 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 393 394 sc->sc_ethercom.ec_mii = &sc->sc_mii; 395 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 396 ether_mediastatus); 397 398 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 399 MII_OFFSET_ANY, mii_flags); 400 401 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 402 aprint_error_dev(self, "no PHY found!\n"); 403 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 404 0, NULL); 405 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 406 } else 407 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 408 409 if_attach(ifp); 410 ether_ifattach(ifp, sc->sc_enaddr); 411 ether_set_ifflags_cb(&sc->sc_ethercom, nfe_ifflags_cb); 412 413 callout_init(&sc->sc_tick_ch, 0); 414 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 415 416 if (pmf_device_register(self, NULL, nfe_resume)) 417 pmf_class_network_register(self, ifp); 418 else 419 aprint_error_dev(self, "couldn't establish power handler\n"); 420 421 return; 422 423 fail: 424 if (sc->sc_ih != NULL) { 425 pci_intr_disestablish(pc, sc->sc_ih); 426 sc->sc_ih = NULL; 427 } 428 if (memsize) 429 bus_space_unmap(sc->sc_memt, sc->sc_memh, memsize); 430 } 431 432 void 433 nfe_miibus_statchg(device_t dev) 434 { 435 struct nfe_softc *sc = device_private(dev); 436 struct mii_data *mii = &sc->sc_mii; 437 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 438 439 phy = NFE_READ(sc, NFE_PHY_IFACE); 440 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 441 442 seed = NFE_READ(sc, NFE_RNDSEED); 443 seed &= ~NFE_SEED_MASK; 444 445 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 446 phy |= NFE_PHY_HDX; /* half-duplex */ 447 misc |= NFE_MISC1_HDX; 448 } 449 450 switch (IFM_SUBTYPE(mii->mii_media_active)) { 451 case IFM_1000_T: /* full-duplex only */ 452 link |= NFE_MEDIA_1000T; 453 seed |= NFE_SEED_1000T; 454 phy |= NFE_PHY_1000T; 455 break; 456 case IFM_100_TX: 457 link |= NFE_MEDIA_100TX; 458 seed |= NFE_SEED_100TX; 459 phy |= NFE_PHY_100TX; 460 break; 461 case IFM_10_T: 462 link |= NFE_MEDIA_10T; 463 seed |= NFE_SEED_10T; 464 break; 465 } 466 467 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 468 469 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 470 NFE_WRITE(sc, NFE_MISC1, misc); 471 NFE_WRITE(sc, NFE_LINKSPEED, link); 472 } 473 474 int 475 nfe_miibus_readreg(device_t dev, int phy, int reg) 476 { 477 struct nfe_softc *sc = device_private(dev); 478 uint32_t val; 479 int ntries; 480 481 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 482 483 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 484 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 485 DELAY(100); 486 } 487 488 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 489 490 for (ntries = 0; ntries < 1000; ntries++) { 491 DELAY(100); 492 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 493 break; 494 } 495 if (ntries == 1000) { 496 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 497 device_xname(sc->sc_dev))); 498 return 0; 499 } 500 501 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 502 DPRINTFN(2, ("%s: could not read PHY\n", 503 device_xname(sc->sc_dev))); 504 return 0; 505 } 506 507 val = NFE_READ(sc, NFE_PHY_DATA); 508 if (val != 0xffffffff && val != 0) 509 sc->mii_phyaddr = phy; 510 511 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 512 device_xname(sc->sc_dev), phy, reg, val)); 513 514 return val; 515 } 516 517 void 518 nfe_miibus_writereg(device_t dev, int phy, int reg, int val) 519 { 520 struct nfe_softc *sc = device_private(dev); 521 uint32_t ctl; 522 int ntries; 523 524 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 525 526 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 527 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 528 DELAY(100); 529 } 530 531 NFE_WRITE(sc, NFE_PHY_DATA, val); 532 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 533 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 534 535 for (ntries = 0; ntries < 1000; ntries++) { 536 DELAY(100); 537 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 538 break; 539 } 540 #ifdef NFE_DEBUG 541 if (nfedebug >= 2 && ntries == 1000) 542 printf("could not write to PHY\n"); 543 #endif 544 } 545 546 int 547 nfe_intr(void *arg) 548 { 549 struct nfe_softc *sc = arg; 550 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 551 uint32_t r; 552 int handled; 553 554 if ((ifp->if_flags & IFF_UP) == 0) 555 return 0; 556 557 handled = 0; 558 559 for (;;) { 560 r = NFE_READ(sc, NFE_IRQ_STATUS); 561 if ((r & NFE_IRQ_WANTED) == 0) 562 break; 563 564 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 565 handled = 1; 566 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 567 568 if ((r & (NFE_IRQ_RXERR|NFE_IRQ_RX_NOBUF|NFE_IRQ_RX)) != 0) { 569 /* check Rx ring */ 570 nfe_rxeof(sc); 571 } 572 if ((r & (NFE_IRQ_TXERR|NFE_IRQ_TXERR2|NFE_IRQ_TX_DONE)) != 0) { 573 /* check Tx ring */ 574 nfe_txeof(sc); 575 } 576 if ((r & NFE_IRQ_LINK) != 0) { 577 NFE_READ(sc, NFE_PHY_STATUS); 578 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 579 DPRINTF(("%s: link state changed\n", 580 device_xname(sc->sc_dev))); 581 } 582 } 583 584 if (handled && !IF_IS_EMPTY(&ifp->if_snd)) 585 nfe_start(ifp); 586 587 return handled; 588 } 589 590 static int 591 nfe_ifflags_cb(struct ethercom *ec) 592 { 593 struct ifnet *ifp = &ec->ec_if; 594 struct nfe_softc *sc = ifp->if_softc; 595 int change = ifp->if_flags ^ sc->sc_if_flags; 596 597 /* 598 * If only the PROMISC flag changes, then 599 * don't do a full re-init of the chip, just update 600 * the Rx filter. 601 */ 602 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 603 return ENETRESET; 604 else if ((change & IFF_PROMISC) != 0) 605 nfe_setmulti(sc); 606 607 return 0; 608 } 609 610 int 611 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 612 { 613 struct nfe_softc *sc = ifp->if_softc; 614 struct ifaddr *ifa = (struct ifaddr *)data; 615 int s, error = 0; 616 617 s = splnet(); 618 619 switch (cmd) { 620 case SIOCINITIFADDR: 621 ifp->if_flags |= IFF_UP; 622 nfe_init(ifp); 623 switch (ifa->ifa_addr->sa_family) { 624 #ifdef INET 625 case AF_INET: 626 arp_ifinit(ifp, ifa); 627 break; 628 #endif 629 default: 630 break; 631 } 632 break; 633 default: 634 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 635 break; 636 637 error = 0; 638 639 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 640 ; 641 else if (ifp->if_flags & IFF_RUNNING) 642 nfe_setmulti(sc); 643 break; 644 } 645 sc->sc_if_flags = ifp->if_flags; 646 647 splx(s); 648 649 return error; 650 } 651 652 void 653 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 654 { 655 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 656 (char *)desc32 - (char *)sc->txq.desc32, 657 sizeof (struct nfe_desc32), ops); 658 } 659 660 void 661 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 662 { 663 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 664 (char *)desc64 - (char *)sc->txq.desc64, 665 sizeof (struct nfe_desc64), ops); 666 } 667 668 void 669 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 670 { 671 if (end > start) { 672 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 673 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 674 (char *)&sc->txq.desc32[end] - 675 (char *)&sc->txq.desc32[start], ops); 676 return; 677 } 678 /* sync from 'start' to end of ring */ 679 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 680 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 681 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 682 (char *)&sc->txq.desc32[start], ops); 683 684 /* sync from start of ring to 'end' */ 685 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 686 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 687 } 688 689 void 690 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 691 { 692 if (end > start) { 693 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 694 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 695 (char *)&sc->txq.desc64[end] - 696 (char *)&sc->txq.desc64[start], ops); 697 return; 698 } 699 /* sync from 'start' to end of ring */ 700 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 701 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 702 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 703 (char *)&sc->txq.desc64[start], ops); 704 705 /* sync from start of ring to 'end' */ 706 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 707 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 708 } 709 710 void 711 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 712 { 713 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 714 (char *)desc32 - (char *)sc->rxq.desc32, 715 sizeof (struct nfe_desc32), ops); 716 } 717 718 void 719 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 720 { 721 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 722 (char *)desc64 - (char *)sc->rxq.desc64, 723 sizeof (struct nfe_desc64), ops); 724 } 725 726 void 727 nfe_rxeof(struct nfe_softc *sc) 728 { 729 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 730 struct nfe_desc32 *desc32; 731 struct nfe_desc64 *desc64; 732 struct nfe_rx_data *data; 733 struct nfe_jbuf *jbuf; 734 struct mbuf *m, *mnew; 735 bus_addr_t physaddr; 736 uint16_t flags; 737 int error, len, i; 738 739 desc32 = NULL; 740 desc64 = NULL; 741 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 742 data = &sc->rxq.data[i]; 743 744 if (sc->sc_flags & NFE_40BIT_ADDR) { 745 desc64 = &sc->rxq.desc64[i]; 746 nfe_rxdesc64_sync(sc, desc64, 747 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 748 749 flags = le16toh(desc64->flags); 750 len = le16toh(desc64->length) & 0x3fff; 751 } else { 752 desc32 = &sc->rxq.desc32[i]; 753 nfe_rxdesc32_sync(sc, desc32, 754 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 755 756 flags = le16toh(desc32->flags); 757 len = le16toh(desc32->length) & 0x3fff; 758 } 759 760 if ((flags & NFE_RX_READY) != 0) 761 break; 762 763 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 764 if ((flags & NFE_RX_VALID_V1) == 0) 765 goto skip; 766 767 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 768 flags &= ~NFE_RX_ERROR; 769 len--; /* fix buffer length */ 770 } 771 } else { 772 if ((flags & NFE_RX_VALID_V2) == 0) 773 goto skip; 774 775 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 776 flags &= ~NFE_RX_ERROR; 777 len--; /* fix buffer length */ 778 } 779 } 780 781 if (flags & NFE_RX_ERROR) { 782 ifp->if_ierrors++; 783 goto skip; 784 } 785 786 /* 787 * Try to allocate a new mbuf for this ring element and load 788 * it before processing the current mbuf. If the ring element 789 * cannot be loaded, drop the received packet and reuse the 790 * old mbuf. In the unlikely case that the old mbuf can't be 791 * reloaded either, explicitly panic. 792 */ 793 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 794 if (mnew == NULL) { 795 ifp->if_ierrors++; 796 goto skip; 797 } 798 799 if (sc->sc_flags & NFE_USE_JUMBO) { 800 physaddr = 801 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 802 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 803 if (len > MCLBYTES) { 804 m_freem(mnew); 805 ifp->if_ierrors++; 806 goto skip1; 807 } 808 MCLGET(mnew, M_DONTWAIT); 809 if ((mnew->m_flags & M_EXT) == 0) { 810 m_freem(mnew); 811 ifp->if_ierrors++; 812 goto skip1; 813 } 814 815 (void)memcpy(mtod(mnew, void *), 816 mtod(data->m, const void *), len); 817 m = mnew; 818 goto mbufcopied; 819 } else { 820 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 821 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 822 mtod(data->m, char *) - (char *)sc->rxq.jpool, 823 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 824 825 physaddr = jbuf->physaddr; 826 } 827 } else { 828 MCLGET(mnew, M_DONTWAIT); 829 if ((mnew->m_flags & M_EXT) == 0) { 830 m_freem(mnew); 831 ifp->if_ierrors++; 832 goto skip; 833 } 834 835 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 836 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 837 bus_dmamap_unload(sc->sc_dmat, data->map); 838 839 error = bus_dmamap_load(sc->sc_dmat, data->map, 840 mtod(mnew, void *), MCLBYTES, NULL, 841 BUS_DMA_READ | BUS_DMA_NOWAIT); 842 if (error != 0) { 843 m_freem(mnew); 844 845 /* try to reload the old mbuf */ 846 error = bus_dmamap_load(sc->sc_dmat, data->map, 847 mtod(data->m, void *), MCLBYTES, NULL, 848 BUS_DMA_READ | BUS_DMA_NOWAIT); 849 if (error != 0) { 850 /* very unlikely that it will fail.. */ 851 panic("%s: could not load old rx mbuf", 852 device_xname(sc->sc_dev)); 853 } 854 ifp->if_ierrors++; 855 goto skip; 856 } 857 physaddr = data->map->dm_segs[0].ds_addr; 858 } 859 860 /* 861 * New mbuf successfully loaded, update Rx ring and continue 862 * processing. 863 */ 864 m = data->m; 865 data->m = mnew; 866 867 mbufcopied: 868 /* finalize mbuf */ 869 m->m_pkthdr.len = m->m_len = len; 870 m->m_pkthdr.rcvif = ifp; 871 872 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 873 /* 874 * XXX 875 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 876 */ 877 if (flags & NFE_RX_IP_CSUMOK) { 878 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 879 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 880 device_xname(sc->sc_dev))); 881 } 882 /* 883 * XXX 884 * no way to check M_CSUM_TCP_UDP_BAD or 885 * other protocols? 886 */ 887 if (flags & NFE_RX_UDP_CSUMOK) { 888 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 889 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 890 device_xname(sc->sc_dev))); 891 } else if (flags & NFE_RX_TCP_CSUMOK) { 892 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 893 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 894 device_xname(sc->sc_dev))); 895 } 896 } 897 bpf_mtap(ifp, m); 898 ifp->if_ipackets++; 899 (*ifp->if_input)(ifp, m); 900 901 skip1: 902 /* update mapping address in h/w descriptor */ 903 if (sc->sc_flags & NFE_40BIT_ADDR) { 904 #if defined(__LP64__) 905 desc64->physaddr[0] = htole32(physaddr >> 32); 906 #endif 907 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 908 } else { 909 desc32->physaddr = htole32(physaddr); 910 } 911 912 skip: 913 if (sc->sc_flags & NFE_40BIT_ADDR) { 914 desc64->length = htole16(sc->rxq.bufsz); 915 desc64->flags = htole16(NFE_RX_READY); 916 917 nfe_rxdesc64_sync(sc, desc64, 918 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 919 } else { 920 desc32->length = htole16(sc->rxq.bufsz); 921 desc32->flags = htole16(NFE_RX_READY); 922 923 nfe_rxdesc32_sync(sc, desc32, 924 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 925 } 926 } 927 /* update current RX pointer */ 928 sc->rxq.cur = i; 929 } 930 931 void 932 nfe_txeof(struct nfe_softc *sc) 933 { 934 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 935 struct nfe_desc32 *desc32; 936 struct nfe_desc64 *desc64; 937 struct nfe_tx_data *data = NULL; 938 int i; 939 uint16_t flags; 940 char buf[128]; 941 942 for (i = sc->txq.next; 943 sc->txq.queued > 0; 944 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 945 if (sc->sc_flags & NFE_40BIT_ADDR) { 946 desc64 = &sc->txq.desc64[i]; 947 nfe_txdesc64_sync(sc, desc64, 948 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 949 950 flags = le16toh(desc64->flags); 951 } else { 952 desc32 = &sc->txq.desc32[i]; 953 nfe_txdesc32_sync(sc, desc32, 954 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 955 956 flags = le16toh(desc32->flags); 957 } 958 959 if ((flags & NFE_TX_VALID) != 0) 960 break; 961 962 data = &sc->txq.data[i]; 963 964 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 965 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 966 data->m == NULL) 967 continue; 968 969 if ((flags & NFE_TX_ERROR_V1) != 0) { 970 snprintb(buf, sizeof(buf), NFE_V1_TXERR, flags); 971 aprint_error_dev(sc->sc_dev, "tx v1 error %s\n", 972 buf); 973 ifp->if_oerrors++; 974 } else 975 ifp->if_opackets++; 976 } else { 977 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 978 data->m == NULL) 979 continue; 980 981 if ((flags & NFE_TX_ERROR_V2) != 0) { 982 snprintb(buf, sizeof(buf), NFE_V2_TXERR, flags); 983 aprint_error_dev(sc->sc_dev, "tx v2 error %s\n", 984 buf); 985 ifp->if_oerrors++; 986 } else 987 ifp->if_opackets++; 988 } 989 990 if (data->m == NULL) { /* should not get there */ 991 aprint_error_dev(sc->sc_dev, 992 "last fragment bit w/o associated mbuf!\n"); 993 continue; 994 } 995 996 /* last fragment of the mbuf chain transmitted */ 997 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 998 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 999 bus_dmamap_unload(sc->sc_dmat, data->active); 1000 m_freem(data->m); 1001 data->m = NULL; 1002 } 1003 1004 sc->txq.next = i; 1005 1006 if (sc->txq.queued < NFE_TX_RING_COUNT) { 1007 /* at least one slot freed */ 1008 ifp->if_flags &= ~IFF_OACTIVE; 1009 } 1010 1011 if (sc->txq.queued == 0) { 1012 /* all queued packets are sent */ 1013 ifp->if_timer = 0; 1014 } 1015 } 1016 1017 int 1018 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 1019 { 1020 struct nfe_desc32 *desc32; 1021 struct nfe_desc64 *desc64; 1022 struct nfe_tx_data *data; 1023 bus_dmamap_t map; 1024 uint16_t flags, csumflags; 1025 #if NVLAN > 0 1026 struct m_tag *mtag; 1027 uint32_t vtag = 0; 1028 #endif 1029 int error, i, first; 1030 1031 desc32 = NULL; 1032 desc64 = NULL; 1033 data = NULL; 1034 1035 flags = 0; 1036 csumflags = 0; 1037 first = sc->txq.cur; 1038 1039 map = sc->txq.data[first].map; 1040 1041 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1042 if (error != 0) { 1043 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1044 error); 1045 return error; 1046 } 1047 1048 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1049 bus_dmamap_unload(sc->sc_dmat, map); 1050 return ENOBUFS; 1051 } 1052 1053 #if NVLAN > 0 1054 /* setup h/w VLAN tagging */ 1055 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1056 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1057 #endif 1058 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1059 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1060 csumflags |= NFE_TX_IP_CSUM; 1061 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1062 csumflags |= NFE_TX_TCP_UDP_CSUM; 1063 } 1064 1065 for (i = 0; i < map->dm_nsegs; i++) { 1066 data = &sc->txq.data[sc->txq.cur]; 1067 1068 if (sc->sc_flags & NFE_40BIT_ADDR) { 1069 desc64 = &sc->txq.desc64[sc->txq.cur]; 1070 #if defined(__LP64__) 1071 desc64->physaddr[0] = 1072 htole32(map->dm_segs[i].ds_addr >> 32); 1073 #endif 1074 desc64->physaddr[1] = 1075 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1076 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1077 desc64->flags = htole16(flags); 1078 desc64->vtag = 0; 1079 } else { 1080 desc32 = &sc->txq.desc32[sc->txq.cur]; 1081 1082 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1083 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1084 desc32->flags = htole16(flags); 1085 } 1086 1087 /* 1088 * Setting of the valid bit in the first descriptor is 1089 * deferred until the whole chain is fully setup. 1090 */ 1091 flags |= NFE_TX_VALID; 1092 1093 sc->txq.queued++; 1094 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1095 } 1096 1097 /* the whole mbuf chain has been setup */ 1098 if (sc->sc_flags & NFE_40BIT_ADDR) { 1099 /* fix last descriptor */ 1100 flags |= NFE_TX_LASTFRAG_V2; 1101 desc64->flags = htole16(flags); 1102 1103 /* Checksum flags and vtag belong to the first fragment only. */ 1104 #if NVLAN > 0 1105 sc->txq.desc64[first].vtag = htole32(vtag); 1106 #endif 1107 sc->txq.desc64[first].flags |= htole16(csumflags); 1108 1109 /* finally, set the valid bit in the first descriptor */ 1110 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1111 } else { 1112 /* fix last descriptor */ 1113 if (sc->sc_flags & NFE_JUMBO_SUP) 1114 flags |= NFE_TX_LASTFRAG_V2; 1115 else 1116 flags |= NFE_TX_LASTFRAG_V1; 1117 desc32->flags = htole16(flags); 1118 1119 /* Checksum flags belong to the first fragment only. */ 1120 sc->txq.desc32[first].flags |= htole16(csumflags); 1121 1122 /* finally, set the valid bit in the first descriptor */ 1123 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1124 } 1125 1126 data->m = m0; 1127 data->active = map; 1128 1129 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1130 BUS_DMASYNC_PREWRITE); 1131 1132 return 0; 1133 } 1134 1135 void 1136 nfe_start(struct ifnet *ifp) 1137 { 1138 struct nfe_softc *sc = ifp->if_softc; 1139 int old = sc->txq.queued; 1140 struct mbuf *m0; 1141 1142 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1143 return; 1144 1145 for (;;) { 1146 IFQ_POLL(&ifp->if_snd, m0); 1147 if (m0 == NULL) 1148 break; 1149 1150 if (nfe_encap(sc, m0) != 0) { 1151 ifp->if_flags |= IFF_OACTIVE; 1152 break; 1153 } 1154 1155 /* packet put in h/w queue, remove from s/w queue */ 1156 IFQ_DEQUEUE(&ifp->if_snd, m0); 1157 1158 bpf_mtap(ifp, m0); 1159 } 1160 1161 if (sc->txq.queued != old) { 1162 /* packets are queued */ 1163 if (sc->sc_flags & NFE_40BIT_ADDR) 1164 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1165 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1166 else 1167 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1168 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1169 /* kick Tx */ 1170 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1171 1172 /* 1173 * Set a timeout in case the chip goes out to lunch. 1174 */ 1175 ifp->if_timer = 5; 1176 } 1177 } 1178 1179 void 1180 nfe_watchdog(struct ifnet *ifp) 1181 { 1182 struct nfe_softc *sc = ifp->if_softc; 1183 1184 aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1185 1186 ifp->if_flags &= ~IFF_RUNNING; 1187 nfe_init(ifp); 1188 1189 ifp->if_oerrors++; 1190 } 1191 1192 int 1193 nfe_init(struct ifnet *ifp) 1194 { 1195 struct nfe_softc *sc = ifp->if_softc; 1196 uint32_t tmp; 1197 int rc = 0, s; 1198 1199 if (ifp->if_flags & IFF_RUNNING) 1200 return 0; 1201 1202 nfe_stop(ifp, 0); 1203 1204 NFE_WRITE(sc, NFE_TX_UNK, 0); 1205 NFE_WRITE(sc, NFE_STATUS, 0); 1206 1207 sc->rxtxctl = NFE_RXTX_BIT2; 1208 if (sc->sc_flags & NFE_40BIT_ADDR) 1209 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1210 else if (sc->sc_flags & NFE_JUMBO_SUP) 1211 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1212 if (sc->sc_flags & NFE_HW_CSUM) 1213 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1214 #if NVLAN > 0 1215 /* 1216 * Although the adapter is capable of stripping VLAN tags from received 1217 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1218 * purpose. This will be done in software by our network stack. 1219 */ 1220 if (sc->sc_flags & NFE_HW_VLAN) 1221 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1222 #endif 1223 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1224 DELAY(10); 1225 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1226 1227 #if NVLAN 1228 if (sc->sc_flags & NFE_HW_VLAN) 1229 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1230 #endif 1231 1232 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1233 1234 /* set MAC address */ 1235 nfe_set_macaddr(sc, sc->sc_enaddr); 1236 1237 /* tell MAC where rings are in memory */ 1238 #ifdef __LP64__ 1239 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1240 #endif 1241 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1242 #ifdef __LP64__ 1243 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1244 #endif 1245 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1246 1247 NFE_WRITE(sc, NFE_RING_SIZE, 1248 (NFE_RX_RING_COUNT - 1) << 16 | 1249 (NFE_TX_RING_COUNT - 1)); 1250 1251 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1252 1253 /* force MAC to wakeup */ 1254 tmp = NFE_READ(sc, NFE_PWR_STATE); 1255 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1256 DELAY(10); 1257 tmp = NFE_READ(sc, NFE_PWR_STATE); 1258 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1259 1260 s = splnet(); 1261 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1262 nfe_intr(sc); /* XXX clear IRQ status registers */ 1263 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1264 splx(s); 1265 1266 #if 1 1267 /* configure interrupts coalescing/mitigation */ 1268 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1269 #else 1270 /* no interrupt mitigation: one interrupt per packet */ 1271 NFE_WRITE(sc, NFE_IMTIMER, 970); 1272 #endif 1273 1274 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1275 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1276 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1277 1278 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1279 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1280 1281 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1282 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_ENABLE); 1283 1284 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1285 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1286 DELAY(10); 1287 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1288 1289 /* set Rx filter */ 1290 nfe_setmulti(sc); 1291 1292 if ((rc = ether_mediachange(ifp)) != 0) 1293 goto out; 1294 1295 nfe_tick(sc); 1296 1297 /* enable Rx */ 1298 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1299 1300 /* enable Tx */ 1301 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1302 1303 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1304 1305 /* enable interrupts */ 1306 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1307 1308 callout_schedule(&sc->sc_tick_ch, hz); 1309 1310 ifp->if_flags |= IFF_RUNNING; 1311 ifp->if_flags &= ~IFF_OACTIVE; 1312 1313 out: 1314 return rc; 1315 } 1316 1317 void 1318 nfe_stop(struct ifnet *ifp, int disable) 1319 { 1320 struct nfe_softc *sc = ifp->if_softc; 1321 1322 callout_stop(&sc->sc_tick_ch); 1323 1324 ifp->if_timer = 0; 1325 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1326 1327 mii_down(&sc->sc_mii); 1328 1329 /* abort Tx */ 1330 NFE_WRITE(sc, NFE_TX_CTL, 0); 1331 1332 /* disable Rx */ 1333 NFE_WRITE(sc, NFE_RX_CTL, 0); 1334 1335 /* disable interrupts */ 1336 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1337 1338 /* reset Tx and Rx rings */ 1339 nfe_reset_tx_ring(sc, &sc->txq); 1340 nfe_reset_rx_ring(sc, &sc->rxq); 1341 } 1342 1343 int 1344 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1345 { 1346 struct nfe_desc32 *desc32; 1347 struct nfe_desc64 *desc64; 1348 struct nfe_rx_data *data; 1349 struct nfe_jbuf *jbuf; 1350 void **desc; 1351 bus_addr_t physaddr; 1352 int i, nsegs, error, descsize; 1353 1354 if (sc->sc_flags & NFE_40BIT_ADDR) { 1355 desc = (void **)&ring->desc64; 1356 descsize = sizeof (struct nfe_desc64); 1357 } else { 1358 desc = (void **)&ring->desc32; 1359 descsize = sizeof (struct nfe_desc32); 1360 } 1361 1362 ring->cur = ring->next = 0; 1363 ring->bufsz = MCLBYTES; 1364 1365 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1366 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1367 if (error != 0) { 1368 aprint_error_dev(sc->sc_dev, 1369 "could not create desc DMA map\n"); 1370 ring->map = NULL; 1371 goto fail; 1372 } 1373 1374 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1375 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1376 if (error != 0) { 1377 aprint_error_dev(sc->sc_dev, 1378 "could not allocate DMA memory\n"); 1379 goto fail; 1380 } 1381 1382 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1383 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1384 if (error != 0) { 1385 aprint_error_dev(sc->sc_dev, 1386 "could not map desc DMA memory\n"); 1387 goto fail; 1388 } 1389 1390 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1391 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1392 if (error != 0) { 1393 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1394 goto fail; 1395 } 1396 1397 memset(*desc, 0, NFE_RX_RING_COUNT * descsize); 1398 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1399 1400 if (sc->sc_flags & NFE_USE_JUMBO) { 1401 ring->bufsz = NFE_JBYTES; 1402 if ((error = nfe_jpool_alloc(sc)) != 0) { 1403 aprint_error_dev(sc->sc_dev, 1404 "could not allocate jumbo frames\n"); 1405 goto fail; 1406 } 1407 } 1408 1409 /* 1410 * Pre-allocate Rx buffers and populate Rx ring. 1411 */ 1412 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1413 data = &sc->rxq.data[i]; 1414 1415 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1416 if (data->m == NULL) { 1417 aprint_error_dev(sc->sc_dev, 1418 "could not allocate rx mbuf\n"); 1419 error = ENOMEM; 1420 goto fail; 1421 } 1422 1423 if (sc->sc_flags & NFE_USE_JUMBO) { 1424 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1425 aprint_error_dev(sc->sc_dev, 1426 "could not allocate jumbo buffer\n"); 1427 goto fail; 1428 } 1429 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1430 sc); 1431 1432 physaddr = jbuf->physaddr; 1433 } else { 1434 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1435 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1436 if (error != 0) { 1437 aprint_error_dev(sc->sc_dev, 1438 "could not create DMA map\n"); 1439 data->map = NULL; 1440 goto fail; 1441 } 1442 MCLGET(data->m, M_DONTWAIT); 1443 if (!(data->m->m_flags & M_EXT)) { 1444 aprint_error_dev(sc->sc_dev, 1445 "could not allocate mbuf cluster\n"); 1446 error = ENOMEM; 1447 goto fail; 1448 } 1449 1450 error = bus_dmamap_load(sc->sc_dmat, data->map, 1451 mtod(data->m, void *), MCLBYTES, NULL, 1452 BUS_DMA_READ | BUS_DMA_NOWAIT); 1453 if (error != 0) { 1454 aprint_error_dev(sc->sc_dev, 1455 "could not load rx buf DMA map"); 1456 goto fail; 1457 } 1458 physaddr = data->map->dm_segs[0].ds_addr; 1459 } 1460 1461 if (sc->sc_flags & NFE_40BIT_ADDR) { 1462 desc64 = &sc->rxq.desc64[i]; 1463 #if defined(__LP64__) 1464 desc64->physaddr[0] = htole32(physaddr >> 32); 1465 #endif 1466 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1467 desc64->length = htole16(sc->rxq.bufsz); 1468 desc64->flags = htole16(NFE_RX_READY); 1469 } else { 1470 desc32 = &sc->rxq.desc32[i]; 1471 desc32->physaddr = htole32(physaddr); 1472 desc32->length = htole16(sc->rxq.bufsz); 1473 desc32->flags = htole16(NFE_RX_READY); 1474 } 1475 } 1476 1477 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1478 BUS_DMASYNC_PREWRITE); 1479 1480 return 0; 1481 1482 fail: nfe_free_rx_ring(sc, ring); 1483 return error; 1484 } 1485 1486 void 1487 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1488 { 1489 int i; 1490 1491 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1492 if (sc->sc_flags & NFE_40BIT_ADDR) { 1493 ring->desc64[i].length = htole16(ring->bufsz); 1494 ring->desc64[i].flags = htole16(NFE_RX_READY); 1495 } else { 1496 ring->desc32[i].length = htole16(ring->bufsz); 1497 ring->desc32[i].flags = htole16(NFE_RX_READY); 1498 } 1499 } 1500 1501 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1502 BUS_DMASYNC_PREWRITE); 1503 1504 ring->cur = ring->next = 0; 1505 } 1506 1507 void 1508 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1509 { 1510 struct nfe_rx_data *data; 1511 void *desc; 1512 int i, descsize; 1513 1514 if (sc->sc_flags & NFE_40BIT_ADDR) { 1515 desc = ring->desc64; 1516 descsize = sizeof (struct nfe_desc64); 1517 } else { 1518 desc = ring->desc32; 1519 descsize = sizeof (struct nfe_desc32); 1520 } 1521 1522 if (desc != NULL) { 1523 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1524 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1525 bus_dmamap_unload(sc->sc_dmat, ring->map); 1526 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1527 NFE_RX_RING_COUNT * descsize); 1528 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1529 } 1530 1531 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1532 data = &ring->data[i]; 1533 1534 if (data->map != NULL) { 1535 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1536 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1537 bus_dmamap_unload(sc->sc_dmat, data->map); 1538 bus_dmamap_destroy(sc->sc_dmat, data->map); 1539 } 1540 if (data->m != NULL) 1541 m_freem(data->m); 1542 } 1543 } 1544 1545 struct nfe_jbuf * 1546 nfe_jalloc(struct nfe_softc *sc, int i) 1547 { 1548 struct nfe_jbuf *jbuf; 1549 1550 mutex_enter(&sc->rxq.mtx); 1551 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1552 if (jbuf != NULL) 1553 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1554 mutex_exit(&sc->rxq.mtx); 1555 if (jbuf == NULL) 1556 return NULL; 1557 sc->rxq.jbufmap[i] = 1558 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1559 return jbuf; 1560 } 1561 1562 /* 1563 * This is called automatically by the network stack when the mbuf is freed. 1564 * Caution must be taken that the NIC might be reset by the time the mbuf is 1565 * freed. 1566 */ 1567 void 1568 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1569 { 1570 struct nfe_softc *sc = arg; 1571 struct nfe_jbuf *jbuf; 1572 int i; 1573 1574 /* find the jbuf from the base pointer */ 1575 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1576 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1577 aprint_error_dev(sc->sc_dev, 1578 "request to free a buffer (%p) not managed by us\n", buf); 1579 return; 1580 } 1581 jbuf = &sc->rxq.jbuf[i]; 1582 1583 /* ..and put it back in the free list */ 1584 mutex_enter(&sc->rxq.mtx); 1585 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1586 mutex_exit(&sc->rxq.mtx); 1587 1588 if (m != NULL) 1589 pool_cache_put(mb_cache, m); 1590 } 1591 1592 int 1593 nfe_jpool_alloc(struct nfe_softc *sc) 1594 { 1595 struct nfe_rx_ring *ring = &sc->rxq; 1596 struct nfe_jbuf *jbuf; 1597 bus_addr_t physaddr; 1598 char *buf; 1599 int i, nsegs, error; 1600 1601 /* 1602 * Allocate a big chunk of DMA'able memory. 1603 */ 1604 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1605 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1606 if (error != 0) { 1607 aprint_error_dev(sc->sc_dev, 1608 "could not create jumbo DMA map\n"); 1609 ring->jmap = NULL; 1610 goto fail; 1611 } 1612 1613 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1614 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1615 if (error != 0) { 1616 aprint_error_dev(sc->sc_dev, 1617 "could not allocate jumbo DMA memory\n"); 1618 goto fail; 1619 } 1620 1621 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1622 &ring->jpool, BUS_DMA_NOWAIT); 1623 if (error != 0) { 1624 aprint_error_dev(sc->sc_dev, 1625 "could not map jumbo DMA memory\n"); 1626 goto fail; 1627 } 1628 1629 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1630 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1631 if (error != 0) { 1632 aprint_error_dev(sc->sc_dev, 1633 "could not load jumbo DMA map\n"); 1634 goto fail; 1635 } 1636 1637 /* ..and split it into 9KB chunks */ 1638 SLIST_INIT(&ring->jfreelist); 1639 1640 buf = ring->jpool; 1641 physaddr = ring->jmap->dm_segs[0].ds_addr; 1642 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1643 jbuf = &ring->jbuf[i]; 1644 1645 jbuf->buf = buf; 1646 jbuf->physaddr = physaddr; 1647 1648 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1649 1650 buf += NFE_JBYTES; 1651 physaddr += NFE_JBYTES; 1652 } 1653 1654 return 0; 1655 1656 fail: nfe_jpool_free(sc); 1657 return error; 1658 } 1659 1660 void 1661 nfe_jpool_free(struct nfe_softc *sc) 1662 { 1663 struct nfe_rx_ring *ring = &sc->rxq; 1664 1665 if (ring->jmap != NULL) { 1666 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1667 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1668 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1669 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1670 } 1671 if (ring->jpool != NULL) { 1672 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1673 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1674 } 1675 } 1676 1677 int 1678 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1679 { 1680 int i, nsegs, error; 1681 void **desc; 1682 int descsize; 1683 1684 if (sc->sc_flags & NFE_40BIT_ADDR) { 1685 desc = (void **)&ring->desc64; 1686 descsize = sizeof (struct nfe_desc64); 1687 } else { 1688 desc = (void **)&ring->desc32; 1689 descsize = sizeof (struct nfe_desc32); 1690 } 1691 1692 ring->queued = 0; 1693 ring->cur = ring->next = 0; 1694 1695 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1696 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1697 1698 if (error != 0) { 1699 aprint_error_dev(sc->sc_dev, 1700 "could not create desc DMA map\n"); 1701 ring->map = NULL; 1702 goto fail; 1703 } 1704 1705 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1706 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1707 if (error != 0) { 1708 aprint_error_dev(sc->sc_dev, 1709 "could not allocate DMA memory\n"); 1710 goto fail; 1711 } 1712 1713 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1714 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1715 if (error != 0) { 1716 aprint_error_dev(sc->sc_dev, 1717 "could not map desc DMA memory\n"); 1718 goto fail; 1719 } 1720 1721 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1722 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1723 if (error != 0) { 1724 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1725 goto fail; 1726 } 1727 1728 memset(*desc, 0, NFE_TX_RING_COUNT * descsize); 1729 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1730 1731 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1732 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1733 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1734 &ring->data[i].map); 1735 if (error != 0) { 1736 aprint_error_dev(sc->sc_dev, 1737 "could not create DMA map\n"); 1738 ring->data[i].map = NULL; 1739 goto fail; 1740 } 1741 } 1742 1743 return 0; 1744 1745 fail: nfe_free_tx_ring(sc, ring); 1746 return error; 1747 } 1748 1749 void 1750 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1751 { 1752 struct nfe_tx_data *data; 1753 int i; 1754 1755 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1756 if (sc->sc_flags & NFE_40BIT_ADDR) 1757 ring->desc64[i].flags = 0; 1758 else 1759 ring->desc32[i].flags = 0; 1760 1761 data = &ring->data[i]; 1762 1763 if (data->m != NULL) { 1764 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1765 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1766 bus_dmamap_unload(sc->sc_dmat, data->active); 1767 m_freem(data->m); 1768 data->m = NULL; 1769 } 1770 } 1771 1772 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1773 BUS_DMASYNC_PREWRITE); 1774 1775 ring->queued = 0; 1776 ring->cur = ring->next = 0; 1777 } 1778 1779 void 1780 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1781 { 1782 struct nfe_tx_data *data; 1783 void *desc; 1784 int i, descsize; 1785 1786 if (sc->sc_flags & NFE_40BIT_ADDR) { 1787 desc = ring->desc64; 1788 descsize = sizeof (struct nfe_desc64); 1789 } else { 1790 desc = ring->desc32; 1791 descsize = sizeof (struct nfe_desc32); 1792 } 1793 1794 if (desc != NULL) { 1795 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1796 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1797 bus_dmamap_unload(sc->sc_dmat, ring->map); 1798 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1799 NFE_TX_RING_COUNT * descsize); 1800 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1801 } 1802 1803 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1804 data = &ring->data[i]; 1805 1806 if (data->m != NULL) { 1807 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1808 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1809 bus_dmamap_unload(sc->sc_dmat, data->active); 1810 m_freem(data->m); 1811 } 1812 } 1813 1814 /* ..and now actually destroy the DMA mappings */ 1815 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1816 data = &ring->data[i]; 1817 if (data->map == NULL) 1818 continue; 1819 bus_dmamap_destroy(sc->sc_dmat, data->map); 1820 } 1821 } 1822 1823 void 1824 nfe_setmulti(struct nfe_softc *sc) 1825 { 1826 struct ethercom *ec = &sc->sc_ethercom; 1827 struct ifnet *ifp = &ec->ec_if; 1828 struct ether_multi *enm; 1829 struct ether_multistep step; 1830 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1831 uint32_t filter = NFE_RXFILTER_MAGIC; 1832 int i; 1833 1834 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1835 memset(addr, 0, ETHER_ADDR_LEN); 1836 memset(mask, 0, ETHER_ADDR_LEN); 1837 goto done; 1838 } 1839 1840 memcpy(addr, etherbroadcastaddr, ETHER_ADDR_LEN); 1841 memcpy(mask, etherbroadcastaddr, ETHER_ADDR_LEN); 1842 1843 ETHER_FIRST_MULTI(step, ec, enm); 1844 while (enm != NULL) { 1845 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1846 ifp->if_flags |= IFF_ALLMULTI; 1847 memset(addr, 0, ETHER_ADDR_LEN); 1848 memset(mask, 0, ETHER_ADDR_LEN); 1849 goto done; 1850 } 1851 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1852 addr[i] &= enm->enm_addrlo[i]; 1853 mask[i] &= ~enm->enm_addrlo[i]; 1854 } 1855 ETHER_NEXT_MULTI(step, enm); 1856 } 1857 for (i = 0; i < ETHER_ADDR_LEN; i++) 1858 mask[i] |= addr[i]; 1859 1860 done: 1861 addr[0] |= 0x01; /* make sure multicast bit is set */ 1862 1863 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1864 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1865 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1866 addr[5] << 8 | addr[4]); 1867 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1868 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1869 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1870 mask[5] << 8 | mask[4]); 1871 1872 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1873 NFE_WRITE(sc, NFE_RXFILTER, filter); 1874 } 1875 1876 void 1877 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1878 { 1879 uint32_t tmp; 1880 1881 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 1882 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1883 addr[0] = (tmp & 0xff); 1884 addr[1] = (tmp >> 8) & 0xff; 1885 addr[2] = (tmp >> 16) & 0xff; 1886 addr[3] = (tmp >> 24) & 0xff; 1887 1888 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1889 addr[4] = (tmp & 0xff); 1890 addr[5] = (tmp >> 8) & 0xff; 1891 1892 } else { 1893 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1894 addr[0] = (tmp >> 8) & 0xff; 1895 addr[1] = (tmp & 0xff); 1896 1897 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1898 addr[2] = (tmp >> 24) & 0xff; 1899 addr[3] = (tmp >> 16) & 0xff; 1900 addr[4] = (tmp >> 8) & 0xff; 1901 addr[5] = (tmp & 0xff); 1902 } 1903 } 1904 1905 void 1906 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1907 { 1908 NFE_WRITE(sc, NFE_MACADDR_LO, 1909 addr[5] << 8 | addr[4]); 1910 NFE_WRITE(sc, NFE_MACADDR_HI, 1911 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1912 } 1913 1914 void 1915 nfe_tick(void *arg) 1916 { 1917 struct nfe_softc *sc = arg; 1918 int s; 1919 1920 s = splnet(); 1921 mii_tick(&sc->sc_mii); 1922 splx(s); 1923 1924 callout_schedule(&sc->sc_tick_ch, hz); 1925 } 1926 1927 void 1928 nfe_poweron(device_t self) 1929 { 1930 struct nfe_softc *sc = device_private(self); 1931 1932 if ((sc->sc_flags & NFE_PWR_MGMT) != 0) { 1933 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 1934 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 1935 DELAY(100); 1936 NFE_WRITE(sc, NFE_MAC_RESET, 0); 1937 DELAY(100); 1938 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 1939 NFE_WRITE(sc, NFE_PWR2_CTL, 1940 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_WAKEUP_MASK); 1941 } 1942 } 1943 1944 bool 1945 nfe_resume(device_t dv, const pmf_qual_t *qual) 1946 { 1947 nfe_poweron(dv); 1948 1949 return true; 1950 } 1951
Indexes created Tue Sep 30 07:10:03 GMT 2025