if_nfe.c revision 1.54
1 /* $NetBSD: if_nfe.c,v 1.54 2011/01/23 03:15:06 tsutsui Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.77 2008/02/05 16:52:50 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006, 2007 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.54 2011/01/23 03:15:06 tsutsui Exp $"); 25 26 #include "opt_inet.h" 27 #include "vlan.h" 28 29 #include <sys/param.h> 30 #include <sys/endian.h> 31 #include <sys/systm.h> 32 #include <sys/types.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/mutex.h> 36 #include <sys/queue.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/callout.h> 40 #include <sys/socket.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #include <net/bpf.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_nfereg.h> 72 #include <dev/pci/if_nfevar.h> 73 74 static int nfe_ifflags_cb(struct ethercom *); 75 76 int nfe_match(device_t, cfdata_t, void *); 77 void nfe_attach(device_t, device_t, void *); 78 int nfe_detach(device_t, int); 79 void nfe_power(int, void *); 80 void nfe_miibus_statchg(device_t); 81 int nfe_miibus_readreg(device_t, int, int); 82 void nfe_miibus_writereg(device_t, int, int, int); 83 int nfe_intr(void *); 84 int nfe_ioctl(struct ifnet *, u_long, void *); 85 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 86 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 87 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 88 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 89 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 90 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 91 void nfe_rxeof(struct nfe_softc *); 92 void nfe_txeof(struct nfe_softc *); 93 int nfe_encap(struct nfe_softc *, struct mbuf *); 94 void nfe_start(struct ifnet *); 95 void nfe_watchdog(struct ifnet *); 96 int nfe_init(struct ifnet *); 97 void nfe_stop(struct ifnet *, int); 98 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 99 void nfe_jfree(struct mbuf *, void *, size_t, void *); 100 int nfe_jpool_alloc(struct nfe_softc *); 101 void nfe_jpool_free(struct nfe_softc *); 102 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 105 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 108 void nfe_setmulti(struct nfe_softc *); 109 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 110 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 111 void nfe_tick(void *); 112 void nfe_poweron(device_t); 113 bool nfe_resume(device_t, const pmf_qual_t *); 114 115 CFATTACH_DECL_NEW(nfe, sizeof(struct nfe_softc), 116 nfe_match, nfe_attach, nfe_detach, NULL); 117 118 /* #define NFE_NO_JUMBO */ 119 120 #ifdef NFE_DEBUG 121 int nfedebug = 0; 122 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 123 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 124 #else 125 #define DPRINTF(x) 126 #define DPRINTFN(n,x) 127 #endif 128 129 /* deal with naming differences */ 130 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 134 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 135 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 136 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 137 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 140 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 141 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 142 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 145 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 146 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 147 148 #ifdef _LP64 149 #define __LP64__ 1 150 #endif 151 152 const struct nfe_product { 153 pci_vendor_id_t vendor; 154 pci_product_id_t product; 155 } nfe_devices[] = { 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 183 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 184 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 185 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 186 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 }, 187 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1 }, 188 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2 }, 189 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3 }, 190 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4 }, 191 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1 }, 192 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2 }, 193 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3 }, 194 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4 } 195 }; 196 197 int 198 nfe_match(device_t dev, cfdata_t match, void *aux) 199 { 200 struct pci_attach_args *pa = aux; 201 const struct nfe_product *np; 202 int i; 203 204 for (i = 0; i < __arraycount(nfe_devices); i++) { 205 np = &nfe_devices[i]; 206 if (PCI_VENDOR(pa->pa_id) == np->vendor && 207 PCI_PRODUCT(pa->pa_id) == np->product) 208 return 1; 209 } 210 return 0; 211 } 212 213 void 214 nfe_attach(device_t parent, device_t self, void *aux) 215 { 216 struct nfe_softc *sc = device_private(self); 217 struct pci_attach_args *pa = aux; 218 pci_chipset_tag_t pc = pa->pa_pc; 219 pci_intr_handle_t ih; 220 const char *intrstr; 221 struct ifnet *ifp; 222 pcireg_t memtype, csr; 223 char devinfo[256]; 224 int mii_flags = 0; 225 226 sc->sc_dev = self; 227 sc->sc_pc = pa->pa_pc; 228 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 229 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 230 231 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 232 switch (memtype) { 233 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 234 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 235 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 236 &sc->sc_memh, NULL, &sc->sc_mems) == 0) 237 break; 238 /* FALLTHROUGH */ 239 default: 240 aprint_error_dev(self, "could not map mem space\n"); 241 return; 242 } 243 244 if (pci_intr_map(pa, &ih) != 0) { 245 aprint_error_dev(self, "could not map interrupt\n"); 246 goto fail; 247 } 248 249 intrstr = pci_intr_string(pc, ih); 250 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 251 if (sc->sc_ih == NULL) { 252 aprint_error_dev(self, "could not establish interrupt"); 253 if (intrstr != NULL) 254 aprint_error(" at %s", intrstr); 255 aprint_error("\n"); 256 goto fail; 257 } 258 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 259 260 sc->sc_dmat = pa->pa_dmat; 261 262 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 263 csr |= PCI_COMMAND_MASTER_ENABLE; 264 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 265 266 sc->sc_flags = 0; 267 268 switch (PCI_PRODUCT(pa->pa_id)) { 269 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 270 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 271 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 272 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 273 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 274 break; 275 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 276 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 277 sc->sc_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT; 278 break; 279 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 280 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 281 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 282 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 283 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 284 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 285 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 286 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 287 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 288 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 289 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 290 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 291 sc->sc_flags |= NFE_40BIT_ADDR | NFE_CORRECT_MACADDR | 292 NFE_PWR_MGMT; 293 break; 294 case PCI_PRODUCT_NVIDIA_MCP77_LAN1: 295 case PCI_PRODUCT_NVIDIA_MCP77_LAN2: 296 case PCI_PRODUCT_NVIDIA_MCP77_LAN3: 297 case PCI_PRODUCT_NVIDIA_MCP77_LAN4: 298 sc->sc_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | 299 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 300 break; 301 case PCI_PRODUCT_NVIDIA_MCP79_LAN1: 302 case PCI_PRODUCT_NVIDIA_MCP79_LAN2: 303 case PCI_PRODUCT_NVIDIA_MCP79_LAN3: 304 case PCI_PRODUCT_NVIDIA_MCP79_LAN4: 305 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 306 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 307 break; 308 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 309 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 310 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 311 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 312 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 313 break; 314 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 315 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 316 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 317 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 318 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 319 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 320 mii_flags = MIIF_DOPAUSE; 321 break; 322 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 323 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 324 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 325 NFE_HW_VLAN | NFE_PWR_MGMT; 326 break; 327 } 328 329 nfe_poweron(self); 330 331 #ifndef NFE_NO_JUMBO 332 /* enable jumbo frames for adapters that support it */ 333 if (sc->sc_flags & NFE_JUMBO_SUP) 334 sc->sc_flags |= NFE_USE_JUMBO; 335 #endif 336 337 /* Check for reversed ethernet address */ 338 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 339 sc->sc_flags |= NFE_CORRECT_MACADDR; 340 341 nfe_get_macaddr(sc, sc->sc_enaddr); 342 aprint_normal_dev(self, "Ethernet address %s\n", 343 ether_sprintf(sc->sc_enaddr)); 344 345 /* 346 * Allocate Tx and Rx rings. 347 */ 348 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 349 aprint_error_dev(self, "could not allocate Tx ring\n"); 350 goto fail; 351 } 352 353 mutex_init(&sc->rxq.mtx, MUTEX_DEFAULT, IPL_NET); 354 355 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 356 aprint_error_dev(self, "could not allocate Rx ring\n"); 357 nfe_free_tx_ring(sc, &sc->txq); 358 goto fail; 359 } 360 361 ifp = &sc->sc_ethercom.ec_if; 362 ifp->if_softc = sc; 363 ifp->if_mtu = ETHERMTU; 364 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 365 ifp->if_ioctl = nfe_ioctl; 366 ifp->if_start = nfe_start; 367 ifp->if_stop = nfe_stop; 368 ifp->if_watchdog = nfe_watchdog; 369 ifp->if_init = nfe_init; 370 ifp->if_baudrate = IF_Gbps(1); 371 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 372 IFQ_SET_READY(&ifp->if_snd); 373 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 374 375 if (sc->sc_flags & NFE_USE_JUMBO) 376 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 377 378 #if NVLAN > 0 379 if (sc->sc_flags & NFE_HW_VLAN) 380 sc->sc_ethercom.ec_capabilities |= 381 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 382 #endif 383 if (sc->sc_flags & NFE_HW_CSUM) { 384 ifp->if_capabilities |= 385 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 386 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 387 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 388 } 389 390 sc->sc_mii.mii_ifp = ifp; 391 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 392 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 393 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 394 395 sc->sc_ethercom.ec_mii = &sc->sc_mii; 396 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 397 ether_mediastatus); 398 399 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 0, mii_flags); 400 401 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 402 aprint_error_dev(self, "no PHY found!\n"); 403 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 404 0, NULL); 405 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 406 } else 407 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 408 409 if_attach(ifp); 410 ether_ifattach(ifp, sc->sc_enaddr); 411 ether_set_ifflags_cb(&sc->sc_ethercom, nfe_ifflags_cb); 412 413 callout_init(&sc->sc_tick_ch, 0); 414 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 415 416 if (pmf_device_register(self, NULL, nfe_resume)) 417 pmf_class_network_register(self, ifp); 418 else 419 aprint_error_dev(self, "couldn't establish power handler\n"); 420 421 return; 422 423 fail: 424 if (sc->sc_ih != NULL) { 425 pci_intr_disestablish(pc, sc->sc_ih); 426 sc->sc_ih = NULL; 427 } 428 if (sc->sc_mems != 0) { 429 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 430 sc->sc_mems = 0; 431 } 432 } 433 434 int 435 nfe_detach(device_t self, int flags) 436 { 437 struct nfe_softc *sc = device_private(self); 438 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 439 int s; 440 441 s = splnet(); 442 443 nfe_stop(ifp, 1); 444 445 pmf_device_deregister(self); 446 callout_destroy(&sc->sc_tick_ch); 447 ether_ifdetach(ifp); 448 if_detach(ifp); 449 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 450 451 nfe_free_rx_ring(sc, &sc->rxq); 452 mutex_destroy(&sc->rxq.mtx); 453 nfe_free_tx_ring(sc, &sc->txq); 454 455 if (sc->sc_ih != NULL) { 456 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 457 sc->sc_ih = NULL; 458 } 459 460 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 461 nfe_set_macaddr(sc, sc->sc_enaddr); 462 } else { 463 NFE_WRITE(sc, NFE_MACADDR_LO, 464 sc->sc_enaddr[0] << 8 | sc->sc_enaddr[1]); 465 NFE_WRITE(sc, NFE_MACADDR_HI, 466 sc->sc_enaddr[2] << 24 | sc->sc_enaddr[3] << 16 | 467 sc->sc_enaddr[4] << 8 | sc->sc_enaddr[5]); 468 } 469 470 if (sc->sc_mems != 0) { 471 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 472 sc->sc_mems = 0; 473 } 474 475 splx(s); 476 477 return 0; 478 } 479 480 void 481 nfe_miibus_statchg(device_t dev) 482 { 483 struct nfe_softc *sc = device_private(dev); 484 struct mii_data *mii = &sc->sc_mii; 485 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 486 487 phy = NFE_READ(sc, NFE_PHY_IFACE); 488 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 489 490 seed = NFE_READ(sc, NFE_RNDSEED); 491 seed &= ~NFE_SEED_MASK; 492 493 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 494 phy |= NFE_PHY_HDX; /* half-duplex */ 495 misc |= NFE_MISC1_HDX; 496 } 497 498 switch (IFM_SUBTYPE(mii->mii_media_active)) { 499 case IFM_1000_T: /* full-duplex only */ 500 link |= NFE_MEDIA_1000T; 501 seed |= NFE_SEED_1000T; 502 phy |= NFE_PHY_1000T; 503 break; 504 case IFM_100_TX: 505 link |= NFE_MEDIA_100TX; 506 seed |= NFE_SEED_100TX; 507 phy |= NFE_PHY_100TX; 508 break; 509 case IFM_10_T: 510 link |= NFE_MEDIA_10T; 511 seed |= NFE_SEED_10T; 512 break; 513 } 514 515 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 516 517 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 518 NFE_WRITE(sc, NFE_MISC1, misc); 519 NFE_WRITE(sc, NFE_LINKSPEED, link); 520 } 521 522 int 523 nfe_miibus_readreg(device_t dev, int phy, int reg) 524 { 525 struct nfe_softc *sc = device_private(dev); 526 uint32_t val; 527 int ntries; 528 529 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 530 531 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 532 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 533 DELAY(100); 534 } 535 536 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 537 538 for (ntries = 0; ntries < 1000; ntries++) { 539 DELAY(100); 540 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 541 break; 542 } 543 if (ntries == 1000) { 544 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 545 device_xname(sc->sc_dev))); 546 return 0; 547 } 548 549 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 550 DPRINTFN(2, ("%s: could not read PHY\n", 551 device_xname(sc->sc_dev))); 552 return 0; 553 } 554 555 val = NFE_READ(sc, NFE_PHY_DATA); 556 if (val != 0xffffffff && val != 0) 557 sc->mii_phyaddr = phy; 558 559 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 560 device_xname(sc->sc_dev), phy, reg, val)); 561 562 return val; 563 } 564 565 void 566 nfe_miibus_writereg(device_t dev, int phy, int reg, int val) 567 { 568 struct nfe_softc *sc = device_private(dev); 569 uint32_t ctl; 570 int ntries; 571 572 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 573 574 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 575 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 576 DELAY(100); 577 } 578 579 NFE_WRITE(sc, NFE_PHY_DATA, val); 580 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 581 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 582 583 for (ntries = 0; ntries < 1000; ntries++) { 584 DELAY(100); 585 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 586 break; 587 } 588 #ifdef NFE_DEBUG 589 if (nfedebug >= 2 && ntries == 1000) 590 printf("could not write to PHY\n"); 591 #endif 592 } 593 594 int 595 nfe_intr(void *arg) 596 { 597 struct nfe_softc *sc = arg; 598 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 599 uint32_t r; 600 int handled; 601 602 if ((ifp->if_flags & IFF_UP) == 0) 603 return 0; 604 605 handled = 0; 606 607 for (;;) { 608 r = NFE_READ(sc, NFE_IRQ_STATUS); 609 if ((r & NFE_IRQ_WANTED) == 0) 610 break; 611 612 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 613 handled = 1; 614 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 615 616 if ((r & (NFE_IRQ_RXERR|NFE_IRQ_RX_NOBUF|NFE_IRQ_RX)) != 0) { 617 /* check Rx ring */ 618 nfe_rxeof(sc); 619 } 620 if ((r & (NFE_IRQ_TXERR|NFE_IRQ_TXERR2|NFE_IRQ_TX_DONE)) != 0) { 621 /* check Tx ring */ 622 nfe_txeof(sc); 623 } 624 if ((r & NFE_IRQ_LINK) != 0) { 625 NFE_READ(sc, NFE_PHY_STATUS); 626 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 627 DPRINTF(("%s: link state changed\n", 628 device_xname(sc->sc_dev))); 629 } 630 } 631 632 if (handled && !IF_IS_EMPTY(&ifp->if_snd)) 633 nfe_start(ifp); 634 635 return handled; 636 } 637 638 static int 639 nfe_ifflags_cb(struct ethercom *ec) 640 { 641 struct ifnet *ifp = &ec->ec_if; 642 struct nfe_softc *sc = ifp->if_softc; 643 int change = ifp->if_flags ^ sc->sc_if_flags; 644 645 /* 646 * If only the PROMISC flag changes, then 647 * don't do a full re-init of the chip, just update 648 * the Rx filter. 649 */ 650 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 651 return ENETRESET; 652 else if ((change & IFF_PROMISC) != 0) 653 nfe_setmulti(sc); 654 655 return 0; 656 } 657 658 int 659 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 660 { 661 struct nfe_softc *sc = ifp->if_softc; 662 struct ifaddr *ifa = (struct ifaddr *)data; 663 int s, error = 0; 664 665 s = splnet(); 666 667 switch (cmd) { 668 case SIOCINITIFADDR: 669 ifp->if_flags |= IFF_UP; 670 nfe_init(ifp); 671 switch (ifa->ifa_addr->sa_family) { 672 #ifdef INET 673 case AF_INET: 674 arp_ifinit(ifp, ifa); 675 break; 676 #endif 677 default: 678 break; 679 } 680 break; 681 default: 682 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 683 break; 684 685 error = 0; 686 687 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 688 ; 689 else if (ifp->if_flags & IFF_RUNNING) 690 nfe_setmulti(sc); 691 break; 692 } 693 sc->sc_if_flags = ifp->if_flags; 694 695 splx(s); 696 697 return error; 698 } 699 700 void 701 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 702 { 703 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 704 (char *)desc32 - (char *)sc->txq.desc32, 705 sizeof (struct nfe_desc32), ops); 706 } 707 708 void 709 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 710 { 711 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 712 (char *)desc64 - (char *)sc->txq.desc64, 713 sizeof (struct nfe_desc64), ops); 714 } 715 716 void 717 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 718 { 719 if (end > start) { 720 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 721 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 722 (char *)&sc->txq.desc32[end] - 723 (char *)&sc->txq.desc32[start], ops); 724 return; 725 } 726 /* sync from 'start' to end of ring */ 727 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 728 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 729 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 730 (char *)&sc->txq.desc32[start], ops); 731 732 /* sync from start of ring to 'end' */ 733 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 734 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 735 } 736 737 void 738 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 739 { 740 if (end > start) { 741 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 742 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 743 (char *)&sc->txq.desc64[end] - 744 (char *)&sc->txq.desc64[start], ops); 745 return; 746 } 747 /* sync from 'start' to end of ring */ 748 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 749 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 750 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 751 (char *)&sc->txq.desc64[start], ops); 752 753 /* sync from start of ring to 'end' */ 754 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 755 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 756 } 757 758 void 759 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 760 { 761 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 762 (char *)desc32 - (char *)sc->rxq.desc32, 763 sizeof (struct nfe_desc32), ops); 764 } 765 766 void 767 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 768 { 769 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 770 (char *)desc64 - (char *)sc->rxq.desc64, 771 sizeof (struct nfe_desc64), ops); 772 } 773 774 void 775 nfe_rxeof(struct nfe_softc *sc) 776 { 777 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 778 struct nfe_desc32 *desc32; 779 struct nfe_desc64 *desc64; 780 struct nfe_rx_data *data; 781 struct nfe_jbuf *jbuf; 782 struct mbuf *m, *mnew; 783 bus_addr_t physaddr; 784 uint16_t flags; 785 int error, len, i; 786 787 desc32 = NULL; 788 desc64 = NULL; 789 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 790 data = &sc->rxq.data[i]; 791 792 if (sc->sc_flags & NFE_40BIT_ADDR) { 793 desc64 = &sc->rxq.desc64[i]; 794 nfe_rxdesc64_sync(sc, desc64, 795 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 796 797 flags = le16toh(desc64->flags); 798 len = le16toh(desc64->length) & 0x3fff; 799 } else { 800 desc32 = &sc->rxq.desc32[i]; 801 nfe_rxdesc32_sync(sc, desc32, 802 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 803 804 flags = le16toh(desc32->flags); 805 len = le16toh(desc32->length) & 0x3fff; 806 } 807 808 if ((flags & NFE_RX_READY) != 0) 809 break; 810 811 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 812 if ((flags & NFE_RX_VALID_V1) == 0) 813 goto skip; 814 815 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 816 flags &= ~NFE_RX_ERROR; 817 len--; /* fix buffer length */ 818 } 819 } else { 820 if ((flags & NFE_RX_VALID_V2) == 0) 821 goto skip; 822 823 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 824 flags &= ~NFE_RX_ERROR; 825 len--; /* fix buffer length */ 826 } 827 } 828 829 if (flags & NFE_RX_ERROR) { 830 ifp->if_ierrors++; 831 goto skip; 832 } 833 834 /* 835 * Try to allocate a new mbuf for this ring element and load 836 * it before processing the current mbuf. If the ring element 837 * cannot be loaded, drop the received packet and reuse the 838 * old mbuf. In the unlikely case that the old mbuf can't be 839 * reloaded either, explicitly panic. 840 */ 841 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 842 if (mnew == NULL) { 843 ifp->if_ierrors++; 844 goto skip; 845 } 846 847 if (sc->sc_flags & NFE_USE_JUMBO) { 848 physaddr = 849 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 850 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 851 if (len > MCLBYTES) { 852 m_freem(mnew); 853 ifp->if_ierrors++; 854 goto skip1; 855 } 856 MCLGET(mnew, M_DONTWAIT); 857 if ((mnew->m_flags & M_EXT) == 0) { 858 m_freem(mnew); 859 ifp->if_ierrors++; 860 goto skip1; 861 } 862 863 (void)memcpy(mtod(mnew, void *), 864 mtod(data->m, const void *), len); 865 m = mnew; 866 goto mbufcopied; 867 } else { 868 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 869 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 870 mtod(data->m, char *) - (char *)sc->rxq.jpool, 871 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 872 873 physaddr = jbuf->physaddr; 874 } 875 } else { 876 MCLGET(mnew, M_DONTWAIT); 877 if ((mnew->m_flags & M_EXT) == 0) { 878 m_freem(mnew); 879 ifp->if_ierrors++; 880 goto skip; 881 } 882 883 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 884 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 885 bus_dmamap_unload(sc->sc_dmat, data->map); 886 887 error = bus_dmamap_load(sc->sc_dmat, data->map, 888 mtod(mnew, void *), MCLBYTES, NULL, 889 BUS_DMA_READ | BUS_DMA_NOWAIT); 890 if (error != 0) { 891 m_freem(mnew); 892 893 /* try to reload the old mbuf */ 894 error = bus_dmamap_load(sc->sc_dmat, data->map, 895 mtod(data->m, void *), MCLBYTES, NULL, 896 BUS_DMA_READ | BUS_DMA_NOWAIT); 897 if (error != 0) { 898 /* very unlikely that it will fail.. */ 899 panic("%s: could not load old rx mbuf", 900 device_xname(sc->sc_dev)); 901 } 902 ifp->if_ierrors++; 903 goto skip; 904 } 905 physaddr = data->map->dm_segs[0].ds_addr; 906 } 907 908 /* 909 * New mbuf successfully loaded, update Rx ring and continue 910 * processing. 911 */ 912 m = data->m; 913 data->m = mnew; 914 915 mbufcopied: 916 /* finalize mbuf */ 917 m->m_pkthdr.len = m->m_len = len; 918 m->m_pkthdr.rcvif = ifp; 919 920 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 921 /* 922 * XXX 923 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 924 */ 925 if (flags & NFE_RX_IP_CSUMOK) { 926 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 927 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 928 device_xname(sc->sc_dev))); 929 } 930 /* 931 * XXX 932 * no way to check M_CSUM_TCP_UDP_BAD or 933 * other protocols? 934 */ 935 if (flags & NFE_RX_UDP_CSUMOK) { 936 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 937 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 938 device_xname(sc->sc_dev))); 939 } else if (flags & NFE_RX_TCP_CSUMOK) { 940 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 941 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 942 device_xname(sc->sc_dev))); 943 } 944 } 945 bpf_mtap(ifp, m); 946 ifp->if_ipackets++; 947 (*ifp->if_input)(ifp, m); 948 949 skip1: 950 /* update mapping address in h/w descriptor */ 951 if (sc->sc_flags & NFE_40BIT_ADDR) { 952 #if defined(__LP64__) 953 desc64->physaddr[0] = htole32(physaddr >> 32); 954 #endif 955 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 956 } else { 957 desc32->physaddr = htole32(physaddr); 958 } 959 960 skip: 961 if (sc->sc_flags & NFE_40BIT_ADDR) { 962 desc64->length = htole16(sc->rxq.bufsz); 963 desc64->flags = htole16(NFE_RX_READY); 964 965 nfe_rxdesc64_sync(sc, desc64, 966 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 967 } else { 968 desc32->length = htole16(sc->rxq.bufsz); 969 desc32->flags = htole16(NFE_RX_READY); 970 971 nfe_rxdesc32_sync(sc, desc32, 972 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 973 } 974 } 975 /* update current RX pointer */ 976 sc->rxq.cur = i; 977 } 978 979 void 980 nfe_txeof(struct nfe_softc *sc) 981 { 982 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 983 struct nfe_desc32 *desc32; 984 struct nfe_desc64 *desc64; 985 struct nfe_tx_data *data = NULL; 986 int i; 987 uint16_t flags; 988 char buf[128]; 989 990 for (i = sc->txq.next; 991 sc->txq.queued > 0; 992 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 993 if (sc->sc_flags & NFE_40BIT_ADDR) { 994 desc64 = &sc->txq.desc64[i]; 995 nfe_txdesc64_sync(sc, desc64, 996 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 997 998 flags = le16toh(desc64->flags); 999 } else { 1000 desc32 = &sc->txq.desc32[i]; 1001 nfe_txdesc32_sync(sc, desc32, 1002 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1003 1004 flags = le16toh(desc32->flags); 1005 } 1006 1007 if ((flags & NFE_TX_VALID) != 0) 1008 break; 1009 1010 data = &sc->txq.data[i]; 1011 1012 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 1013 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 1014 data->m == NULL) 1015 continue; 1016 1017 if ((flags & NFE_TX_ERROR_V1) != 0) { 1018 snprintb(buf, sizeof(buf), NFE_V1_TXERR, flags); 1019 aprint_error_dev(sc->sc_dev, "tx v1 error %s\n", 1020 buf); 1021 ifp->if_oerrors++; 1022 } else 1023 ifp->if_opackets++; 1024 } else { 1025 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 1026 data->m == NULL) 1027 continue; 1028 1029 if ((flags & NFE_TX_ERROR_V2) != 0) { 1030 snprintb(buf, sizeof(buf), NFE_V2_TXERR, flags); 1031 aprint_error_dev(sc->sc_dev, "tx v2 error %s\n", 1032 buf); 1033 ifp->if_oerrors++; 1034 } else 1035 ifp->if_opackets++; 1036 } 1037 1038 if (data->m == NULL) { /* should not get there */ 1039 aprint_error_dev(sc->sc_dev, 1040 "last fragment bit w/o associated mbuf!\n"); 1041 continue; 1042 } 1043 1044 /* last fragment of the mbuf chain transmitted */ 1045 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1046 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1047 bus_dmamap_unload(sc->sc_dmat, data->active); 1048 m_freem(data->m); 1049 data->m = NULL; 1050 } 1051 1052 sc->txq.next = i; 1053 1054 if (sc->txq.queued < NFE_TX_RING_COUNT) { 1055 /* at least one slot freed */ 1056 ifp->if_flags &= ~IFF_OACTIVE; 1057 } 1058 1059 if (sc->txq.queued == 0) { 1060 /* all queued packets are sent */ 1061 ifp->if_timer = 0; 1062 } 1063 } 1064 1065 int 1066 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 1067 { 1068 struct nfe_desc32 *desc32; 1069 struct nfe_desc64 *desc64; 1070 struct nfe_tx_data *data; 1071 bus_dmamap_t map; 1072 uint16_t flags, csumflags; 1073 #if NVLAN > 0 1074 struct m_tag *mtag; 1075 uint32_t vtag = 0; 1076 #endif 1077 int error, i, first; 1078 1079 desc32 = NULL; 1080 desc64 = NULL; 1081 data = NULL; 1082 1083 flags = 0; 1084 csumflags = 0; 1085 first = sc->txq.cur; 1086 1087 map = sc->txq.data[first].map; 1088 1089 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1090 if (error != 0) { 1091 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1092 error); 1093 return error; 1094 } 1095 1096 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1097 bus_dmamap_unload(sc->sc_dmat, map); 1098 return ENOBUFS; 1099 } 1100 1101 #if NVLAN > 0 1102 /* setup h/w VLAN tagging */ 1103 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1104 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1105 #endif 1106 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1107 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1108 csumflags |= NFE_TX_IP_CSUM; 1109 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1110 csumflags |= NFE_TX_TCP_UDP_CSUM; 1111 } 1112 1113 for (i = 0; i < map->dm_nsegs; i++) { 1114 data = &sc->txq.data[sc->txq.cur]; 1115 1116 if (sc->sc_flags & NFE_40BIT_ADDR) { 1117 desc64 = &sc->txq.desc64[sc->txq.cur]; 1118 #if defined(__LP64__) 1119 desc64->physaddr[0] = 1120 htole32(map->dm_segs[i].ds_addr >> 32); 1121 #endif 1122 desc64->physaddr[1] = 1123 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1124 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1125 desc64->flags = htole16(flags); 1126 desc64->vtag = 0; 1127 } else { 1128 desc32 = &sc->txq.desc32[sc->txq.cur]; 1129 1130 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1131 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1132 desc32->flags = htole16(flags); 1133 } 1134 1135 /* 1136 * Setting of the valid bit in the first descriptor is 1137 * deferred until the whole chain is fully setup. 1138 */ 1139 flags |= NFE_TX_VALID; 1140 1141 sc->txq.queued++; 1142 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1143 } 1144 1145 /* the whole mbuf chain has been setup */ 1146 if (sc->sc_flags & NFE_40BIT_ADDR) { 1147 /* fix last descriptor */ 1148 flags |= NFE_TX_LASTFRAG_V2; 1149 desc64->flags = htole16(flags); 1150 1151 /* Checksum flags and vtag belong to the first fragment only. */ 1152 #if NVLAN > 0 1153 sc->txq.desc64[first].vtag = htole32(vtag); 1154 #endif 1155 sc->txq.desc64[first].flags |= htole16(csumflags); 1156 1157 /* finally, set the valid bit in the first descriptor */ 1158 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1159 } else { 1160 /* fix last descriptor */ 1161 if (sc->sc_flags & NFE_JUMBO_SUP) 1162 flags |= NFE_TX_LASTFRAG_V2; 1163 else 1164 flags |= NFE_TX_LASTFRAG_V1; 1165 desc32->flags = htole16(flags); 1166 1167 /* Checksum flags belong to the first fragment only. */ 1168 sc->txq.desc32[first].flags |= htole16(csumflags); 1169 1170 /* finally, set the valid bit in the first descriptor */ 1171 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1172 } 1173 1174 data->m = m0; 1175 data->active = map; 1176 1177 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1178 BUS_DMASYNC_PREWRITE); 1179 1180 return 0; 1181 } 1182 1183 void 1184 nfe_start(struct ifnet *ifp) 1185 { 1186 struct nfe_softc *sc = ifp->if_softc; 1187 int old = sc->txq.queued; 1188 struct mbuf *m0; 1189 1190 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1191 return; 1192 1193 for (;;) { 1194 IFQ_POLL(&ifp->if_snd, m0); 1195 if (m0 == NULL) 1196 break; 1197 1198 if (nfe_encap(sc, m0) != 0) { 1199 ifp->if_flags |= IFF_OACTIVE; 1200 break; 1201 } 1202 1203 /* packet put in h/w queue, remove from s/w queue */ 1204 IFQ_DEQUEUE(&ifp->if_snd, m0); 1205 1206 bpf_mtap(ifp, m0); 1207 } 1208 1209 if (sc->txq.queued != old) { 1210 /* packets are queued */ 1211 if (sc->sc_flags & NFE_40BIT_ADDR) 1212 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1213 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1214 else 1215 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1216 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1217 /* kick Tx */ 1218 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1219 1220 /* 1221 * Set a timeout in case the chip goes out to lunch. 1222 */ 1223 ifp->if_timer = 5; 1224 } 1225 } 1226 1227 void 1228 nfe_watchdog(struct ifnet *ifp) 1229 { 1230 struct nfe_softc *sc = ifp->if_softc; 1231 1232 aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1233 1234 ifp->if_flags &= ~IFF_RUNNING; 1235 nfe_init(ifp); 1236 1237 ifp->if_oerrors++; 1238 } 1239 1240 int 1241 nfe_init(struct ifnet *ifp) 1242 { 1243 struct nfe_softc *sc = ifp->if_softc; 1244 uint32_t tmp; 1245 int rc = 0, s; 1246 1247 if (ifp->if_flags & IFF_RUNNING) 1248 return 0; 1249 1250 nfe_stop(ifp, 0); 1251 1252 NFE_WRITE(sc, NFE_TX_UNK, 0); 1253 NFE_WRITE(sc, NFE_STATUS, 0); 1254 1255 sc->rxtxctl = NFE_RXTX_BIT2; 1256 if (sc->sc_flags & NFE_40BIT_ADDR) 1257 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1258 else if (sc->sc_flags & NFE_JUMBO_SUP) 1259 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1260 if (sc->sc_flags & NFE_HW_CSUM) 1261 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1262 #if NVLAN > 0 1263 /* 1264 * Although the adapter is capable of stripping VLAN tags from received 1265 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1266 * purpose. This will be done in software by our network stack. 1267 */ 1268 if (sc->sc_flags & NFE_HW_VLAN) 1269 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1270 #endif 1271 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1272 DELAY(10); 1273 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1274 1275 #if NVLAN 1276 if (sc->sc_flags & NFE_HW_VLAN) 1277 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1278 #endif 1279 1280 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1281 1282 /* set MAC address */ 1283 nfe_set_macaddr(sc, sc->sc_enaddr); 1284 1285 /* tell MAC where rings are in memory */ 1286 #ifdef __LP64__ 1287 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1288 #endif 1289 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1290 #ifdef __LP64__ 1291 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1292 #endif 1293 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1294 1295 NFE_WRITE(sc, NFE_RING_SIZE, 1296 (NFE_RX_RING_COUNT - 1) << 16 | 1297 (NFE_TX_RING_COUNT - 1)); 1298 1299 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1300 1301 /* force MAC to wakeup */ 1302 tmp = NFE_READ(sc, NFE_PWR_STATE); 1303 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1304 DELAY(10); 1305 tmp = NFE_READ(sc, NFE_PWR_STATE); 1306 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1307 1308 s = splnet(); 1309 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1310 nfe_intr(sc); /* XXX clear IRQ status registers */ 1311 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1312 splx(s); 1313 1314 #if 1 1315 /* configure interrupts coalescing/mitigation */ 1316 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1317 #else 1318 /* no interrupt mitigation: one interrupt per packet */ 1319 NFE_WRITE(sc, NFE_IMTIMER, 970); 1320 #endif 1321 1322 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1323 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1324 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1325 1326 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1327 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1328 1329 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1330 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_ENABLE); 1331 1332 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1333 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1334 DELAY(10); 1335 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1336 1337 /* set Rx filter */ 1338 nfe_setmulti(sc); 1339 1340 if ((rc = ether_mediachange(ifp)) != 0) 1341 goto out; 1342 1343 nfe_tick(sc); 1344 1345 /* enable Rx */ 1346 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1347 1348 /* enable Tx */ 1349 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1350 1351 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1352 1353 /* enable interrupts */ 1354 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1355 1356 callout_schedule(&sc->sc_tick_ch, hz); 1357 1358 ifp->if_flags |= IFF_RUNNING; 1359 ifp->if_flags &= ~IFF_OACTIVE; 1360 1361 out: 1362 return rc; 1363 } 1364 1365 void 1366 nfe_stop(struct ifnet *ifp, int disable) 1367 { 1368 struct nfe_softc *sc = ifp->if_softc; 1369 1370 callout_stop(&sc->sc_tick_ch); 1371 1372 ifp->if_timer = 0; 1373 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1374 1375 mii_down(&sc->sc_mii); 1376 1377 /* abort Tx */ 1378 NFE_WRITE(sc, NFE_TX_CTL, 0); 1379 1380 /* disable Rx */ 1381 NFE_WRITE(sc, NFE_RX_CTL, 0); 1382 1383 /* disable interrupts */ 1384 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1385 1386 /* reset Tx and Rx rings */ 1387 nfe_reset_tx_ring(sc, &sc->txq); 1388 nfe_reset_rx_ring(sc, &sc->rxq); 1389 } 1390 1391 int 1392 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1393 { 1394 struct nfe_desc32 *desc32; 1395 struct nfe_desc64 *desc64; 1396 struct nfe_rx_data *data; 1397 struct nfe_jbuf *jbuf; 1398 void **desc; 1399 bus_addr_t physaddr; 1400 int i, nsegs, error, descsize; 1401 1402 if (sc->sc_flags & NFE_40BIT_ADDR) { 1403 desc = (void **)&ring->desc64; 1404 descsize = sizeof (struct nfe_desc64); 1405 } else { 1406 desc = (void **)&ring->desc32; 1407 descsize = sizeof (struct nfe_desc32); 1408 } 1409 1410 ring->cur = ring->next = 0; 1411 ring->bufsz = MCLBYTES; 1412 1413 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1414 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1415 if (error != 0) { 1416 aprint_error_dev(sc->sc_dev, 1417 "could not create desc DMA map\n"); 1418 ring->map = NULL; 1419 goto fail; 1420 } 1421 1422 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1423 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1424 if (error != 0) { 1425 aprint_error_dev(sc->sc_dev, 1426 "could not allocate DMA memory\n"); 1427 goto fail; 1428 } 1429 1430 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1431 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1432 if (error != 0) { 1433 aprint_error_dev(sc->sc_dev, 1434 "could not map desc DMA memory\n"); 1435 goto fail; 1436 } 1437 1438 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1439 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1440 if (error != 0) { 1441 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1442 goto fail; 1443 } 1444 1445 memset(*desc, 0, NFE_RX_RING_COUNT * descsize); 1446 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1447 1448 if (sc->sc_flags & NFE_USE_JUMBO) { 1449 ring->bufsz = NFE_JBYTES; 1450 if ((error = nfe_jpool_alloc(sc)) != 0) { 1451 aprint_error_dev(sc->sc_dev, 1452 "could not allocate jumbo frames\n"); 1453 goto fail; 1454 } 1455 } 1456 1457 /* 1458 * Pre-allocate Rx buffers and populate Rx ring. 1459 */ 1460 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1461 data = &sc->rxq.data[i]; 1462 1463 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1464 if (data->m == NULL) { 1465 aprint_error_dev(sc->sc_dev, 1466 "could not allocate rx mbuf\n"); 1467 error = ENOMEM; 1468 goto fail; 1469 } 1470 1471 if (sc->sc_flags & NFE_USE_JUMBO) { 1472 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1473 aprint_error_dev(sc->sc_dev, 1474 "could not allocate jumbo buffer\n"); 1475 goto fail; 1476 } 1477 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1478 sc); 1479 1480 physaddr = jbuf->physaddr; 1481 } else { 1482 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1483 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1484 if (error != 0) { 1485 aprint_error_dev(sc->sc_dev, 1486 "could not create DMA map\n"); 1487 data->map = NULL; 1488 goto fail; 1489 } 1490 MCLGET(data->m, M_DONTWAIT); 1491 if (!(data->m->m_flags & M_EXT)) { 1492 aprint_error_dev(sc->sc_dev, 1493 "could not allocate mbuf cluster\n"); 1494 error = ENOMEM; 1495 goto fail; 1496 } 1497 1498 error = bus_dmamap_load(sc->sc_dmat, data->map, 1499 mtod(data->m, void *), MCLBYTES, NULL, 1500 BUS_DMA_READ | BUS_DMA_NOWAIT); 1501 if (error != 0) { 1502 aprint_error_dev(sc->sc_dev, 1503 "could not load rx buf DMA map"); 1504 goto fail; 1505 } 1506 physaddr = data->map->dm_segs[0].ds_addr; 1507 } 1508 1509 if (sc->sc_flags & NFE_40BIT_ADDR) { 1510 desc64 = &sc->rxq.desc64[i]; 1511 #if defined(__LP64__) 1512 desc64->physaddr[0] = htole32(physaddr >> 32); 1513 #endif 1514 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1515 desc64->length = htole16(sc->rxq.bufsz); 1516 desc64->flags = htole16(NFE_RX_READY); 1517 } else { 1518 desc32 = &sc->rxq.desc32[i]; 1519 desc32->physaddr = htole32(physaddr); 1520 desc32->length = htole16(sc->rxq.bufsz); 1521 desc32->flags = htole16(NFE_RX_READY); 1522 } 1523 } 1524 1525 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1526 BUS_DMASYNC_PREWRITE); 1527 1528 return 0; 1529 1530 fail: nfe_free_rx_ring(sc, ring); 1531 return error; 1532 } 1533 1534 void 1535 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1536 { 1537 int i; 1538 1539 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1540 if (sc->sc_flags & NFE_40BIT_ADDR) { 1541 ring->desc64[i].length = htole16(ring->bufsz); 1542 ring->desc64[i].flags = htole16(NFE_RX_READY); 1543 } else { 1544 ring->desc32[i].length = htole16(ring->bufsz); 1545 ring->desc32[i].flags = htole16(NFE_RX_READY); 1546 } 1547 } 1548 1549 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1550 BUS_DMASYNC_PREWRITE); 1551 1552 ring->cur = ring->next = 0; 1553 } 1554 1555 void 1556 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1557 { 1558 struct nfe_rx_data *data; 1559 void *desc; 1560 int i, descsize; 1561 1562 if (sc->sc_flags & NFE_40BIT_ADDR) { 1563 desc = ring->desc64; 1564 descsize = sizeof (struct nfe_desc64); 1565 } else { 1566 desc = ring->desc32; 1567 descsize = sizeof (struct nfe_desc32); 1568 } 1569 1570 if (desc != NULL) { 1571 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1572 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1573 bus_dmamap_unload(sc->sc_dmat, ring->map); 1574 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1575 NFE_RX_RING_COUNT * descsize); 1576 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1577 } 1578 1579 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1580 data = &ring->data[i]; 1581 1582 if (data->map != NULL) { 1583 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1584 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1585 bus_dmamap_unload(sc->sc_dmat, data->map); 1586 bus_dmamap_destroy(sc->sc_dmat, data->map); 1587 } 1588 if (data->m != NULL) 1589 m_freem(data->m); 1590 } 1591 1592 nfe_jpool_free(sc); 1593 } 1594 1595 struct nfe_jbuf * 1596 nfe_jalloc(struct nfe_softc *sc, int i) 1597 { 1598 struct nfe_jbuf *jbuf; 1599 1600 mutex_enter(&sc->rxq.mtx); 1601 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1602 if (jbuf != NULL) 1603 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1604 mutex_exit(&sc->rxq.mtx); 1605 if (jbuf == NULL) 1606 return NULL; 1607 sc->rxq.jbufmap[i] = 1608 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1609 return jbuf; 1610 } 1611 1612 /* 1613 * This is called automatically by the network stack when the mbuf is freed. 1614 * Caution must be taken that the NIC might be reset by the time the mbuf is 1615 * freed. 1616 */ 1617 void 1618 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1619 { 1620 struct nfe_softc *sc = arg; 1621 struct nfe_jbuf *jbuf; 1622 int i; 1623 1624 /* find the jbuf from the base pointer */ 1625 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1626 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1627 aprint_error_dev(sc->sc_dev, 1628 "request to free a buffer (%p) not managed by us\n", buf); 1629 return; 1630 } 1631 jbuf = &sc->rxq.jbuf[i]; 1632 1633 /* ..and put it back in the free list */ 1634 mutex_enter(&sc->rxq.mtx); 1635 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1636 mutex_exit(&sc->rxq.mtx); 1637 1638 if (m != NULL) 1639 pool_cache_put(mb_cache, m); 1640 } 1641 1642 int 1643 nfe_jpool_alloc(struct nfe_softc *sc) 1644 { 1645 struct nfe_rx_ring *ring = &sc->rxq; 1646 struct nfe_jbuf *jbuf; 1647 bus_addr_t physaddr; 1648 char *buf; 1649 int i, nsegs, error; 1650 1651 /* 1652 * Allocate a big chunk of DMA'able memory. 1653 */ 1654 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1655 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1656 if (error != 0) { 1657 aprint_error_dev(sc->sc_dev, 1658 "could not create jumbo DMA map\n"); 1659 ring->jmap = NULL; 1660 goto fail; 1661 } 1662 1663 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1664 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1665 if (error != 0) { 1666 aprint_error_dev(sc->sc_dev, 1667 "could not allocate jumbo DMA memory\n"); 1668 goto fail; 1669 } 1670 1671 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1672 &ring->jpool, BUS_DMA_NOWAIT); 1673 if (error != 0) { 1674 aprint_error_dev(sc->sc_dev, 1675 "could not map jumbo DMA memory\n"); 1676 goto fail; 1677 } 1678 1679 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1680 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1681 if (error != 0) { 1682 aprint_error_dev(sc->sc_dev, 1683 "could not load jumbo DMA map\n"); 1684 goto fail; 1685 } 1686 1687 /* ..and split it into 9KB chunks */ 1688 SLIST_INIT(&ring->jfreelist); 1689 1690 buf = ring->jpool; 1691 physaddr = ring->jmap->dm_segs[0].ds_addr; 1692 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1693 jbuf = &ring->jbuf[i]; 1694 1695 jbuf->buf = buf; 1696 jbuf->physaddr = physaddr; 1697 1698 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1699 1700 buf += NFE_JBYTES; 1701 physaddr += NFE_JBYTES; 1702 } 1703 1704 return 0; 1705 1706 fail: nfe_jpool_free(sc); 1707 return error; 1708 } 1709 1710 void 1711 nfe_jpool_free(struct nfe_softc *sc) 1712 { 1713 struct nfe_rx_ring *ring = &sc->rxq; 1714 1715 if (ring->jmap != NULL) { 1716 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1717 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1718 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1719 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1720 ring->jmap = NULL; 1721 } 1722 if (ring->jpool != NULL) { 1723 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1724 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1725 ring->jpool = NULL; 1726 } 1727 } 1728 1729 int 1730 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1731 { 1732 int i, nsegs, error; 1733 void **desc; 1734 int descsize; 1735 1736 if (sc->sc_flags & NFE_40BIT_ADDR) { 1737 desc = (void **)&ring->desc64; 1738 descsize = sizeof (struct nfe_desc64); 1739 } else { 1740 desc = (void **)&ring->desc32; 1741 descsize = sizeof (struct nfe_desc32); 1742 } 1743 1744 ring->queued = 0; 1745 ring->cur = ring->next = 0; 1746 1747 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1748 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1749 1750 if (error != 0) { 1751 aprint_error_dev(sc->sc_dev, 1752 "could not create desc DMA map\n"); 1753 ring->map = NULL; 1754 goto fail; 1755 } 1756 1757 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1758 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1759 if (error != 0) { 1760 aprint_error_dev(sc->sc_dev, 1761 "could not allocate DMA memory\n"); 1762 goto fail; 1763 } 1764 1765 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1766 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1767 if (error != 0) { 1768 aprint_error_dev(sc->sc_dev, 1769 "could not map desc DMA memory\n"); 1770 goto fail; 1771 } 1772 1773 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1774 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1775 if (error != 0) { 1776 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1777 goto fail; 1778 } 1779 1780 memset(*desc, 0, NFE_TX_RING_COUNT * descsize); 1781 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1782 1783 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1784 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1785 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1786 &ring->data[i].map); 1787 if (error != 0) { 1788 aprint_error_dev(sc->sc_dev, 1789 "could not create DMA map\n"); 1790 ring->data[i].map = NULL; 1791 goto fail; 1792 } 1793 } 1794 1795 return 0; 1796 1797 fail: nfe_free_tx_ring(sc, ring); 1798 return error; 1799 } 1800 1801 void 1802 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1803 { 1804 struct nfe_tx_data *data; 1805 int i; 1806 1807 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1808 if (sc->sc_flags & NFE_40BIT_ADDR) 1809 ring->desc64[i].flags = 0; 1810 else 1811 ring->desc32[i].flags = 0; 1812 1813 data = &ring->data[i]; 1814 1815 if (data->m != NULL) { 1816 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1817 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1818 bus_dmamap_unload(sc->sc_dmat, data->active); 1819 m_freem(data->m); 1820 data->m = NULL; 1821 } 1822 } 1823 1824 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1825 BUS_DMASYNC_PREWRITE); 1826 1827 ring->queued = 0; 1828 ring->cur = ring->next = 0; 1829 } 1830 1831 void 1832 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1833 { 1834 struct nfe_tx_data *data; 1835 void *desc; 1836 int i, descsize; 1837 1838 if (sc->sc_flags & NFE_40BIT_ADDR) { 1839 desc = ring->desc64; 1840 descsize = sizeof (struct nfe_desc64); 1841 } else { 1842 desc = ring->desc32; 1843 descsize = sizeof (struct nfe_desc32); 1844 } 1845 1846 if (desc != NULL) { 1847 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1848 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1849 bus_dmamap_unload(sc->sc_dmat, ring->map); 1850 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1851 NFE_TX_RING_COUNT * descsize); 1852 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1853 } 1854 1855 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1856 data = &ring->data[i]; 1857 1858 if (data->m != NULL) { 1859 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1860 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1861 bus_dmamap_unload(sc->sc_dmat, data->active); 1862 m_freem(data->m); 1863 } 1864 } 1865 1866 /* ..and now actually destroy the DMA mappings */ 1867 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1868 data = &ring->data[i]; 1869 if (data->map == NULL) 1870 continue; 1871 bus_dmamap_destroy(sc->sc_dmat, data->map); 1872 } 1873 } 1874 1875 void 1876 nfe_setmulti(struct nfe_softc *sc) 1877 { 1878 struct ethercom *ec = &sc->sc_ethercom; 1879 struct ifnet *ifp = &ec->ec_if; 1880 struct ether_multi *enm; 1881 struct ether_multistep step; 1882 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1883 uint32_t filter = NFE_RXFILTER_MAGIC; 1884 int i; 1885 1886 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1887 memset(addr, 0, ETHER_ADDR_LEN); 1888 memset(mask, 0, ETHER_ADDR_LEN); 1889 goto done; 1890 } 1891 1892 memcpy(addr, etherbroadcastaddr, ETHER_ADDR_LEN); 1893 memcpy(mask, etherbroadcastaddr, ETHER_ADDR_LEN); 1894 1895 ETHER_FIRST_MULTI(step, ec, enm); 1896 while (enm != NULL) { 1897 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1898 ifp->if_flags |= IFF_ALLMULTI; 1899 memset(addr, 0, ETHER_ADDR_LEN); 1900 memset(mask, 0, ETHER_ADDR_LEN); 1901 goto done; 1902 } 1903 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1904 addr[i] &= enm->enm_addrlo[i]; 1905 mask[i] &= ~enm->enm_addrlo[i]; 1906 } 1907 ETHER_NEXT_MULTI(step, enm); 1908 } 1909 for (i = 0; i < ETHER_ADDR_LEN; i++) 1910 mask[i] |= addr[i]; 1911 1912 done: 1913 addr[0] |= 0x01; /* make sure multicast bit is set */ 1914 1915 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1916 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1917 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1918 addr[5] << 8 | addr[4]); 1919 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1920 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1921 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1922 mask[5] << 8 | mask[4]); 1923 1924 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1925 NFE_WRITE(sc, NFE_RXFILTER, filter); 1926 } 1927 1928 void 1929 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1930 { 1931 uint32_t tmp; 1932 1933 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 1934 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1935 addr[0] = (tmp & 0xff); 1936 addr[1] = (tmp >> 8) & 0xff; 1937 addr[2] = (tmp >> 16) & 0xff; 1938 addr[3] = (tmp >> 24) & 0xff; 1939 1940 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1941 addr[4] = (tmp & 0xff); 1942 addr[5] = (tmp >> 8) & 0xff; 1943 1944 } else { 1945 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1946 addr[0] = (tmp >> 8) & 0xff; 1947 addr[1] = (tmp & 0xff); 1948 1949 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1950 addr[2] = (tmp >> 24) & 0xff; 1951 addr[3] = (tmp >> 16) & 0xff; 1952 addr[4] = (tmp >> 8) & 0xff; 1953 addr[5] = (tmp & 0xff); 1954 } 1955 } 1956 1957 void 1958 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1959 { 1960 NFE_WRITE(sc, NFE_MACADDR_LO, 1961 addr[5] << 8 | addr[4]); 1962 NFE_WRITE(sc, NFE_MACADDR_HI, 1963 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1964 } 1965 1966 void 1967 nfe_tick(void *arg) 1968 { 1969 struct nfe_softc *sc = arg; 1970 int s; 1971 1972 s = splnet(); 1973 mii_tick(&sc->sc_mii); 1974 splx(s); 1975 1976 callout_schedule(&sc->sc_tick_ch, hz); 1977 } 1978 1979 void 1980 nfe_poweron(device_t self) 1981 { 1982 struct nfe_softc *sc = device_private(self); 1983 1984 if ((sc->sc_flags & NFE_PWR_MGMT) != 0) { 1985 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 1986 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 1987 DELAY(100); 1988 NFE_WRITE(sc, NFE_MAC_RESET, 0); 1989 DELAY(100); 1990 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 1991 NFE_WRITE(sc, NFE_PWR2_CTL, 1992 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_WAKEUP_MASK); 1993 } 1994 } 1995 1996 bool 1997 nfe_resume(device_t dv, const pmf_qual_t *qual) 1998 { 1999 nfe_poweron(dv); 2000 2001 return true; 2002 } 2003
Indexes created Tue Sep 30 20:09:53 GMT 2025