if_nfe.c revision 1.56
1 /* $NetBSD: if_nfe.c,v 1.56 2012/07/22 14:33:03 matt Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.77 2008/02/05 16:52:50 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006, 2007 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.56 2012/07/22 14:33:03 matt Exp $"); 25 26 #include "opt_inet.h" 27 #include "vlan.h" 28 29 #include <sys/param.h> 30 #include <sys/endian.h> 31 #include <sys/systm.h> 32 #include <sys/types.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/mutex.h> 36 #include <sys/queue.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/callout.h> 40 #include <sys/socket.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #include <net/bpf.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_nfereg.h> 72 #include <dev/pci/if_nfevar.h> 73 74 static int nfe_ifflags_cb(struct ethercom *); 75 76 int nfe_match(device_t, cfdata_t, void *); 77 void nfe_attach(device_t, device_t, void *); 78 int nfe_detach(device_t, int); 79 void nfe_power(int, void *); 80 void nfe_miibus_statchg(struct ifnet *); 81 int nfe_miibus_readreg(device_t, int, int); 82 void nfe_miibus_writereg(device_t, int, int, int); 83 int nfe_intr(void *); 84 int nfe_ioctl(struct ifnet *, u_long, void *); 85 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 86 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 87 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 88 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 89 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 90 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 91 void nfe_rxeof(struct nfe_softc *); 92 void nfe_txeof(struct nfe_softc *); 93 int nfe_encap(struct nfe_softc *, struct mbuf *); 94 void nfe_start(struct ifnet *); 95 void nfe_watchdog(struct ifnet *); 96 int nfe_init(struct ifnet *); 97 void nfe_stop(struct ifnet *, int); 98 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 99 void nfe_jfree(struct mbuf *, void *, size_t, void *); 100 int nfe_jpool_alloc(struct nfe_softc *); 101 void nfe_jpool_free(struct nfe_softc *); 102 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 105 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 108 void nfe_setmulti(struct nfe_softc *); 109 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 110 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 111 void nfe_tick(void *); 112 void nfe_poweron(device_t); 113 bool nfe_resume(device_t, const pmf_qual_t *); 114 115 CFATTACH_DECL_NEW(nfe, sizeof(struct nfe_softc), 116 nfe_match, nfe_attach, nfe_detach, NULL); 117 118 /* #define NFE_NO_JUMBO */ 119 120 #ifdef NFE_DEBUG 121 int nfedebug = 0; 122 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 123 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 124 #else 125 #define DPRINTF(x) 126 #define DPRINTFN(n,x) 127 #endif 128 129 /* deal with naming differences */ 130 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 134 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 135 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 136 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 137 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 140 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 141 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 142 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 145 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 146 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 147 148 #ifdef _LP64 149 #define __LP64__ 1 150 #endif 151 152 const struct nfe_product { 153 pci_vendor_id_t vendor; 154 pci_product_id_t product; 155 } nfe_devices[] = { 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 183 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 184 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 185 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 186 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 }, 187 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1 }, 188 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2 }, 189 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3 }, 190 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4 }, 191 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1 }, 192 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2 }, 193 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3 }, 194 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4 } 195 }; 196 197 int 198 nfe_match(device_t dev, cfdata_t match, void *aux) 199 { 200 struct pci_attach_args *pa = aux; 201 const struct nfe_product *np; 202 int i; 203 204 for (i = 0; i < __arraycount(nfe_devices); i++) { 205 np = &nfe_devices[i]; 206 if (PCI_VENDOR(pa->pa_id) == np->vendor && 207 PCI_PRODUCT(pa->pa_id) == np->product) 208 return 1; 209 } 210 return 0; 211 } 212 213 void 214 nfe_attach(device_t parent, device_t self, void *aux) 215 { 216 struct nfe_softc *sc = device_private(self); 217 struct pci_attach_args *pa = aux; 218 pci_chipset_tag_t pc = pa->pa_pc; 219 pci_intr_handle_t ih; 220 const char *intrstr; 221 struct ifnet *ifp; 222 pcireg_t memtype, csr; 223 int mii_flags = 0; 224 225 sc->sc_dev = self; 226 sc->sc_pc = pa->pa_pc; 227 pci_aprint_devinfo(pa, NULL); 228 229 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 230 switch (memtype) { 231 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 232 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 233 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 234 &sc->sc_memh, NULL, &sc->sc_mems) == 0) 235 break; 236 /* FALLTHROUGH */ 237 default: 238 aprint_error_dev(self, "could not map mem space\n"); 239 return; 240 } 241 242 if (pci_intr_map(pa, &ih) != 0) { 243 aprint_error_dev(self, "could not map interrupt\n"); 244 goto fail; 245 } 246 247 intrstr = pci_intr_string(pc, ih); 248 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 249 if (sc->sc_ih == NULL) { 250 aprint_error_dev(self, "could not establish interrupt"); 251 if (intrstr != NULL) 252 aprint_error(" at %s", intrstr); 253 aprint_error("\n"); 254 goto fail; 255 } 256 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 257 258 sc->sc_dmat = pa->pa_dmat; 259 260 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 261 csr |= PCI_COMMAND_MASTER_ENABLE; 262 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 263 264 sc->sc_flags = 0; 265 266 switch (PCI_PRODUCT(pa->pa_id)) { 267 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 268 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 269 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 270 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 271 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 272 break; 273 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 274 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 275 sc->sc_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT; 276 break; 277 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 278 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 279 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 280 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 281 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 282 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 283 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 284 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 285 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 286 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 287 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 288 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 289 sc->sc_flags |= NFE_40BIT_ADDR | NFE_CORRECT_MACADDR | 290 NFE_PWR_MGMT; 291 break; 292 case PCI_PRODUCT_NVIDIA_MCP77_LAN1: 293 case PCI_PRODUCT_NVIDIA_MCP77_LAN2: 294 case PCI_PRODUCT_NVIDIA_MCP77_LAN3: 295 case PCI_PRODUCT_NVIDIA_MCP77_LAN4: 296 sc->sc_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | 297 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 298 break; 299 case PCI_PRODUCT_NVIDIA_MCP79_LAN1: 300 case PCI_PRODUCT_NVIDIA_MCP79_LAN2: 301 case PCI_PRODUCT_NVIDIA_MCP79_LAN3: 302 case PCI_PRODUCT_NVIDIA_MCP79_LAN4: 303 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 304 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 305 break; 306 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 307 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 308 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 309 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 310 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 311 break; 312 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 313 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 314 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 315 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 316 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 317 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 318 mii_flags = MIIF_DOPAUSE; 319 break; 320 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 321 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 322 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 323 NFE_HW_VLAN | NFE_PWR_MGMT; 324 break; 325 } 326 327 nfe_poweron(self); 328 329 #ifndef NFE_NO_JUMBO 330 /* enable jumbo frames for adapters that support it */ 331 if (sc->sc_flags & NFE_JUMBO_SUP) 332 sc->sc_flags |= NFE_USE_JUMBO; 333 #endif 334 335 /* Check for reversed ethernet address */ 336 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 337 sc->sc_flags |= NFE_CORRECT_MACADDR; 338 339 nfe_get_macaddr(sc, sc->sc_enaddr); 340 aprint_normal_dev(self, "Ethernet address %s\n", 341 ether_sprintf(sc->sc_enaddr)); 342 343 /* 344 * Allocate Tx and Rx rings. 345 */ 346 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 347 aprint_error_dev(self, "could not allocate Tx ring\n"); 348 goto fail; 349 } 350 351 mutex_init(&sc->rxq.mtx, MUTEX_DEFAULT, IPL_NET); 352 353 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 354 aprint_error_dev(self, "could not allocate Rx ring\n"); 355 nfe_free_tx_ring(sc, &sc->txq); 356 goto fail; 357 } 358 359 ifp = &sc->sc_ethercom.ec_if; 360 ifp->if_softc = sc; 361 ifp->if_mtu = ETHERMTU; 362 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 363 ifp->if_ioctl = nfe_ioctl; 364 ifp->if_start = nfe_start; 365 ifp->if_stop = nfe_stop; 366 ifp->if_watchdog = nfe_watchdog; 367 ifp->if_init = nfe_init; 368 ifp->if_baudrate = IF_Gbps(1); 369 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 370 IFQ_SET_READY(&ifp->if_snd); 371 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 372 373 if (sc->sc_flags & NFE_USE_JUMBO) 374 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 375 376 #if NVLAN > 0 377 if (sc->sc_flags & NFE_HW_VLAN) 378 sc->sc_ethercom.ec_capabilities |= 379 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 380 #endif 381 if (sc->sc_flags & NFE_HW_CSUM) { 382 ifp->if_capabilities |= 383 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 384 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 385 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 386 } 387 388 sc->sc_mii.mii_ifp = ifp; 389 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 390 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 391 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 392 393 sc->sc_ethercom.ec_mii = &sc->sc_mii; 394 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 395 ether_mediastatus); 396 397 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 0, mii_flags); 398 399 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 400 aprint_error_dev(self, "no PHY found!\n"); 401 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 402 0, NULL); 403 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 404 } else 405 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 406 407 if_attach(ifp); 408 ether_ifattach(ifp, sc->sc_enaddr); 409 ether_set_ifflags_cb(&sc->sc_ethercom, nfe_ifflags_cb); 410 411 callout_init(&sc->sc_tick_ch, 0); 412 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 413 414 if (pmf_device_register(self, NULL, nfe_resume)) 415 pmf_class_network_register(self, ifp); 416 else 417 aprint_error_dev(self, "couldn't establish power handler\n"); 418 419 return; 420 421 fail: 422 if (sc->sc_ih != NULL) { 423 pci_intr_disestablish(pc, sc->sc_ih); 424 sc->sc_ih = NULL; 425 } 426 if (sc->sc_mems != 0) { 427 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 428 sc->sc_mems = 0; 429 } 430 } 431 432 int 433 nfe_detach(device_t self, int flags) 434 { 435 struct nfe_softc *sc = device_private(self); 436 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 437 int s; 438 439 s = splnet(); 440 441 nfe_stop(ifp, 1); 442 443 pmf_device_deregister(self); 444 callout_destroy(&sc->sc_tick_ch); 445 ether_ifdetach(ifp); 446 if_detach(ifp); 447 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 448 449 nfe_free_rx_ring(sc, &sc->rxq); 450 mutex_destroy(&sc->rxq.mtx); 451 nfe_free_tx_ring(sc, &sc->txq); 452 453 if (sc->sc_ih != NULL) { 454 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 455 sc->sc_ih = NULL; 456 } 457 458 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 459 nfe_set_macaddr(sc, sc->sc_enaddr); 460 } else { 461 NFE_WRITE(sc, NFE_MACADDR_LO, 462 sc->sc_enaddr[0] << 8 | sc->sc_enaddr[1]); 463 NFE_WRITE(sc, NFE_MACADDR_HI, 464 sc->sc_enaddr[2] << 24 | sc->sc_enaddr[3] << 16 | 465 sc->sc_enaddr[4] << 8 | sc->sc_enaddr[5]); 466 } 467 468 if (sc->sc_mems != 0) { 469 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 470 sc->sc_mems = 0; 471 } 472 473 splx(s); 474 475 return 0; 476 } 477 478 void 479 nfe_miibus_statchg(struct ifnet *ifp) 480 { 481 struct nfe_softc *sc = ifp->if_softc; 482 struct mii_data *mii = &sc->sc_mii; 483 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 484 485 phy = NFE_READ(sc, NFE_PHY_IFACE); 486 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 487 488 seed = NFE_READ(sc, NFE_RNDSEED); 489 seed &= ~NFE_SEED_MASK; 490 491 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 492 phy |= NFE_PHY_HDX; /* half-duplex */ 493 misc |= NFE_MISC1_HDX; 494 } 495 496 switch (IFM_SUBTYPE(mii->mii_media_active)) { 497 case IFM_1000_T: /* full-duplex only */ 498 link |= NFE_MEDIA_1000T; 499 seed |= NFE_SEED_1000T; 500 phy |= NFE_PHY_1000T; 501 break; 502 case IFM_100_TX: 503 link |= NFE_MEDIA_100TX; 504 seed |= NFE_SEED_100TX; 505 phy |= NFE_PHY_100TX; 506 break; 507 case IFM_10_T: 508 link |= NFE_MEDIA_10T; 509 seed |= NFE_SEED_10T; 510 break; 511 } 512 513 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 514 515 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 516 NFE_WRITE(sc, NFE_MISC1, misc); 517 NFE_WRITE(sc, NFE_LINKSPEED, link); 518 } 519 520 int 521 nfe_miibus_readreg(device_t dev, int phy, int reg) 522 { 523 struct nfe_softc *sc = device_private(dev); 524 uint32_t val; 525 int ntries; 526 527 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 528 529 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 530 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 531 DELAY(100); 532 } 533 534 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 535 536 for (ntries = 0; ntries < 1000; ntries++) { 537 DELAY(100); 538 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 539 break; 540 } 541 if (ntries == 1000) { 542 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 543 device_xname(sc->sc_dev))); 544 return 0; 545 } 546 547 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 548 DPRINTFN(2, ("%s: could not read PHY\n", 549 device_xname(sc->sc_dev))); 550 return 0; 551 } 552 553 val = NFE_READ(sc, NFE_PHY_DATA); 554 if (val != 0xffffffff && val != 0) 555 sc->mii_phyaddr = phy; 556 557 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 558 device_xname(sc->sc_dev), phy, reg, val)); 559 560 return val; 561 } 562 563 void 564 nfe_miibus_writereg(device_t dev, int phy, int reg, int val) 565 { 566 struct nfe_softc *sc = device_private(dev); 567 uint32_t ctl; 568 int ntries; 569 570 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 571 572 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 573 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 574 DELAY(100); 575 } 576 577 NFE_WRITE(sc, NFE_PHY_DATA, val); 578 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 579 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 580 581 for (ntries = 0; ntries < 1000; ntries++) { 582 DELAY(100); 583 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 584 break; 585 } 586 #ifdef NFE_DEBUG 587 if (nfedebug >= 2 && ntries == 1000) 588 printf("could not write to PHY\n"); 589 #endif 590 } 591 592 int 593 nfe_intr(void *arg) 594 { 595 struct nfe_softc *sc = arg; 596 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 597 uint32_t r; 598 int handled; 599 600 if ((ifp->if_flags & IFF_UP) == 0) 601 return 0; 602 603 handled = 0; 604 605 for (;;) { 606 r = NFE_READ(sc, NFE_IRQ_STATUS); 607 if ((r & NFE_IRQ_WANTED) == 0) 608 break; 609 610 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 611 handled = 1; 612 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 613 614 if ((r & (NFE_IRQ_RXERR|NFE_IRQ_RX_NOBUF|NFE_IRQ_RX)) != 0) { 615 /* check Rx ring */ 616 nfe_rxeof(sc); 617 } 618 if ((r & (NFE_IRQ_TXERR|NFE_IRQ_TXERR2|NFE_IRQ_TX_DONE)) != 0) { 619 /* check Tx ring */ 620 nfe_txeof(sc); 621 } 622 if ((r & NFE_IRQ_LINK) != 0) { 623 NFE_READ(sc, NFE_PHY_STATUS); 624 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 625 DPRINTF(("%s: link state changed\n", 626 device_xname(sc->sc_dev))); 627 } 628 } 629 630 if (handled && !IF_IS_EMPTY(&ifp->if_snd)) 631 nfe_start(ifp); 632 633 return handled; 634 } 635 636 static int 637 nfe_ifflags_cb(struct ethercom *ec) 638 { 639 struct ifnet *ifp = &ec->ec_if; 640 struct nfe_softc *sc = ifp->if_softc; 641 int change = ifp->if_flags ^ sc->sc_if_flags; 642 643 /* 644 * If only the PROMISC flag changes, then 645 * don't do a full re-init of the chip, just update 646 * the Rx filter. 647 */ 648 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 649 return ENETRESET; 650 else if ((change & IFF_PROMISC) != 0) 651 nfe_setmulti(sc); 652 653 return 0; 654 } 655 656 int 657 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 658 { 659 struct nfe_softc *sc = ifp->if_softc; 660 struct ifaddr *ifa = (struct ifaddr *)data; 661 int s, error = 0; 662 663 s = splnet(); 664 665 switch (cmd) { 666 case SIOCINITIFADDR: 667 ifp->if_flags |= IFF_UP; 668 nfe_init(ifp); 669 switch (ifa->ifa_addr->sa_family) { 670 #ifdef INET 671 case AF_INET: 672 arp_ifinit(ifp, ifa); 673 break; 674 #endif 675 default: 676 break; 677 } 678 break; 679 default: 680 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 681 break; 682 683 error = 0; 684 685 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 686 ; 687 else if (ifp->if_flags & IFF_RUNNING) 688 nfe_setmulti(sc); 689 break; 690 } 691 sc->sc_if_flags = ifp->if_flags; 692 693 splx(s); 694 695 return error; 696 } 697 698 void 699 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 700 { 701 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 702 (char *)desc32 - (char *)sc->txq.desc32, 703 sizeof (struct nfe_desc32), ops); 704 } 705 706 void 707 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 708 { 709 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 710 (char *)desc64 - (char *)sc->txq.desc64, 711 sizeof (struct nfe_desc64), ops); 712 } 713 714 void 715 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 716 { 717 if (end > start) { 718 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 719 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 720 (char *)&sc->txq.desc32[end] - 721 (char *)&sc->txq.desc32[start], ops); 722 return; 723 } 724 /* sync from 'start' to end of ring */ 725 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 726 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 727 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 728 (char *)&sc->txq.desc32[start], ops); 729 730 /* sync from start of ring to 'end' */ 731 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 732 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 733 } 734 735 void 736 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 737 { 738 if (end > start) { 739 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 740 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 741 (char *)&sc->txq.desc64[end] - 742 (char *)&sc->txq.desc64[start], ops); 743 return; 744 } 745 /* sync from 'start' to end of ring */ 746 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 747 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 748 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 749 (char *)&sc->txq.desc64[start], ops); 750 751 /* sync from start of ring to 'end' */ 752 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 753 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 754 } 755 756 void 757 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 758 { 759 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 760 (char *)desc32 - (char *)sc->rxq.desc32, 761 sizeof (struct nfe_desc32), ops); 762 } 763 764 void 765 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 766 { 767 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 768 (char *)desc64 - (char *)sc->rxq.desc64, 769 sizeof (struct nfe_desc64), ops); 770 } 771 772 void 773 nfe_rxeof(struct nfe_softc *sc) 774 { 775 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 776 struct nfe_desc32 *desc32; 777 struct nfe_desc64 *desc64; 778 struct nfe_rx_data *data; 779 struct nfe_jbuf *jbuf; 780 struct mbuf *m, *mnew; 781 bus_addr_t physaddr; 782 uint16_t flags; 783 int error, len, i; 784 785 desc32 = NULL; 786 desc64 = NULL; 787 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 788 data = &sc->rxq.data[i]; 789 790 if (sc->sc_flags & NFE_40BIT_ADDR) { 791 desc64 = &sc->rxq.desc64[i]; 792 nfe_rxdesc64_sync(sc, desc64, 793 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 794 795 flags = le16toh(desc64->flags); 796 len = le16toh(desc64->length) & 0x3fff; 797 } else { 798 desc32 = &sc->rxq.desc32[i]; 799 nfe_rxdesc32_sync(sc, desc32, 800 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 801 802 flags = le16toh(desc32->flags); 803 len = le16toh(desc32->length) & 0x3fff; 804 } 805 806 if ((flags & NFE_RX_READY) != 0) 807 break; 808 809 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 810 if ((flags & NFE_RX_VALID_V1) == 0) 811 goto skip; 812 813 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 814 flags &= ~NFE_RX_ERROR; 815 len--; /* fix buffer length */ 816 } 817 } else { 818 if ((flags & NFE_RX_VALID_V2) == 0) 819 goto skip; 820 821 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 822 flags &= ~NFE_RX_ERROR; 823 len--; /* fix buffer length */ 824 } 825 } 826 827 if (flags & NFE_RX_ERROR) { 828 ifp->if_ierrors++; 829 goto skip; 830 } 831 832 /* 833 * Try to allocate a new mbuf for this ring element and load 834 * it before processing the current mbuf. If the ring element 835 * cannot be loaded, drop the received packet and reuse the 836 * old mbuf. In the unlikely case that the old mbuf can't be 837 * reloaded either, explicitly panic. 838 */ 839 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 840 if (mnew == NULL) { 841 ifp->if_ierrors++; 842 goto skip; 843 } 844 845 if (sc->sc_flags & NFE_USE_JUMBO) { 846 physaddr = 847 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 848 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 849 if (len > MCLBYTES) { 850 m_freem(mnew); 851 ifp->if_ierrors++; 852 goto skip1; 853 } 854 MCLGET(mnew, M_DONTWAIT); 855 if ((mnew->m_flags & M_EXT) == 0) { 856 m_freem(mnew); 857 ifp->if_ierrors++; 858 goto skip1; 859 } 860 861 (void)memcpy(mtod(mnew, void *), 862 mtod(data->m, const void *), len); 863 m = mnew; 864 goto mbufcopied; 865 } else { 866 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 867 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 868 mtod(data->m, char *) - (char *)sc->rxq.jpool, 869 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 870 871 physaddr = jbuf->physaddr; 872 } 873 } else { 874 MCLGET(mnew, M_DONTWAIT); 875 if ((mnew->m_flags & M_EXT) == 0) { 876 m_freem(mnew); 877 ifp->if_ierrors++; 878 goto skip; 879 } 880 881 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 882 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 883 bus_dmamap_unload(sc->sc_dmat, data->map); 884 885 error = bus_dmamap_load(sc->sc_dmat, data->map, 886 mtod(mnew, void *), MCLBYTES, NULL, 887 BUS_DMA_READ | BUS_DMA_NOWAIT); 888 if (error != 0) { 889 m_freem(mnew); 890 891 /* try to reload the old mbuf */ 892 error = bus_dmamap_load(sc->sc_dmat, data->map, 893 mtod(data->m, void *), MCLBYTES, NULL, 894 BUS_DMA_READ | BUS_DMA_NOWAIT); 895 if (error != 0) { 896 /* very unlikely that it will fail.. */ 897 panic("%s: could not load old rx mbuf", 898 device_xname(sc->sc_dev)); 899 } 900 ifp->if_ierrors++; 901 goto skip; 902 } 903 physaddr = data->map->dm_segs[0].ds_addr; 904 } 905 906 /* 907 * New mbuf successfully loaded, update Rx ring and continue 908 * processing. 909 */ 910 m = data->m; 911 data->m = mnew; 912 913 mbufcopied: 914 /* finalize mbuf */ 915 m->m_pkthdr.len = m->m_len = len; 916 m->m_pkthdr.rcvif = ifp; 917 918 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 919 /* 920 * XXX 921 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 922 */ 923 if (flags & NFE_RX_IP_CSUMOK) { 924 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 925 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 926 device_xname(sc->sc_dev))); 927 } 928 /* 929 * XXX 930 * no way to check M_CSUM_TCP_UDP_BAD or 931 * other protocols? 932 */ 933 if (flags & NFE_RX_UDP_CSUMOK) { 934 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 935 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 936 device_xname(sc->sc_dev))); 937 } else if (flags & NFE_RX_TCP_CSUMOK) { 938 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 939 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 940 device_xname(sc->sc_dev))); 941 } 942 } 943 bpf_mtap(ifp, m); 944 ifp->if_ipackets++; 945 (*ifp->if_input)(ifp, m); 946 947 skip1: 948 /* update mapping address in h/w descriptor */ 949 if (sc->sc_flags & NFE_40BIT_ADDR) { 950 #if defined(__LP64__) 951 desc64->physaddr[0] = htole32(physaddr >> 32); 952 #endif 953 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 954 } else { 955 desc32->physaddr = htole32(physaddr); 956 } 957 958 skip: 959 if (sc->sc_flags & NFE_40BIT_ADDR) { 960 desc64->length = htole16(sc->rxq.bufsz); 961 desc64->flags = htole16(NFE_RX_READY); 962 963 nfe_rxdesc64_sync(sc, desc64, 964 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 965 } else { 966 desc32->length = htole16(sc->rxq.bufsz); 967 desc32->flags = htole16(NFE_RX_READY); 968 969 nfe_rxdesc32_sync(sc, desc32, 970 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 971 } 972 } 973 /* update current RX pointer */ 974 sc->rxq.cur = i; 975 } 976 977 void 978 nfe_txeof(struct nfe_softc *sc) 979 { 980 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 981 struct nfe_desc32 *desc32; 982 struct nfe_desc64 *desc64; 983 struct nfe_tx_data *data = NULL; 984 int i; 985 uint16_t flags; 986 char buf[128]; 987 988 for (i = sc->txq.next; 989 sc->txq.queued > 0; 990 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 991 if (sc->sc_flags & NFE_40BIT_ADDR) { 992 desc64 = &sc->txq.desc64[i]; 993 nfe_txdesc64_sync(sc, desc64, 994 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 995 996 flags = le16toh(desc64->flags); 997 } else { 998 desc32 = &sc->txq.desc32[i]; 999 nfe_txdesc32_sync(sc, desc32, 1000 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1001 1002 flags = le16toh(desc32->flags); 1003 } 1004 1005 if ((flags & NFE_TX_VALID) != 0) 1006 break; 1007 1008 data = &sc->txq.data[i]; 1009 1010 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 1011 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 1012 data->m == NULL) 1013 continue; 1014 1015 if ((flags & NFE_TX_ERROR_V1) != 0) { 1016 snprintb(buf, sizeof(buf), NFE_V1_TXERR, flags); 1017 aprint_error_dev(sc->sc_dev, "tx v1 error %s\n", 1018 buf); 1019 ifp->if_oerrors++; 1020 } else 1021 ifp->if_opackets++; 1022 } else { 1023 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 1024 data->m == NULL) 1025 continue; 1026 1027 if ((flags & NFE_TX_ERROR_V2) != 0) { 1028 snprintb(buf, sizeof(buf), NFE_V2_TXERR, flags); 1029 aprint_error_dev(sc->sc_dev, "tx v2 error %s\n", 1030 buf); 1031 ifp->if_oerrors++; 1032 } else 1033 ifp->if_opackets++; 1034 } 1035 1036 if (data->m == NULL) { /* should not get there */ 1037 aprint_error_dev(sc->sc_dev, 1038 "last fragment bit w/o associated mbuf!\n"); 1039 continue; 1040 } 1041 1042 /* last fragment of the mbuf chain transmitted */ 1043 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1044 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1045 bus_dmamap_unload(sc->sc_dmat, data->active); 1046 m_freem(data->m); 1047 data->m = NULL; 1048 } 1049 1050 sc->txq.next = i; 1051 1052 if (sc->txq.queued < NFE_TX_RING_COUNT) { 1053 /* at least one slot freed */ 1054 ifp->if_flags &= ~IFF_OACTIVE; 1055 } 1056 1057 if (sc->txq.queued == 0) { 1058 /* all queued packets are sent */ 1059 ifp->if_timer = 0; 1060 } 1061 } 1062 1063 int 1064 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 1065 { 1066 struct nfe_desc32 *desc32; 1067 struct nfe_desc64 *desc64; 1068 struct nfe_tx_data *data; 1069 bus_dmamap_t map; 1070 uint16_t flags, csumflags; 1071 #if NVLAN > 0 1072 struct m_tag *mtag; 1073 uint32_t vtag = 0; 1074 #endif 1075 int error, i, first; 1076 1077 desc32 = NULL; 1078 desc64 = NULL; 1079 data = NULL; 1080 1081 flags = 0; 1082 csumflags = 0; 1083 first = sc->txq.cur; 1084 1085 map = sc->txq.data[first].map; 1086 1087 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1088 if (error != 0) { 1089 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1090 error); 1091 return error; 1092 } 1093 1094 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1095 bus_dmamap_unload(sc->sc_dmat, map); 1096 return ENOBUFS; 1097 } 1098 1099 #if NVLAN > 0 1100 /* setup h/w VLAN tagging */ 1101 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1102 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1103 #endif 1104 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1105 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1106 csumflags |= NFE_TX_IP_CSUM; 1107 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1108 csumflags |= NFE_TX_TCP_UDP_CSUM; 1109 } 1110 1111 for (i = 0; i < map->dm_nsegs; i++) { 1112 data = &sc->txq.data[sc->txq.cur]; 1113 1114 if (sc->sc_flags & NFE_40BIT_ADDR) { 1115 desc64 = &sc->txq.desc64[sc->txq.cur]; 1116 #if defined(__LP64__) 1117 desc64->physaddr[0] = 1118 htole32(map->dm_segs[i].ds_addr >> 32); 1119 #endif 1120 desc64->physaddr[1] = 1121 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1122 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1123 desc64->flags = htole16(flags); 1124 desc64->vtag = 0; 1125 } else { 1126 desc32 = &sc->txq.desc32[sc->txq.cur]; 1127 1128 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1129 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1130 desc32->flags = htole16(flags); 1131 } 1132 1133 /* 1134 * Setting of the valid bit in the first descriptor is 1135 * deferred until the whole chain is fully setup. 1136 */ 1137 flags |= NFE_TX_VALID; 1138 1139 sc->txq.queued++; 1140 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1141 } 1142 1143 /* the whole mbuf chain has been setup */ 1144 if (sc->sc_flags & NFE_40BIT_ADDR) { 1145 /* fix last descriptor */ 1146 flags |= NFE_TX_LASTFRAG_V2; 1147 desc64->flags = htole16(flags); 1148 1149 /* Checksum flags and vtag belong to the first fragment only. */ 1150 #if NVLAN > 0 1151 sc->txq.desc64[first].vtag = htole32(vtag); 1152 #endif 1153 sc->txq.desc64[first].flags |= htole16(csumflags); 1154 1155 /* finally, set the valid bit in the first descriptor */ 1156 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1157 } else { 1158 /* fix last descriptor */ 1159 if (sc->sc_flags & NFE_JUMBO_SUP) 1160 flags |= NFE_TX_LASTFRAG_V2; 1161 else 1162 flags |= NFE_TX_LASTFRAG_V1; 1163 desc32->flags = htole16(flags); 1164 1165 /* Checksum flags belong to the first fragment only. */ 1166 sc->txq.desc32[first].flags |= htole16(csumflags); 1167 1168 /* finally, set the valid bit in the first descriptor */ 1169 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1170 } 1171 1172 data->m = m0; 1173 data->active = map; 1174 1175 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1176 BUS_DMASYNC_PREWRITE); 1177 1178 return 0; 1179 } 1180 1181 void 1182 nfe_start(struct ifnet *ifp) 1183 { 1184 struct nfe_softc *sc = ifp->if_softc; 1185 int old = sc->txq.queued; 1186 struct mbuf *m0; 1187 1188 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1189 return; 1190 1191 for (;;) { 1192 IFQ_POLL(&ifp->if_snd, m0); 1193 if (m0 == NULL) 1194 break; 1195 1196 if (nfe_encap(sc, m0) != 0) { 1197 ifp->if_flags |= IFF_OACTIVE; 1198 break; 1199 } 1200 1201 /* packet put in h/w queue, remove from s/w queue */ 1202 IFQ_DEQUEUE(&ifp->if_snd, m0); 1203 1204 bpf_mtap(ifp, m0); 1205 } 1206 1207 if (sc->txq.queued != old) { 1208 /* packets are queued */ 1209 if (sc->sc_flags & NFE_40BIT_ADDR) 1210 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1211 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1212 else 1213 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1214 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1215 /* kick Tx */ 1216 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1217 1218 /* 1219 * Set a timeout in case the chip goes out to lunch. 1220 */ 1221 ifp->if_timer = 5; 1222 } 1223 } 1224 1225 void 1226 nfe_watchdog(struct ifnet *ifp) 1227 { 1228 struct nfe_softc *sc = ifp->if_softc; 1229 1230 aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1231 1232 ifp->if_flags &= ~IFF_RUNNING; 1233 nfe_init(ifp); 1234 1235 ifp->if_oerrors++; 1236 } 1237 1238 int 1239 nfe_init(struct ifnet *ifp) 1240 { 1241 struct nfe_softc *sc = ifp->if_softc; 1242 uint32_t tmp; 1243 int rc = 0, s; 1244 1245 if (ifp->if_flags & IFF_RUNNING) 1246 return 0; 1247 1248 nfe_stop(ifp, 0); 1249 1250 NFE_WRITE(sc, NFE_TX_UNK, 0); 1251 NFE_WRITE(sc, NFE_STATUS, 0); 1252 1253 sc->rxtxctl = NFE_RXTX_BIT2; 1254 if (sc->sc_flags & NFE_40BIT_ADDR) 1255 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1256 else if (sc->sc_flags & NFE_JUMBO_SUP) 1257 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1258 if (sc->sc_flags & NFE_HW_CSUM) 1259 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1260 #if NVLAN > 0 1261 /* 1262 * Although the adapter is capable of stripping VLAN tags from received 1263 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1264 * purpose. This will be done in software by our network stack. 1265 */ 1266 if (sc->sc_flags & NFE_HW_VLAN) 1267 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1268 #endif 1269 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1270 DELAY(10); 1271 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1272 1273 #if NVLAN 1274 if (sc->sc_flags & NFE_HW_VLAN) 1275 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1276 #endif 1277 1278 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1279 1280 /* set MAC address */ 1281 nfe_set_macaddr(sc, sc->sc_enaddr); 1282 1283 /* tell MAC where rings are in memory */ 1284 #ifdef __LP64__ 1285 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1286 #endif 1287 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1288 #ifdef __LP64__ 1289 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1290 #endif 1291 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1292 1293 NFE_WRITE(sc, NFE_RING_SIZE, 1294 (NFE_RX_RING_COUNT - 1) << 16 | 1295 (NFE_TX_RING_COUNT - 1)); 1296 1297 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1298 1299 /* force MAC to wakeup */ 1300 tmp = NFE_READ(sc, NFE_PWR_STATE); 1301 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1302 DELAY(10); 1303 tmp = NFE_READ(sc, NFE_PWR_STATE); 1304 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1305 1306 s = splnet(); 1307 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1308 nfe_intr(sc); /* XXX clear IRQ status registers */ 1309 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1310 splx(s); 1311 1312 #if 1 1313 /* configure interrupts coalescing/mitigation */ 1314 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1315 #else 1316 /* no interrupt mitigation: one interrupt per packet */ 1317 NFE_WRITE(sc, NFE_IMTIMER, 970); 1318 #endif 1319 1320 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1321 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1322 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1323 1324 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1325 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1326 1327 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1328 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_ENABLE); 1329 1330 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1331 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1332 DELAY(10); 1333 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1334 1335 /* set Rx filter */ 1336 nfe_setmulti(sc); 1337 1338 if ((rc = ether_mediachange(ifp)) != 0) 1339 goto out; 1340 1341 nfe_tick(sc); 1342 1343 /* enable Rx */ 1344 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1345 1346 /* enable Tx */ 1347 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1348 1349 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1350 1351 /* enable interrupts */ 1352 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1353 1354 callout_schedule(&sc->sc_tick_ch, hz); 1355 1356 ifp->if_flags |= IFF_RUNNING; 1357 ifp->if_flags &= ~IFF_OACTIVE; 1358 1359 out: 1360 return rc; 1361 } 1362 1363 void 1364 nfe_stop(struct ifnet *ifp, int disable) 1365 { 1366 struct nfe_softc *sc = ifp->if_softc; 1367 1368 callout_stop(&sc->sc_tick_ch); 1369 1370 ifp->if_timer = 0; 1371 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1372 1373 mii_down(&sc->sc_mii); 1374 1375 /* abort Tx */ 1376 NFE_WRITE(sc, NFE_TX_CTL, 0); 1377 1378 /* disable Rx */ 1379 NFE_WRITE(sc, NFE_RX_CTL, 0); 1380 1381 /* disable interrupts */ 1382 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1383 1384 /* reset Tx and Rx rings */ 1385 nfe_reset_tx_ring(sc, &sc->txq); 1386 nfe_reset_rx_ring(sc, &sc->rxq); 1387 } 1388 1389 int 1390 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1391 { 1392 struct nfe_desc32 *desc32; 1393 struct nfe_desc64 *desc64; 1394 struct nfe_rx_data *data; 1395 struct nfe_jbuf *jbuf; 1396 void **desc; 1397 bus_addr_t physaddr; 1398 int i, nsegs, error, descsize; 1399 1400 if (sc->sc_flags & NFE_40BIT_ADDR) { 1401 desc = (void **)&ring->desc64; 1402 descsize = sizeof (struct nfe_desc64); 1403 } else { 1404 desc = (void **)&ring->desc32; 1405 descsize = sizeof (struct nfe_desc32); 1406 } 1407 1408 ring->cur = ring->next = 0; 1409 ring->bufsz = MCLBYTES; 1410 1411 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1412 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1413 if (error != 0) { 1414 aprint_error_dev(sc->sc_dev, 1415 "could not create desc DMA map\n"); 1416 ring->map = NULL; 1417 goto fail; 1418 } 1419 1420 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1421 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1422 if (error != 0) { 1423 aprint_error_dev(sc->sc_dev, 1424 "could not allocate DMA memory\n"); 1425 goto fail; 1426 } 1427 1428 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1429 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1430 if (error != 0) { 1431 aprint_error_dev(sc->sc_dev, 1432 "could not map desc DMA memory\n"); 1433 goto fail; 1434 } 1435 1436 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1437 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1438 if (error != 0) { 1439 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1440 goto fail; 1441 } 1442 1443 memset(*desc, 0, NFE_RX_RING_COUNT * descsize); 1444 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1445 1446 if (sc->sc_flags & NFE_USE_JUMBO) { 1447 ring->bufsz = NFE_JBYTES; 1448 if ((error = nfe_jpool_alloc(sc)) != 0) { 1449 aprint_error_dev(sc->sc_dev, 1450 "could not allocate jumbo frames\n"); 1451 goto fail; 1452 } 1453 } 1454 1455 /* 1456 * Pre-allocate Rx buffers and populate Rx ring. 1457 */ 1458 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1459 data = &sc->rxq.data[i]; 1460 1461 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1462 if (data->m == NULL) { 1463 aprint_error_dev(sc->sc_dev, 1464 "could not allocate rx mbuf\n"); 1465 error = ENOMEM; 1466 goto fail; 1467 } 1468 1469 if (sc->sc_flags & NFE_USE_JUMBO) { 1470 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1471 aprint_error_dev(sc->sc_dev, 1472 "could not allocate jumbo buffer\n"); 1473 goto fail; 1474 } 1475 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1476 sc); 1477 1478 physaddr = jbuf->physaddr; 1479 } else { 1480 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1481 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1482 if (error != 0) { 1483 aprint_error_dev(sc->sc_dev, 1484 "could not create DMA map\n"); 1485 data->map = NULL; 1486 goto fail; 1487 } 1488 MCLGET(data->m, M_DONTWAIT); 1489 if (!(data->m->m_flags & M_EXT)) { 1490 aprint_error_dev(sc->sc_dev, 1491 "could not allocate mbuf cluster\n"); 1492 error = ENOMEM; 1493 goto fail; 1494 } 1495 1496 error = bus_dmamap_load(sc->sc_dmat, data->map, 1497 mtod(data->m, void *), MCLBYTES, NULL, 1498 BUS_DMA_READ | BUS_DMA_NOWAIT); 1499 if (error != 0) { 1500 aprint_error_dev(sc->sc_dev, 1501 "could not load rx buf DMA map"); 1502 goto fail; 1503 } 1504 physaddr = data->map->dm_segs[0].ds_addr; 1505 } 1506 1507 if (sc->sc_flags & NFE_40BIT_ADDR) { 1508 desc64 = &sc->rxq.desc64[i]; 1509 #if defined(__LP64__) 1510 desc64->physaddr[0] = htole32(physaddr >> 32); 1511 #endif 1512 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1513 desc64->length = htole16(sc->rxq.bufsz); 1514 desc64->flags = htole16(NFE_RX_READY); 1515 } else { 1516 desc32 = &sc->rxq.desc32[i]; 1517 desc32->physaddr = htole32(physaddr); 1518 desc32->length = htole16(sc->rxq.bufsz); 1519 desc32->flags = htole16(NFE_RX_READY); 1520 } 1521 } 1522 1523 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1524 BUS_DMASYNC_PREWRITE); 1525 1526 return 0; 1527 1528 fail: nfe_free_rx_ring(sc, ring); 1529 return error; 1530 } 1531 1532 void 1533 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1534 { 1535 int i; 1536 1537 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1538 if (sc->sc_flags & NFE_40BIT_ADDR) { 1539 ring->desc64[i].length = htole16(ring->bufsz); 1540 ring->desc64[i].flags = htole16(NFE_RX_READY); 1541 } else { 1542 ring->desc32[i].length = htole16(ring->bufsz); 1543 ring->desc32[i].flags = htole16(NFE_RX_READY); 1544 } 1545 } 1546 1547 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1548 BUS_DMASYNC_PREWRITE); 1549 1550 ring->cur = ring->next = 0; 1551 } 1552 1553 void 1554 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1555 { 1556 struct nfe_rx_data *data; 1557 void *desc; 1558 int i, descsize; 1559 1560 if (sc->sc_flags & NFE_40BIT_ADDR) { 1561 desc = ring->desc64; 1562 descsize = sizeof (struct nfe_desc64); 1563 } else { 1564 desc = ring->desc32; 1565 descsize = sizeof (struct nfe_desc32); 1566 } 1567 1568 if (desc != NULL) { 1569 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1570 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1571 bus_dmamap_unload(sc->sc_dmat, ring->map); 1572 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1573 NFE_RX_RING_COUNT * descsize); 1574 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1575 } 1576 1577 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1578 data = &ring->data[i]; 1579 1580 if (data->map != NULL) { 1581 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1582 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1583 bus_dmamap_unload(sc->sc_dmat, data->map); 1584 bus_dmamap_destroy(sc->sc_dmat, data->map); 1585 } 1586 if (data->m != NULL) 1587 m_freem(data->m); 1588 } 1589 1590 nfe_jpool_free(sc); 1591 } 1592 1593 struct nfe_jbuf * 1594 nfe_jalloc(struct nfe_softc *sc, int i) 1595 { 1596 struct nfe_jbuf *jbuf; 1597 1598 mutex_enter(&sc->rxq.mtx); 1599 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1600 if (jbuf != NULL) 1601 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1602 mutex_exit(&sc->rxq.mtx); 1603 if (jbuf == NULL) 1604 return NULL; 1605 sc->rxq.jbufmap[i] = 1606 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1607 return jbuf; 1608 } 1609 1610 /* 1611 * This is called automatically by the network stack when the mbuf is freed. 1612 * Caution must be taken that the NIC might be reset by the time the mbuf is 1613 * freed. 1614 */ 1615 void 1616 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1617 { 1618 struct nfe_softc *sc = arg; 1619 struct nfe_jbuf *jbuf; 1620 int i; 1621 1622 /* find the jbuf from the base pointer */ 1623 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1624 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1625 aprint_error_dev(sc->sc_dev, 1626 "request to free a buffer (%p) not managed by us\n", buf); 1627 return; 1628 } 1629 jbuf = &sc->rxq.jbuf[i]; 1630 1631 /* ..and put it back in the free list */ 1632 mutex_enter(&sc->rxq.mtx); 1633 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1634 mutex_exit(&sc->rxq.mtx); 1635 1636 if (m != NULL) 1637 pool_cache_put(mb_cache, m); 1638 } 1639 1640 int 1641 nfe_jpool_alloc(struct nfe_softc *sc) 1642 { 1643 struct nfe_rx_ring *ring = &sc->rxq; 1644 struct nfe_jbuf *jbuf; 1645 bus_addr_t physaddr; 1646 char *buf; 1647 int i, nsegs, error; 1648 1649 /* 1650 * Allocate a big chunk of DMA'able memory. 1651 */ 1652 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1653 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1654 if (error != 0) { 1655 aprint_error_dev(sc->sc_dev, 1656 "could not create jumbo DMA map\n"); 1657 ring->jmap = NULL; 1658 goto fail; 1659 } 1660 1661 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1662 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1663 if (error != 0) { 1664 aprint_error_dev(sc->sc_dev, 1665 "could not allocate jumbo DMA memory\n"); 1666 goto fail; 1667 } 1668 1669 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1670 &ring->jpool, BUS_DMA_NOWAIT); 1671 if (error != 0) { 1672 aprint_error_dev(sc->sc_dev, 1673 "could not map jumbo DMA memory\n"); 1674 goto fail; 1675 } 1676 1677 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1678 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1679 if (error != 0) { 1680 aprint_error_dev(sc->sc_dev, 1681 "could not load jumbo DMA map\n"); 1682 goto fail; 1683 } 1684 1685 /* ..and split it into 9KB chunks */ 1686 SLIST_INIT(&ring->jfreelist); 1687 1688 buf = ring->jpool; 1689 physaddr = ring->jmap->dm_segs[0].ds_addr; 1690 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1691 jbuf = &ring->jbuf[i]; 1692 1693 jbuf->buf = buf; 1694 jbuf->physaddr = physaddr; 1695 1696 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1697 1698 buf += NFE_JBYTES; 1699 physaddr += NFE_JBYTES; 1700 } 1701 1702 return 0; 1703 1704 fail: nfe_jpool_free(sc); 1705 return error; 1706 } 1707 1708 void 1709 nfe_jpool_free(struct nfe_softc *sc) 1710 { 1711 struct nfe_rx_ring *ring = &sc->rxq; 1712 1713 if (ring->jmap != NULL) { 1714 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1715 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1716 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1717 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1718 ring->jmap = NULL; 1719 } 1720 if (ring->jpool != NULL) { 1721 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1722 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1723 ring->jpool = NULL; 1724 } 1725 } 1726 1727 int 1728 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1729 { 1730 int i, nsegs, error; 1731 void **desc; 1732 int descsize; 1733 1734 if (sc->sc_flags & NFE_40BIT_ADDR) { 1735 desc = (void **)&ring->desc64; 1736 descsize = sizeof (struct nfe_desc64); 1737 } else { 1738 desc = (void **)&ring->desc32; 1739 descsize = sizeof (struct nfe_desc32); 1740 } 1741 1742 ring->queued = 0; 1743 ring->cur = ring->next = 0; 1744 1745 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1746 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1747 1748 if (error != 0) { 1749 aprint_error_dev(sc->sc_dev, 1750 "could not create desc DMA map\n"); 1751 ring->map = NULL; 1752 goto fail; 1753 } 1754 1755 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1756 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1757 if (error != 0) { 1758 aprint_error_dev(sc->sc_dev, 1759 "could not allocate DMA memory\n"); 1760 goto fail; 1761 } 1762 1763 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1764 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1765 if (error != 0) { 1766 aprint_error_dev(sc->sc_dev, 1767 "could not map desc DMA memory\n"); 1768 goto fail; 1769 } 1770 1771 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1772 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1773 if (error != 0) { 1774 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1775 goto fail; 1776 } 1777 1778 memset(*desc, 0, NFE_TX_RING_COUNT * descsize); 1779 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1780 1781 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1782 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1783 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1784 &ring->data[i].map); 1785 if (error != 0) { 1786 aprint_error_dev(sc->sc_dev, 1787 "could not create DMA map\n"); 1788 ring->data[i].map = NULL; 1789 goto fail; 1790 } 1791 } 1792 1793 return 0; 1794 1795 fail: nfe_free_tx_ring(sc, ring); 1796 return error; 1797 } 1798 1799 void 1800 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1801 { 1802 struct nfe_tx_data *data; 1803 int i; 1804 1805 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1806 if (sc->sc_flags & NFE_40BIT_ADDR) 1807 ring->desc64[i].flags = 0; 1808 else 1809 ring->desc32[i].flags = 0; 1810 1811 data = &ring->data[i]; 1812 1813 if (data->m != NULL) { 1814 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1815 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1816 bus_dmamap_unload(sc->sc_dmat, data->active); 1817 m_freem(data->m); 1818 data->m = NULL; 1819 } 1820 } 1821 1822 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1823 BUS_DMASYNC_PREWRITE); 1824 1825 ring->queued = 0; 1826 ring->cur = ring->next = 0; 1827 } 1828 1829 void 1830 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1831 { 1832 struct nfe_tx_data *data; 1833 void *desc; 1834 int i, descsize; 1835 1836 if (sc->sc_flags & NFE_40BIT_ADDR) { 1837 desc = ring->desc64; 1838 descsize = sizeof (struct nfe_desc64); 1839 } else { 1840 desc = ring->desc32; 1841 descsize = sizeof (struct nfe_desc32); 1842 } 1843 1844 if (desc != NULL) { 1845 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1846 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1847 bus_dmamap_unload(sc->sc_dmat, ring->map); 1848 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1849 NFE_TX_RING_COUNT * descsize); 1850 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1851 } 1852 1853 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1854 data = &ring->data[i]; 1855 1856 if (data->m != NULL) { 1857 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1858 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1859 bus_dmamap_unload(sc->sc_dmat, data->active); 1860 m_freem(data->m); 1861 } 1862 } 1863 1864 /* ..and now actually destroy the DMA mappings */ 1865 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1866 data = &ring->data[i]; 1867 if (data->map == NULL) 1868 continue; 1869 bus_dmamap_destroy(sc->sc_dmat, data->map); 1870 } 1871 } 1872 1873 void 1874 nfe_setmulti(struct nfe_softc *sc) 1875 { 1876 struct ethercom *ec = &sc->sc_ethercom; 1877 struct ifnet *ifp = &ec->ec_if; 1878 struct ether_multi *enm; 1879 struct ether_multistep step; 1880 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1881 uint32_t filter = NFE_RXFILTER_MAGIC; 1882 int i; 1883 1884 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1885 memset(addr, 0, ETHER_ADDR_LEN); 1886 memset(mask, 0, ETHER_ADDR_LEN); 1887 goto done; 1888 } 1889 1890 memcpy(addr, etherbroadcastaddr, ETHER_ADDR_LEN); 1891 memcpy(mask, etherbroadcastaddr, ETHER_ADDR_LEN); 1892 1893 ETHER_FIRST_MULTI(step, ec, enm); 1894 while (enm != NULL) { 1895 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1896 ifp->if_flags |= IFF_ALLMULTI; 1897 memset(addr, 0, ETHER_ADDR_LEN); 1898 memset(mask, 0, ETHER_ADDR_LEN); 1899 goto done; 1900 } 1901 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1902 addr[i] &= enm->enm_addrlo[i]; 1903 mask[i] &= ~enm->enm_addrlo[i]; 1904 } 1905 ETHER_NEXT_MULTI(step, enm); 1906 } 1907 for (i = 0; i < ETHER_ADDR_LEN; i++) 1908 mask[i] |= addr[i]; 1909 1910 done: 1911 addr[0] |= 0x01; /* make sure multicast bit is set */ 1912 1913 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1914 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1915 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1916 addr[5] << 8 | addr[4]); 1917 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1918 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1919 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1920 mask[5] << 8 | mask[4]); 1921 1922 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1923 NFE_WRITE(sc, NFE_RXFILTER, filter); 1924 } 1925 1926 void 1927 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1928 { 1929 uint32_t tmp; 1930 1931 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 1932 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1933 addr[0] = (tmp & 0xff); 1934 addr[1] = (tmp >> 8) & 0xff; 1935 addr[2] = (tmp >> 16) & 0xff; 1936 addr[3] = (tmp >> 24) & 0xff; 1937 1938 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1939 addr[4] = (tmp & 0xff); 1940 addr[5] = (tmp >> 8) & 0xff; 1941 1942 } else { 1943 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1944 addr[0] = (tmp >> 8) & 0xff; 1945 addr[1] = (tmp & 0xff); 1946 1947 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1948 addr[2] = (tmp >> 24) & 0xff; 1949 addr[3] = (tmp >> 16) & 0xff; 1950 addr[4] = (tmp >> 8) & 0xff; 1951 addr[5] = (tmp & 0xff); 1952 } 1953 } 1954 1955 void 1956 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1957 { 1958 NFE_WRITE(sc, NFE_MACADDR_LO, 1959 addr[5] << 8 | addr[4]); 1960 NFE_WRITE(sc, NFE_MACADDR_HI, 1961 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1962 } 1963 1964 void 1965 nfe_tick(void *arg) 1966 { 1967 struct nfe_softc *sc = arg; 1968 int s; 1969 1970 s = splnet(); 1971 mii_tick(&sc->sc_mii); 1972 splx(s); 1973 1974 callout_schedule(&sc->sc_tick_ch, hz); 1975 } 1976 1977 void 1978 nfe_poweron(device_t self) 1979 { 1980 struct nfe_softc *sc = device_private(self); 1981 1982 if ((sc->sc_flags & NFE_PWR_MGMT) != 0) { 1983 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 1984 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 1985 DELAY(100); 1986 NFE_WRITE(sc, NFE_MAC_RESET, 0); 1987 DELAY(100); 1988 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 1989 NFE_WRITE(sc, NFE_PWR2_CTL, 1990 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_WAKEUP_MASK); 1991 } 1992 } 1993 1994 bool 1995 nfe_resume(device_t dv, const pmf_qual_t *qual) 1996 { 1997 nfe_poweron(dv); 1998 1999 return true; 2000 } 2001
Indexes created Tue Sep 30 07:10:03 GMT 2025