if_nfe.c revision 1.62
1 /* $NetBSD: if_nfe.c,v 1.62 2016/12/08 01:12:01 ozaki-r Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.77 2008/02/05 16:52:50 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006, 2007 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.62 2016/12/08 01:12:01 ozaki-r Exp $"); 25 26 #include "opt_inet.h" 27 #include "vlan.h" 28 29 #include <sys/param.h> 30 #include <sys/endian.h> 31 #include <sys/systm.h> 32 #include <sys/types.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/mutex.h> 36 #include <sys/queue.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/callout.h> 40 #include <sys/socket.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #include <net/bpf.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_nfereg.h> 72 #include <dev/pci/if_nfevar.h> 73 74 static int nfe_ifflags_cb(struct ethercom *); 75 76 int nfe_match(device_t, cfdata_t, void *); 77 void nfe_attach(device_t, device_t, void *); 78 int nfe_detach(device_t, int); 79 void nfe_power(int, void *); 80 void nfe_miibus_statchg(struct ifnet *); 81 int nfe_miibus_readreg(device_t, int, int); 82 void nfe_miibus_writereg(device_t, int, int, int); 83 int nfe_intr(void *); 84 int nfe_ioctl(struct ifnet *, u_long, void *); 85 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 86 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 87 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 88 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 89 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 90 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 91 void nfe_rxeof(struct nfe_softc *); 92 void nfe_txeof(struct nfe_softc *); 93 int nfe_encap(struct nfe_softc *, struct mbuf *); 94 void nfe_start(struct ifnet *); 95 void nfe_watchdog(struct ifnet *); 96 int nfe_init(struct ifnet *); 97 void nfe_stop(struct ifnet *, int); 98 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 99 void nfe_jfree(struct mbuf *, void *, size_t, void *); 100 int nfe_jpool_alloc(struct nfe_softc *); 101 void nfe_jpool_free(struct nfe_softc *); 102 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 105 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 108 void nfe_setmulti(struct nfe_softc *); 109 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 110 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 111 void nfe_tick(void *); 112 void nfe_poweron(device_t); 113 bool nfe_resume(device_t, const pmf_qual_t *); 114 115 CFATTACH_DECL_NEW(nfe, sizeof(struct nfe_softc), 116 nfe_match, nfe_attach, nfe_detach, NULL); 117 118 /* #define NFE_NO_JUMBO */ 119 120 #ifdef NFE_DEBUG 121 int nfedebug = 0; 122 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 123 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 124 #else 125 #define DPRINTF(x) 126 #define DPRINTFN(n,x) 127 #endif 128 129 /* deal with naming differences */ 130 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 134 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 135 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 136 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 137 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 140 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 141 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 142 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 145 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 146 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 147 148 #ifdef _LP64 149 #define __LP64__ 1 150 #endif 151 152 const struct nfe_product { 153 pci_vendor_id_t vendor; 154 pci_product_id_t product; 155 } nfe_devices[] = { 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 183 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 184 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 185 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 186 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 }, 187 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1 }, 188 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2 }, 189 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3 }, 190 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4 }, 191 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1 }, 192 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2 }, 193 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3 }, 194 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4 } 195 }; 196 197 int 198 nfe_match(device_t dev, cfdata_t match, void *aux) 199 { 200 struct pci_attach_args *pa = aux; 201 const struct nfe_product *np; 202 int i; 203 204 for (i = 0; i < __arraycount(nfe_devices); i++) { 205 np = &nfe_devices[i]; 206 if (PCI_VENDOR(pa->pa_id) == np->vendor && 207 PCI_PRODUCT(pa->pa_id) == np->product) 208 return 1; 209 } 210 return 0; 211 } 212 213 void 214 nfe_attach(device_t parent, device_t self, void *aux) 215 { 216 struct nfe_softc *sc = device_private(self); 217 struct pci_attach_args *pa = aux; 218 pci_chipset_tag_t pc = pa->pa_pc; 219 pci_intr_handle_t ih; 220 const char *intrstr; 221 struct ifnet *ifp; 222 pcireg_t memtype, csr; 223 int mii_flags = 0; 224 char intrbuf[PCI_INTRSTR_LEN]; 225 226 sc->sc_dev = self; 227 sc->sc_pc = pa->pa_pc; 228 pci_aprint_devinfo(pa, NULL); 229 230 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 231 switch (memtype) { 232 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 233 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 234 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 235 &sc->sc_memh, NULL, &sc->sc_mems) == 0) 236 break; 237 /* FALLTHROUGH */ 238 default: 239 aprint_error_dev(self, "could not map mem space\n"); 240 return; 241 } 242 243 if (pci_intr_map(pa, &ih) != 0) { 244 aprint_error_dev(self, "could not map interrupt\n"); 245 goto fail; 246 } 247 248 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 249 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 250 if (sc->sc_ih == NULL) { 251 aprint_error_dev(self, "could not establish interrupt"); 252 if (intrstr != NULL) 253 aprint_error(" at %s", intrstr); 254 aprint_error("\n"); 255 goto fail; 256 } 257 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 258 259 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 260 csr |= PCI_COMMAND_MASTER_ENABLE; 261 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 262 263 sc->sc_flags = 0; 264 265 switch (PCI_PRODUCT(pa->pa_id)) { 266 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 267 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 268 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 269 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 270 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 271 break; 272 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 273 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 274 sc->sc_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT; 275 break; 276 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 277 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 278 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 279 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 280 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 281 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 282 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 283 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 284 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 285 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 286 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 287 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 288 sc->sc_flags |= NFE_40BIT_ADDR | NFE_CORRECT_MACADDR | 289 NFE_PWR_MGMT; 290 break; 291 case PCI_PRODUCT_NVIDIA_MCP77_LAN1: 292 case PCI_PRODUCT_NVIDIA_MCP77_LAN2: 293 case PCI_PRODUCT_NVIDIA_MCP77_LAN3: 294 case PCI_PRODUCT_NVIDIA_MCP77_LAN4: 295 sc->sc_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | 296 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 297 break; 298 case PCI_PRODUCT_NVIDIA_MCP79_LAN1: 299 case PCI_PRODUCT_NVIDIA_MCP79_LAN2: 300 case PCI_PRODUCT_NVIDIA_MCP79_LAN3: 301 case PCI_PRODUCT_NVIDIA_MCP79_LAN4: 302 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 303 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 304 break; 305 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 306 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 307 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 308 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 309 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 310 break; 311 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 312 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 313 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 314 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 315 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 316 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 317 mii_flags = MIIF_DOPAUSE; 318 break; 319 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 320 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 321 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 322 NFE_HW_VLAN | NFE_PWR_MGMT; 323 break; 324 } 325 326 if (pci_dma64_available(pa) && (sc->sc_flags & NFE_40BIT_ADDR) != 0) 327 sc->sc_dmat = pa->pa_dmat64; 328 else 329 sc->sc_dmat = pa->pa_dmat; 330 331 nfe_poweron(self); 332 333 #ifndef NFE_NO_JUMBO 334 /* enable jumbo frames for adapters that support it */ 335 if (sc->sc_flags & NFE_JUMBO_SUP) 336 sc->sc_flags |= NFE_USE_JUMBO; 337 #endif 338 339 /* Check for reversed ethernet address */ 340 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 341 sc->sc_flags |= NFE_CORRECT_MACADDR; 342 343 nfe_get_macaddr(sc, sc->sc_enaddr); 344 aprint_normal_dev(self, "Ethernet address %s\n", 345 ether_sprintf(sc->sc_enaddr)); 346 347 /* 348 * Allocate Tx and Rx rings. 349 */ 350 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 351 aprint_error_dev(self, "could not allocate Tx ring\n"); 352 goto fail; 353 } 354 355 mutex_init(&sc->rxq.mtx, MUTEX_DEFAULT, IPL_NET); 356 357 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 358 aprint_error_dev(self, "could not allocate Rx ring\n"); 359 nfe_free_tx_ring(sc, &sc->txq); 360 goto fail; 361 } 362 363 ifp = &sc->sc_ethercom.ec_if; 364 ifp->if_softc = sc; 365 ifp->if_mtu = ETHERMTU; 366 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 367 ifp->if_ioctl = nfe_ioctl; 368 ifp->if_start = nfe_start; 369 ifp->if_stop = nfe_stop; 370 ifp->if_watchdog = nfe_watchdog; 371 ifp->if_init = nfe_init; 372 ifp->if_baudrate = IF_Gbps(1); 373 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 374 IFQ_SET_READY(&ifp->if_snd); 375 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 376 377 if (sc->sc_flags & NFE_USE_JUMBO) 378 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 379 380 #if NVLAN > 0 381 if (sc->sc_flags & NFE_HW_VLAN) 382 sc->sc_ethercom.ec_capabilities |= 383 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 384 #endif 385 if (sc->sc_flags & NFE_HW_CSUM) { 386 ifp->if_capabilities |= 387 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 388 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 389 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 390 } 391 392 sc->sc_mii.mii_ifp = ifp; 393 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 394 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 395 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 396 397 sc->sc_ethercom.ec_mii = &sc->sc_mii; 398 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 399 ether_mediastatus); 400 401 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 0, mii_flags); 402 403 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 404 aprint_error_dev(self, "no PHY found!\n"); 405 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 406 0, NULL); 407 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 408 } else 409 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 410 411 if_attach(ifp); 412 if_deferred_start_init(ifp, NULL); 413 ether_ifattach(ifp, sc->sc_enaddr); 414 ether_set_ifflags_cb(&sc->sc_ethercom, nfe_ifflags_cb); 415 416 callout_init(&sc->sc_tick_ch, 0); 417 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 418 419 if (pmf_device_register(self, NULL, nfe_resume)) 420 pmf_class_network_register(self, ifp); 421 else 422 aprint_error_dev(self, "couldn't establish power handler\n"); 423 424 return; 425 426 fail: 427 if (sc->sc_ih != NULL) { 428 pci_intr_disestablish(pc, sc->sc_ih); 429 sc->sc_ih = NULL; 430 } 431 if (sc->sc_mems != 0) { 432 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 433 sc->sc_mems = 0; 434 } 435 } 436 437 int 438 nfe_detach(device_t self, int flags) 439 { 440 struct nfe_softc *sc = device_private(self); 441 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 442 int s; 443 444 s = splnet(); 445 446 nfe_stop(ifp, 1); 447 448 pmf_device_deregister(self); 449 callout_destroy(&sc->sc_tick_ch); 450 ether_ifdetach(ifp); 451 if_detach(ifp); 452 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 453 454 nfe_free_rx_ring(sc, &sc->rxq); 455 mutex_destroy(&sc->rxq.mtx); 456 nfe_free_tx_ring(sc, &sc->txq); 457 458 if (sc->sc_ih != NULL) { 459 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 460 sc->sc_ih = NULL; 461 } 462 463 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 464 nfe_set_macaddr(sc, sc->sc_enaddr); 465 } else { 466 NFE_WRITE(sc, NFE_MACADDR_LO, 467 sc->sc_enaddr[0] << 8 | sc->sc_enaddr[1]); 468 NFE_WRITE(sc, NFE_MACADDR_HI, 469 sc->sc_enaddr[2] << 24 | sc->sc_enaddr[3] << 16 | 470 sc->sc_enaddr[4] << 8 | sc->sc_enaddr[5]); 471 } 472 473 if (sc->sc_mems != 0) { 474 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 475 sc->sc_mems = 0; 476 } 477 478 splx(s); 479 480 return 0; 481 } 482 483 void 484 nfe_miibus_statchg(struct ifnet *ifp) 485 { 486 struct nfe_softc *sc = ifp->if_softc; 487 struct mii_data *mii = &sc->sc_mii; 488 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 489 490 phy = NFE_READ(sc, NFE_PHY_IFACE); 491 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 492 493 seed = NFE_READ(sc, NFE_RNDSEED); 494 seed &= ~NFE_SEED_MASK; 495 496 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 497 phy |= NFE_PHY_HDX; /* half-duplex */ 498 misc |= NFE_MISC1_HDX; 499 } 500 501 switch (IFM_SUBTYPE(mii->mii_media_active)) { 502 case IFM_1000_T: /* full-duplex only */ 503 link |= NFE_MEDIA_1000T; 504 seed |= NFE_SEED_1000T; 505 phy |= NFE_PHY_1000T; 506 break; 507 case IFM_100_TX: 508 link |= NFE_MEDIA_100TX; 509 seed |= NFE_SEED_100TX; 510 phy |= NFE_PHY_100TX; 511 break; 512 case IFM_10_T: 513 link |= NFE_MEDIA_10T; 514 seed |= NFE_SEED_10T; 515 break; 516 } 517 518 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 519 520 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 521 NFE_WRITE(sc, NFE_MISC1, misc); 522 NFE_WRITE(sc, NFE_LINKSPEED, link); 523 } 524 525 int 526 nfe_miibus_readreg(device_t dev, int phy, int reg) 527 { 528 struct nfe_softc *sc = device_private(dev); 529 uint32_t val; 530 int ntries; 531 532 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 533 534 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 535 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 536 DELAY(100); 537 } 538 539 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 540 541 for (ntries = 0; ntries < 1000; ntries++) { 542 DELAY(100); 543 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 544 break; 545 } 546 if (ntries == 1000) { 547 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 548 device_xname(sc->sc_dev))); 549 return 0; 550 } 551 552 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 553 DPRINTFN(2, ("%s: could not read PHY\n", 554 device_xname(sc->sc_dev))); 555 return 0; 556 } 557 558 val = NFE_READ(sc, NFE_PHY_DATA); 559 if (val != 0xffffffff && val != 0) 560 sc->mii_phyaddr = phy; 561 562 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 563 device_xname(sc->sc_dev), phy, reg, val)); 564 565 return val; 566 } 567 568 void 569 nfe_miibus_writereg(device_t dev, int phy, int reg, int val) 570 { 571 struct nfe_softc *sc = device_private(dev); 572 uint32_t ctl; 573 int ntries; 574 575 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 576 577 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 578 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 579 DELAY(100); 580 } 581 582 NFE_WRITE(sc, NFE_PHY_DATA, val); 583 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 584 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 585 586 for (ntries = 0; ntries < 1000; ntries++) { 587 DELAY(100); 588 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 589 break; 590 } 591 #ifdef NFE_DEBUG 592 if (nfedebug >= 2 && ntries == 1000) 593 printf("could not write to PHY\n"); 594 #endif 595 } 596 597 int 598 nfe_intr(void *arg) 599 { 600 struct nfe_softc *sc = arg; 601 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 602 uint32_t r; 603 int handled; 604 605 if ((ifp->if_flags & IFF_UP) == 0) 606 return 0; 607 608 handled = 0; 609 610 for (;;) { 611 r = NFE_READ(sc, NFE_IRQ_STATUS); 612 if ((r & NFE_IRQ_WANTED) == 0) 613 break; 614 615 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 616 handled = 1; 617 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 618 619 if ((r & (NFE_IRQ_RXERR|NFE_IRQ_RX_NOBUF|NFE_IRQ_RX)) != 0) { 620 /* check Rx ring */ 621 nfe_rxeof(sc); 622 } 623 if ((r & (NFE_IRQ_TXERR|NFE_IRQ_TXERR2|NFE_IRQ_TX_DONE)) != 0) { 624 /* check Tx ring */ 625 nfe_txeof(sc); 626 } 627 if ((r & NFE_IRQ_LINK) != 0) { 628 NFE_READ(sc, NFE_PHY_STATUS); 629 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 630 DPRINTF(("%s: link state changed\n", 631 device_xname(sc->sc_dev))); 632 } 633 } 634 635 if (handled) 636 if_schedule_deferred_start(ifp); 637 638 return handled; 639 } 640 641 static int 642 nfe_ifflags_cb(struct ethercom *ec) 643 { 644 struct ifnet *ifp = &ec->ec_if; 645 struct nfe_softc *sc = ifp->if_softc; 646 int change = ifp->if_flags ^ sc->sc_if_flags; 647 648 /* 649 * If only the PROMISC flag changes, then 650 * don't do a full re-init of the chip, just update 651 * the Rx filter. 652 */ 653 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 654 return ENETRESET; 655 else if ((change & IFF_PROMISC) != 0) 656 nfe_setmulti(sc); 657 658 return 0; 659 } 660 661 int 662 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 663 { 664 struct nfe_softc *sc = ifp->if_softc; 665 struct ifaddr *ifa = (struct ifaddr *)data; 666 int s, error = 0; 667 668 s = splnet(); 669 670 switch (cmd) { 671 case SIOCINITIFADDR: 672 ifp->if_flags |= IFF_UP; 673 nfe_init(ifp); 674 switch (ifa->ifa_addr->sa_family) { 675 #ifdef INET 676 case AF_INET: 677 arp_ifinit(ifp, ifa); 678 break; 679 #endif 680 default: 681 break; 682 } 683 break; 684 default: 685 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 686 break; 687 688 error = 0; 689 690 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 691 ; 692 else if (ifp->if_flags & IFF_RUNNING) 693 nfe_setmulti(sc); 694 break; 695 } 696 sc->sc_if_flags = ifp->if_flags; 697 698 splx(s); 699 700 return error; 701 } 702 703 void 704 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 705 { 706 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 707 (char *)desc32 - (char *)sc->txq.desc32, 708 sizeof (struct nfe_desc32), ops); 709 } 710 711 void 712 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 713 { 714 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 715 (char *)desc64 - (char *)sc->txq.desc64, 716 sizeof (struct nfe_desc64), ops); 717 } 718 719 void 720 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 721 { 722 if (end > start) { 723 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 724 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 725 (char *)&sc->txq.desc32[end] - 726 (char *)&sc->txq.desc32[start], ops); 727 return; 728 } 729 /* sync from 'start' to end of ring */ 730 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 731 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 732 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 733 (char *)&sc->txq.desc32[start], ops); 734 735 /* sync from start of ring to 'end' */ 736 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 737 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 738 } 739 740 void 741 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 742 { 743 if (end > start) { 744 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 745 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 746 (char *)&sc->txq.desc64[end] - 747 (char *)&sc->txq.desc64[start], ops); 748 return; 749 } 750 /* sync from 'start' to end of ring */ 751 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 752 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 753 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 754 (char *)&sc->txq.desc64[start], ops); 755 756 /* sync from start of ring to 'end' */ 757 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 758 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 759 } 760 761 void 762 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 763 { 764 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 765 (char *)desc32 - (char *)sc->rxq.desc32, 766 sizeof (struct nfe_desc32), ops); 767 } 768 769 void 770 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 771 { 772 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 773 (char *)desc64 - (char *)sc->rxq.desc64, 774 sizeof (struct nfe_desc64), ops); 775 } 776 777 void 778 nfe_rxeof(struct nfe_softc *sc) 779 { 780 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 781 struct nfe_desc32 *desc32; 782 struct nfe_desc64 *desc64; 783 struct nfe_rx_data *data; 784 struct nfe_jbuf *jbuf; 785 struct mbuf *m, *mnew; 786 bus_addr_t physaddr; 787 uint16_t flags; 788 int error, len, i; 789 790 desc32 = NULL; 791 desc64 = NULL; 792 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 793 data = &sc->rxq.data[i]; 794 795 if (sc->sc_flags & NFE_40BIT_ADDR) { 796 desc64 = &sc->rxq.desc64[i]; 797 nfe_rxdesc64_sync(sc, desc64, 798 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 799 800 flags = le16toh(desc64->flags); 801 len = le16toh(desc64->length) & 0x3fff; 802 } else { 803 desc32 = &sc->rxq.desc32[i]; 804 nfe_rxdesc32_sync(sc, desc32, 805 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 806 807 flags = le16toh(desc32->flags); 808 len = le16toh(desc32->length) & 0x3fff; 809 } 810 811 if ((flags & NFE_RX_READY) != 0) 812 break; 813 814 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 815 if ((flags & NFE_RX_VALID_V1) == 0) 816 goto skip; 817 818 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 819 flags &= ~NFE_RX_ERROR; 820 len--; /* fix buffer length */ 821 } 822 } else { 823 if ((flags & NFE_RX_VALID_V2) == 0) 824 goto skip; 825 826 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 827 flags &= ~NFE_RX_ERROR; 828 len--; /* fix buffer length */ 829 } 830 } 831 832 if (flags & NFE_RX_ERROR) { 833 ifp->if_ierrors++; 834 goto skip; 835 } 836 837 /* 838 * Try to allocate a new mbuf for this ring element and load 839 * it before processing the current mbuf. If the ring element 840 * cannot be loaded, drop the received packet and reuse the 841 * old mbuf. In the unlikely case that the old mbuf can't be 842 * reloaded either, explicitly panic. 843 */ 844 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 845 if (mnew == NULL) { 846 ifp->if_ierrors++; 847 goto skip; 848 } 849 850 if (sc->sc_flags & NFE_USE_JUMBO) { 851 physaddr = 852 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 853 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 854 if (len > MCLBYTES) { 855 m_freem(mnew); 856 ifp->if_ierrors++; 857 goto skip1; 858 } 859 MCLGET(mnew, M_DONTWAIT); 860 if ((mnew->m_flags & M_EXT) == 0) { 861 m_freem(mnew); 862 ifp->if_ierrors++; 863 goto skip1; 864 } 865 866 (void)memcpy(mtod(mnew, void *), 867 mtod(data->m, const void *), len); 868 m = mnew; 869 goto mbufcopied; 870 } else { 871 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 872 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 873 mtod(data->m, char *) - (char *)sc->rxq.jpool, 874 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 875 876 physaddr = jbuf->physaddr; 877 } 878 } else { 879 MCLGET(mnew, M_DONTWAIT); 880 if ((mnew->m_flags & M_EXT) == 0) { 881 m_freem(mnew); 882 ifp->if_ierrors++; 883 goto skip; 884 } 885 886 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 887 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 888 bus_dmamap_unload(sc->sc_dmat, data->map); 889 890 error = bus_dmamap_load(sc->sc_dmat, data->map, 891 mtod(mnew, void *), MCLBYTES, NULL, 892 BUS_DMA_READ | BUS_DMA_NOWAIT); 893 if (error != 0) { 894 m_freem(mnew); 895 896 /* try to reload the old mbuf */ 897 error = bus_dmamap_load(sc->sc_dmat, data->map, 898 mtod(data->m, void *), MCLBYTES, NULL, 899 BUS_DMA_READ | BUS_DMA_NOWAIT); 900 if (error != 0) { 901 /* very unlikely that it will fail.. */ 902 panic("%s: could not load old rx mbuf", 903 device_xname(sc->sc_dev)); 904 } 905 ifp->if_ierrors++; 906 goto skip; 907 } 908 physaddr = data->map->dm_segs[0].ds_addr; 909 } 910 911 /* 912 * New mbuf successfully loaded, update Rx ring and continue 913 * processing. 914 */ 915 m = data->m; 916 data->m = mnew; 917 918 mbufcopied: 919 /* finalize mbuf */ 920 m->m_pkthdr.len = m->m_len = len; 921 m_set_rcvif(m, ifp); 922 923 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 924 /* 925 * XXX 926 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 927 */ 928 if (flags & NFE_RX_IP_CSUMOK) { 929 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 930 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 931 device_xname(sc->sc_dev))); 932 } 933 /* 934 * XXX 935 * no way to check M_CSUM_TCP_UDP_BAD or 936 * other protocols? 937 */ 938 if (flags & NFE_RX_UDP_CSUMOK) { 939 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 940 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 941 device_xname(sc->sc_dev))); 942 } else if (flags & NFE_RX_TCP_CSUMOK) { 943 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 944 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 945 device_xname(sc->sc_dev))); 946 } 947 } 948 bpf_mtap(ifp, m); 949 ifp->if_ipackets++; 950 if_percpuq_enqueue(ifp->if_percpuq, m); 951 952 skip1: 953 /* update mapping address in h/w descriptor */ 954 if (sc->sc_flags & NFE_40BIT_ADDR) { 955 #if defined(__LP64__) 956 desc64->physaddr[0] = htole32(physaddr >> 32); 957 #endif 958 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 959 } else { 960 desc32->physaddr = htole32(physaddr); 961 } 962 963 skip: 964 if (sc->sc_flags & NFE_40BIT_ADDR) { 965 desc64->length = htole16(sc->rxq.bufsz); 966 desc64->flags = htole16(NFE_RX_READY); 967 968 nfe_rxdesc64_sync(sc, desc64, 969 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 970 } else { 971 desc32->length = htole16(sc->rxq.bufsz); 972 desc32->flags = htole16(NFE_RX_READY); 973 974 nfe_rxdesc32_sync(sc, desc32, 975 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 976 } 977 } 978 /* update current RX pointer */ 979 sc->rxq.cur = i; 980 } 981 982 void 983 nfe_txeof(struct nfe_softc *sc) 984 { 985 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 986 struct nfe_desc32 *desc32; 987 struct nfe_desc64 *desc64; 988 struct nfe_tx_data *data = NULL; 989 int i; 990 uint16_t flags; 991 char buf[128]; 992 993 for (i = sc->txq.next; 994 sc->txq.queued > 0; 995 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 996 if (sc->sc_flags & NFE_40BIT_ADDR) { 997 desc64 = &sc->txq.desc64[i]; 998 nfe_txdesc64_sync(sc, desc64, 999 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1000 1001 flags = le16toh(desc64->flags); 1002 } else { 1003 desc32 = &sc->txq.desc32[i]; 1004 nfe_txdesc32_sync(sc, desc32, 1005 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1006 1007 flags = le16toh(desc32->flags); 1008 } 1009 1010 if ((flags & NFE_TX_VALID) != 0) 1011 break; 1012 1013 data = &sc->txq.data[i]; 1014 1015 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 1016 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 1017 data->m == NULL) 1018 continue; 1019 1020 if ((flags & NFE_TX_ERROR_V1) != 0) { 1021 snprintb(buf, sizeof(buf), NFE_V1_TXERR, flags); 1022 aprint_error_dev(sc->sc_dev, "tx v1 error %s\n", 1023 buf); 1024 ifp->if_oerrors++; 1025 } else 1026 ifp->if_opackets++; 1027 } else { 1028 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 1029 data->m == NULL) 1030 continue; 1031 1032 if ((flags & NFE_TX_ERROR_V2) != 0) { 1033 snprintb(buf, sizeof(buf), NFE_V2_TXERR, flags); 1034 aprint_error_dev(sc->sc_dev, "tx v2 error %s\n", 1035 buf); 1036 ifp->if_oerrors++; 1037 } else 1038 ifp->if_opackets++; 1039 } 1040 1041 if (data->m == NULL) { /* should not get there */ 1042 aprint_error_dev(sc->sc_dev, 1043 "last fragment bit w/o associated mbuf!\n"); 1044 continue; 1045 } 1046 1047 /* last fragment of the mbuf chain transmitted */ 1048 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1049 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1050 bus_dmamap_unload(sc->sc_dmat, data->active); 1051 m_freem(data->m); 1052 data->m = NULL; 1053 } 1054 1055 sc->txq.next = i; 1056 1057 if (sc->txq.queued < NFE_TX_RING_COUNT) { 1058 /* at least one slot freed */ 1059 ifp->if_flags &= ~IFF_OACTIVE; 1060 } 1061 1062 if (sc->txq.queued == 0) { 1063 /* all queued packets are sent */ 1064 ifp->if_timer = 0; 1065 } 1066 } 1067 1068 int 1069 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 1070 { 1071 struct nfe_desc32 *desc32; 1072 struct nfe_desc64 *desc64; 1073 struct nfe_tx_data *data; 1074 bus_dmamap_t map; 1075 uint16_t flags, csumflags; 1076 #if NVLAN > 0 1077 struct m_tag *mtag; 1078 uint32_t vtag = 0; 1079 #endif 1080 int error, i, first; 1081 1082 desc32 = NULL; 1083 desc64 = NULL; 1084 data = NULL; 1085 1086 flags = 0; 1087 csumflags = 0; 1088 first = sc->txq.cur; 1089 1090 map = sc->txq.data[first].map; 1091 1092 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1093 if (error != 0) { 1094 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1095 error); 1096 return error; 1097 } 1098 1099 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1100 bus_dmamap_unload(sc->sc_dmat, map); 1101 return ENOBUFS; 1102 } 1103 1104 #if NVLAN > 0 1105 /* setup h/w VLAN tagging */ 1106 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1107 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1108 #endif 1109 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1110 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1111 csumflags |= NFE_TX_IP_CSUM; 1112 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1113 csumflags |= NFE_TX_TCP_UDP_CSUM; 1114 } 1115 1116 for (i = 0; i < map->dm_nsegs; i++) { 1117 data = &sc->txq.data[sc->txq.cur]; 1118 1119 if (sc->sc_flags & NFE_40BIT_ADDR) { 1120 desc64 = &sc->txq.desc64[sc->txq.cur]; 1121 #if defined(__LP64__) 1122 desc64->physaddr[0] = 1123 htole32(map->dm_segs[i].ds_addr >> 32); 1124 #endif 1125 desc64->physaddr[1] = 1126 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1127 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1128 desc64->flags = htole16(flags); 1129 desc64->vtag = 0; 1130 } else { 1131 desc32 = &sc->txq.desc32[sc->txq.cur]; 1132 1133 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1134 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1135 desc32->flags = htole16(flags); 1136 } 1137 1138 /* 1139 * Setting of the valid bit in the first descriptor is 1140 * deferred until the whole chain is fully setup. 1141 */ 1142 flags |= NFE_TX_VALID; 1143 1144 sc->txq.queued++; 1145 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1146 } 1147 1148 /* the whole mbuf chain has been setup */ 1149 if (sc->sc_flags & NFE_40BIT_ADDR) { 1150 /* fix last descriptor */ 1151 flags |= NFE_TX_LASTFRAG_V2; 1152 desc64->flags = htole16(flags); 1153 1154 /* Checksum flags and vtag belong to the first fragment only. */ 1155 #if NVLAN > 0 1156 sc->txq.desc64[first].vtag = htole32(vtag); 1157 #endif 1158 sc->txq.desc64[first].flags |= htole16(csumflags); 1159 1160 /* finally, set the valid bit in the first descriptor */ 1161 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1162 } else { 1163 /* fix last descriptor */ 1164 if (sc->sc_flags & NFE_JUMBO_SUP) 1165 flags |= NFE_TX_LASTFRAG_V2; 1166 else 1167 flags |= NFE_TX_LASTFRAG_V1; 1168 desc32->flags = htole16(flags); 1169 1170 /* Checksum flags belong to the first fragment only. */ 1171 sc->txq.desc32[first].flags |= htole16(csumflags); 1172 1173 /* finally, set the valid bit in the first descriptor */ 1174 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1175 } 1176 1177 data->m = m0; 1178 data->active = map; 1179 1180 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1181 BUS_DMASYNC_PREWRITE); 1182 1183 return 0; 1184 } 1185 1186 void 1187 nfe_start(struct ifnet *ifp) 1188 { 1189 struct nfe_softc *sc = ifp->if_softc; 1190 int old = sc->txq.queued; 1191 struct mbuf *m0; 1192 1193 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1194 return; 1195 1196 for (;;) { 1197 IFQ_POLL(&ifp->if_snd, m0); 1198 if (m0 == NULL) 1199 break; 1200 1201 if (nfe_encap(sc, m0) != 0) { 1202 ifp->if_flags |= IFF_OACTIVE; 1203 break; 1204 } 1205 1206 /* packet put in h/w queue, remove from s/w queue */ 1207 IFQ_DEQUEUE(&ifp->if_snd, m0); 1208 1209 bpf_mtap(ifp, m0); 1210 } 1211 1212 if (sc->txq.queued != old) { 1213 /* packets are queued */ 1214 if (sc->sc_flags & NFE_40BIT_ADDR) 1215 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1216 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1217 else 1218 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1219 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1220 /* kick Tx */ 1221 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1222 1223 /* 1224 * Set a timeout in case the chip goes out to lunch. 1225 */ 1226 ifp->if_timer = 5; 1227 } 1228 } 1229 1230 void 1231 nfe_watchdog(struct ifnet *ifp) 1232 { 1233 struct nfe_softc *sc = ifp->if_softc; 1234 1235 aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1236 1237 ifp->if_flags &= ~IFF_RUNNING; 1238 nfe_init(ifp); 1239 1240 ifp->if_oerrors++; 1241 } 1242 1243 int 1244 nfe_init(struct ifnet *ifp) 1245 { 1246 struct nfe_softc *sc = ifp->if_softc; 1247 uint32_t tmp; 1248 int rc = 0, s; 1249 1250 if (ifp->if_flags & IFF_RUNNING) 1251 return 0; 1252 1253 nfe_stop(ifp, 0); 1254 1255 NFE_WRITE(sc, NFE_TX_UNK, 0); 1256 NFE_WRITE(sc, NFE_STATUS, 0); 1257 1258 sc->rxtxctl = NFE_RXTX_BIT2; 1259 if (sc->sc_flags & NFE_40BIT_ADDR) 1260 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1261 else if (sc->sc_flags & NFE_JUMBO_SUP) 1262 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1263 if (sc->sc_flags & NFE_HW_CSUM) 1264 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1265 #if NVLAN > 0 1266 /* 1267 * Although the adapter is capable of stripping VLAN tags from received 1268 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1269 * purpose. This will be done in software by our network stack. 1270 */ 1271 if (sc->sc_flags & NFE_HW_VLAN) 1272 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1273 #endif 1274 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1275 DELAY(10); 1276 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1277 1278 #if NVLAN 1279 if (sc->sc_flags & NFE_HW_VLAN) 1280 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1281 #endif 1282 1283 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1284 1285 /* set MAC address */ 1286 nfe_set_macaddr(sc, sc->sc_enaddr); 1287 1288 /* tell MAC where rings are in memory */ 1289 #ifdef __LP64__ 1290 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1291 #endif 1292 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1293 #ifdef __LP64__ 1294 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1295 #endif 1296 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1297 1298 NFE_WRITE(sc, NFE_RING_SIZE, 1299 (NFE_RX_RING_COUNT - 1) << 16 | 1300 (NFE_TX_RING_COUNT - 1)); 1301 1302 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1303 1304 /* force MAC to wakeup */ 1305 tmp = NFE_READ(sc, NFE_PWR_STATE); 1306 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1307 DELAY(10); 1308 tmp = NFE_READ(sc, NFE_PWR_STATE); 1309 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1310 1311 s = splnet(); 1312 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1313 nfe_intr(sc); /* XXX clear IRQ status registers */ 1314 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1315 splx(s); 1316 1317 #if 1 1318 /* configure interrupts coalescing/mitigation */ 1319 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1320 #else 1321 /* no interrupt mitigation: one interrupt per packet */ 1322 NFE_WRITE(sc, NFE_IMTIMER, 970); 1323 #endif 1324 1325 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1326 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1327 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1328 1329 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1330 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1331 1332 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1333 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_ENABLE); 1334 1335 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1336 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1337 DELAY(10); 1338 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1339 1340 /* set Rx filter */ 1341 nfe_setmulti(sc); 1342 1343 if ((rc = ether_mediachange(ifp)) != 0) 1344 goto out; 1345 1346 nfe_tick(sc); 1347 1348 /* enable Rx */ 1349 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1350 1351 /* enable Tx */ 1352 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1353 1354 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1355 1356 /* enable interrupts */ 1357 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1358 1359 callout_schedule(&sc->sc_tick_ch, hz); 1360 1361 ifp->if_flags |= IFF_RUNNING; 1362 ifp->if_flags &= ~IFF_OACTIVE; 1363 1364 out: 1365 return rc; 1366 } 1367 1368 void 1369 nfe_stop(struct ifnet *ifp, int disable) 1370 { 1371 struct nfe_softc *sc = ifp->if_softc; 1372 1373 callout_stop(&sc->sc_tick_ch); 1374 1375 ifp->if_timer = 0; 1376 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1377 1378 mii_down(&sc->sc_mii); 1379 1380 /* abort Tx */ 1381 NFE_WRITE(sc, NFE_TX_CTL, 0); 1382 1383 /* disable Rx */ 1384 NFE_WRITE(sc, NFE_RX_CTL, 0); 1385 1386 /* disable interrupts */ 1387 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1388 1389 /* reset Tx and Rx rings */ 1390 nfe_reset_tx_ring(sc, &sc->txq); 1391 nfe_reset_rx_ring(sc, &sc->rxq); 1392 } 1393 1394 int 1395 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1396 { 1397 struct nfe_desc32 *desc32; 1398 struct nfe_desc64 *desc64; 1399 struct nfe_rx_data *data; 1400 struct nfe_jbuf *jbuf; 1401 void **desc; 1402 bus_addr_t physaddr; 1403 int i, nsegs, error, descsize; 1404 1405 if (sc->sc_flags & NFE_40BIT_ADDR) { 1406 desc = (void **)&ring->desc64; 1407 descsize = sizeof (struct nfe_desc64); 1408 } else { 1409 desc = (void **)&ring->desc32; 1410 descsize = sizeof (struct nfe_desc32); 1411 } 1412 1413 ring->cur = ring->next = 0; 1414 ring->bufsz = MCLBYTES; 1415 1416 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1417 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1418 if (error != 0) { 1419 aprint_error_dev(sc->sc_dev, 1420 "could not create desc DMA map\n"); 1421 ring->map = NULL; 1422 goto fail; 1423 } 1424 1425 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1426 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1427 if (error != 0) { 1428 aprint_error_dev(sc->sc_dev, 1429 "could not allocate DMA memory\n"); 1430 goto fail; 1431 } 1432 1433 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1434 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1435 if (error != 0) { 1436 aprint_error_dev(sc->sc_dev, 1437 "could not map desc DMA memory\n"); 1438 goto fail; 1439 } 1440 1441 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1442 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1443 if (error != 0) { 1444 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1445 goto fail; 1446 } 1447 1448 memset(*desc, 0, NFE_RX_RING_COUNT * descsize); 1449 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1450 1451 if (sc->sc_flags & NFE_USE_JUMBO) { 1452 ring->bufsz = NFE_JBYTES; 1453 if ((error = nfe_jpool_alloc(sc)) != 0) { 1454 aprint_error_dev(sc->sc_dev, 1455 "could not allocate jumbo frames\n"); 1456 goto fail; 1457 } 1458 } 1459 1460 /* 1461 * Pre-allocate Rx buffers and populate Rx ring. 1462 */ 1463 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1464 data = &sc->rxq.data[i]; 1465 1466 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1467 if (data->m == NULL) { 1468 aprint_error_dev(sc->sc_dev, 1469 "could not allocate rx mbuf\n"); 1470 error = ENOMEM; 1471 goto fail; 1472 } 1473 1474 if (sc->sc_flags & NFE_USE_JUMBO) { 1475 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1476 aprint_error_dev(sc->sc_dev, 1477 "could not allocate jumbo buffer\n"); 1478 goto fail; 1479 } 1480 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1481 sc); 1482 1483 physaddr = jbuf->physaddr; 1484 } else { 1485 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1486 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1487 if (error != 0) { 1488 aprint_error_dev(sc->sc_dev, 1489 "could not create DMA map\n"); 1490 data->map = NULL; 1491 goto fail; 1492 } 1493 MCLGET(data->m, M_DONTWAIT); 1494 if (!(data->m->m_flags & M_EXT)) { 1495 aprint_error_dev(sc->sc_dev, 1496 "could not allocate mbuf cluster\n"); 1497 error = ENOMEM; 1498 goto fail; 1499 } 1500 1501 error = bus_dmamap_load(sc->sc_dmat, data->map, 1502 mtod(data->m, void *), MCLBYTES, NULL, 1503 BUS_DMA_READ | BUS_DMA_NOWAIT); 1504 if (error != 0) { 1505 aprint_error_dev(sc->sc_dev, 1506 "could not load rx buf DMA map"); 1507 goto fail; 1508 } 1509 physaddr = data->map->dm_segs[0].ds_addr; 1510 } 1511 1512 if (sc->sc_flags & NFE_40BIT_ADDR) { 1513 desc64 = &sc->rxq.desc64[i]; 1514 #if defined(__LP64__) 1515 desc64->physaddr[0] = htole32(physaddr >> 32); 1516 #endif 1517 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1518 desc64->length = htole16(sc->rxq.bufsz); 1519 desc64->flags = htole16(NFE_RX_READY); 1520 } else { 1521 desc32 = &sc->rxq.desc32[i]; 1522 desc32->physaddr = htole32(physaddr); 1523 desc32->length = htole16(sc->rxq.bufsz); 1524 desc32->flags = htole16(NFE_RX_READY); 1525 } 1526 } 1527 1528 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1529 BUS_DMASYNC_PREWRITE); 1530 1531 return 0; 1532 1533 fail: nfe_free_rx_ring(sc, ring); 1534 return error; 1535 } 1536 1537 void 1538 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1539 { 1540 int i; 1541 1542 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1543 if (sc->sc_flags & NFE_40BIT_ADDR) { 1544 ring->desc64[i].length = htole16(ring->bufsz); 1545 ring->desc64[i].flags = htole16(NFE_RX_READY); 1546 } else { 1547 ring->desc32[i].length = htole16(ring->bufsz); 1548 ring->desc32[i].flags = htole16(NFE_RX_READY); 1549 } 1550 } 1551 1552 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1553 BUS_DMASYNC_PREWRITE); 1554 1555 ring->cur = ring->next = 0; 1556 } 1557 1558 void 1559 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1560 { 1561 struct nfe_rx_data *data; 1562 void *desc; 1563 int i, descsize; 1564 1565 if (sc->sc_flags & NFE_40BIT_ADDR) { 1566 desc = ring->desc64; 1567 descsize = sizeof (struct nfe_desc64); 1568 } else { 1569 desc = ring->desc32; 1570 descsize = sizeof (struct nfe_desc32); 1571 } 1572 1573 if (desc != NULL) { 1574 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1575 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1576 bus_dmamap_unload(sc->sc_dmat, ring->map); 1577 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1578 NFE_RX_RING_COUNT * descsize); 1579 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1580 } 1581 1582 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1583 data = &ring->data[i]; 1584 1585 if (data->map != NULL) { 1586 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1587 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1588 bus_dmamap_unload(sc->sc_dmat, data->map); 1589 bus_dmamap_destroy(sc->sc_dmat, data->map); 1590 } 1591 if (data->m != NULL) 1592 m_freem(data->m); 1593 } 1594 1595 nfe_jpool_free(sc); 1596 } 1597 1598 struct nfe_jbuf * 1599 nfe_jalloc(struct nfe_softc *sc, int i) 1600 { 1601 struct nfe_jbuf *jbuf; 1602 1603 mutex_enter(&sc->rxq.mtx); 1604 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1605 if (jbuf != NULL) 1606 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1607 mutex_exit(&sc->rxq.mtx); 1608 if (jbuf == NULL) 1609 return NULL; 1610 sc->rxq.jbufmap[i] = 1611 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1612 return jbuf; 1613 } 1614 1615 /* 1616 * This is called automatically by the network stack when the mbuf is freed. 1617 * Caution must be taken that the NIC might be reset by the time the mbuf is 1618 * freed. 1619 */ 1620 void 1621 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1622 { 1623 struct nfe_softc *sc = arg; 1624 struct nfe_jbuf *jbuf; 1625 int i; 1626 1627 /* find the jbuf from the base pointer */ 1628 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1629 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1630 aprint_error_dev(sc->sc_dev, 1631 "request to free a buffer (%p) not managed by us\n", buf); 1632 return; 1633 } 1634 jbuf = &sc->rxq.jbuf[i]; 1635 1636 /* ..and put it back in the free list */ 1637 mutex_enter(&sc->rxq.mtx); 1638 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1639 mutex_exit(&sc->rxq.mtx); 1640 1641 if (m != NULL) 1642 pool_cache_put(mb_cache, m); 1643 } 1644 1645 int 1646 nfe_jpool_alloc(struct nfe_softc *sc) 1647 { 1648 struct nfe_rx_ring *ring = &sc->rxq; 1649 struct nfe_jbuf *jbuf; 1650 bus_addr_t physaddr; 1651 char *buf; 1652 int i, nsegs, error; 1653 1654 /* 1655 * Allocate a big chunk of DMA'able memory. 1656 */ 1657 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1658 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1659 if (error != 0) { 1660 aprint_error_dev(sc->sc_dev, 1661 "could not create jumbo DMA map\n"); 1662 ring->jmap = NULL; 1663 goto fail; 1664 } 1665 1666 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1667 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1668 if (error != 0) { 1669 aprint_error_dev(sc->sc_dev, 1670 "could not allocate jumbo DMA memory\n"); 1671 goto fail; 1672 } 1673 1674 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1675 &ring->jpool, BUS_DMA_NOWAIT); 1676 if (error != 0) { 1677 aprint_error_dev(sc->sc_dev, 1678 "could not map jumbo DMA memory\n"); 1679 goto fail; 1680 } 1681 1682 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1683 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1684 if (error != 0) { 1685 aprint_error_dev(sc->sc_dev, 1686 "could not load jumbo DMA map\n"); 1687 goto fail; 1688 } 1689 1690 /* ..and split it into 9KB chunks */ 1691 SLIST_INIT(&ring->jfreelist); 1692 1693 buf = ring->jpool; 1694 physaddr = ring->jmap->dm_segs[0].ds_addr; 1695 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1696 jbuf = &ring->jbuf[i]; 1697 1698 jbuf->buf = buf; 1699 jbuf->physaddr = physaddr; 1700 1701 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1702 1703 buf += NFE_JBYTES; 1704 physaddr += NFE_JBYTES; 1705 } 1706 1707 return 0; 1708 1709 fail: nfe_jpool_free(sc); 1710 return error; 1711 } 1712 1713 void 1714 nfe_jpool_free(struct nfe_softc *sc) 1715 { 1716 struct nfe_rx_ring *ring = &sc->rxq; 1717 1718 if (ring->jmap != NULL) { 1719 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1720 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1721 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1722 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1723 ring->jmap = NULL; 1724 } 1725 if (ring->jpool != NULL) { 1726 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1727 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1728 ring->jpool = NULL; 1729 } 1730 } 1731 1732 int 1733 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1734 { 1735 int i, nsegs, error; 1736 void **desc; 1737 int descsize; 1738 1739 if (sc->sc_flags & NFE_40BIT_ADDR) { 1740 desc = (void **)&ring->desc64; 1741 descsize = sizeof (struct nfe_desc64); 1742 } else { 1743 desc = (void **)&ring->desc32; 1744 descsize = sizeof (struct nfe_desc32); 1745 } 1746 1747 ring->queued = 0; 1748 ring->cur = ring->next = 0; 1749 1750 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1751 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1752 1753 if (error != 0) { 1754 aprint_error_dev(sc->sc_dev, 1755 "could not create desc DMA map\n"); 1756 ring->map = NULL; 1757 goto fail; 1758 } 1759 1760 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1761 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1762 if (error != 0) { 1763 aprint_error_dev(sc->sc_dev, 1764 "could not allocate DMA memory\n"); 1765 goto fail; 1766 } 1767 1768 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1769 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1770 if (error != 0) { 1771 aprint_error_dev(sc->sc_dev, 1772 "could not map desc DMA memory\n"); 1773 goto fail; 1774 } 1775 1776 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1777 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1778 if (error != 0) { 1779 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1780 goto fail; 1781 } 1782 1783 memset(*desc, 0, NFE_TX_RING_COUNT * descsize); 1784 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1785 1786 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1787 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1788 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1789 &ring->data[i].map); 1790 if (error != 0) { 1791 aprint_error_dev(sc->sc_dev, 1792 "could not create DMA map\n"); 1793 ring->data[i].map = NULL; 1794 goto fail; 1795 } 1796 } 1797 1798 return 0; 1799 1800 fail: nfe_free_tx_ring(sc, ring); 1801 return error; 1802 } 1803 1804 void 1805 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1806 { 1807 struct nfe_tx_data *data; 1808 int i; 1809 1810 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1811 if (sc->sc_flags & NFE_40BIT_ADDR) 1812 ring->desc64[i].flags = 0; 1813 else 1814 ring->desc32[i].flags = 0; 1815 1816 data = &ring->data[i]; 1817 1818 if (data->m != NULL) { 1819 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1820 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1821 bus_dmamap_unload(sc->sc_dmat, data->active); 1822 m_freem(data->m); 1823 data->m = NULL; 1824 } 1825 } 1826 1827 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1828 BUS_DMASYNC_PREWRITE); 1829 1830 ring->queued = 0; 1831 ring->cur = ring->next = 0; 1832 } 1833 1834 void 1835 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1836 { 1837 struct nfe_tx_data *data; 1838 void *desc; 1839 int i, descsize; 1840 1841 if (sc->sc_flags & NFE_40BIT_ADDR) { 1842 desc = ring->desc64; 1843 descsize = sizeof (struct nfe_desc64); 1844 } else { 1845 desc = ring->desc32; 1846 descsize = sizeof (struct nfe_desc32); 1847 } 1848 1849 if (desc != NULL) { 1850 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1851 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1852 bus_dmamap_unload(sc->sc_dmat, ring->map); 1853 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1854 NFE_TX_RING_COUNT * descsize); 1855 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1856 } 1857 1858 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1859 data = &ring->data[i]; 1860 1861 if (data->m != NULL) { 1862 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1863 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1864 bus_dmamap_unload(sc->sc_dmat, data->active); 1865 m_freem(data->m); 1866 } 1867 } 1868 1869 /* ..and now actually destroy the DMA mappings */ 1870 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1871 data = &ring->data[i]; 1872 if (data->map == NULL) 1873 continue; 1874 bus_dmamap_destroy(sc->sc_dmat, data->map); 1875 } 1876 } 1877 1878 void 1879 nfe_setmulti(struct nfe_softc *sc) 1880 { 1881 struct ethercom *ec = &sc->sc_ethercom; 1882 struct ifnet *ifp = &ec->ec_if; 1883 struct ether_multi *enm; 1884 struct ether_multistep step; 1885 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1886 uint32_t filter = NFE_RXFILTER_MAGIC; 1887 int i; 1888 1889 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1890 memset(addr, 0, ETHER_ADDR_LEN); 1891 memset(mask, 0, ETHER_ADDR_LEN); 1892 goto done; 1893 } 1894 1895 memcpy(addr, etherbroadcastaddr, ETHER_ADDR_LEN); 1896 memcpy(mask, etherbroadcastaddr, ETHER_ADDR_LEN); 1897 1898 ETHER_FIRST_MULTI(step, ec, enm); 1899 while (enm != NULL) { 1900 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1901 ifp->if_flags |= IFF_ALLMULTI; 1902 memset(addr, 0, ETHER_ADDR_LEN); 1903 memset(mask, 0, ETHER_ADDR_LEN); 1904 goto done; 1905 } 1906 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1907 addr[i] &= enm->enm_addrlo[i]; 1908 mask[i] &= ~enm->enm_addrlo[i]; 1909 } 1910 ETHER_NEXT_MULTI(step, enm); 1911 } 1912 for (i = 0; i < ETHER_ADDR_LEN; i++) 1913 mask[i] |= addr[i]; 1914 1915 done: 1916 addr[0] |= 0x01; /* make sure multicast bit is set */ 1917 1918 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1919 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1920 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1921 addr[5] << 8 | addr[4]); 1922 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1923 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1924 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1925 mask[5] << 8 | mask[4]); 1926 1927 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1928 NFE_WRITE(sc, NFE_RXFILTER, filter); 1929 } 1930 1931 void 1932 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1933 { 1934 uint32_t tmp; 1935 1936 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 1937 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1938 addr[0] = (tmp & 0xff); 1939 addr[1] = (tmp >> 8) & 0xff; 1940 addr[2] = (tmp >> 16) & 0xff; 1941 addr[3] = (tmp >> 24) & 0xff; 1942 1943 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1944 addr[4] = (tmp & 0xff); 1945 addr[5] = (tmp >> 8) & 0xff; 1946 1947 } else { 1948 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1949 addr[0] = (tmp >> 8) & 0xff; 1950 addr[1] = (tmp & 0xff); 1951 1952 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1953 addr[2] = (tmp >> 24) & 0xff; 1954 addr[3] = (tmp >> 16) & 0xff; 1955 addr[4] = (tmp >> 8) & 0xff; 1956 addr[5] = (tmp & 0xff); 1957 } 1958 } 1959 1960 void 1961 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1962 { 1963 NFE_WRITE(sc, NFE_MACADDR_LO, 1964 addr[5] << 8 | addr[4]); 1965 NFE_WRITE(sc, NFE_MACADDR_HI, 1966 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1967 } 1968 1969 void 1970 nfe_tick(void *arg) 1971 { 1972 struct nfe_softc *sc = arg; 1973 int s; 1974 1975 s = splnet(); 1976 mii_tick(&sc->sc_mii); 1977 splx(s); 1978 1979 callout_schedule(&sc->sc_tick_ch, hz); 1980 } 1981 1982 void 1983 nfe_poweron(device_t self) 1984 { 1985 struct nfe_softc *sc = device_private(self); 1986 1987 if ((sc->sc_flags & NFE_PWR_MGMT) != 0) { 1988 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 1989 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 1990 DELAY(100); 1991 NFE_WRITE(sc, NFE_MAC_RESET, 0); 1992 DELAY(100); 1993 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 1994 NFE_WRITE(sc, NFE_PWR2_CTL, 1995 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_WAKEUP_MASK); 1996 } 1997 } 1998 1999 bool 2000 nfe_resume(device_t dv, const pmf_qual_t *qual) 2001 { 2002 nfe_poweron(dv); 2003 2004 return true; 2005 } 2006
Indexes created Tue Sep 30 07:10:03 GMT 2025