if_nfe.c revision 1.65.2.2
1 /* $NetBSD: if_nfe.c,v 1.65.2.2 2020/04/08 14:08:09 martin Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.77 2008/02/05 16:52:50 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006, 2007 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.65.2.2 2020/04/08 14:08:09 martin Exp $"); 25 26 #include "opt_inet.h" 27 #include "vlan.h" 28 29 #include <sys/param.h> 30 #include <sys/endian.h> 31 #include <sys/systm.h> 32 #include <sys/types.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/mutex.h> 36 #include <sys/queue.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/callout.h> 40 #include <sys/socket.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #include <net/bpf.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_nfereg.h> 72 #include <dev/pci/if_nfevar.h> 73 74 static int nfe_ifflags_cb(struct ethercom *); 75 76 int nfe_match(device_t, cfdata_t, void *); 77 void nfe_attach(device_t, device_t, void *); 78 int nfe_detach(device_t, int); 79 void nfe_power(int, void *); 80 void nfe_miibus_statchg(struct ifnet *); 81 int nfe_miibus_readreg(device_t, int, int, uint16_t *); 82 int nfe_miibus_writereg(device_t, int, int, uint16_t); 83 int nfe_intr(void *); 84 int nfe_ioctl(struct ifnet *, u_long, void *); 85 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 86 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 87 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 88 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 89 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 90 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 91 void nfe_rxeof(struct nfe_softc *); 92 void nfe_txeof(struct nfe_softc *); 93 int nfe_encap(struct nfe_softc *, struct mbuf *); 94 void nfe_start(struct ifnet *); 95 void nfe_watchdog(struct ifnet *); 96 int nfe_init(struct ifnet *); 97 void nfe_stop(struct ifnet *, int); 98 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 99 void nfe_jfree(struct mbuf *, void *, size_t, void *); 100 int nfe_jpool_alloc(struct nfe_softc *); 101 void nfe_jpool_free(struct nfe_softc *); 102 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 105 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 108 void nfe_setmulti(struct nfe_softc *); 109 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 110 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 111 void nfe_tick(void *); 112 void nfe_poweron(device_t); 113 bool nfe_resume(device_t, const pmf_qual_t *); 114 115 CFATTACH_DECL_NEW(nfe, sizeof(struct nfe_softc), 116 nfe_match, nfe_attach, nfe_detach, NULL); 117 118 /* #define NFE_NO_JUMBO */ 119 120 #ifdef NFE_DEBUG 121 int nfedebug = 0; 122 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 123 #define DPRINTFN(n, x) do { if (nfedebug >= (n)) printf x; } while (0) 124 #else 125 #define DPRINTF(x) 126 #define DPRINTFN(n, x) 127 #endif 128 129 /* deal with naming differences */ 130 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 134 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 135 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 136 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 137 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 140 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 141 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 142 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 145 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 146 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 147 148 const struct nfe_product { 149 pci_vendor_id_t vendor; 150 pci_product_id_t product; 151 } nfe_devices[] = { 152 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 153 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 155 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 }, 183 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1 }, 184 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2 }, 185 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3 }, 186 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4 }, 187 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1 }, 188 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2 }, 189 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3 }, 190 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4 } 191 }; 192 193 int 194 nfe_match(device_t dev, cfdata_t match, void *aux) 195 { 196 struct pci_attach_args *pa = aux; 197 const struct nfe_product *np; 198 int i; 199 200 for (i = 0; i < __arraycount(nfe_devices); i++) { 201 np = &nfe_devices[i]; 202 if (PCI_VENDOR(pa->pa_id) == np->vendor && 203 PCI_PRODUCT(pa->pa_id) == np->product) 204 return 1; 205 } 206 return 0; 207 } 208 209 void 210 nfe_attach(device_t parent, device_t self, void *aux) 211 { 212 struct nfe_softc *sc = device_private(self); 213 struct pci_attach_args *pa = aux; 214 pci_chipset_tag_t pc = pa->pa_pc; 215 pci_intr_handle_t ih; 216 const char *intrstr; 217 struct ifnet *ifp; 218 struct mii_data * const mii = &sc->sc_mii; 219 pcireg_t memtype, csr; 220 int mii_flags = 0; 221 char intrbuf[PCI_INTRSTR_LEN]; 222 223 sc->sc_dev = self; 224 sc->sc_pc = pa->pa_pc; 225 pci_aprint_devinfo(pa, NULL); 226 227 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 228 switch (memtype) { 229 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 230 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 231 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 232 &sc->sc_memh, NULL, &sc->sc_mems) == 0) 233 break; 234 /* FALLTHROUGH */ 235 default: 236 aprint_error_dev(self, "could not map mem space\n"); 237 return; 238 } 239 240 if (pci_intr_map(pa, &ih) != 0) { 241 aprint_error_dev(self, "could not map interrupt\n"); 242 goto fail; 243 } 244 245 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 246 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, nfe_intr, sc, 247 device_xname(self)); 248 if (sc->sc_ih == NULL) { 249 aprint_error_dev(self, "could not establish interrupt"); 250 if (intrstr != NULL) 251 aprint_error(" at %s", intrstr); 252 aprint_error("\n"); 253 goto fail; 254 } 255 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 256 257 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 258 csr |= PCI_COMMAND_MASTER_ENABLE; 259 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 260 261 sc->sc_flags = 0; 262 263 switch (PCI_PRODUCT(pa->pa_id)) { 264 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 265 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 266 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 267 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 268 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 269 break; 270 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 271 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 272 sc->sc_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT; 273 break; 274 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 275 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 276 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 277 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 278 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 279 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 280 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 281 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 282 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 283 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 284 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 285 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 286 sc->sc_flags |= NFE_40BIT_ADDR | NFE_CORRECT_MACADDR | 287 NFE_PWR_MGMT; 288 break; 289 case PCI_PRODUCT_NVIDIA_MCP77_LAN1: 290 case PCI_PRODUCT_NVIDIA_MCP77_LAN2: 291 case PCI_PRODUCT_NVIDIA_MCP77_LAN3: 292 case PCI_PRODUCT_NVIDIA_MCP77_LAN4: 293 sc->sc_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | 294 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 295 break; 296 case PCI_PRODUCT_NVIDIA_MCP79_LAN1: 297 case PCI_PRODUCT_NVIDIA_MCP79_LAN2: 298 case PCI_PRODUCT_NVIDIA_MCP79_LAN3: 299 case PCI_PRODUCT_NVIDIA_MCP79_LAN4: 300 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 301 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 302 break; 303 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 304 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 305 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 306 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 307 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 308 break; 309 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 310 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 311 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 312 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 313 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 314 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 315 mii_flags = MIIF_DOPAUSE; 316 break; 317 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 318 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 319 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 320 NFE_HW_VLAN | NFE_PWR_MGMT; 321 break; 322 } 323 324 if (pci_dma64_available(pa) && (sc->sc_flags & NFE_40BIT_ADDR) != 0) { 325 if (bus_dmatag_subregion(pa->pa_dmat64, 326 0, 327 (bus_addr_t)(1ULL << 40), 328 &sc->sc_dmat, 329 BUS_DMA_WAITOK) != 0) { 330 aprint_error_dev(self, 331 "unable to create 40-bit DMA tag\n"); 332 sc->sc_dmat = pa->pa_dmat64; 333 } else 334 sc->sc_dmat_needs_free = true; 335 } else 336 sc->sc_dmat = pa->pa_dmat; 337 338 nfe_poweron(self); 339 340 #ifndef NFE_NO_JUMBO 341 /* enable jumbo frames for adapters that support it */ 342 if (sc->sc_flags & NFE_JUMBO_SUP) 343 sc->sc_flags |= NFE_USE_JUMBO; 344 #endif 345 346 /* Check for reversed ethernet address */ 347 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 348 sc->sc_flags |= NFE_CORRECT_MACADDR; 349 350 nfe_get_macaddr(sc, sc->sc_enaddr); 351 aprint_normal_dev(self, "Ethernet address %s\n", 352 ether_sprintf(sc->sc_enaddr)); 353 354 /* 355 * Allocate Tx and Rx rings. 356 */ 357 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 358 aprint_error_dev(self, "could not allocate Tx ring\n"); 359 goto fail; 360 } 361 362 mutex_init(&sc->rxq.mtx, MUTEX_DEFAULT, IPL_NET); 363 364 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 365 aprint_error_dev(self, "could not allocate Rx ring\n"); 366 nfe_free_tx_ring(sc, &sc->txq); 367 goto fail; 368 } 369 370 ifp = &sc->sc_ethercom.ec_if; 371 ifp->if_softc = sc; 372 ifp->if_mtu = ETHERMTU; 373 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 374 ifp->if_ioctl = nfe_ioctl; 375 ifp->if_start = nfe_start; 376 ifp->if_stop = nfe_stop; 377 ifp->if_watchdog = nfe_watchdog; 378 ifp->if_init = nfe_init; 379 ifp->if_baudrate = IF_Gbps(1); 380 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 381 IFQ_SET_READY(&ifp->if_snd); 382 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 383 384 if (sc->sc_flags & NFE_USE_JUMBO) 385 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 386 387 #if NVLAN > 0 388 if (sc->sc_flags & NFE_HW_VLAN) 389 sc->sc_ethercom.ec_capabilities |= 390 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 391 #endif 392 if (sc->sc_flags & NFE_HW_CSUM) { 393 ifp->if_capabilities |= 394 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 395 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 396 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 397 } 398 399 mii->mii_ifp = ifp; 400 mii->mii_readreg = nfe_miibus_readreg; 401 mii->mii_writereg = nfe_miibus_writereg; 402 mii->mii_statchg = nfe_miibus_statchg; 403 404 sc->sc_ethercom.ec_mii = mii; 405 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 406 407 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 0, mii_flags); 408 409 if (LIST_FIRST(&mii->mii_phys) == NULL) { 410 aprint_error_dev(self, "no PHY found!\n"); 411 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 412 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 413 } else 414 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 415 416 if_attach(ifp); 417 if_deferred_start_init(ifp, NULL); 418 ether_ifattach(ifp, sc->sc_enaddr); 419 ether_set_ifflags_cb(&sc->sc_ethercom, nfe_ifflags_cb); 420 421 callout_init(&sc->sc_tick_ch, 0); 422 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 423 424 if (pmf_device_register(self, NULL, nfe_resume)) 425 pmf_class_network_register(self, ifp); 426 else 427 aprint_error_dev(self, "couldn't establish power handler\n"); 428 429 return; 430 431 fail: 432 if (sc->sc_ih != NULL) { 433 pci_intr_disestablish(pc, sc->sc_ih); 434 sc->sc_ih = NULL; 435 } 436 if (sc->sc_mems != 0) { 437 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 438 sc->sc_mems = 0; 439 } 440 } 441 442 int 443 nfe_detach(device_t self, int flags) 444 { 445 struct nfe_softc *sc = device_private(self); 446 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 447 int s; 448 449 s = splnet(); 450 451 nfe_stop(ifp, 1); 452 453 pmf_device_deregister(self); 454 callout_destroy(&sc->sc_tick_ch); 455 ether_ifdetach(ifp); 456 if_detach(ifp); 457 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 458 ifmedia_fini(&sc->sc_mii.mii_media); 459 460 nfe_free_rx_ring(sc, &sc->rxq); 461 mutex_destroy(&sc->rxq.mtx); 462 nfe_free_tx_ring(sc, &sc->txq); 463 464 if (sc->sc_dmat_needs_free) 465 bus_dmatag_destroy(sc->sc_dmat); 466 467 if (sc->sc_ih != NULL) { 468 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 469 sc->sc_ih = NULL; 470 } 471 472 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 473 nfe_set_macaddr(sc, sc->sc_enaddr); 474 } else { 475 NFE_WRITE(sc, NFE_MACADDR_LO, 476 sc->sc_enaddr[0] << 8 | sc->sc_enaddr[1]); 477 NFE_WRITE(sc, NFE_MACADDR_HI, 478 sc->sc_enaddr[2] << 24 | sc->sc_enaddr[3] << 16 | 479 sc->sc_enaddr[4] << 8 | sc->sc_enaddr[5]); 480 } 481 482 if (sc->sc_mems != 0) { 483 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 484 sc->sc_mems = 0; 485 } 486 487 splx(s); 488 489 return 0; 490 } 491 492 void 493 nfe_miibus_statchg(struct ifnet *ifp) 494 { 495 struct nfe_softc *sc = ifp->if_softc; 496 struct mii_data *mii = &sc->sc_mii; 497 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 498 499 phy = NFE_READ(sc, NFE_PHY_IFACE); 500 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 501 502 seed = NFE_READ(sc, NFE_RNDSEED); 503 seed &= ~NFE_SEED_MASK; 504 505 if ((mii->mii_media_active & IFM_HDX) != 0) { 506 phy |= NFE_PHY_HDX; /* half-duplex */ 507 misc |= NFE_MISC1_HDX; 508 } 509 510 switch (IFM_SUBTYPE(mii->mii_media_active)) { 511 case IFM_1000_T: /* full-duplex only */ 512 link |= NFE_MEDIA_1000T; 513 seed |= NFE_SEED_1000T; 514 phy |= NFE_PHY_1000T; 515 break; 516 case IFM_100_TX: 517 link |= NFE_MEDIA_100TX; 518 seed |= NFE_SEED_100TX; 519 phy |= NFE_PHY_100TX; 520 break; 521 case IFM_10_T: 522 link |= NFE_MEDIA_10T; 523 seed |= NFE_SEED_10T; 524 break; 525 } 526 527 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 528 529 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 530 NFE_WRITE(sc, NFE_MISC1, misc); 531 NFE_WRITE(sc, NFE_LINKSPEED, link); 532 } 533 534 int 535 nfe_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 536 { 537 struct nfe_softc *sc = device_private(dev); 538 uint32_t data; 539 int ntries; 540 541 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 542 543 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 544 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 545 DELAY(100); 546 } 547 548 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 549 550 for (ntries = 0; ntries < 1000; ntries++) { 551 DELAY(100); 552 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 553 break; 554 } 555 if (ntries == 1000) { 556 DPRINTFN(2, ("%s: timeout waiting for PHY read (%d, %d)\n", 557 device_xname(sc->sc_dev), phy, reg)); 558 return ETIMEDOUT; 559 } 560 561 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 562 DPRINTFN(2, ("%s: could not read PHY (%d, %d)\n", 563 device_xname(sc->sc_dev), phy, reg)); 564 return -1; 565 } 566 567 data = NFE_READ(sc, NFE_PHY_DATA); 568 sc->mii_phyaddr = phy; 569 570 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x data 0x%x\n", 571 device_xname(sc->sc_dev), phy, reg, data)); 572 573 *val = data & 0x0000ffff; 574 return 0; 575 } 576 577 int 578 nfe_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 579 { 580 struct nfe_softc *sc = device_private(dev); 581 uint32_t ctl; 582 int ntries; 583 584 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 585 586 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 587 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 588 DELAY(100); 589 } 590 591 NFE_WRITE(sc, NFE_PHY_DATA, val); 592 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 593 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 594 595 for (ntries = 0; ntries < 1000; ntries++) { 596 DELAY(100); 597 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 598 break; 599 } 600 if (ntries == 1000) { 601 #ifdef NFE_DEBUG 602 if (nfedebug >= 2) 603 printf("timeout waiting for PHY write (%d, %d)\n", 604 phy, reg); 605 #endif 606 return ETIMEDOUT; 607 } 608 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 609 DPRINTFN(2, ("%s: could not write PHY (%d, %d)\n", 610 device_xname(sc->sc_dev), phy, reg)); 611 return -1; 612 } 613 return 0; 614 } 615 616 int 617 nfe_intr(void *arg) 618 { 619 struct nfe_softc *sc = arg; 620 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 621 uint32_t r; 622 int handled; 623 624 if ((ifp->if_flags & IFF_UP) == 0) 625 return 0; 626 627 handled = 0; 628 629 for (;;) { 630 r = NFE_READ(sc, NFE_IRQ_STATUS); 631 if ((r & NFE_IRQ_WANTED) == 0) 632 break; 633 634 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 635 handled = 1; 636 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 637 638 if ((r & (NFE_IRQ_RXERR |NFE_IRQ_RX_NOBUF |NFE_IRQ_RX)) != 0) { 639 /* check Rx ring */ 640 nfe_rxeof(sc); 641 } 642 if ((r & (NFE_IRQ_TXERR|NFE_IRQ_TXERR2|NFE_IRQ_TX_DONE)) != 0) { 643 /* check Tx ring */ 644 nfe_txeof(sc); 645 } 646 if ((r & NFE_IRQ_LINK) != 0) { 647 NFE_READ(sc, NFE_PHY_STATUS); 648 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 649 DPRINTF(("%s: link state changed\n", 650 device_xname(sc->sc_dev))); 651 } 652 } 653 654 if (handled) 655 if_schedule_deferred_start(ifp); 656 657 return handled; 658 } 659 660 static int 661 nfe_ifflags_cb(struct ethercom *ec) 662 { 663 struct ifnet *ifp = &ec->ec_if; 664 struct nfe_softc *sc = ifp->if_softc; 665 int change = ifp->if_flags ^ sc->sc_if_flags; 666 667 /* 668 * If only the PROMISC flag changes, then 669 * don't do a full re-init of the chip, just update 670 * the Rx filter. 671 */ 672 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 673 return ENETRESET; 674 else if ((change & IFF_PROMISC) != 0) 675 nfe_setmulti(sc); 676 677 return 0; 678 } 679 680 int 681 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 682 { 683 struct nfe_softc *sc = ifp->if_softc; 684 struct ifaddr *ifa = (struct ifaddr *)data; 685 int s, error = 0; 686 687 s = splnet(); 688 689 switch (cmd) { 690 case SIOCINITIFADDR: 691 ifp->if_flags |= IFF_UP; 692 nfe_init(ifp); 693 switch (ifa->ifa_addr->sa_family) { 694 #ifdef INET 695 case AF_INET: 696 arp_ifinit(ifp, ifa); 697 break; 698 #endif 699 default: 700 break; 701 } 702 break; 703 default: 704 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 705 break; 706 707 error = 0; 708 709 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 710 ; 711 else if (ifp->if_flags & IFF_RUNNING) 712 nfe_setmulti(sc); 713 break; 714 } 715 sc->sc_if_flags = ifp->if_flags; 716 717 splx(s); 718 719 return error; 720 } 721 722 void 723 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 724 { 725 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 726 (char *)desc32 - (char *)sc->txq.desc32, 727 sizeof (struct nfe_desc32), ops); 728 } 729 730 void 731 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 732 { 733 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 734 (char *)desc64 - (char *)sc->txq.desc64, 735 sizeof (struct nfe_desc64), ops); 736 } 737 738 void 739 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 740 { 741 if (end > start) { 742 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 743 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 744 (char *)&sc->txq.desc32[end] - 745 (char *)&sc->txq.desc32[start], ops); 746 return; 747 } 748 /* sync from 'start' to end of ring */ 749 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 750 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 751 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 752 (char *)&sc->txq.desc32[start], ops); 753 754 /* sync from start of ring to 'end' */ 755 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 756 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 757 } 758 759 void 760 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 761 { 762 if (end > start) { 763 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 764 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 765 (char *)&sc->txq.desc64[end] - 766 (char *)&sc->txq.desc64[start], ops); 767 return; 768 } 769 /* sync from 'start' to end of ring */ 770 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 771 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 772 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 773 (char *)&sc->txq.desc64[start], ops); 774 775 /* sync from start of ring to 'end' */ 776 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 777 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 778 } 779 780 void 781 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 782 { 783 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 784 (char *)desc32 - (char *)sc->rxq.desc32, 785 sizeof (struct nfe_desc32), ops); 786 } 787 788 void 789 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 790 { 791 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 792 (char *)desc64 - (char *)sc->rxq.desc64, 793 sizeof (struct nfe_desc64), ops); 794 } 795 796 void 797 nfe_rxeof(struct nfe_softc *sc) 798 { 799 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 800 struct nfe_desc32 *desc32; 801 struct nfe_desc64 *desc64; 802 struct nfe_rx_data *data; 803 struct nfe_jbuf *jbuf; 804 struct mbuf *m, *mnew; 805 bus_addr_t physaddr; 806 uint16_t flags; 807 int error, len, i; 808 809 desc32 = NULL; 810 desc64 = NULL; 811 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 812 data = &sc->rxq.data[i]; 813 814 if (sc->sc_flags & NFE_40BIT_ADDR) { 815 desc64 = &sc->rxq.desc64[i]; 816 nfe_rxdesc64_sync(sc, desc64, 817 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 818 819 flags = le16toh(desc64->flags); 820 len = le16toh(desc64->length) & 0x3fff; 821 } else { 822 desc32 = &sc->rxq.desc32[i]; 823 nfe_rxdesc32_sync(sc, desc32, 824 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 825 826 flags = le16toh(desc32->flags); 827 len = le16toh(desc32->length) & 0x3fff; 828 } 829 830 if ((flags & NFE_RX_READY) != 0) 831 break; 832 833 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 834 if ((flags & NFE_RX_VALID_V1) == 0) 835 goto skip; 836 837 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 838 flags &= ~NFE_RX_ERROR; 839 len--; /* fix buffer length */ 840 } 841 } else { 842 if ((flags & NFE_RX_VALID_V2) == 0) 843 goto skip; 844 845 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 846 flags &= ~NFE_RX_ERROR; 847 len--; /* fix buffer length */ 848 } 849 } 850 851 if (flags & NFE_RX_ERROR) { 852 if_statinc(ifp, if_ierrors); 853 goto skip; 854 } 855 856 /* 857 * Try to allocate a new mbuf for this ring element and load 858 * it before processing the current mbuf. If the ring element 859 * cannot be loaded, drop the received packet and reuse the 860 * old mbuf. In the unlikely case that the old mbuf can't be 861 * reloaded either, explicitly panic. 862 */ 863 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 864 if (mnew == NULL) { 865 if_statinc(ifp, if_ierrors); 866 goto skip; 867 } 868 869 if (sc->sc_flags & NFE_USE_JUMBO) { 870 physaddr = 871 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 872 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 873 if (len > MCLBYTES) { 874 m_freem(mnew); 875 if_statinc(ifp, if_ierrors); 876 goto skip1; 877 } 878 MCLGET(mnew, M_DONTWAIT); 879 if ((mnew->m_flags & M_EXT) == 0) { 880 m_freem(mnew); 881 if_statinc(ifp, if_ierrors); 882 goto skip1; 883 } 884 885 (void)memcpy(mtod(mnew, void *), 886 mtod(data->m, const void *), len); 887 m = mnew; 888 goto mbufcopied; 889 } else { 890 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 891 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 892 mtod(data->m, char *) - (char *)sc->rxq.jpool, 893 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 894 895 physaddr = jbuf->physaddr; 896 } 897 } else { 898 MCLGET(mnew, M_DONTWAIT); 899 if ((mnew->m_flags & M_EXT) == 0) { 900 m_freem(mnew); 901 if_statinc(ifp, if_ierrors); 902 goto skip; 903 } 904 905 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 906 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 907 bus_dmamap_unload(sc->sc_dmat, data->map); 908 909 error = bus_dmamap_load(sc->sc_dmat, data->map, 910 mtod(mnew, void *), MCLBYTES, NULL, 911 BUS_DMA_READ | BUS_DMA_NOWAIT); 912 if (error != 0) { 913 m_freem(mnew); 914 915 /* try to reload the old mbuf */ 916 error = bus_dmamap_load(sc->sc_dmat, data->map, 917 mtod(data->m, void *), MCLBYTES, NULL, 918 BUS_DMA_READ | BUS_DMA_NOWAIT); 919 if (error != 0) { 920 /* very unlikely that it will fail.. */ 921 panic("%s: could not load old rx mbuf", 922 device_xname(sc->sc_dev)); 923 } 924 if_statinc(ifp, if_ierrors); 925 goto skip; 926 } 927 physaddr = data->map->dm_segs[0].ds_addr; 928 } 929 930 /* 931 * New mbuf successfully loaded, update Rx ring and continue 932 * processing. 933 */ 934 m = data->m; 935 data->m = mnew; 936 937 mbufcopied: 938 /* finalize mbuf */ 939 m->m_pkthdr.len = m->m_len = len; 940 m_set_rcvif(m, ifp); 941 942 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 943 /* 944 * XXX 945 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 946 */ 947 if (flags & NFE_RX_IP_CSUMOK) { 948 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 949 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 950 device_xname(sc->sc_dev))); 951 } 952 /* 953 * XXX 954 * no way to check M_CSUM_TCP_UDP_BAD or 955 * other protocols? 956 */ 957 if (flags & NFE_RX_UDP_CSUMOK) { 958 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 959 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 960 device_xname(sc->sc_dev))); 961 } else if (flags & NFE_RX_TCP_CSUMOK) { 962 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 963 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 964 device_xname(sc->sc_dev))); 965 } 966 } 967 if_percpuq_enqueue(ifp->if_percpuq, m); 968 969 skip1: 970 /* update mapping address in h/w descriptor */ 971 if (sc->sc_flags & NFE_40BIT_ADDR) { 972 desc64->physaddr[0] = 973 htole32(((uint64_t)physaddr) >> 32); 974 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 975 } else { 976 desc32->physaddr = htole32(physaddr); 977 } 978 979 skip: 980 if (sc->sc_flags & NFE_40BIT_ADDR) { 981 desc64->length = htole16(sc->rxq.bufsz); 982 desc64->flags = htole16(NFE_RX_READY); 983 984 nfe_rxdesc64_sync(sc, desc64, 985 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 986 } else { 987 desc32->length = htole16(sc->rxq.bufsz); 988 desc32->flags = htole16(NFE_RX_READY); 989 990 nfe_rxdesc32_sync(sc, desc32, 991 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 992 } 993 } 994 /* update current RX pointer */ 995 sc->rxq.cur = i; 996 } 997 998 void 999 nfe_txeof(struct nfe_softc *sc) 1000 { 1001 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1002 struct nfe_desc32 *desc32; 1003 struct nfe_desc64 *desc64; 1004 struct nfe_tx_data *data = NULL; 1005 int i; 1006 uint16_t flags; 1007 char buf[128]; 1008 1009 for (i = sc->txq.next; 1010 sc->txq.queued > 0; 1011 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 1012 if (sc->sc_flags & NFE_40BIT_ADDR) { 1013 desc64 = &sc->txq.desc64[i]; 1014 nfe_txdesc64_sync(sc, desc64, 1015 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1016 1017 flags = le16toh(desc64->flags); 1018 } else { 1019 desc32 = &sc->txq.desc32[i]; 1020 nfe_txdesc32_sync(sc, desc32, 1021 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1022 1023 flags = le16toh(desc32->flags); 1024 } 1025 1026 if ((flags & NFE_TX_VALID) != 0) 1027 break; 1028 1029 data = &sc->txq.data[i]; 1030 1031 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 1032 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 1033 data->m == NULL) 1034 continue; 1035 1036 if ((flags & NFE_TX_ERROR_V1) != 0) { 1037 snprintb(buf, sizeof(buf), NFE_V1_TXERR, flags); 1038 aprint_error_dev(sc->sc_dev, "tx v1 error %s\n", 1039 buf); 1040 if_statinc(ifp, if_oerrors); 1041 } else 1042 if_statinc(ifp, if_opackets); 1043 } else { 1044 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 1045 data->m == NULL) 1046 continue; 1047 1048 if ((flags & NFE_TX_ERROR_V2) != 0) { 1049 snprintb(buf, sizeof(buf), NFE_V2_TXERR, flags); 1050 aprint_error_dev(sc->sc_dev, "tx v2 error %s\n", 1051 buf); 1052 if_statinc(ifp, if_oerrors); 1053 } else 1054 if_statinc(ifp, if_opackets); 1055 } 1056 1057 if (data->m == NULL) { /* should not get there */ 1058 aprint_error_dev(sc->sc_dev, 1059 "last fragment bit w/o associated mbuf!\n"); 1060 continue; 1061 } 1062 1063 /* last fragment of the mbuf chain transmitted */ 1064 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1065 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1066 bus_dmamap_unload(sc->sc_dmat, data->active); 1067 m_freem(data->m); 1068 data->m = NULL; 1069 } 1070 1071 sc->txq.next = i; 1072 1073 if (sc->txq.queued < NFE_TX_RING_COUNT) { 1074 /* at least one slot freed */ 1075 ifp->if_flags &= ~IFF_OACTIVE; 1076 } 1077 1078 if (sc->txq.queued == 0) { 1079 /* all queued packets are sent */ 1080 ifp->if_timer = 0; 1081 } 1082 } 1083 1084 int 1085 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 1086 { 1087 struct nfe_desc32 *desc32; 1088 struct nfe_desc64 *desc64; 1089 struct nfe_tx_data *data; 1090 bus_dmamap_t map; 1091 uint16_t flags, csumflags; 1092 #if NVLAN > 0 1093 uint32_t vtag = 0; 1094 #endif 1095 int error, i, first; 1096 1097 desc32 = NULL; 1098 desc64 = NULL; 1099 data = NULL; 1100 1101 flags = 0; 1102 csumflags = 0; 1103 first = sc->txq.cur; 1104 1105 map = sc->txq.data[first].map; 1106 1107 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1108 if (error != 0) { 1109 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1110 error); 1111 return error; 1112 } 1113 1114 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1115 bus_dmamap_unload(sc->sc_dmat, map); 1116 return ENOBUFS; 1117 } 1118 1119 #if NVLAN > 0 1120 /* setup h/w VLAN tagging */ 1121 if (vlan_has_tag(m0)) 1122 vtag = NFE_TX_VTAG | vlan_get_tag(m0); 1123 #endif 1124 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1125 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1126 csumflags |= NFE_TX_IP_CSUM; 1127 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1128 csumflags |= NFE_TX_TCP_UDP_CSUM; 1129 } 1130 1131 for (i = 0; i < map->dm_nsegs; i++) { 1132 data = &sc->txq.data[sc->txq.cur]; 1133 1134 if (sc->sc_flags & NFE_40BIT_ADDR) { 1135 desc64 = &sc->txq.desc64[sc->txq.cur]; 1136 desc64->physaddr[0] = 1137 htole32(((uint64_t)map->dm_segs[i].ds_addr) >> 32); 1138 desc64->physaddr[1] = 1139 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1140 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1141 desc64->flags = htole16(flags); 1142 desc64->vtag = 0; 1143 } else { 1144 desc32 = &sc->txq.desc32[sc->txq.cur]; 1145 1146 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1147 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1148 desc32->flags = htole16(flags); 1149 } 1150 1151 /* 1152 * Setting of the valid bit in the first descriptor is 1153 * deferred until the whole chain is fully setup. 1154 */ 1155 flags |= NFE_TX_VALID; 1156 1157 sc->txq.queued++; 1158 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1159 } 1160 1161 /* the whole mbuf chain has been setup */ 1162 if (sc->sc_flags & NFE_40BIT_ADDR) { 1163 /* fix last descriptor */ 1164 flags |= NFE_TX_LASTFRAG_V2; 1165 desc64->flags = htole16(flags); 1166 1167 /* Checksum flags and vtag belong to the first fragment only. */ 1168 #if NVLAN > 0 1169 sc->txq.desc64[first].vtag = htole32(vtag); 1170 #endif 1171 sc->txq.desc64[first].flags |= htole16(csumflags); 1172 1173 /* finally, set the valid bit in the first descriptor */ 1174 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1175 } else { 1176 /* fix last descriptor */ 1177 if (sc->sc_flags & NFE_JUMBO_SUP) 1178 flags |= NFE_TX_LASTFRAG_V2; 1179 else 1180 flags |= NFE_TX_LASTFRAG_V1; 1181 desc32->flags = htole16(flags); 1182 1183 /* Checksum flags belong to the first fragment only. */ 1184 sc->txq.desc32[first].flags |= htole16(csumflags); 1185 1186 /* finally, set the valid bit in the first descriptor */ 1187 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1188 } 1189 1190 data->m = m0; 1191 data->active = map; 1192 1193 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1194 BUS_DMASYNC_PREWRITE); 1195 1196 return 0; 1197 } 1198 1199 void 1200 nfe_start(struct ifnet *ifp) 1201 { 1202 struct nfe_softc *sc = ifp->if_softc; 1203 int old = sc->txq.queued; 1204 struct mbuf *m0; 1205 1206 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1207 return; 1208 1209 for (;;) { 1210 IFQ_POLL(&ifp->if_snd, m0); 1211 if (m0 == NULL) 1212 break; 1213 1214 if (nfe_encap(sc, m0) != 0) { 1215 ifp->if_flags |= IFF_OACTIVE; 1216 break; 1217 } 1218 1219 /* packet put in h/w queue, remove from s/w queue */ 1220 IFQ_DEQUEUE(&ifp->if_snd, m0); 1221 1222 bpf_mtap(ifp, m0, BPF_D_OUT); 1223 } 1224 1225 if (sc->txq.queued != old) { 1226 /* packets are queued */ 1227 if (sc->sc_flags & NFE_40BIT_ADDR) 1228 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1229 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1230 else 1231 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1232 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1233 /* kick Tx */ 1234 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1235 1236 /* 1237 * Set a timeout in case the chip goes out to lunch. 1238 */ 1239 ifp->if_timer = 5; 1240 } 1241 } 1242 1243 void 1244 nfe_watchdog(struct ifnet *ifp) 1245 { 1246 struct nfe_softc *sc = ifp->if_softc; 1247 1248 aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1249 1250 ifp->if_flags &= ~IFF_RUNNING; 1251 nfe_init(ifp); 1252 1253 if_statinc(ifp, if_oerrors); 1254 } 1255 1256 int 1257 nfe_init(struct ifnet *ifp) 1258 { 1259 struct nfe_softc *sc = ifp->if_softc; 1260 uint32_t tmp; 1261 int rc = 0, s; 1262 1263 if (ifp->if_flags & IFF_RUNNING) 1264 return 0; 1265 1266 nfe_stop(ifp, 0); 1267 1268 NFE_WRITE(sc, NFE_TX_UNK, 0); 1269 NFE_WRITE(sc, NFE_STATUS, 0); 1270 1271 sc->rxtxctl = NFE_RXTX_BIT2; 1272 if (sc->sc_flags & NFE_40BIT_ADDR) 1273 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1274 else if (sc->sc_flags & NFE_JUMBO_SUP) 1275 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1276 if (sc->sc_flags & NFE_HW_CSUM) 1277 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1278 #if NVLAN > 0 1279 /* 1280 * Although the adapter is capable of stripping VLAN tags from received 1281 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1282 * purpose. This will be done in software by our network stack. 1283 */ 1284 if (sc->sc_flags & NFE_HW_VLAN) 1285 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1286 #endif 1287 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1288 DELAY(10); 1289 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1290 1291 #if NVLAN 1292 if (sc->sc_flags & NFE_HW_VLAN) 1293 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1294 #endif 1295 1296 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1297 1298 /* set MAC address */ 1299 nfe_set_macaddr(sc, sc->sc_enaddr); 1300 1301 /* tell MAC where rings are in memory */ 1302 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, ((uint64_t)sc->rxq.physaddr) >> 32); 1303 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1304 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, ((uint64_t)sc->txq.physaddr) >> 32); 1305 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1306 1307 NFE_WRITE(sc, NFE_RING_SIZE, 1308 (NFE_RX_RING_COUNT - 1) << 16 | 1309 (NFE_TX_RING_COUNT - 1)); 1310 1311 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1312 1313 /* force MAC to wakeup */ 1314 tmp = NFE_READ(sc, NFE_PWR_STATE); 1315 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1316 DELAY(10); 1317 tmp = NFE_READ(sc, NFE_PWR_STATE); 1318 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1319 1320 s = splnet(); 1321 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1322 nfe_intr(sc); /* XXX clear IRQ status registers */ 1323 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1324 splx(s); 1325 1326 #if 1 1327 /* configure interrupts coalescing/mitigation */ 1328 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1329 #else 1330 /* no interrupt mitigation: one interrupt per packet */ 1331 NFE_WRITE(sc, NFE_IMTIMER, 970); 1332 #endif 1333 1334 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1335 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1336 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1337 1338 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1339 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1340 1341 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1342 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_ENABLE); 1343 1344 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1345 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1346 DELAY(10); 1347 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1348 1349 /* set Rx filter */ 1350 nfe_setmulti(sc); 1351 1352 if ((rc = ether_mediachange(ifp)) != 0) 1353 goto out; 1354 1355 nfe_tick(sc); 1356 1357 /* enable Rx */ 1358 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1359 1360 /* enable Tx */ 1361 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1362 1363 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1364 1365 /* enable interrupts */ 1366 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1367 1368 callout_schedule(&sc->sc_tick_ch, hz); 1369 1370 ifp->if_flags |= IFF_RUNNING; 1371 ifp->if_flags &= ~IFF_OACTIVE; 1372 1373 out: 1374 return rc; 1375 } 1376 1377 void 1378 nfe_stop(struct ifnet *ifp, int disable) 1379 { 1380 struct nfe_softc *sc = ifp->if_softc; 1381 1382 callout_stop(&sc->sc_tick_ch); 1383 1384 ifp->if_timer = 0; 1385 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1386 1387 mii_down(&sc->sc_mii); 1388 1389 /* abort Tx */ 1390 NFE_WRITE(sc, NFE_TX_CTL, 0); 1391 1392 /* disable Rx */ 1393 NFE_WRITE(sc, NFE_RX_CTL, 0); 1394 1395 /* disable interrupts */ 1396 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1397 1398 /* reset Tx and Rx rings */ 1399 nfe_reset_tx_ring(sc, &sc->txq); 1400 nfe_reset_rx_ring(sc, &sc->rxq); 1401 } 1402 1403 int 1404 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1405 { 1406 struct nfe_desc32 *desc32; 1407 struct nfe_desc64 *desc64; 1408 struct nfe_rx_data *data; 1409 struct nfe_jbuf *jbuf; 1410 void **desc; 1411 bus_addr_t physaddr; 1412 int i, nsegs, error, descsize; 1413 1414 if (sc->sc_flags & NFE_40BIT_ADDR) { 1415 desc = (void **)&ring->desc64; 1416 descsize = sizeof (struct nfe_desc64); 1417 } else { 1418 desc = (void **)&ring->desc32; 1419 descsize = sizeof (struct nfe_desc32); 1420 } 1421 1422 ring->cur = ring->next = 0; 1423 ring->bufsz = MCLBYTES; 1424 1425 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1426 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1427 if (error != 0) { 1428 aprint_error_dev(sc->sc_dev, 1429 "could not create desc DMA map\n"); 1430 ring->map = NULL; 1431 goto fail; 1432 } 1433 1434 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1435 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1436 if (error != 0) { 1437 aprint_error_dev(sc->sc_dev, 1438 "could not allocate DMA memory\n"); 1439 goto fail; 1440 } 1441 1442 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1443 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1444 if (error != 0) { 1445 aprint_error_dev(sc->sc_dev, 1446 "could not map desc DMA memory\n"); 1447 goto fail; 1448 } 1449 1450 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1451 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1452 if (error != 0) { 1453 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1454 goto fail; 1455 } 1456 1457 memset(*desc, 0, NFE_RX_RING_COUNT * descsize); 1458 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1459 1460 if (sc->sc_flags & NFE_USE_JUMBO) { 1461 ring->bufsz = NFE_JBYTES; 1462 if ((error = nfe_jpool_alloc(sc)) != 0) { 1463 aprint_error_dev(sc->sc_dev, 1464 "could not allocate jumbo frames\n"); 1465 goto fail; 1466 } 1467 } 1468 1469 /* 1470 * Pre-allocate Rx buffers and populate Rx ring. 1471 */ 1472 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1473 data = &sc->rxq.data[i]; 1474 1475 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1476 if (data->m == NULL) { 1477 aprint_error_dev(sc->sc_dev, 1478 "could not allocate rx mbuf\n"); 1479 error = ENOMEM; 1480 goto fail; 1481 } 1482 1483 if (sc->sc_flags & NFE_USE_JUMBO) { 1484 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1485 aprint_error_dev(sc->sc_dev, 1486 "could not allocate jumbo buffer\n"); 1487 goto fail; 1488 } 1489 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1490 sc); 1491 1492 physaddr = jbuf->physaddr; 1493 } else { 1494 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1495 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1496 if (error != 0) { 1497 aprint_error_dev(sc->sc_dev, 1498 "could not create DMA map\n"); 1499 data->map = NULL; 1500 goto fail; 1501 } 1502 MCLGET(data->m, M_DONTWAIT); 1503 if (!(data->m->m_flags & M_EXT)) { 1504 aprint_error_dev(sc->sc_dev, 1505 "could not allocate mbuf cluster\n"); 1506 error = ENOMEM; 1507 goto fail; 1508 } 1509 1510 error = bus_dmamap_load(sc->sc_dmat, data->map, 1511 mtod(data->m, void *), MCLBYTES, NULL, 1512 BUS_DMA_READ | BUS_DMA_NOWAIT); 1513 if (error != 0) { 1514 aprint_error_dev(sc->sc_dev, 1515 "could not load rx buf DMA map"); 1516 goto fail; 1517 } 1518 physaddr = data->map->dm_segs[0].ds_addr; 1519 } 1520 1521 if (sc->sc_flags & NFE_40BIT_ADDR) { 1522 desc64 = &sc->rxq.desc64[i]; 1523 desc64->physaddr[0] = 1524 htole32(((uint64_t)physaddr) >> 32); 1525 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1526 desc64->length = htole16(sc->rxq.bufsz); 1527 desc64->flags = htole16(NFE_RX_READY); 1528 } else { 1529 desc32 = &sc->rxq.desc32[i]; 1530 desc32->physaddr = htole32(physaddr); 1531 desc32->length = htole16(sc->rxq.bufsz); 1532 desc32->flags = htole16(NFE_RX_READY); 1533 } 1534 } 1535 1536 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1537 BUS_DMASYNC_PREWRITE); 1538 1539 return 0; 1540 1541 fail: nfe_free_rx_ring(sc, ring); 1542 return error; 1543 } 1544 1545 void 1546 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1547 { 1548 int i; 1549 1550 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1551 if (sc->sc_flags & NFE_40BIT_ADDR) { 1552 ring->desc64[i].length = htole16(ring->bufsz); 1553 ring->desc64[i].flags = htole16(NFE_RX_READY); 1554 } else { 1555 ring->desc32[i].length = htole16(ring->bufsz); 1556 ring->desc32[i].flags = htole16(NFE_RX_READY); 1557 } 1558 } 1559 1560 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1561 BUS_DMASYNC_PREWRITE); 1562 1563 ring->cur = ring->next = 0; 1564 } 1565 1566 void 1567 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1568 { 1569 struct nfe_rx_data *data; 1570 void *desc; 1571 int i, descsize; 1572 1573 if (sc->sc_flags & NFE_40BIT_ADDR) { 1574 desc = ring->desc64; 1575 descsize = sizeof (struct nfe_desc64); 1576 } else { 1577 desc = ring->desc32; 1578 descsize = sizeof (struct nfe_desc32); 1579 } 1580 1581 if (desc != NULL) { 1582 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1583 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1584 bus_dmamap_unload(sc->sc_dmat, ring->map); 1585 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1586 NFE_RX_RING_COUNT * descsize); 1587 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1588 } 1589 1590 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1591 data = &ring->data[i]; 1592 1593 if (data->map != NULL) { 1594 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1595 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1596 bus_dmamap_unload(sc->sc_dmat, data->map); 1597 bus_dmamap_destroy(sc->sc_dmat, data->map); 1598 } 1599 if (data->m != NULL) 1600 m_freem(data->m); 1601 } 1602 1603 nfe_jpool_free(sc); 1604 } 1605 1606 struct nfe_jbuf * 1607 nfe_jalloc(struct nfe_softc *sc, int i) 1608 { 1609 struct nfe_jbuf *jbuf; 1610 1611 mutex_enter(&sc->rxq.mtx); 1612 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1613 if (jbuf != NULL) 1614 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1615 mutex_exit(&sc->rxq.mtx); 1616 if (jbuf == NULL) 1617 return NULL; 1618 sc->rxq.jbufmap[i] = 1619 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1620 return jbuf; 1621 } 1622 1623 /* 1624 * This is called automatically by the network stack when the mbuf is freed. 1625 * Caution must be taken that the NIC might be reset by the time the mbuf is 1626 * freed. 1627 */ 1628 void 1629 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1630 { 1631 struct nfe_softc *sc = arg; 1632 struct nfe_jbuf *jbuf; 1633 int i; 1634 1635 /* find the jbuf from the base pointer */ 1636 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1637 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1638 aprint_error_dev(sc->sc_dev, 1639 "request to free a buffer (%p) not managed by us\n", buf); 1640 return; 1641 } 1642 jbuf = &sc->rxq.jbuf[i]; 1643 1644 /* ..and put it back in the free list */ 1645 mutex_enter(&sc->rxq.mtx); 1646 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1647 mutex_exit(&sc->rxq.mtx); 1648 1649 if (m != NULL) 1650 pool_cache_put(mb_cache, m); 1651 } 1652 1653 int 1654 nfe_jpool_alloc(struct nfe_softc *sc) 1655 { 1656 struct nfe_rx_ring *ring = &sc->rxq; 1657 struct nfe_jbuf *jbuf; 1658 bus_addr_t physaddr; 1659 char *buf; 1660 int i, nsegs, error; 1661 1662 /* 1663 * Allocate a big chunk of DMA'able memory. 1664 */ 1665 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1666 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1667 if (error != 0) { 1668 aprint_error_dev(sc->sc_dev, 1669 "could not create jumbo DMA map\n"); 1670 ring->jmap = NULL; 1671 goto fail; 1672 } 1673 1674 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1675 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1676 if (error != 0) { 1677 aprint_error_dev(sc->sc_dev, 1678 "could not allocate jumbo DMA memory\n"); 1679 goto fail; 1680 } 1681 1682 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1683 &ring->jpool, BUS_DMA_NOWAIT); 1684 if (error != 0) { 1685 aprint_error_dev(sc->sc_dev, 1686 "could not map jumbo DMA memory\n"); 1687 goto fail; 1688 } 1689 1690 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1691 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1692 if (error != 0) { 1693 aprint_error_dev(sc->sc_dev, 1694 "could not load jumbo DMA map\n"); 1695 goto fail; 1696 } 1697 1698 /* ..and split it into 9KB chunks */ 1699 SLIST_INIT(&ring->jfreelist); 1700 1701 buf = ring->jpool; 1702 physaddr = ring->jmap->dm_segs[0].ds_addr; 1703 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1704 jbuf = &ring->jbuf[i]; 1705 1706 jbuf->buf = buf; 1707 jbuf->physaddr = physaddr; 1708 1709 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1710 1711 buf += NFE_JBYTES; 1712 physaddr += NFE_JBYTES; 1713 } 1714 1715 return 0; 1716 1717 fail: nfe_jpool_free(sc); 1718 return error; 1719 } 1720 1721 void 1722 nfe_jpool_free(struct nfe_softc *sc) 1723 { 1724 struct nfe_rx_ring *ring = &sc->rxq; 1725 1726 if (ring->jmap != NULL) { 1727 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1728 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1729 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1730 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1731 ring->jmap = NULL; 1732 } 1733 if (ring->jpool != NULL) { 1734 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1735 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1736 ring->jpool = NULL; 1737 } 1738 } 1739 1740 int 1741 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1742 { 1743 int i, nsegs, error; 1744 void **desc; 1745 int descsize; 1746 1747 if (sc->sc_flags & NFE_40BIT_ADDR) { 1748 desc = (void **)&ring->desc64; 1749 descsize = sizeof (struct nfe_desc64); 1750 } else { 1751 desc = (void **)&ring->desc32; 1752 descsize = sizeof (struct nfe_desc32); 1753 } 1754 1755 ring->queued = 0; 1756 ring->cur = ring->next = 0; 1757 1758 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1759 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1760 1761 if (error != 0) { 1762 aprint_error_dev(sc->sc_dev, 1763 "could not create desc DMA map\n"); 1764 ring->map = NULL; 1765 goto fail; 1766 } 1767 1768 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1769 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1770 if (error != 0) { 1771 aprint_error_dev(sc->sc_dev, 1772 "could not allocate DMA memory\n"); 1773 goto fail; 1774 } 1775 1776 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1777 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1778 if (error != 0) { 1779 aprint_error_dev(sc->sc_dev, 1780 "could not map desc DMA memory\n"); 1781 goto fail; 1782 } 1783 1784 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1785 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1786 if (error != 0) { 1787 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1788 goto fail; 1789 } 1790 1791 memset(*desc, 0, NFE_TX_RING_COUNT * descsize); 1792 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1793 1794 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1795 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1796 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1797 &ring->data[i].map); 1798 if (error != 0) { 1799 aprint_error_dev(sc->sc_dev, 1800 "could not create DMA map\n"); 1801 ring->data[i].map = NULL; 1802 goto fail; 1803 } 1804 } 1805 1806 return 0; 1807 1808 fail: nfe_free_tx_ring(sc, ring); 1809 return error; 1810 } 1811 1812 void 1813 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1814 { 1815 struct nfe_tx_data *data; 1816 int i; 1817 1818 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1819 if (sc->sc_flags & NFE_40BIT_ADDR) 1820 ring->desc64[i].flags = 0; 1821 else 1822 ring->desc32[i].flags = 0; 1823 1824 data = &ring->data[i]; 1825 1826 if (data->m != NULL) { 1827 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1828 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1829 bus_dmamap_unload(sc->sc_dmat, data->active); 1830 m_freem(data->m); 1831 data->m = NULL; 1832 } 1833 } 1834 1835 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1836 BUS_DMASYNC_PREWRITE); 1837 1838 ring->queued = 0; 1839 ring->cur = ring->next = 0; 1840 } 1841 1842 void 1843 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1844 { 1845 struct nfe_tx_data *data; 1846 void *desc; 1847 int i, descsize; 1848 1849 if (sc->sc_flags & NFE_40BIT_ADDR) { 1850 desc = ring->desc64; 1851 descsize = sizeof (struct nfe_desc64); 1852 } else { 1853 desc = ring->desc32; 1854 descsize = sizeof (struct nfe_desc32); 1855 } 1856 1857 if (desc != NULL) { 1858 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1859 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1860 bus_dmamap_unload(sc->sc_dmat, ring->map); 1861 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1862 NFE_TX_RING_COUNT * descsize); 1863 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1864 } 1865 1866 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1867 data = &ring->data[i]; 1868 1869 if (data->m != NULL) { 1870 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1871 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1872 bus_dmamap_unload(sc->sc_dmat, data->active); 1873 m_freem(data->m); 1874 } 1875 } 1876 1877 /* ..and now actually destroy the DMA mappings */ 1878 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1879 data = &ring->data[i]; 1880 if (data->map == NULL) 1881 continue; 1882 bus_dmamap_destroy(sc->sc_dmat, data->map); 1883 } 1884 } 1885 1886 void 1887 nfe_setmulti(struct nfe_softc *sc) 1888 { 1889 struct ethercom *ec = &sc->sc_ethercom; 1890 struct ifnet *ifp = &ec->ec_if; 1891 struct ether_multi *enm; 1892 struct ether_multistep step; 1893 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1894 uint32_t filter = NFE_RXFILTER_MAGIC; 1895 int i; 1896 1897 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1898 memset(addr, 0, ETHER_ADDR_LEN); 1899 memset(mask, 0, ETHER_ADDR_LEN); 1900 goto done; 1901 } 1902 1903 memcpy(addr, etherbroadcastaddr, ETHER_ADDR_LEN); 1904 memcpy(mask, etherbroadcastaddr, ETHER_ADDR_LEN); 1905 1906 ETHER_LOCK(ec); 1907 ETHER_FIRST_MULTI(step, ec, enm); 1908 while (enm != NULL) { 1909 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1910 ifp->if_flags |= IFF_ALLMULTI; 1911 memset(addr, 0, ETHER_ADDR_LEN); 1912 memset(mask, 0, ETHER_ADDR_LEN); 1913 ETHER_UNLOCK(ec); 1914 goto done; 1915 } 1916 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1917 addr[i] &= enm->enm_addrlo[i]; 1918 mask[i] &= ~enm->enm_addrlo[i]; 1919 } 1920 ETHER_NEXT_MULTI(step, enm); 1921 } 1922 ETHER_UNLOCK(ec); 1923 for (i = 0; i < ETHER_ADDR_LEN; i++) 1924 mask[i] |= addr[i]; 1925 1926 done: 1927 addr[0] |= 0x01; /* make sure multicast bit is set */ 1928 1929 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1930 (uint32_t)addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1931 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1932 addr[5] << 8 | addr[4]); 1933 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1934 (uint32_t)mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1935 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1936 mask[5] << 8 | mask[4]); 1937 1938 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1939 NFE_WRITE(sc, NFE_RXFILTER, filter); 1940 } 1941 1942 void 1943 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1944 { 1945 uint32_t tmp; 1946 1947 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 1948 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1949 addr[0] = (tmp & 0xff); 1950 addr[1] = (tmp >> 8) & 0xff; 1951 addr[2] = (tmp >> 16) & 0xff; 1952 addr[3] = (tmp >> 24) & 0xff; 1953 1954 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1955 addr[4] = (tmp & 0xff); 1956 addr[5] = (tmp >> 8) & 0xff; 1957 1958 } else { 1959 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1960 addr[0] = (tmp >> 8) & 0xff; 1961 addr[1] = (tmp & 0xff); 1962 1963 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1964 addr[2] = (tmp >> 24) & 0xff; 1965 addr[3] = (tmp >> 16) & 0xff; 1966 addr[4] = (tmp >> 8) & 0xff; 1967 addr[5] = (tmp & 0xff); 1968 } 1969 } 1970 1971 void 1972 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1973 { 1974 NFE_WRITE(sc, NFE_MACADDR_LO, 1975 addr[5] << 8 | addr[4]); 1976 NFE_WRITE(sc, NFE_MACADDR_HI, 1977 (uint32_t)addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1978 } 1979 1980 void 1981 nfe_tick(void *arg) 1982 { 1983 struct nfe_softc *sc = arg; 1984 int s; 1985 1986 s = splnet(); 1987 mii_tick(&sc->sc_mii); 1988 splx(s); 1989 1990 callout_schedule(&sc->sc_tick_ch, hz); 1991 } 1992 1993 void 1994 nfe_poweron(device_t self) 1995 { 1996 struct nfe_softc *sc = device_private(self); 1997 1998 if ((sc->sc_flags & NFE_PWR_MGMT) != 0) { 1999 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 2000 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 2001 DELAY(100); 2002 NFE_WRITE(sc, NFE_MAC_RESET, 0); 2003 DELAY(100); 2004 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 2005 NFE_WRITE(sc, NFE_PWR2_CTL, 2006 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_WAKEUP_MASK); 2007 } 2008 } 2009 2010 bool 2011 nfe_resume(device_t dv, const pmf_qual_t *qual) 2012 { 2013 nfe_poweron(dv); 2014 2015 return true; 2016 } 2017
Indexes created Mon Oct 13 16:09:52 GMT 2025