if_nfe.c revision 1.66
1 /* $NetBSD: if_nfe.c,v 1.66 2018/12/09 11:14:02 jdolecek Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.77 2008/02/05 16:52:50 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006, 2007 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.66 2018/12/09 11:14:02 jdolecek Exp $"); 25 26 #include "opt_inet.h" 27 #include "vlan.h" 28 29 #include <sys/param.h> 30 #include <sys/endian.h> 31 #include <sys/systm.h> 32 #include <sys/types.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/mutex.h> 36 #include <sys/queue.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/callout.h> 40 #include <sys/socket.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #include <net/bpf.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_nfereg.h> 72 #include <dev/pci/if_nfevar.h> 73 74 static int nfe_ifflags_cb(struct ethercom *); 75 76 int nfe_match(device_t, cfdata_t, void *); 77 void nfe_attach(device_t, device_t, void *); 78 int nfe_detach(device_t, int); 79 void nfe_power(int, void *); 80 void nfe_miibus_statchg(struct ifnet *); 81 int nfe_miibus_readreg(device_t, int, int); 82 void nfe_miibus_writereg(device_t, int, int, int); 83 int nfe_intr(void *); 84 int nfe_ioctl(struct ifnet *, u_long, void *); 85 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 86 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 87 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 88 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 89 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 90 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 91 void nfe_rxeof(struct nfe_softc *); 92 void nfe_txeof(struct nfe_softc *); 93 int nfe_encap(struct nfe_softc *, struct mbuf *); 94 void nfe_start(struct ifnet *); 95 void nfe_watchdog(struct ifnet *); 96 int nfe_init(struct ifnet *); 97 void nfe_stop(struct ifnet *, int); 98 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 99 void nfe_jfree(struct mbuf *, void *, size_t, void *); 100 int nfe_jpool_alloc(struct nfe_softc *); 101 void nfe_jpool_free(struct nfe_softc *); 102 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 105 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 108 void nfe_setmulti(struct nfe_softc *); 109 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 110 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 111 void nfe_tick(void *); 112 void nfe_poweron(device_t); 113 bool nfe_resume(device_t, const pmf_qual_t *); 114 115 CFATTACH_DECL_NEW(nfe, sizeof(struct nfe_softc), 116 nfe_match, nfe_attach, nfe_detach, NULL); 117 118 /* #define NFE_NO_JUMBO */ 119 120 #ifdef NFE_DEBUG 121 int nfedebug = 0; 122 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 123 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 124 #else 125 #define DPRINTF(x) 126 #define DPRINTFN(n,x) 127 #endif 128 129 /* deal with naming differences */ 130 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 134 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 135 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 136 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 137 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 140 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 141 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 142 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 145 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 146 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 147 148 #ifdef _LP64 149 #define __LP64__ 1 150 #endif 151 152 const struct nfe_product { 153 pci_vendor_id_t vendor; 154 pci_product_id_t product; 155 } nfe_devices[] = { 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 183 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 184 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 185 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 186 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 }, 187 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1 }, 188 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2 }, 189 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3 }, 190 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4 }, 191 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1 }, 192 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2 }, 193 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3 }, 194 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4 } 195 }; 196 197 int 198 nfe_match(device_t dev, cfdata_t match, void *aux) 199 { 200 struct pci_attach_args *pa = aux; 201 const struct nfe_product *np; 202 int i; 203 204 for (i = 0; i < __arraycount(nfe_devices); i++) { 205 np = &nfe_devices[i]; 206 if (PCI_VENDOR(pa->pa_id) == np->vendor && 207 PCI_PRODUCT(pa->pa_id) == np->product) 208 return 1; 209 } 210 return 0; 211 } 212 213 void 214 nfe_attach(device_t parent, device_t self, void *aux) 215 { 216 struct nfe_softc *sc = device_private(self); 217 struct pci_attach_args *pa = aux; 218 pci_chipset_tag_t pc = pa->pa_pc; 219 pci_intr_handle_t ih; 220 const char *intrstr; 221 struct ifnet *ifp; 222 pcireg_t memtype, csr; 223 int mii_flags = 0; 224 char intrbuf[PCI_INTRSTR_LEN]; 225 226 sc->sc_dev = self; 227 sc->sc_pc = pa->pa_pc; 228 pci_aprint_devinfo(pa, NULL); 229 230 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 231 switch (memtype) { 232 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 233 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 234 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 235 &sc->sc_memh, NULL, &sc->sc_mems) == 0) 236 break; 237 /* FALLTHROUGH */ 238 default: 239 aprint_error_dev(self, "could not map mem space\n"); 240 return; 241 } 242 243 if (pci_intr_map(pa, &ih) != 0) { 244 aprint_error_dev(self, "could not map interrupt\n"); 245 goto fail; 246 } 247 248 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 249 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, nfe_intr, sc, 250 device_xname(self)); 251 if (sc->sc_ih == NULL) { 252 aprint_error_dev(self, "could not establish interrupt"); 253 if (intrstr != NULL) 254 aprint_error(" at %s", intrstr); 255 aprint_error("\n"); 256 goto fail; 257 } 258 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 259 260 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 261 csr |= PCI_COMMAND_MASTER_ENABLE; 262 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 263 264 sc->sc_flags = 0; 265 266 switch (PCI_PRODUCT(pa->pa_id)) { 267 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 268 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 269 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 270 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 271 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 272 break; 273 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 274 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 275 sc->sc_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT; 276 break; 277 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 278 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 279 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 280 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 281 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 282 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 283 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 284 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 285 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 286 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 287 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 288 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 289 sc->sc_flags |= NFE_40BIT_ADDR | NFE_CORRECT_MACADDR | 290 NFE_PWR_MGMT; 291 break; 292 case PCI_PRODUCT_NVIDIA_MCP77_LAN1: 293 case PCI_PRODUCT_NVIDIA_MCP77_LAN2: 294 case PCI_PRODUCT_NVIDIA_MCP77_LAN3: 295 case PCI_PRODUCT_NVIDIA_MCP77_LAN4: 296 sc->sc_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | 297 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 298 break; 299 case PCI_PRODUCT_NVIDIA_MCP79_LAN1: 300 case PCI_PRODUCT_NVIDIA_MCP79_LAN2: 301 case PCI_PRODUCT_NVIDIA_MCP79_LAN3: 302 case PCI_PRODUCT_NVIDIA_MCP79_LAN4: 303 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 304 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 305 break; 306 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 307 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 308 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 309 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 310 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 311 break; 312 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 313 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 314 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 315 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 316 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 317 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 318 mii_flags = MIIF_DOPAUSE; 319 break; 320 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 321 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 322 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 323 NFE_HW_VLAN | NFE_PWR_MGMT; 324 break; 325 } 326 327 if (pci_dma64_available(pa) && (sc->sc_flags & NFE_40BIT_ADDR) != 0) 328 sc->sc_dmat = pa->pa_dmat64; 329 else 330 sc->sc_dmat = pa->pa_dmat; 331 332 nfe_poweron(self); 333 334 #ifndef NFE_NO_JUMBO 335 /* enable jumbo frames for adapters that support it */ 336 if (sc->sc_flags & NFE_JUMBO_SUP) 337 sc->sc_flags |= NFE_USE_JUMBO; 338 #endif 339 340 /* Check for reversed ethernet address */ 341 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 342 sc->sc_flags |= NFE_CORRECT_MACADDR; 343 344 nfe_get_macaddr(sc, sc->sc_enaddr); 345 aprint_normal_dev(self, "Ethernet address %s\n", 346 ether_sprintf(sc->sc_enaddr)); 347 348 /* 349 * Allocate Tx and Rx rings. 350 */ 351 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 352 aprint_error_dev(self, "could not allocate Tx ring\n"); 353 goto fail; 354 } 355 356 mutex_init(&sc->rxq.mtx, MUTEX_DEFAULT, IPL_NET); 357 358 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 359 aprint_error_dev(self, "could not allocate Rx ring\n"); 360 nfe_free_tx_ring(sc, &sc->txq); 361 goto fail; 362 } 363 364 ifp = &sc->sc_ethercom.ec_if; 365 ifp->if_softc = sc; 366 ifp->if_mtu = ETHERMTU; 367 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 368 ifp->if_ioctl = nfe_ioctl; 369 ifp->if_start = nfe_start; 370 ifp->if_stop = nfe_stop; 371 ifp->if_watchdog = nfe_watchdog; 372 ifp->if_init = nfe_init; 373 ifp->if_baudrate = IF_Gbps(1); 374 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 375 IFQ_SET_READY(&ifp->if_snd); 376 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 377 378 if (sc->sc_flags & NFE_USE_JUMBO) 379 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 380 381 #if NVLAN > 0 382 if (sc->sc_flags & NFE_HW_VLAN) 383 sc->sc_ethercom.ec_capabilities |= 384 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 385 #endif 386 if (sc->sc_flags & NFE_HW_CSUM) { 387 ifp->if_capabilities |= 388 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 389 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 390 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 391 } 392 393 sc->sc_mii.mii_ifp = ifp; 394 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 395 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 396 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 397 398 sc->sc_ethercom.ec_mii = &sc->sc_mii; 399 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 400 ether_mediastatus); 401 402 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 0, mii_flags); 403 404 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 405 aprint_error_dev(self, "no PHY found!\n"); 406 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 407 0, NULL); 408 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 409 } else 410 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 411 412 if_attach(ifp); 413 if_deferred_start_init(ifp, NULL); 414 ether_ifattach(ifp, sc->sc_enaddr); 415 ether_set_ifflags_cb(&sc->sc_ethercom, nfe_ifflags_cb); 416 417 callout_init(&sc->sc_tick_ch, 0); 418 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 419 420 if (pmf_device_register(self, NULL, nfe_resume)) 421 pmf_class_network_register(self, ifp); 422 else 423 aprint_error_dev(self, "couldn't establish power handler\n"); 424 425 return; 426 427 fail: 428 if (sc->sc_ih != NULL) { 429 pci_intr_disestablish(pc, sc->sc_ih); 430 sc->sc_ih = NULL; 431 } 432 if (sc->sc_mems != 0) { 433 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 434 sc->sc_mems = 0; 435 } 436 } 437 438 int 439 nfe_detach(device_t self, int flags) 440 { 441 struct nfe_softc *sc = device_private(self); 442 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 443 int s; 444 445 s = splnet(); 446 447 nfe_stop(ifp, 1); 448 449 pmf_device_deregister(self); 450 callout_destroy(&sc->sc_tick_ch); 451 ether_ifdetach(ifp); 452 if_detach(ifp); 453 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 454 455 nfe_free_rx_ring(sc, &sc->rxq); 456 mutex_destroy(&sc->rxq.mtx); 457 nfe_free_tx_ring(sc, &sc->txq); 458 459 if (sc->sc_ih != NULL) { 460 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 461 sc->sc_ih = NULL; 462 } 463 464 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 465 nfe_set_macaddr(sc, sc->sc_enaddr); 466 } else { 467 NFE_WRITE(sc, NFE_MACADDR_LO, 468 sc->sc_enaddr[0] << 8 | sc->sc_enaddr[1]); 469 NFE_WRITE(sc, NFE_MACADDR_HI, 470 sc->sc_enaddr[2] << 24 | sc->sc_enaddr[3] << 16 | 471 sc->sc_enaddr[4] << 8 | sc->sc_enaddr[5]); 472 } 473 474 if (sc->sc_mems != 0) { 475 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 476 sc->sc_mems = 0; 477 } 478 479 splx(s); 480 481 return 0; 482 } 483 484 void 485 nfe_miibus_statchg(struct ifnet *ifp) 486 { 487 struct nfe_softc *sc = ifp->if_softc; 488 struct mii_data *mii = &sc->sc_mii; 489 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 490 491 phy = NFE_READ(sc, NFE_PHY_IFACE); 492 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 493 494 seed = NFE_READ(sc, NFE_RNDSEED); 495 seed &= ~NFE_SEED_MASK; 496 497 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 498 phy |= NFE_PHY_HDX; /* half-duplex */ 499 misc |= NFE_MISC1_HDX; 500 } 501 502 switch (IFM_SUBTYPE(mii->mii_media_active)) { 503 case IFM_1000_T: /* full-duplex only */ 504 link |= NFE_MEDIA_1000T; 505 seed |= NFE_SEED_1000T; 506 phy |= NFE_PHY_1000T; 507 break; 508 case IFM_100_TX: 509 link |= NFE_MEDIA_100TX; 510 seed |= NFE_SEED_100TX; 511 phy |= NFE_PHY_100TX; 512 break; 513 case IFM_10_T: 514 link |= NFE_MEDIA_10T; 515 seed |= NFE_SEED_10T; 516 break; 517 } 518 519 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 520 521 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 522 NFE_WRITE(sc, NFE_MISC1, misc); 523 NFE_WRITE(sc, NFE_LINKSPEED, link); 524 } 525 526 int 527 nfe_miibus_readreg(device_t dev, int phy, int reg) 528 { 529 struct nfe_softc *sc = device_private(dev); 530 uint32_t val; 531 int ntries; 532 533 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 534 535 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 536 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 537 DELAY(100); 538 } 539 540 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 541 542 for (ntries = 0; ntries < 1000; ntries++) { 543 DELAY(100); 544 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 545 break; 546 } 547 if (ntries == 1000) { 548 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 549 device_xname(sc->sc_dev))); 550 return 0; 551 } 552 553 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 554 DPRINTFN(2, ("%s: could not read PHY\n", 555 device_xname(sc->sc_dev))); 556 return 0; 557 } 558 559 val = NFE_READ(sc, NFE_PHY_DATA); 560 if (val != 0xffffffff && val != 0) 561 sc->mii_phyaddr = phy; 562 563 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 564 device_xname(sc->sc_dev), phy, reg, val)); 565 566 return val; 567 } 568 569 void 570 nfe_miibus_writereg(device_t dev, int phy, int reg, int val) 571 { 572 struct nfe_softc *sc = device_private(dev); 573 uint32_t ctl; 574 int ntries; 575 576 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 577 578 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 579 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 580 DELAY(100); 581 } 582 583 NFE_WRITE(sc, NFE_PHY_DATA, val); 584 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 585 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 586 587 for (ntries = 0; ntries < 1000; ntries++) { 588 DELAY(100); 589 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 590 break; 591 } 592 #ifdef NFE_DEBUG 593 if (nfedebug >= 2 && ntries == 1000) 594 printf("could not write to PHY\n"); 595 #endif 596 } 597 598 int 599 nfe_intr(void *arg) 600 { 601 struct nfe_softc *sc = arg; 602 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 603 uint32_t r; 604 int handled; 605 606 if ((ifp->if_flags & IFF_UP) == 0) 607 return 0; 608 609 handled = 0; 610 611 for (;;) { 612 r = NFE_READ(sc, NFE_IRQ_STATUS); 613 if ((r & NFE_IRQ_WANTED) == 0) 614 break; 615 616 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 617 handled = 1; 618 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 619 620 if ((r & (NFE_IRQ_RXERR|NFE_IRQ_RX_NOBUF|NFE_IRQ_RX)) != 0) { 621 /* check Rx ring */ 622 nfe_rxeof(sc); 623 } 624 if ((r & (NFE_IRQ_TXERR|NFE_IRQ_TXERR2|NFE_IRQ_TX_DONE)) != 0) { 625 /* check Tx ring */ 626 nfe_txeof(sc); 627 } 628 if ((r & NFE_IRQ_LINK) != 0) { 629 NFE_READ(sc, NFE_PHY_STATUS); 630 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 631 DPRINTF(("%s: link state changed\n", 632 device_xname(sc->sc_dev))); 633 } 634 } 635 636 if (handled) 637 if_schedule_deferred_start(ifp); 638 639 return handled; 640 } 641 642 static int 643 nfe_ifflags_cb(struct ethercom *ec) 644 { 645 struct ifnet *ifp = &ec->ec_if; 646 struct nfe_softc *sc = ifp->if_softc; 647 int change = ifp->if_flags ^ sc->sc_if_flags; 648 649 /* 650 * If only the PROMISC flag changes, then 651 * don't do a full re-init of the chip, just update 652 * the Rx filter. 653 */ 654 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 655 return ENETRESET; 656 else if ((change & IFF_PROMISC) != 0) 657 nfe_setmulti(sc); 658 659 return 0; 660 } 661 662 int 663 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 664 { 665 struct nfe_softc *sc = ifp->if_softc; 666 struct ifaddr *ifa = (struct ifaddr *)data; 667 int s, error = 0; 668 669 s = splnet(); 670 671 switch (cmd) { 672 case SIOCINITIFADDR: 673 ifp->if_flags |= IFF_UP; 674 nfe_init(ifp); 675 switch (ifa->ifa_addr->sa_family) { 676 #ifdef INET 677 case AF_INET: 678 arp_ifinit(ifp, ifa); 679 break; 680 #endif 681 default: 682 break; 683 } 684 break; 685 default: 686 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 687 break; 688 689 error = 0; 690 691 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 692 ; 693 else if (ifp->if_flags & IFF_RUNNING) 694 nfe_setmulti(sc); 695 break; 696 } 697 sc->sc_if_flags = ifp->if_flags; 698 699 splx(s); 700 701 return error; 702 } 703 704 void 705 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 706 { 707 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 708 (char *)desc32 - (char *)sc->txq.desc32, 709 sizeof (struct nfe_desc32), ops); 710 } 711 712 void 713 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 714 { 715 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 716 (char *)desc64 - (char *)sc->txq.desc64, 717 sizeof (struct nfe_desc64), ops); 718 } 719 720 void 721 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 722 { 723 if (end > start) { 724 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 725 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 726 (char *)&sc->txq.desc32[end] - 727 (char *)&sc->txq.desc32[start], ops); 728 return; 729 } 730 /* sync from 'start' to end of ring */ 731 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 732 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 733 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 734 (char *)&sc->txq.desc32[start], ops); 735 736 /* sync from start of ring to 'end' */ 737 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 738 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 739 } 740 741 void 742 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 743 { 744 if (end > start) { 745 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 746 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 747 (char *)&sc->txq.desc64[end] - 748 (char *)&sc->txq.desc64[start], ops); 749 return; 750 } 751 /* sync from 'start' to end of ring */ 752 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 753 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 754 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 755 (char *)&sc->txq.desc64[start], ops); 756 757 /* sync from start of ring to 'end' */ 758 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 759 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 760 } 761 762 void 763 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 764 { 765 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 766 (char *)desc32 - (char *)sc->rxq.desc32, 767 sizeof (struct nfe_desc32), ops); 768 } 769 770 void 771 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 772 { 773 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 774 (char *)desc64 - (char *)sc->rxq.desc64, 775 sizeof (struct nfe_desc64), ops); 776 } 777 778 void 779 nfe_rxeof(struct nfe_softc *sc) 780 { 781 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 782 struct nfe_desc32 *desc32; 783 struct nfe_desc64 *desc64; 784 struct nfe_rx_data *data; 785 struct nfe_jbuf *jbuf; 786 struct mbuf *m, *mnew; 787 bus_addr_t physaddr; 788 uint16_t flags; 789 int error, len, i; 790 791 desc32 = NULL; 792 desc64 = NULL; 793 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 794 data = &sc->rxq.data[i]; 795 796 if (sc->sc_flags & NFE_40BIT_ADDR) { 797 desc64 = &sc->rxq.desc64[i]; 798 nfe_rxdesc64_sync(sc, desc64, 799 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 800 801 flags = le16toh(desc64->flags); 802 len = le16toh(desc64->length) & 0x3fff; 803 } else { 804 desc32 = &sc->rxq.desc32[i]; 805 nfe_rxdesc32_sync(sc, desc32, 806 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 807 808 flags = le16toh(desc32->flags); 809 len = le16toh(desc32->length) & 0x3fff; 810 } 811 812 if ((flags & NFE_RX_READY) != 0) 813 break; 814 815 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 816 if ((flags & NFE_RX_VALID_V1) == 0) 817 goto skip; 818 819 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 820 flags &= ~NFE_RX_ERROR; 821 len--; /* fix buffer length */ 822 } 823 } else { 824 if ((flags & NFE_RX_VALID_V2) == 0) 825 goto skip; 826 827 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 828 flags &= ~NFE_RX_ERROR; 829 len--; /* fix buffer length */ 830 } 831 } 832 833 if (flags & NFE_RX_ERROR) { 834 ifp->if_ierrors++; 835 goto skip; 836 } 837 838 /* 839 * Try to allocate a new mbuf for this ring element and load 840 * it before processing the current mbuf. If the ring element 841 * cannot be loaded, drop the received packet and reuse the 842 * old mbuf. In the unlikely case that the old mbuf can't be 843 * reloaded either, explicitly panic. 844 */ 845 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 846 if (mnew == NULL) { 847 ifp->if_ierrors++; 848 goto skip; 849 } 850 851 if (sc->sc_flags & NFE_USE_JUMBO) { 852 physaddr = 853 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 854 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 855 if (len > MCLBYTES) { 856 m_freem(mnew); 857 ifp->if_ierrors++; 858 goto skip1; 859 } 860 MCLGET(mnew, M_DONTWAIT); 861 if ((mnew->m_flags & M_EXT) == 0) { 862 m_freem(mnew); 863 ifp->if_ierrors++; 864 goto skip1; 865 } 866 867 (void)memcpy(mtod(mnew, void *), 868 mtod(data->m, const void *), len); 869 m = mnew; 870 goto mbufcopied; 871 } else { 872 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 873 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 874 mtod(data->m, char *) - (char *)sc->rxq.jpool, 875 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 876 877 physaddr = jbuf->physaddr; 878 } 879 } else { 880 MCLGET(mnew, M_DONTWAIT); 881 if ((mnew->m_flags & M_EXT) == 0) { 882 m_freem(mnew); 883 ifp->if_ierrors++; 884 goto skip; 885 } 886 887 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 888 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 889 bus_dmamap_unload(sc->sc_dmat, data->map); 890 891 error = bus_dmamap_load(sc->sc_dmat, data->map, 892 mtod(mnew, void *), MCLBYTES, NULL, 893 BUS_DMA_READ | BUS_DMA_NOWAIT); 894 if (error != 0) { 895 m_freem(mnew); 896 897 /* try to reload the old mbuf */ 898 error = bus_dmamap_load(sc->sc_dmat, data->map, 899 mtod(data->m, void *), MCLBYTES, NULL, 900 BUS_DMA_READ | BUS_DMA_NOWAIT); 901 if (error != 0) { 902 /* very unlikely that it will fail.. */ 903 panic("%s: could not load old rx mbuf", 904 device_xname(sc->sc_dev)); 905 } 906 ifp->if_ierrors++; 907 goto skip; 908 } 909 physaddr = data->map->dm_segs[0].ds_addr; 910 } 911 912 /* 913 * New mbuf successfully loaded, update Rx ring and continue 914 * processing. 915 */ 916 m = data->m; 917 data->m = mnew; 918 919 mbufcopied: 920 /* finalize mbuf */ 921 m->m_pkthdr.len = m->m_len = len; 922 m_set_rcvif(m, ifp); 923 924 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 925 /* 926 * XXX 927 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 928 */ 929 if (flags & NFE_RX_IP_CSUMOK) { 930 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 931 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 932 device_xname(sc->sc_dev))); 933 } 934 /* 935 * XXX 936 * no way to check M_CSUM_TCP_UDP_BAD or 937 * other protocols? 938 */ 939 if (flags & NFE_RX_UDP_CSUMOK) { 940 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 941 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 942 device_xname(sc->sc_dev))); 943 } else if (flags & NFE_RX_TCP_CSUMOK) { 944 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 945 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 946 device_xname(sc->sc_dev))); 947 } 948 } 949 if_percpuq_enqueue(ifp->if_percpuq, m); 950 951 skip1: 952 /* update mapping address in h/w descriptor */ 953 if (sc->sc_flags & NFE_40BIT_ADDR) { 954 #if defined(__LP64__) 955 desc64->physaddr[0] = htole32(physaddr >> 32); 956 #endif 957 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 958 } else { 959 desc32->physaddr = htole32(physaddr); 960 } 961 962 skip: 963 if (sc->sc_flags & NFE_40BIT_ADDR) { 964 desc64->length = htole16(sc->rxq.bufsz); 965 desc64->flags = htole16(NFE_RX_READY); 966 967 nfe_rxdesc64_sync(sc, desc64, 968 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 969 } else { 970 desc32->length = htole16(sc->rxq.bufsz); 971 desc32->flags = htole16(NFE_RX_READY); 972 973 nfe_rxdesc32_sync(sc, desc32, 974 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 975 } 976 } 977 /* update current RX pointer */ 978 sc->rxq.cur = i; 979 } 980 981 void 982 nfe_txeof(struct nfe_softc *sc) 983 { 984 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 985 struct nfe_desc32 *desc32; 986 struct nfe_desc64 *desc64; 987 struct nfe_tx_data *data = NULL; 988 int i; 989 uint16_t flags; 990 char buf[128]; 991 992 for (i = sc->txq.next; 993 sc->txq.queued > 0; 994 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 995 if (sc->sc_flags & NFE_40BIT_ADDR) { 996 desc64 = &sc->txq.desc64[i]; 997 nfe_txdesc64_sync(sc, desc64, 998 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 999 1000 flags = le16toh(desc64->flags); 1001 } else { 1002 desc32 = &sc->txq.desc32[i]; 1003 nfe_txdesc32_sync(sc, desc32, 1004 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1005 1006 flags = le16toh(desc32->flags); 1007 } 1008 1009 if ((flags & NFE_TX_VALID) != 0) 1010 break; 1011 1012 data = &sc->txq.data[i]; 1013 1014 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 1015 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 1016 data->m == NULL) 1017 continue; 1018 1019 if ((flags & NFE_TX_ERROR_V1) != 0) { 1020 snprintb(buf, sizeof(buf), NFE_V1_TXERR, flags); 1021 aprint_error_dev(sc->sc_dev, "tx v1 error %s\n", 1022 buf); 1023 ifp->if_oerrors++; 1024 } else 1025 ifp->if_opackets++; 1026 } else { 1027 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 1028 data->m == NULL) 1029 continue; 1030 1031 if ((flags & NFE_TX_ERROR_V2) != 0) { 1032 snprintb(buf, sizeof(buf), NFE_V2_TXERR, flags); 1033 aprint_error_dev(sc->sc_dev, "tx v2 error %s\n", 1034 buf); 1035 ifp->if_oerrors++; 1036 } else 1037 ifp->if_opackets++; 1038 } 1039 1040 if (data->m == NULL) { /* should not get there */ 1041 aprint_error_dev(sc->sc_dev, 1042 "last fragment bit w/o associated mbuf!\n"); 1043 continue; 1044 } 1045 1046 /* last fragment of the mbuf chain transmitted */ 1047 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1048 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1049 bus_dmamap_unload(sc->sc_dmat, data->active); 1050 m_freem(data->m); 1051 data->m = NULL; 1052 } 1053 1054 sc->txq.next = i; 1055 1056 if (sc->txq.queued < NFE_TX_RING_COUNT) { 1057 /* at least one slot freed */ 1058 ifp->if_flags &= ~IFF_OACTIVE; 1059 } 1060 1061 if (sc->txq.queued == 0) { 1062 /* all queued packets are sent */ 1063 ifp->if_timer = 0; 1064 } 1065 } 1066 1067 int 1068 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 1069 { 1070 struct nfe_desc32 *desc32; 1071 struct nfe_desc64 *desc64; 1072 struct nfe_tx_data *data; 1073 bus_dmamap_t map; 1074 uint16_t flags, csumflags; 1075 #if NVLAN > 0 1076 uint32_t vtag = 0; 1077 #endif 1078 int error, i, first; 1079 1080 desc32 = NULL; 1081 desc64 = NULL; 1082 data = NULL; 1083 1084 flags = 0; 1085 csumflags = 0; 1086 first = sc->txq.cur; 1087 1088 map = sc->txq.data[first].map; 1089 1090 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1091 if (error != 0) { 1092 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1093 error); 1094 return error; 1095 } 1096 1097 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1098 bus_dmamap_unload(sc->sc_dmat, map); 1099 return ENOBUFS; 1100 } 1101 1102 #if NVLAN > 0 1103 /* setup h/w VLAN tagging */ 1104 if (vlan_has_tag(m0)) 1105 vtag = NFE_TX_VTAG | vlan_get_tag(m0); 1106 #endif 1107 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1108 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1109 csumflags |= NFE_TX_IP_CSUM; 1110 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1111 csumflags |= NFE_TX_TCP_UDP_CSUM; 1112 } 1113 1114 for (i = 0; i < map->dm_nsegs; i++) { 1115 data = &sc->txq.data[sc->txq.cur]; 1116 1117 if (sc->sc_flags & NFE_40BIT_ADDR) { 1118 desc64 = &sc->txq.desc64[sc->txq.cur]; 1119 #if defined(__LP64__) 1120 desc64->physaddr[0] = 1121 htole32(map->dm_segs[i].ds_addr >> 32); 1122 #endif 1123 desc64->physaddr[1] = 1124 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1125 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1126 desc64->flags = htole16(flags); 1127 desc64->vtag = 0; 1128 } else { 1129 desc32 = &sc->txq.desc32[sc->txq.cur]; 1130 1131 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1132 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1133 desc32->flags = htole16(flags); 1134 } 1135 1136 /* 1137 * Setting of the valid bit in the first descriptor is 1138 * deferred until the whole chain is fully setup. 1139 */ 1140 flags |= NFE_TX_VALID; 1141 1142 sc->txq.queued++; 1143 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1144 } 1145 1146 /* the whole mbuf chain has been setup */ 1147 if (sc->sc_flags & NFE_40BIT_ADDR) { 1148 /* fix last descriptor */ 1149 flags |= NFE_TX_LASTFRAG_V2; 1150 desc64->flags = htole16(flags); 1151 1152 /* Checksum flags and vtag belong to the first fragment only. */ 1153 #if NVLAN > 0 1154 sc->txq.desc64[first].vtag = htole32(vtag); 1155 #endif 1156 sc->txq.desc64[first].flags |= htole16(csumflags); 1157 1158 /* finally, set the valid bit in the first descriptor */ 1159 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1160 } else { 1161 /* fix last descriptor */ 1162 if (sc->sc_flags & NFE_JUMBO_SUP) 1163 flags |= NFE_TX_LASTFRAG_V2; 1164 else 1165 flags |= NFE_TX_LASTFRAG_V1; 1166 desc32->flags = htole16(flags); 1167 1168 /* Checksum flags belong to the first fragment only. */ 1169 sc->txq.desc32[first].flags |= htole16(csumflags); 1170 1171 /* finally, set the valid bit in the first descriptor */ 1172 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1173 } 1174 1175 data->m = m0; 1176 data->active = map; 1177 1178 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1179 BUS_DMASYNC_PREWRITE); 1180 1181 return 0; 1182 } 1183 1184 void 1185 nfe_start(struct ifnet *ifp) 1186 { 1187 struct nfe_softc *sc = ifp->if_softc; 1188 int old = sc->txq.queued; 1189 struct mbuf *m0; 1190 1191 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1192 return; 1193 1194 for (;;) { 1195 IFQ_POLL(&ifp->if_snd, m0); 1196 if (m0 == NULL) 1197 break; 1198 1199 if (nfe_encap(sc, m0) != 0) { 1200 ifp->if_flags |= IFF_OACTIVE; 1201 break; 1202 } 1203 1204 /* packet put in h/w queue, remove from s/w queue */ 1205 IFQ_DEQUEUE(&ifp->if_snd, m0); 1206 1207 bpf_mtap(ifp, m0, BPF_D_OUT); 1208 } 1209 1210 if (sc->txq.queued != old) { 1211 /* packets are queued */ 1212 if (sc->sc_flags & NFE_40BIT_ADDR) 1213 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1214 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1215 else 1216 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1217 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1218 /* kick Tx */ 1219 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1220 1221 /* 1222 * Set a timeout in case the chip goes out to lunch. 1223 */ 1224 ifp->if_timer = 5; 1225 } 1226 } 1227 1228 void 1229 nfe_watchdog(struct ifnet *ifp) 1230 { 1231 struct nfe_softc *sc = ifp->if_softc; 1232 1233 aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1234 1235 ifp->if_flags &= ~IFF_RUNNING; 1236 nfe_init(ifp); 1237 1238 ifp->if_oerrors++; 1239 } 1240 1241 int 1242 nfe_init(struct ifnet *ifp) 1243 { 1244 struct nfe_softc *sc = ifp->if_softc; 1245 uint32_t tmp; 1246 int rc = 0, s; 1247 1248 if (ifp->if_flags & IFF_RUNNING) 1249 return 0; 1250 1251 nfe_stop(ifp, 0); 1252 1253 NFE_WRITE(sc, NFE_TX_UNK, 0); 1254 NFE_WRITE(sc, NFE_STATUS, 0); 1255 1256 sc->rxtxctl = NFE_RXTX_BIT2; 1257 if (sc->sc_flags & NFE_40BIT_ADDR) 1258 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1259 else if (sc->sc_flags & NFE_JUMBO_SUP) 1260 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1261 if (sc->sc_flags & NFE_HW_CSUM) 1262 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1263 #if NVLAN > 0 1264 /* 1265 * Although the adapter is capable of stripping VLAN tags from received 1266 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1267 * purpose. This will be done in software by our network stack. 1268 */ 1269 if (sc->sc_flags & NFE_HW_VLAN) 1270 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1271 #endif 1272 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1273 DELAY(10); 1274 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1275 1276 #if NVLAN 1277 if (sc->sc_flags & NFE_HW_VLAN) 1278 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1279 #endif 1280 1281 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1282 1283 /* set MAC address */ 1284 nfe_set_macaddr(sc, sc->sc_enaddr); 1285 1286 /* tell MAC where rings are in memory */ 1287 #ifdef __LP64__ 1288 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1289 #endif 1290 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1291 #ifdef __LP64__ 1292 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1293 #endif 1294 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1295 1296 NFE_WRITE(sc, NFE_RING_SIZE, 1297 (NFE_RX_RING_COUNT - 1) << 16 | 1298 (NFE_TX_RING_COUNT - 1)); 1299 1300 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1301 1302 /* force MAC to wakeup */ 1303 tmp = NFE_READ(sc, NFE_PWR_STATE); 1304 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1305 DELAY(10); 1306 tmp = NFE_READ(sc, NFE_PWR_STATE); 1307 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1308 1309 s = splnet(); 1310 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1311 nfe_intr(sc); /* XXX clear IRQ status registers */ 1312 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1313 splx(s); 1314 1315 #if 1 1316 /* configure interrupts coalescing/mitigation */ 1317 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1318 #else 1319 /* no interrupt mitigation: one interrupt per packet */ 1320 NFE_WRITE(sc, NFE_IMTIMER, 970); 1321 #endif 1322 1323 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1324 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1325 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1326 1327 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1328 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1329 1330 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1331 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_ENABLE); 1332 1333 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1334 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1335 DELAY(10); 1336 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1337 1338 /* set Rx filter */ 1339 nfe_setmulti(sc); 1340 1341 if ((rc = ether_mediachange(ifp)) != 0) 1342 goto out; 1343 1344 nfe_tick(sc); 1345 1346 /* enable Rx */ 1347 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1348 1349 /* enable Tx */ 1350 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1351 1352 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1353 1354 /* enable interrupts */ 1355 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1356 1357 callout_schedule(&sc->sc_tick_ch, hz); 1358 1359 ifp->if_flags |= IFF_RUNNING; 1360 ifp->if_flags &= ~IFF_OACTIVE; 1361 1362 out: 1363 return rc; 1364 } 1365 1366 void 1367 nfe_stop(struct ifnet *ifp, int disable) 1368 { 1369 struct nfe_softc *sc = ifp->if_softc; 1370 1371 callout_stop(&sc->sc_tick_ch); 1372 1373 ifp->if_timer = 0; 1374 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1375 1376 mii_down(&sc->sc_mii); 1377 1378 /* abort Tx */ 1379 NFE_WRITE(sc, NFE_TX_CTL, 0); 1380 1381 /* disable Rx */ 1382 NFE_WRITE(sc, NFE_RX_CTL, 0); 1383 1384 /* disable interrupts */ 1385 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1386 1387 /* reset Tx and Rx rings */ 1388 nfe_reset_tx_ring(sc, &sc->txq); 1389 nfe_reset_rx_ring(sc, &sc->rxq); 1390 } 1391 1392 int 1393 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1394 { 1395 struct nfe_desc32 *desc32; 1396 struct nfe_desc64 *desc64; 1397 struct nfe_rx_data *data; 1398 struct nfe_jbuf *jbuf; 1399 void **desc; 1400 bus_addr_t physaddr; 1401 int i, nsegs, error, descsize; 1402 1403 if (sc->sc_flags & NFE_40BIT_ADDR) { 1404 desc = (void **)&ring->desc64; 1405 descsize = sizeof (struct nfe_desc64); 1406 } else { 1407 desc = (void **)&ring->desc32; 1408 descsize = sizeof (struct nfe_desc32); 1409 } 1410 1411 ring->cur = ring->next = 0; 1412 ring->bufsz = MCLBYTES; 1413 1414 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1415 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1416 if (error != 0) { 1417 aprint_error_dev(sc->sc_dev, 1418 "could not create desc DMA map\n"); 1419 ring->map = NULL; 1420 goto fail; 1421 } 1422 1423 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1424 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1425 if (error != 0) { 1426 aprint_error_dev(sc->sc_dev, 1427 "could not allocate DMA memory\n"); 1428 goto fail; 1429 } 1430 1431 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1432 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1433 if (error != 0) { 1434 aprint_error_dev(sc->sc_dev, 1435 "could not map desc DMA memory\n"); 1436 goto fail; 1437 } 1438 1439 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1440 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1441 if (error != 0) { 1442 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1443 goto fail; 1444 } 1445 1446 memset(*desc, 0, NFE_RX_RING_COUNT * descsize); 1447 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1448 1449 if (sc->sc_flags & NFE_USE_JUMBO) { 1450 ring->bufsz = NFE_JBYTES; 1451 if ((error = nfe_jpool_alloc(sc)) != 0) { 1452 aprint_error_dev(sc->sc_dev, 1453 "could not allocate jumbo frames\n"); 1454 goto fail; 1455 } 1456 } 1457 1458 /* 1459 * Pre-allocate Rx buffers and populate Rx ring. 1460 */ 1461 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1462 data = &sc->rxq.data[i]; 1463 1464 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1465 if (data->m == NULL) { 1466 aprint_error_dev(sc->sc_dev, 1467 "could not allocate rx mbuf\n"); 1468 error = ENOMEM; 1469 goto fail; 1470 } 1471 1472 if (sc->sc_flags & NFE_USE_JUMBO) { 1473 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1474 aprint_error_dev(sc->sc_dev, 1475 "could not allocate jumbo buffer\n"); 1476 goto fail; 1477 } 1478 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1479 sc); 1480 1481 physaddr = jbuf->physaddr; 1482 } else { 1483 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1484 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1485 if (error != 0) { 1486 aprint_error_dev(sc->sc_dev, 1487 "could not create DMA map\n"); 1488 data->map = NULL; 1489 goto fail; 1490 } 1491 MCLGET(data->m, M_DONTWAIT); 1492 if (!(data->m->m_flags & M_EXT)) { 1493 aprint_error_dev(sc->sc_dev, 1494 "could not allocate mbuf cluster\n"); 1495 error = ENOMEM; 1496 goto fail; 1497 } 1498 1499 error = bus_dmamap_load(sc->sc_dmat, data->map, 1500 mtod(data->m, void *), MCLBYTES, NULL, 1501 BUS_DMA_READ | BUS_DMA_NOWAIT); 1502 if (error != 0) { 1503 aprint_error_dev(sc->sc_dev, 1504 "could not load rx buf DMA map"); 1505 goto fail; 1506 } 1507 physaddr = data->map->dm_segs[0].ds_addr; 1508 } 1509 1510 if (sc->sc_flags & NFE_40BIT_ADDR) { 1511 desc64 = &sc->rxq.desc64[i]; 1512 #if defined(__LP64__) 1513 desc64->physaddr[0] = htole32(physaddr >> 32); 1514 #endif 1515 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1516 desc64->length = htole16(sc->rxq.bufsz); 1517 desc64->flags = htole16(NFE_RX_READY); 1518 } else { 1519 desc32 = &sc->rxq.desc32[i]; 1520 desc32->physaddr = htole32(physaddr); 1521 desc32->length = htole16(sc->rxq.bufsz); 1522 desc32->flags = htole16(NFE_RX_READY); 1523 } 1524 } 1525 1526 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1527 BUS_DMASYNC_PREWRITE); 1528 1529 return 0; 1530 1531 fail: nfe_free_rx_ring(sc, ring); 1532 return error; 1533 } 1534 1535 void 1536 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1537 { 1538 int i; 1539 1540 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1541 if (sc->sc_flags & NFE_40BIT_ADDR) { 1542 ring->desc64[i].length = htole16(ring->bufsz); 1543 ring->desc64[i].flags = htole16(NFE_RX_READY); 1544 } else { 1545 ring->desc32[i].length = htole16(ring->bufsz); 1546 ring->desc32[i].flags = htole16(NFE_RX_READY); 1547 } 1548 } 1549 1550 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1551 BUS_DMASYNC_PREWRITE); 1552 1553 ring->cur = ring->next = 0; 1554 } 1555 1556 void 1557 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1558 { 1559 struct nfe_rx_data *data; 1560 void *desc; 1561 int i, descsize; 1562 1563 if (sc->sc_flags & NFE_40BIT_ADDR) { 1564 desc = ring->desc64; 1565 descsize = sizeof (struct nfe_desc64); 1566 } else { 1567 desc = ring->desc32; 1568 descsize = sizeof (struct nfe_desc32); 1569 } 1570 1571 if (desc != NULL) { 1572 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1573 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1574 bus_dmamap_unload(sc->sc_dmat, ring->map); 1575 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1576 NFE_RX_RING_COUNT * descsize); 1577 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1578 } 1579 1580 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1581 data = &ring->data[i]; 1582 1583 if (data->map != NULL) { 1584 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1585 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1586 bus_dmamap_unload(sc->sc_dmat, data->map); 1587 bus_dmamap_destroy(sc->sc_dmat, data->map); 1588 } 1589 if (data->m != NULL) 1590 m_freem(data->m); 1591 } 1592 1593 nfe_jpool_free(sc); 1594 } 1595 1596 struct nfe_jbuf * 1597 nfe_jalloc(struct nfe_softc *sc, int i) 1598 { 1599 struct nfe_jbuf *jbuf; 1600 1601 mutex_enter(&sc->rxq.mtx); 1602 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1603 if (jbuf != NULL) 1604 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1605 mutex_exit(&sc->rxq.mtx); 1606 if (jbuf == NULL) 1607 return NULL; 1608 sc->rxq.jbufmap[i] = 1609 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1610 return jbuf; 1611 } 1612 1613 /* 1614 * This is called automatically by the network stack when the mbuf is freed. 1615 * Caution must be taken that the NIC might be reset by the time the mbuf is 1616 * freed. 1617 */ 1618 void 1619 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1620 { 1621 struct nfe_softc *sc = arg; 1622 struct nfe_jbuf *jbuf; 1623 int i; 1624 1625 /* find the jbuf from the base pointer */ 1626 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1627 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1628 aprint_error_dev(sc->sc_dev, 1629 "request to free a buffer (%p) not managed by us\n", buf); 1630 return; 1631 } 1632 jbuf = &sc->rxq.jbuf[i]; 1633 1634 /* ..and put it back in the free list */ 1635 mutex_enter(&sc->rxq.mtx); 1636 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1637 mutex_exit(&sc->rxq.mtx); 1638 1639 if (m != NULL) 1640 pool_cache_put(mb_cache, m); 1641 } 1642 1643 int 1644 nfe_jpool_alloc(struct nfe_softc *sc) 1645 { 1646 struct nfe_rx_ring *ring = &sc->rxq; 1647 struct nfe_jbuf *jbuf; 1648 bus_addr_t physaddr; 1649 char *buf; 1650 int i, nsegs, error; 1651 1652 /* 1653 * Allocate a big chunk of DMA'able memory. 1654 */ 1655 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1656 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1657 if (error != 0) { 1658 aprint_error_dev(sc->sc_dev, 1659 "could not create jumbo DMA map\n"); 1660 ring->jmap = NULL; 1661 goto fail; 1662 } 1663 1664 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1665 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1666 if (error != 0) { 1667 aprint_error_dev(sc->sc_dev, 1668 "could not allocate jumbo DMA memory\n"); 1669 goto fail; 1670 } 1671 1672 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1673 &ring->jpool, BUS_DMA_NOWAIT); 1674 if (error != 0) { 1675 aprint_error_dev(sc->sc_dev, 1676 "could not map jumbo DMA memory\n"); 1677 goto fail; 1678 } 1679 1680 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1681 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1682 if (error != 0) { 1683 aprint_error_dev(sc->sc_dev, 1684 "could not load jumbo DMA map\n"); 1685 goto fail; 1686 } 1687 1688 /* ..and split it into 9KB chunks */ 1689 SLIST_INIT(&ring->jfreelist); 1690 1691 buf = ring->jpool; 1692 physaddr = ring->jmap->dm_segs[0].ds_addr; 1693 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1694 jbuf = &ring->jbuf[i]; 1695 1696 jbuf->buf = buf; 1697 jbuf->physaddr = physaddr; 1698 1699 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1700 1701 buf += NFE_JBYTES; 1702 physaddr += NFE_JBYTES; 1703 } 1704 1705 return 0; 1706 1707 fail: nfe_jpool_free(sc); 1708 return error; 1709 } 1710 1711 void 1712 nfe_jpool_free(struct nfe_softc *sc) 1713 { 1714 struct nfe_rx_ring *ring = &sc->rxq; 1715 1716 if (ring->jmap != NULL) { 1717 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1718 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1719 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1720 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1721 ring->jmap = NULL; 1722 } 1723 if (ring->jpool != NULL) { 1724 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1725 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1726 ring->jpool = NULL; 1727 } 1728 } 1729 1730 int 1731 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1732 { 1733 int i, nsegs, error; 1734 void **desc; 1735 int descsize; 1736 1737 if (sc->sc_flags & NFE_40BIT_ADDR) { 1738 desc = (void **)&ring->desc64; 1739 descsize = sizeof (struct nfe_desc64); 1740 } else { 1741 desc = (void **)&ring->desc32; 1742 descsize = sizeof (struct nfe_desc32); 1743 } 1744 1745 ring->queued = 0; 1746 ring->cur = ring->next = 0; 1747 1748 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1749 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1750 1751 if (error != 0) { 1752 aprint_error_dev(sc->sc_dev, 1753 "could not create desc DMA map\n"); 1754 ring->map = NULL; 1755 goto fail; 1756 } 1757 1758 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1759 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1760 if (error != 0) { 1761 aprint_error_dev(sc->sc_dev, 1762 "could not allocate DMA memory\n"); 1763 goto fail; 1764 } 1765 1766 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1767 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1768 if (error != 0) { 1769 aprint_error_dev(sc->sc_dev, 1770 "could not map desc DMA memory\n"); 1771 goto fail; 1772 } 1773 1774 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1775 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1776 if (error != 0) { 1777 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1778 goto fail; 1779 } 1780 1781 memset(*desc, 0, NFE_TX_RING_COUNT * descsize); 1782 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1783 1784 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1785 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1786 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1787 &ring->data[i].map); 1788 if (error != 0) { 1789 aprint_error_dev(sc->sc_dev, 1790 "could not create DMA map\n"); 1791 ring->data[i].map = NULL; 1792 goto fail; 1793 } 1794 } 1795 1796 return 0; 1797 1798 fail: nfe_free_tx_ring(sc, ring); 1799 return error; 1800 } 1801 1802 void 1803 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1804 { 1805 struct nfe_tx_data *data; 1806 int i; 1807 1808 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1809 if (sc->sc_flags & NFE_40BIT_ADDR) 1810 ring->desc64[i].flags = 0; 1811 else 1812 ring->desc32[i].flags = 0; 1813 1814 data = &ring->data[i]; 1815 1816 if (data->m != NULL) { 1817 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1818 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1819 bus_dmamap_unload(sc->sc_dmat, data->active); 1820 m_freem(data->m); 1821 data->m = NULL; 1822 } 1823 } 1824 1825 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1826 BUS_DMASYNC_PREWRITE); 1827 1828 ring->queued = 0; 1829 ring->cur = ring->next = 0; 1830 } 1831 1832 void 1833 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1834 { 1835 struct nfe_tx_data *data; 1836 void *desc; 1837 int i, descsize; 1838 1839 if (sc->sc_flags & NFE_40BIT_ADDR) { 1840 desc = ring->desc64; 1841 descsize = sizeof (struct nfe_desc64); 1842 } else { 1843 desc = ring->desc32; 1844 descsize = sizeof (struct nfe_desc32); 1845 } 1846 1847 if (desc != NULL) { 1848 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1849 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1850 bus_dmamap_unload(sc->sc_dmat, ring->map); 1851 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1852 NFE_TX_RING_COUNT * descsize); 1853 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1854 } 1855 1856 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1857 data = &ring->data[i]; 1858 1859 if (data->m != NULL) { 1860 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1861 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1862 bus_dmamap_unload(sc->sc_dmat, data->active); 1863 m_freem(data->m); 1864 } 1865 } 1866 1867 /* ..and now actually destroy the DMA mappings */ 1868 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1869 data = &ring->data[i]; 1870 if (data->map == NULL) 1871 continue; 1872 bus_dmamap_destroy(sc->sc_dmat, data->map); 1873 } 1874 } 1875 1876 void 1877 nfe_setmulti(struct nfe_softc *sc) 1878 { 1879 struct ethercom *ec = &sc->sc_ethercom; 1880 struct ifnet *ifp = &ec->ec_if; 1881 struct ether_multi *enm; 1882 struct ether_multistep step; 1883 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1884 uint32_t filter = NFE_RXFILTER_MAGIC; 1885 int i; 1886 1887 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1888 memset(addr, 0, ETHER_ADDR_LEN); 1889 memset(mask, 0, ETHER_ADDR_LEN); 1890 goto done; 1891 } 1892 1893 memcpy(addr, etherbroadcastaddr, ETHER_ADDR_LEN); 1894 memcpy(mask, etherbroadcastaddr, ETHER_ADDR_LEN); 1895 1896 ETHER_FIRST_MULTI(step, ec, enm); 1897 while (enm != NULL) { 1898 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1899 ifp->if_flags |= IFF_ALLMULTI; 1900 memset(addr, 0, ETHER_ADDR_LEN); 1901 memset(mask, 0, ETHER_ADDR_LEN); 1902 goto done; 1903 } 1904 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1905 addr[i] &= enm->enm_addrlo[i]; 1906 mask[i] &= ~enm->enm_addrlo[i]; 1907 } 1908 ETHER_NEXT_MULTI(step, enm); 1909 } 1910 for (i = 0; i < ETHER_ADDR_LEN; i++) 1911 mask[i] |= addr[i]; 1912 1913 done: 1914 addr[0] |= 0x01; /* make sure multicast bit is set */ 1915 1916 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1917 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1918 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1919 addr[5] << 8 | addr[4]); 1920 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1921 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1922 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1923 mask[5] << 8 | mask[4]); 1924 1925 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1926 NFE_WRITE(sc, NFE_RXFILTER, filter); 1927 } 1928 1929 void 1930 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1931 { 1932 uint32_t tmp; 1933 1934 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 1935 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1936 addr[0] = (tmp & 0xff); 1937 addr[1] = (tmp >> 8) & 0xff; 1938 addr[2] = (tmp >> 16) & 0xff; 1939 addr[3] = (tmp >> 24) & 0xff; 1940 1941 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1942 addr[4] = (tmp & 0xff); 1943 addr[5] = (tmp >> 8) & 0xff; 1944 1945 } else { 1946 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1947 addr[0] = (tmp >> 8) & 0xff; 1948 addr[1] = (tmp & 0xff); 1949 1950 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1951 addr[2] = (tmp >> 24) & 0xff; 1952 addr[3] = (tmp >> 16) & 0xff; 1953 addr[4] = (tmp >> 8) & 0xff; 1954 addr[5] = (tmp & 0xff); 1955 } 1956 } 1957 1958 void 1959 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1960 { 1961 NFE_WRITE(sc, NFE_MACADDR_LO, 1962 addr[5] << 8 | addr[4]); 1963 NFE_WRITE(sc, NFE_MACADDR_HI, 1964 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1965 } 1966 1967 void 1968 nfe_tick(void *arg) 1969 { 1970 struct nfe_softc *sc = arg; 1971 int s; 1972 1973 s = splnet(); 1974 mii_tick(&sc->sc_mii); 1975 splx(s); 1976 1977 callout_schedule(&sc->sc_tick_ch, hz); 1978 } 1979 1980 void 1981 nfe_poweron(device_t self) 1982 { 1983 struct nfe_softc *sc = device_private(self); 1984 1985 if ((sc->sc_flags & NFE_PWR_MGMT) != 0) { 1986 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 1987 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 1988 DELAY(100); 1989 NFE_WRITE(sc, NFE_MAC_RESET, 0); 1990 DELAY(100); 1991 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 1992 NFE_WRITE(sc, NFE_PWR2_CTL, 1993 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_WAKEUP_MASK); 1994 } 1995 } 1996 1997 bool 1998 nfe_resume(device_t dv, const pmf_qual_t *qual) 1999 { 2000 nfe_poweron(dv); 2001 2002 return true; 2003 } 2004
Indexes created Tue Sep 30 11:09:46 GMT 2025