if_nfe.c revision 1.67
1 /* $NetBSD: if_nfe.c,v 1.67 2019/01/22 03:42:27 msaitoh Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.77 2008/02/05 16:52:50 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006, 2007 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.67 2019/01/22 03:42:27 msaitoh Exp $"); 25 26 #include "opt_inet.h" 27 #include "vlan.h" 28 29 #include <sys/param.h> 30 #include <sys/endian.h> 31 #include <sys/systm.h> 32 #include <sys/types.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/mutex.h> 36 #include <sys/queue.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/callout.h> 40 #include <sys/socket.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #include <net/bpf.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_nfereg.h> 72 #include <dev/pci/if_nfevar.h> 73 74 static int nfe_ifflags_cb(struct ethercom *); 75 76 int nfe_match(device_t, cfdata_t, void *); 77 void nfe_attach(device_t, device_t, void *); 78 int nfe_detach(device_t, int); 79 void nfe_power(int, void *); 80 void nfe_miibus_statchg(struct ifnet *); 81 int nfe_miibus_readreg(device_t, int, int, uint16_t *); 82 int nfe_miibus_writereg(device_t, int, int, uint16_t); 83 int nfe_intr(void *); 84 int nfe_ioctl(struct ifnet *, u_long, void *); 85 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 86 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 87 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 88 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 89 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 90 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 91 void nfe_rxeof(struct nfe_softc *); 92 void nfe_txeof(struct nfe_softc *); 93 int nfe_encap(struct nfe_softc *, struct mbuf *); 94 void nfe_start(struct ifnet *); 95 void nfe_watchdog(struct ifnet *); 96 int nfe_init(struct ifnet *); 97 void nfe_stop(struct ifnet *, int); 98 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 99 void nfe_jfree(struct mbuf *, void *, size_t, void *); 100 int nfe_jpool_alloc(struct nfe_softc *); 101 void nfe_jpool_free(struct nfe_softc *); 102 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 105 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 108 void nfe_setmulti(struct nfe_softc *); 109 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 110 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 111 void nfe_tick(void *); 112 void nfe_poweron(device_t); 113 bool nfe_resume(device_t, const pmf_qual_t *); 114 115 CFATTACH_DECL_NEW(nfe, sizeof(struct nfe_softc), 116 nfe_match, nfe_attach, nfe_detach, NULL); 117 118 /* #define NFE_NO_JUMBO */ 119 120 #ifdef NFE_DEBUG 121 int nfedebug = 0; 122 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 123 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 124 #else 125 #define DPRINTF(x) 126 #define DPRINTFN(n,x) 127 #endif 128 129 /* deal with naming differences */ 130 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 134 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 135 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 136 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 137 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 140 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 141 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 142 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 145 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 146 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 147 148 #ifdef _LP64 149 #define __LP64__ 1 150 #endif 151 152 const struct nfe_product { 153 pci_vendor_id_t vendor; 154 pci_product_id_t product; 155 } nfe_devices[] = { 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 183 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 184 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 185 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 186 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 }, 187 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1 }, 188 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2 }, 189 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3 }, 190 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4 }, 191 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1 }, 192 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2 }, 193 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3 }, 194 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4 } 195 }; 196 197 int 198 nfe_match(device_t dev, cfdata_t match, void *aux) 199 { 200 struct pci_attach_args *pa = aux; 201 const struct nfe_product *np; 202 int i; 203 204 for (i = 0; i < __arraycount(nfe_devices); i++) { 205 np = &nfe_devices[i]; 206 if (PCI_VENDOR(pa->pa_id) == np->vendor && 207 PCI_PRODUCT(pa->pa_id) == np->product) 208 return 1; 209 } 210 return 0; 211 } 212 213 void 214 nfe_attach(device_t parent, device_t self, void *aux) 215 { 216 struct nfe_softc *sc = device_private(self); 217 struct pci_attach_args *pa = aux; 218 pci_chipset_tag_t pc = pa->pa_pc; 219 pci_intr_handle_t ih; 220 const char *intrstr; 221 struct ifnet *ifp; 222 pcireg_t memtype, csr; 223 int mii_flags = 0; 224 char intrbuf[PCI_INTRSTR_LEN]; 225 226 sc->sc_dev = self; 227 sc->sc_pc = pa->pa_pc; 228 pci_aprint_devinfo(pa, NULL); 229 230 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 231 switch (memtype) { 232 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 233 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 234 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 235 &sc->sc_memh, NULL, &sc->sc_mems) == 0) 236 break; 237 /* FALLTHROUGH */ 238 default: 239 aprint_error_dev(self, "could not map mem space\n"); 240 return; 241 } 242 243 if (pci_intr_map(pa, &ih) != 0) { 244 aprint_error_dev(self, "could not map interrupt\n"); 245 goto fail; 246 } 247 248 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 249 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, nfe_intr, sc, 250 device_xname(self)); 251 if (sc->sc_ih == NULL) { 252 aprint_error_dev(self, "could not establish interrupt"); 253 if (intrstr != NULL) 254 aprint_error(" at %s", intrstr); 255 aprint_error("\n"); 256 goto fail; 257 } 258 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 259 260 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 261 csr |= PCI_COMMAND_MASTER_ENABLE; 262 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 263 264 sc->sc_flags = 0; 265 266 switch (PCI_PRODUCT(pa->pa_id)) { 267 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 268 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 269 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 270 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 271 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 272 break; 273 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 274 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 275 sc->sc_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT; 276 break; 277 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 278 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 279 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 280 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 281 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 282 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 283 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 284 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 285 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 286 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 287 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 288 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 289 sc->sc_flags |= NFE_40BIT_ADDR | NFE_CORRECT_MACADDR | 290 NFE_PWR_MGMT; 291 break; 292 case PCI_PRODUCT_NVIDIA_MCP77_LAN1: 293 case PCI_PRODUCT_NVIDIA_MCP77_LAN2: 294 case PCI_PRODUCT_NVIDIA_MCP77_LAN3: 295 case PCI_PRODUCT_NVIDIA_MCP77_LAN4: 296 sc->sc_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | 297 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 298 break; 299 case PCI_PRODUCT_NVIDIA_MCP79_LAN1: 300 case PCI_PRODUCT_NVIDIA_MCP79_LAN2: 301 case PCI_PRODUCT_NVIDIA_MCP79_LAN3: 302 case PCI_PRODUCT_NVIDIA_MCP79_LAN4: 303 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 304 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 305 break; 306 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 307 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 308 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 309 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 310 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 311 break; 312 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 313 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 314 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 315 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 316 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 317 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 318 mii_flags = MIIF_DOPAUSE; 319 break; 320 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 321 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 322 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 323 NFE_HW_VLAN | NFE_PWR_MGMT; 324 break; 325 } 326 327 if (pci_dma64_available(pa) && (sc->sc_flags & NFE_40BIT_ADDR) != 0) 328 sc->sc_dmat = pa->pa_dmat64; 329 else 330 sc->sc_dmat = pa->pa_dmat; 331 332 nfe_poweron(self); 333 334 #ifndef NFE_NO_JUMBO 335 /* enable jumbo frames for adapters that support it */ 336 if (sc->sc_flags & NFE_JUMBO_SUP) 337 sc->sc_flags |= NFE_USE_JUMBO; 338 #endif 339 340 /* Check for reversed ethernet address */ 341 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 342 sc->sc_flags |= NFE_CORRECT_MACADDR; 343 344 nfe_get_macaddr(sc, sc->sc_enaddr); 345 aprint_normal_dev(self, "Ethernet address %s\n", 346 ether_sprintf(sc->sc_enaddr)); 347 348 /* 349 * Allocate Tx and Rx rings. 350 */ 351 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 352 aprint_error_dev(self, "could not allocate Tx ring\n"); 353 goto fail; 354 } 355 356 mutex_init(&sc->rxq.mtx, MUTEX_DEFAULT, IPL_NET); 357 358 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 359 aprint_error_dev(self, "could not allocate Rx ring\n"); 360 nfe_free_tx_ring(sc, &sc->txq); 361 goto fail; 362 } 363 364 ifp = &sc->sc_ethercom.ec_if; 365 ifp->if_softc = sc; 366 ifp->if_mtu = ETHERMTU; 367 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 368 ifp->if_ioctl = nfe_ioctl; 369 ifp->if_start = nfe_start; 370 ifp->if_stop = nfe_stop; 371 ifp->if_watchdog = nfe_watchdog; 372 ifp->if_init = nfe_init; 373 ifp->if_baudrate = IF_Gbps(1); 374 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 375 IFQ_SET_READY(&ifp->if_snd); 376 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 377 378 if (sc->sc_flags & NFE_USE_JUMBO) 379 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 380 381 #if NVLAN > 0 382 if (sc->sc_flags & NFE_HW_VLAN) 383 sc->sc_ethercom.ec_capabilities |= 384 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 385 #endif 386 if (sc->sc_flags & NFE_HW_CSUM) { 387 ifp->if_capabilities |= 388 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 389 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 390 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 391 } 392 393 sc->sc_mii.mii_ifp = ifp; 394 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 395 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 396 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 397 398 sc->sc_ethercom.ec_mii = &sc->sc_mii; 399 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 400 ether_mediastatus); 401 402 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 0, mii_flags); 403 404 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 405 aprint_error_dev(self, "no PHY found!\n"); 406 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 407 0, NULL); 408 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 409 } else 410 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 411 412 if_attach(ifp); 413 if_deferred_start_init(ifp, NULL); 414 ether_ifattach(ifp, sc->sc_enaddr); 415 ether_set_ifflags_cb(&sc->sc_ethercom, nfe_ifflags_cb); 416 417 callout_init(&sc->sc_tick_ch, 0); 418 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 419 420 if (pmf_device_register(self, NULL, nfe_resume)) 421 pmf_class_network_register(self, ifp); 422 else 423 aprint_error_dev(self, "couldn't establish power handler\n"); 424 425 return; 426 427 fail: 428 if (sc->sc_ih != NULL) { 429 pci_intr_disestablish(pc, sc->sc_ih); 430 sc->sc_ih = NULL; 431 } 432 if (sc->sc_mems != 0) { 433 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 434 sc->sc_mems = 0; 435 } 436 } 437 438 int 439 nfe_detach(device_t self, int flags) 440 { 441 struct nfe_softc *sc = device_private(self); 442 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 443 int s; 444 445 s = splnet(); 446 447 nfe_stop(ifp, 1); 448 449 pmf_device_deregister(self); 450 callout_destroy(&sc->sc_tick_ch); 451 ether_ifdetach(ifp); 452 if_detach(ifp); 453 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 454 455 nfe_free_rx_ring(sc, &sc->rxq); 456 mutex_destroy(&sc->rxq.mtx); 457 nfe_free_tx_ring(sc, &sc->txq); 458 459 if (sc->sc_ih != NULL) { 460 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 461 sc->sc_ih = NULL; 462 } 463 464 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 465 nfe_set_macaddr(sc, sc->sc_enaddr); 466 } else { 467 NFE_WRITE(sc, NFE_MACADDR_LO, 468 sc->sc_enaddr[0] << 8 | sc->sc_enaddr[1]); 469 NFE_WRITE(sc, NFE_MACADDR_HI, 470 sc->sc_enaddr[2] << 24 | sc->sc_enaddr[3] << 16 | 471 sc->sc_enaddr[4] << 8 | sc->sc_enaddr[5]); 472 } 473 474 if (sc->sc_mems != 0) { 475 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 476 sc->sc_mems = 0; 477 } 478 479 splx(s); 480 481 return 0; 482 } 483 484 void 485 nfe_miibus_statchg(struct ifnet *ifp) 486 { 487 struct nfe_softc *sc = ifp->if_softc; 488 struct mii_data *mii = &sc->sc_mii; 489 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 490 491 phy = NFE_READ(sc, NFE_PHY_IFACE); 492 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 493 494 seed = NFE_READ(sc, NFE_RNDSEED); 495 seed &= ~NFE_SEED_MASK; 496 497 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 498 phy |= NFE_PHY_HDX; /* half-duplex */ 499 misc |= NFE_MISC1_HDX; 500 } 501 502 switch (IFM_SUBTYPE(mii->mii_media_active)) { 503 case IFM_1000_T: /* full-duplex only */ 504 link |= NFE_MEDIA_1000T; 505 seed |= NFE_SEED_1000T; 506 phy |= NFE_PHY_1000T; 507 break; 508 case IFM_100_TX: 509 link |= NFE_MEDIA_100TX; 510 seed |= NFE_SEED_100TX; 511 phy |= NFE_PHY_100TX; 512 break; 513 case IFM_10_T: 514 link |= NFE_MEDIA_10T; 515 seed |= NFE_SEED_10T; 516 break; 517 } 518 519 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 520 521 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 522 NFE_WRITE(sc, NFE_MISC1, misc); 523 NFE_WRITE(sc, NFE_LINKSPEED, link); 524 } 525 526 int 527 nfe_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 528 { 529 struct nfe_softc *sc = device_private(dev); 530 uint32_t data; 531 int ntries; 532 533 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 534 535 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 536 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 537 DELAY(100); 538 } 539 540 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 541 542 for (ntries = 0; ntries < 1000; ntries++) { 543 DELAY(100); 544 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 545 break; 546 } 547 if (ntries == 1000) { 548 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 549 device_xname(sc->sc_dev))); 550 return ETIMEDOUT; 551 } 552 553 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 554 DPRINTFN(2, ("%s: could not read PHY\n", 555 device_xname(sc->sc_dev))); 556 return -1; 557 } 558 559 data = NFE_READ(sc, NFE_PHY_DATA); 560 if (data != 0xffffffff && data != 0) 561 sc->mii_phyaddr = phy; 562 563 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x data 0x%x\n", 564 device_xname(sc->sc_dev), phy, reg, data)); 565 566 *val = data & 0x0000ffff; 567 return 0; 568 } 569 570 int 571 nfe_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 572 { 573 struct nfe_softc *sc = device_private(dev); 574 uint32_t ctl; 575 int ntries; 576 577 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 578 579 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 580 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 581 DELAY(100); 582 } 583 584 NFE_WRITE(sc, NFE_PHY_DATA, val); 585 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 586 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 587 588 for (ntries = 0; ntries < 1000; ntries++) { 589 DELAY(100); 590 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 591 break; 592 } 593 if (ntries == 1000) { 594 #ifdef NFE_DEBUG 595 if (nfedebug >= 2) 596 printf("could not write to PHY\n"); 597 #endif 598 return ETIMEDOUT; 599 } 600 return 0; 601 } 602 603 int 604 nfe_intr(void *arg) 605 { 606 struct nfe_softc *sc = arg; 607 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 608 uint32_t r; 609 int handled; 610 611 if ((ifp->if_flags & IFF_UP) == 0) 612 return 0; 613 614 handled = 0; 615 616 for (;;) { 617 r = NFE_READ(sc, NFE_IRQ_STATUS); 618 if ((r & NFE_IRQ_WANTED) == 0) 619 break; 620 621 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 622 handled = 1; 623 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 624 625 if ((r & (NFE_IRQ_RXERR|NFE_IRQ_RX_NOBUF|NFE_IRQ_RX)) != 0) { 626 /* check Rx ring */ 627 nfe_rxeof(sc); 628 } 629 if ((r & (NFE_IRQ_TXERR|NFE_IRQ_TXERR2|NFE_IRQ_TX_DONE)) != 0) { 630 /* check Tx ring */ 631 nfe_txeof(sc); 632 } 633 if ((r & NFE_IRQ_LINK) != 0) { 634 NFE_READ(sc, NFE_PHY_STATUS); 635 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 636 DPRINTF(("%s: link state changed\n", 637 device_xname(sc->sc_dev))); 638 } 639 } 640 641 if (handled) 642 if_schedule_deferred_start(ifp); 643 644 return handled; 645 } 646 647 static int 648 nfe_ifflags_cb(struct ethercom *ec) 649 { 650 struct ifnet *ifp = &ec->ec_if; 651 struct nfe_softc *sc = ifp->if_softc; 652 int change = ifp->if_flags ^ sc->sc_if_flags; 653 654 /* 655 * If only the PROMISC flag changes, then 656 * don't do a full re-init of the chip, just update 657 * the Rx filter. 658 */ 659 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 660 return ENETRESET; 661 else if ((change & IFF_PROMISC) != 0) 662 nfe_setmulti(sc); 663 664 return 0; 665 } 666 667 int 668 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 669 { 670 struct nfe_softc *sc = ifp->if_softc; 671 struct ifaddr *ifa = (struct ifaddr *)data; 672 int s, error = 0; 673 674 s = splnet(); 675 676 switch (cmd) { 677 case SIOCINITIFADDR: 678 ifp->if_flags |= IFF_UP; 679 nfe_init(ifp); 680 switch (ifa->ifa_addr->sa_family) { 681 #ifdef INET 682 case AF_INET: 683 arp_ifinit(ifp, ifa); 684 break; 685 #endif 686 default: 687 break; 688 } 689 break; 690 default: 691 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 692 break; 693 694 error = 0; 695 696 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 697 ; 698 else if (ifp->if_flags & IFF_RUNNING) 699 nfe_setmulti(sc); 700 break; 701 } 702 sc->sc_if_flags = ifp->if_flags; 703 704 splx(s); 705 706 return error; 707 } 708 709 void 710 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 711 { 712 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 713 (char *)desc32 - (char *)sc->txq.desc32, 714 sizeof (struct nfe_desc32), ops); 715 } 716 717 void 718 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 719 { 720 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 721 (char *)desc64 - (char *)sc->txq.desc64, 722 sizeof (struct nfe_desc64), ops); 723 } 724 725 void 726 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 727 { 728 if (end > start) { 729 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 730 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 731 (char *)&sc->txq.desc32[end] - 732 (char *)&sc->txq.desc32[start], ops); 733 return; 734 } 735 /* sync from 'start' to end of ring */ 736 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 737 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 738 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 739 (char *)&sc->txq.desc32[start], ops); 740 741 /* sync from start of ring to 'end' */ 742 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 743 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 744 } 745 746 void 747 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 748 { 749 if (end > start) { 750 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 751 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 752 (char *)&sc->txq.desc64[end] - 753 (char *)&sc->txq.desc64[start], ops); 754 return; 755 } 756 /* sync from 'start' to end of ring */ 757 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 758 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 759 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 760 (char *)&sc->txq.desc64[start], ops); 761 762 /* sync from start of ring to 'end' */ 763 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 764 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 765 } 766 767 void 768 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 769 { 770 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 771 (char *)desc32 - (char *)sc->rxq.desc32, 772 sizeof (struct nfe_desc32), ops); 773 } 774 775 void 776 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 777 { 778 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 779 (char *)desc64 - (char *)sc->rxq.desc64, 780 sizeof (struct nfe_desc64), ops); 781 } 782 783 void 784 nfe_rxeof(struct nfe_softc *sc) 785 { 786 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 787 struct nfe_desc32 *desc32; 788 struct nfe_desc64 *desc64; 789 struct nfe_rx_data *data; 790 struct nfe_jbuf *jbuf; 791 struct mbuf *m, *mnew; 792 bus_addr_t physaddr; 793 uint16_t flags; 794 int error, len, i; 795 796 desc32 = NULL; 797 desc64 = NULL; 798 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 799 data = &sc->rxq.data[i]; 800 801 if (sc->sc_flags & NFE_40BIT_ADDR) { 802 desc64 = &sc->rxq.desc64[i]; 803 nfe_rxdesc64_sync(sc, desc64, 804 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 805 806 flags = le16toh(desc64->flags); 807 len = le16toh(desc64->length) & 0x3fff; 808 } else { 809 desc32 = &sc->rxq.desc32[i]; 810 nfe_rxdesc32_sync(sc, desc32, 811 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 812 813 flags = le16toh(desc32->flags); 814 len = le16toh(desc32->length) & 0x3fff; 815 } 816 817 if ((flags & NFE_RX_READY) != 0) 818 break; 819 820 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 821 if ((flags & NFE_RX_VALID_V1) == 0) 822 goto skip; 823 824 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 825 flags &= ~NFE_RX_ERROR; 826 len--; /* fix buffer length */ 827 } 828 } else { 829 if ((flags & NFE_RX_VALID_V2) == 0) 830 goto skip; 831 832 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 833 flags &= ~NFE_RX_ERROR; 834 len--; /* fix buffer length */ 835 } 836 } 837 838 if (flags & NFE_RX_ERROR) { 839 ifp->if_ierrors++; 840 goto skip; 841 } 842 843 /* 844 * Try to allocate a new mbuf for this ring element and load 845 * it before processing the current mbuf. If the ring element 846 * cannot be loaded, drop the received packet and reuse the 847 * old mbuf. In the unlikely case that the old mbuf can't be 848 * reloaded either, explicitly panic. 849 */ 850 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 851 if (mnew == NULL) { 852 ifp->if_ierrors++; 853 goto skip; 854 } 855 856 if (sc->sc_flags & NFE_USE_JUMBO) { 857 physaddr = 858 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 859 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 860 if (len > MCLBYTES) { 861 m_freem(mnew); 862 ifp->if_ierrors++; 863 goto skip1; 864 } 865 MCLGET(mnew, M_DONTWAIT); 866 if ((mnew->m_flags & M_EXT) == 0) { 867 m_freem(mnew); 868 ifp->if_ierrors++; 869 goto skip1; 870 } 871 872 (void)memcpy(mtod(mnew, void *), 873 mtod(data->m, const void *), len); 874 m = mnew; 875 goto mbufcopied; 876 } else { 877 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 878 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 879 mtod(data->m, char *) - (char *)sc->rxq.jpool, 880 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 881 882 physaddr = jbuf->physaddr; 883 } 884 } else { 885 MCLGET(mnew, M_DONTWAIT); 886 if ((mnew->m_flags & M_EXT) == 0) { 887 m_freem(mnew); 888 ifp->if_ierrors++; 889 goto skip; 890 } 891 892 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 893 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 894 bus_dmamap_unload(sc->sc_dmat, data->map); 895 896 error = bus_dmamap_load(sc->sc_dmat, data->map, 897 mtod(mnew, void *), MCLBYTES, NULL, 898 BUS_DMA_READ | BUS_DMA_NOWAIT); 899 if (error != 0) { 900 m_freem(mnew); 901 902 /* try to reload the old mbuf */ 903 error = bus_dmamap_load(sc->sc_dmat, data->map, 904 mtod(data->m, void *), MCLBYTES, NULL, 905 BUS_DMA_READ | BUS_DMA_NOWAIT); 906 if (error != 0) { 907 /* very unlikely that it will fail.. */ 908 panic("%s: could not load old rx mbuf", 909 device_xname(sc->sc_dev)); 910 } 911 ifp->if_ierrors++; 912 goto skip; 913 } 914 physaddr = data->map->dm_segs[0].ds_addr; 915 } 916 917 /* 918 * New mbuf successfully loaded, update Rx ring and continue 919 * processing. 920 */ 921 m = data->m; 922 data->m = mnew; 923 924 mbufcopied: 925 /* finalize mbuf */ 926 m->m_pkthdr.len = m->m_len = len; 927 m_set_rcvif(m, ifp); 928 929 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 930 /* 931 * XXX 932 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 933 */ 934 if (flags & NFE_RX_IP_CSUMOK) { 935 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 936 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 937 device_xname(sc->sc_dev))); 938 } 939 /* 940 * XXX 941 * no way to check M_CSUM_TCP_UDP_BAD or 942 * other protocols? 943 */ 944 if (flags & NFE_RX_UDP_CSUMOK) { 945 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 946 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 947 device_xname(sc->sc_dev))); 948 } else if (flags & NFE_RX_TCP_CSUMOK) { 949 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 950 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 951 device_xname(sc->sc_dev))); 952 } 953 } 954 if_percpuq_enqueue(ifp->if_percpuq, m); 955 956 skip1: 957 /* update mapping address in h/w descriptor */ 958 if (sc->sc_flags & NFE_40BIT_ADDR) { 959 #if defined(__LP64__) 960 desc64->physaddr[0] = htole32(physaddr >> 32); 961 #endif 962 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 963 } else { 964 desc32->physaddr = htole32(physaddr); 965 } 966 967 skip: 968 if (sc->sc_flags & NFE_40BIT_ADDR) { 969 desc64->length = htole16(sc->rxq.bufsz); 970 desc64->flags = htole16(NFE_RX_READY); 971 972 nfe_rxdesc64_sync(sc, desc64, 973 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 974 } else { 975 desc32->length = htole16(sc->rxq.bufsz); 976 desc32->flags = htole16(NFE_RX_READY); 977 978 nfe_rxdesc32_sync(sc, desc32, 979 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 980 } 981 } 982 /* update current RX pointer */ 983 sc->rxq.cur = i; 984 } 985 986 void 987 nfe_txeof(struct nfe_softc *sc) 988 { 989 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 990 struct nfe_desc32 *desc32; 991 struct nfe_desc64 *desc64; 992 struct nfe_tx_data *data = NULL; 993 int i; 994 uint16_t flags; 995 char buf[128]; 996 997 for (i = sc->txq.next; 998 sc->txq.queued > 0; 999 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 1000 if (sc->sc_flags & NFE_40BIT_ADDR) { 1001 desc64 = &sc->txq.desc64[i]; 1002 nfe_txdesc64_sync(sc, desc64, 1003 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1004 1005 flags = le16toh(desc64->flags); 1006 } else { 1007 desc32 = &sc->txq.desc32[i]; 1008 nfe_txdesc32_sync(sc, desc32, 1009 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1010 1011 flags = le16toh(desc32->flags); 1012 } 1013 1014 if ((flags & NFE_TX_VALID) != 0) 1015 break; 1016 1017 data = &sc->txq.data[i]; 1018 1019 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 1020 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 1021 data->m == NULL) 1022 continue; 1023 1024 if ((flags & NFE_TX_ERROR_V1) != 0) { 1025 snprintb(buf, sizeof(buf), NFE_V1_TXERR, flags); 1026 aprint_error_dev(sc->sc_dev, "tx v1 error %s\n", 1027 buf); 1028 ifp->if_oerrors++; 1029 } else 1030 ifp->if_opackets++; 1031 } else { 1032 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 1033 data->m == NULL) 1034 continue; 1035 1036 if ((flags & NFE_TX_ERROR_V2) != 0) { 1037 snprintb(buf, sizeof(buf), NFE_V2_TXERR, flags); 1038 aprint_error_dev(sc->sc_dev, "tx v2 error %s\n", 1039 buf); 1040 ifp->if_oerrors++; 1041 } else 1042 ifp->if_opackets++; 1043 } 1044 1045 if (data->m == NULL) { /* should not get there */ 1046 aprint_error_dev(sc->sc_dev, 1047 "last fragment bit w/o associated mbuf!\n"); 1048 continue; 1049 } 1050 1051 /* last fragment of the mbuf chain transmitted */ 1052 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1053 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1054 bus_dmamap_unload(sc->sc_dmat, data->active); 1055 m_freem(data->m); 1056 data->m = NULL; 1057 } 1058 1059 sc->txq.next = i; 1060 1061 if (sc->txq.queued < NFE_TX_RING_COUNT) { 1062 /* at least one slot freed */ 1063 ifp->if_flags &= ~IFF_OACTIVE; 1064 } 1065 1066 if (sc->txq.queued == 0) { 1067 /* all queued packets are sent */ 1068 ifp->if_timer = 0; 1069 } 1070 } 1071 1072 int 1073 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 1074 { 1075 struct nfe_desc32 *desc32; 1076 struct nfe_desc64 *desc64; 1077 struct nfe_tx_data *data; 1078 bus_dmamap_t map; 1079 uint16_t flags, csumflags; 1080 #if NVLAN > 0 1081 uint32_t vtag = 0; 1082 #endif 1083 int error, i, first; 1084 1085 desc32 = NULL; 1086 desc64 = NULL; 1087 data = NULL; 1088 1089 flags = 0; 1090 csumflags = 0; 1091 first = sc->txq.cur; 1092 1093 map = sc->txq.data[first].map; 1094 1095 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1096 if (error != 0) { 1097 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1098 error); 1099 return error; 1100 } 1101 1102 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1103 bus_dmamap_unload(sc->sc_dmat, map); 1104 return ENOBUFS; 1105 } 1106 1107 #if NVLAN > 0 1108 /* setup h/w VLAN tagging */ 1109 if (vlan_has_tag(m0)) 1110 vtag = NFE_TX_VTAG | vlan_get_tag(m0); 1111 #endif 1112 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1113 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1114 csumflags |= NFE_TX_IP_CSUM; 1115 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1116 csumflags |= NFE_TX_TCP_UDP_CSUM; 1117 } 1118 1119 for (i = 0; i < map->dm_nsegs; i++) { 1120 data = &sc->txq.data[sc->txq.cur]; 1121 1122 if (sc->sc_flags & NFE_40BIT_ADDR) { 1123 desc64 = &sc->txq.desc64[sc->txq.cur]; 1124 #if defined(__LP64__) 1125 desc64->physaddr[0] = 1126 htole32(map->dm_segs[i].ds_addr >> 32); 1127 #endif 1128 desc64->physaddr[1] = 1129 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1130 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1131 desc64->flags = htole16(flags); 1132 desc64->vtag = 0; 1133 } else { 1134 desc32 = &sc->txq.desc32[sc->txq.cur]; 1135 1136 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1137 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1138 desc32->flags = htole16(flags); 1139 } 1140 1141 /* 1142 * Setting of the valid bit in the first descriptor is 1143 * deferred until the whole chain is fully setup. 1144 */ 1145 flags |= NFE_TX_VALID; 1146 1147 sc->txq.queued++; 1148 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1149 } 1150 1151 /* the whole mbuf chain has been setup */ 1152 if (sc->sc_flags & NFE_40BIT_ADDR) { 1153 /* fix last descriptor */ 1154 flags |= NFE_TX_LASTFRAG_V2; 1155 desc64->flags = htole16(flags); 1156 1157 /* Checksum flags and vtag belong to the first fragment only. */ 1158 #if NVLAN > 0 1159 sc->txq.desc64[first].vtag = htole32(vtag); 1160 #endif 1161 sc->txq.desc64[first].flags |= htole16(csumflags); 1162 1163 /* finally, set the valid bit in the first descriptor */ 1164 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1165 } else { 1166 /* fix last descriptor */ 1167 if (sc->sc_flags & NFE_JUMBO_SUP) 1168 flags |= NFE_TX_LASTFRAG_V2; 1169 else 1170 flags |= NFE_TX_LASTFRAG_V1; 1171 desc32->flags = htole16(flags); 1172 1173 /* Checksum flags belong to the first fragment only. */ 1174 sc->txq.desc32[first].flags |= htole16(csumflags); 1175 1176 /* finally, set the valid bit in the first descriptor */ 1177 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1178 } 1179 1180 data->m = m0; 1181 data->active = map; 1182 1183 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1184 BUS_DMASYNC_PREWRITE); 1185 1186 return 0; 1187 } 1188 1189 void 1190 nfe_start(struct ifnet *ifp) 1191 { 1192 struct nfe_softc *sc = ifp->if_softc; 1193 int old = sc->txq.queued; 1194 struct mbuf *m0; 1195 1196 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1197 return; 1198 1199 for (;;) { 1200 IFQ_POLL(&ifp->if_snd, m0); 1201 if (m0 == NULL) 1202 break; 1203 1204 if (nfe_encap(sc, m0) != 0) { 1205 ifp->if_flags |= IFF_OACTIVE; 1206 break; 1207 } 1208 1209 /* packet put in h/w queue, remove from s/w queue */ 1210 IFQ_DEQUEUE(&ifp->if_snd, m0); 1211 1212 bpf_mtap(ifp, m0, BPF_D_OUT); 1213 } 1214 1215 if (sc->txq.queued != old) { 1216 /* packets are queued */ 1217 if (sc->sc_flags & NFE_40BIT_ADDR) 1218 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1219 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1220 else 1221 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1222 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1223 /* kick Tx */ 1224 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1225 1226 /* 1227 * Set a timeout in case the chip goes out to lunch. 1228 */ 1229 ifp->if_timer = 5; 1230 } 1231 } 1232 1233 void 1234 nfe_watchdog(struct ifnet *ifp) 1235 { 1236 struct nfe_softc *sc = ifp->if_softc; 1237 1238 aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1239 1240 ifp->if_flags &= ~IFF_RUNNING; 1241 nfe_init(ifp); 1242 1243 ifp->if_oerrors++; 1244 } 1245 1246 int 1247 nfe_init(struct ifnet *ifp) 1248 { 1249 struct nfe_softc *sc = ifp->if_softc; 1250 uint32_t tmp; 1251 int rc = 0, s; 1252 1253 if (ifp->if_flags & IFF_RUNNING) 1254 return 0; 1255 1256 nfe_stop(ifp, 0); 1257 1258 NFE_WRITE(sc, NFE_TX_UNK, 0); 1259 NFE_WRITE(sc, NFE_STATUS, 0); 1260 1261 sc->rxtxctl = NFE_RXTX_BIT2; 1262 if (sc->sc_flags & NFE_40BIT_ADDR) 1263 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1264 else if (sc->sc_flags & NFE_JUMBO_SUP) 1265 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1266 if (sc->sc_flags & NFE_HW_CSUM) 1267 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1268 #if NVLAN > 0 1269 /* 1270 * Although the adapter is capable of stripping VLAN tags from received 1271 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1272 * purpose. This will be done in software by our network stack. 1273 */ 1274 if (sc->sc_flags & NFE_HW_VLAN) 1275 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1276 #endif 1277 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1278 DELAY(10); 1279 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1280 1281 #if NVLAN 1282 if (sc->sc_flags & NFE_HW_VLAN) 1283 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1284 #endif 1285 1286 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1287 1288 /* set MAC address */ 1289 nfe_set_macaddr(sc, sc->sc_enaddr); 1290 1291 /* tell MAC where rings are in memory */ 1292 #ifdef __LP64__ 1293 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1294 #endif 1295 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1296 #ifdef __LP64__ 1297 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1298 #endif 1299 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1300 1301 NFE_WRITE(sc, NFE_RING_SIZE, 1302 (NFE_RX_RING_COUNT - 1) << 16 | 1303 (NFE_TX_RING_COUNT - 1)); 1304 1305 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1306 1307 /* force MAC to wakeup */ 1308 tmp = NFE_READ(sc, NFE_PWR_STATE); 1309 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1310 DELAY(10); 1311 tmp = NFE_READ(sc, NFE_PWR_STATE); 1312 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1313 1314 s = splnet(); 1315 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1316 nfe_intr(sc); /* XXX clear IRQ status registers */ 1317 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1318 splx(s); 1319 1320 #if 1 1321 /* configure interrupts coalescing/mitigation */ 1322 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1323 #else 1324 /* no interrupt mitigation: one interrupt per packet */ 1325 NFE_WRITE(sc, NFE_IMTIMER, 970); 1326 #endif 1327 1328 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1329 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1330 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1331 1332 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1333 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1334 1335 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1336 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_ENABLE); 1337 1338 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1339 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1340 DELAY(10); 1341 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1342 1343 /* set Rx filter */ 1344 nfe_setmulti(sc); 1345 1346 if ((rc = ether_mediachange(ifp)) != 0) 1347 goto out; 1348 1349 nfe_tick(sc); 1350 1351 /* enable Rx */ 1352 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1353 1354 /* enable Tx */ 1355 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1356 1357 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1358 1359 /* enable interrupts */ 1360 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1361 1362 callout_schedule(&sc->sc_tick_ch, hz); 1363 1364 ifp->if_flags |= IFF_RUNNING; 1365 ifp->if_flags &= ~IFF_OACTIVE; 1366 1367 out: 1368 return rc; 1369 } 1370 1371 void 1372 nfe_stop(struct ifnet *ifp, int disable) 1373 { 1374 struct nfe_softc *sc = ifp->if_softc; 1375 1376 callout_stop(&sc->sc_tick_ch); 1377 1378 ifp->if_timer = 0; 1379 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1380 1381 mii_down(&sc->sc_mii); 1382 1383 /* abort Tx */ 1384 NFE_WRITE(sc, NFE_TX_CTL, 0); 1385 1386 /* disable Rx */ 1387 NFE_WRITE(sc, NFE_RX_CTL, 0); 1388 1389 /* disable interrupts */ 1390 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1391 1392 /* reset Tx and Rx rings */ 1393 nfe_reset_tx_ring(sc, &sc->txq); 1394 nfe_reset_rx_ring(sc, &sc->rxq); 1395 } 1396 1397 int 1398 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1399 { 1400 struct nfe_desc32 *desc32; 1401 struct nfe_desc64 *desc64; 1402 struct nfe_rx_data *data; 1403 struct nfe_jbuf *jbuf; 1404 void **desc; 1405 bus_addr_t physaddr; 1406 int i, nsegs, error, descsize; 1407 1408 if (sc->sc_flags & NFE_40BIT_ADDR) { 1409 desc = (void **)&ring->desc64; 1410 descsize = sizeof (struct nfe_desc64); 1411 } else { 1412 desc = (void **)&ring->desc32; 1413 descsize = sizeof (struct nfe_desc32); 1414 } 1415 1416 ring->cur = ring->next = 0; 1417 ring->bufsz = MCLBYTES; 1418 1419 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1420 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1421 if (error != 0) { 1422 aprint_error_dev(sc->sc_dev, 1423 "could not create desc DMA map\n"); 1424 ring->map = NULL; 1425 goto fail; 1426 } 1427 1428 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1429 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1430 if (error != 0) { 1431 aprint_error_dev(sc->sc_dev, 1432 "could not allocate DMA memory\n"); 1433 goto fail; 1434 } 1435 1436 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1437 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1438 if (error != 0) { 1439 aprint_error_dev(sc->sc_dev, 1440 "could not map desc DMA memory\n"); 1441 goto fail; 1442 } 1443 1444 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1445 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1446 if (error != 0) { 1447 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1448 goto fail; 1449 } 1450 1451 memset(*desc, 0, NFE_RX_RING_COUNT * descsize); 1452 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1453 1454 if (sc->sc_flags & NFE_USE_JUMBO) { 1455 ring->bufsz = NFE_JBYTES; 1456 if ((error = nfe_jpool_alloc(sc)) != 0) { 1457 aprint_error_dev(sc->sc_dev, 1458 "could not allocate jumbo frames\n"); 1459 goto fail; 1460 } 1461 } 1462 1463 /* 1464 * Pre-allocate Rx buffers and populate Rx ring. 1465 */ 1466 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1467 data = &sc->rxq.data[i]; 1468 1469 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1470 if (data->m == NULL) { 1471 aprint_error_dev(sc->sc_dev, 1472 "could not allocate rx mbuf\n"); 1473 error = ENOMEM; 1474 goto fail; 1475 } 1476 1477 if (sc->sc_flags & NFE_USE_JUMBO) { 1478 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1479 aprint_error_dev(sc->sc_dev, 1480 "could not allocate jumbo buffer\n"); 1481 goto fail; 1482 } 1483 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1484 sc); 1485 1486 physaddr = jbuf->physaddr; 1487 } else { 1488 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1489 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1490 if (error != 0) { 1491 aprint_error_dev(sc->sc_dev, 1492 "could not create DMA map\n"); 1493 data->map = NULL; 1494 goto fail; 1495 } 1496 MCLGET(data->m, M_DONTWAIT); 1497 if (!(data->m->m_flags & M_EXT)) { 1498 aprint_error_dev(sc->sc_dev, 1499 "could not allocate mbuf cluster\n"); 1500 error = ENOMEM; 1501 goto fail; 1502 } 1503 1504 error = bus_dmamap_load(sc->sc_dmat, data->map, 1505 mtod(data->m, void *), MCLBYTES, NULL, 1506 BUS_DMA_READ | BUS_DMA_NOWAIT); 1507 if (error != 0) { 1508 aprint_error_dev(sc->sc_dev, 1509 "could not load rx buf DMA map"); 1510 goto fail; 1511 } 1512 physaddr = data->map->dm_segs[0].ds_addr; 1513 } 1514 1515 if (sc->sc_flags & NFE_40BIT_ADDR) { 1516 desc64 = &sc->rxq.desc64[i]; 1517 #if defined(__LP64__) 1518 desc64->physaddr[0] = htole32(physaddr >> 32); 1519 #endif 1520 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1521 desc64->length = htole16(sc->rxq.bufsz); 1522 desc64->flags = htole16(NFE_RX_READY); 1523 } else { 1524 desc32 = &sc->rxq.desc32[i]; 1525 desc32->physaddr = htole32(physaddr); 1526 desc32->length = htole16(sc->rxq.bufsz); 1527 desc32->flags = htole16(NFE_RX_READY); 1528 } 1529 } 1530 1531 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1532 BUS_DMASYNC_PREWRITE); 1533 1534 return 0; 1535 1536 fail: nfe_free_rx_ring(sc, ring); 1537 return error; 1538 } 1539 1540 void 1541 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1542 { 1543 int i; 1544 1545 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1546 if (sc->sc_flags & NFE_40BIT_ADDR) { 1547 ring->desc64[i].length = htole16(ring->bufsz); 1548 ring->desc64[i].flags = htole16(NFE_RX_READY); 1549 } else { 1550 ring->desc32[i].length = htole16(ring->bufsz); 1551 ring->desc32[i].flags = htole16(NFE_RX_READY); 1552 } 1553 } 1554 1555 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1556 BUS_DMASYNC_PREWRITE); 1557 1558 ring->cur = ring->next = 0; 1559 } 1560 1561 void 1562 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1563 { 1564 struct nfe_rx_data *data; 1565 void *desc; 1566 int i, descsize; 1567 1568 if (sc->sc_flags & NFE_40BIT_ADDR) { 1569 desc = ring->desc64; 1570 descsize = sizeof (struct nfe_desc64); 1571 } else { 1572 desc = ring->desc32; 1573 descsize = sizeof (struct nfe_desc32); 1574 } 1575 1576 if (desc != NULL) { 1577 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1578 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1579 bus_dmamap_unload(sc->sc_dmat, ring->map); 1580 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1581 NFE_RX_RING_COUNT * descsize); 1582 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1583 } 1584 1585 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1586 data = &ring->data[i]; 1587 1588 if (data->map != NULL) { 1589 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1590 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1591 bus_dmamap_unload(sc->sc_dmat, data->map); 1592 bus_dmamap_destroy(sc->sc_dmat, data->map); 1593 } 1594 if (data->m != NULL) 1595 m_freem(data->m); 1596 } 1597 1598 nfe_jpool_free(sc); 1599 } 1600 1601 struct nfe_jbuf * 1602 nfe_jalloc(struct nfe_softc *sc, int i) 1603 { 1604 struct nfe_jbuf *jbuf; 1605 1606 mutex_enter(&sc->rxq.mtx); 1607 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1608 if (jbuf != NULL) 1609 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1610 mutex_exit(&sc->rxq.mtx); 1611 if (jbuf == NULL) 1612 return NULL; 1613 sc->rxq.jbufmap[i] = 1614 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1615 return jbuf; 1616 } 1617 1618 /* 1619 * This is called automatically by the network stack when the mbuf is freed. 1620 * Caution must be taken that the NIC might be reset by the time the mbuf is 1621 * freed. 1622 */ 1623 void 1624 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1625 { 1626 struct nfe_softc *sc = arg; 1627 struct nfe_jbuf *jbuf; 1628 int i; 1629 1630 /* find the jbuf from the base pointer */ 1631 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1632 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1633 aprint_error_dev(sc->sc_dev, 1634 "request to free a buffer (%p) not managed by us\n", buf); 1635 return; 1636 } 1637 jbuf = &sc->rxq.jbuf[i]; 1638 1639 /* ..and put it back in the free list */ 1640 mutex_enter(&sc->rxq.mtx); 1641 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1642 mutex_exit(&sc->rxq.mtx); 1643 1644 if (m != NULL) 1645 pool_cache_put(mb_cache, m); 1646 } 1647 1648 int 1649 nfe_jpool_alloc(struct nfe_softc *sc) 1650 { 1651 struct nfe_rx_ring *ring = &sc->rxq; 1652 struct nfe_jbuf *jbuf; 1653 bus_addr_t physaddr; 1654 char *buf; 1655 int i, nsegs, error; 1656 1657 /* 1658 * Allocate a big chunk of DMA'able memory. 1659 */ 1660 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1661 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1662 if (error != 0) { 1663 aprint_error_dev(sc->sc_dev, 1664 "could not create jumbo DMA map\n"); 1665 ring->jmap = NULL; 1666 goto fail; 1667 } 1668 1669 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1670 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1671 if (error != 0) { 1672 aprint_error_dev(sc->sc_dev, 1673 "could not allocate jumbo DMA memory\n"); 1674 goto fail; 1675 } 1676 1677 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1678 &ring->jpool, BUS_DMA_NOWAIT); 1679 if (error != 0) { 1680 aprint_error_dev(sc->sc_dev, 1681 "could not map jumbo DMA memory\n"); 1682 goto fail; 1683 } 1684 1685 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1686 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1687 if (error != 0) { 1688 aprint_error_dev(sc->sc_dev, 1689 "could not load jumbo DMA map\n"); 1690 goto fail; 1691 } 1692 1693 /* ..and split it into 9KB chunks */ 1694 SLIST_INIT(&ring->jfreelist); 1695 1696 buf = ring->jpool; 1697 physaddr = ring->jmap->dm_segs[0].ds_addr; 1698 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1699 jbuf = &ring->jbuf[i]; 1700 1701 jbuf->buf = buf; 1702 jbuf->physaddr = physaddr; 1703 1704 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1705 1706 buf += NFE_JBYTES; 1707 physaddr += NFE_JBYTES; 1708 } 1709 1710 return 0; 1711 1712 fail: nfe_jpool_free(sc); 1713 return error; 1714 } 1715 1716 void 1717 nfe_jpool_free(struct nfe_softc *sc) 1718 { 1719 struct nfe_rx_ring *ring = &sc->rxq; 1720 1721 if (ring->jmap != NULL) { 1722 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1723 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1724 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1725 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1726 ring->jmap = NULL; 1727 } 1728 if (ring->jpool != NULL) { 1729 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1730 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1731 ring->jpool = NULL; 1732 } 1733 } 1734 1735 int 1736 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1737 { 1738 int i, nsegs, error; 1739 void **desc; 1740 int descsize; 1741 1742 if (sc->sc_flags & NFE_40BIT_ADDR) { 1743 desc = (void **)&ring->desc64; 1744 descsize = sizeof (struct nfe_desc64); 1745 } else { 1746 desc = (void **)&ring->desc32; 1747 descsize = sizeof (struct nfe_desc32); 1748 } 1749 1750 ring->queued = 0; 1751 ring->cur = ring->next = 0; 1752 1753 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1754 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1755 1756 if (error != 0) { 1757 aprint_error_dev(sc->sc_dev, 1758 "could not create desc DMA map\n"); 1759 ring->map = NULL; 1760 goto fail; 1761 } 1762 1763 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1764 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1765 if (error != 0) { 1766 aprint_error_dev(sc->sc_dev, 1767 "could not allocate DMA memory\n"); 1768 goto fail; 1769 } 1770 1771 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1772 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1773 if (error != 0) { 1774 aprint_error_dev(sc->sc_dev, 1775 "could not map desc DMA memory\n"); 1776 goto fail; 1777 } 1778 1779 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1780 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1781 if (error != 0) { 1782 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1783 goto fail; 1784 } 1785 1786 memset(*desc, 0, NFE_TX_RING_COUNT * descsize); 1787 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1788 1789 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1790 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1791 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1792 &ring->data[i].map); 1793 if (error != 0) { 1794 aprint_error_dev(sc->sc_dev, 1795 "could not create DMA map\n"); 1796 ring->data[i].map = NULL; 1797 goto fail; 1798 } 1799 } 1800 1801 return 0; 1802 1803 fail: nfe_free_tx_ring(sc, ring); 1804 return error; 1805 } 1806 1807 void 1808 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1809 { 1810 struct nfe_tx_data *data; 1811 int i; 1812 1813 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1814 if (sc->sc_flags & NFE_40BIT_ADDR) 1815 ring->desc64[i].flags = 0; 1816 else 1817 ring->desc32[i].flags = 0; 1818 1819 data = &ring->data[i]; 1820 1821 if (data->m != NULL) { 1822 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1823 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1824 bus_dmamap_unload(sc->sc_dmat, data->active); 1825 m_freem(data->m); 1826 data->m = NULL; 1827 } 1828 } 1829 1830 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1831 BUS_DMASYNC_PREWRITE); 1832 1833 ring->queued = 0; 1834 ring->cur = ring->next = 0; 1835 } 1836 1837 void 1838 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1839 { 1840 struct nfe_tx_data *data; 1841 void *desc; 1842 int i, descsize; 1843 1844 if (sc->sc_flags & NFE_40BIT_ADDR) { 1845 desc = ring->desc64; 1846 descsize = sizeof (struct nfe_desc64); 1847 } else { 1848 desc = ring->desc32; 1849 descsize = sizeof (struct nfe_desc32); 1850 } 1851 1852 if (desc != NULL) { 1853 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1854 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1855 bus_dmamap_unload(sc->sc_dmat, ring->map); 1856 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1857 NFE_TX_RING_COUNT * descsize); 1858 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1859 } 1860 1861 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1862 data = &ring->data[i]; 1863 1864 if (data->m != NULL) { 1865 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1866 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1867 bus_dmamap_unload(sc->sc_dmat, data->active); 1868 m_freem(data->m); 1869 } 1870 } 1871 1872 /* ..and now actually destroy the DMA mappings */ 1873 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1874 data = &ring->data[i]; 1875 if (data->map == NULL) 1876 continue; 1877 bus_dmamap_destroy(sc->sc_dmat, data->map); 1878 } 1879 } 1880 1881 void 1882 nfe_setmulti(struct nfe_softc *sc) 1883 { 1884 struct ethercom *ec = &sc->sc_ethercom; 1885 struct ifnet *ifp = &ec->ec_if; 1886 struct ether_multi *enm; 1887 struct ether_multistep step; 1888 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1889 uint32_t filter = NFE_RXFILTER_MAGIC; 1890 int i; 1891 1892 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1893 memset(addr, 0, ETHER_ADDR_LEN); 1894 memset(mask, 0, ETHER_ADDR_LEN); 1895 goto done; 1896 } 1897 1898 memcpy(addr, etherbroadcastaddr, ETHER_ADDR_LEN); 1899 memcpy(mask, etherbroadcastaddr, ETHER_ADDR_LEN); 1900 1901 ETHER_FIRST_MULTI(step, ec, enm); 1902 while (enm != NULL) { 1903 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1904 ifp->if_flags |= IFF_ALLMULTI; 1905 memset(addr, 0, ETHER_ADDR_LEN); 1906 memset(mask, 0, ETHER_ADDR_LEN); 1907 goto done; 1908 } 1909 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1910 addr[i] &= enm->enm_addrlo[i]; 1911 mask[i] &= ~enm->enm_addrlo[i]; 1912 } 1913 ETHER_NEXT_MULTI(step, enm); 1914 } 1915 for (i = 0; i < ETHER_ADDR_LEN; i++) 1916 mask[i] |= addr[i]; 1917 1918 done: 1919 addr[0] |= 0x01; /* make sure multicast bit is set */ 1920 1921 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1922 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1923 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1924 addr[5] << 8 | addr[4]); 1925 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1926 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1927 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1928 mask[5] << 8 | mask[4]); 1929 1930 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1931 NFE_WRITE(sc, NFE_RXFILTER, filter); 1932 } 1933 1934 void 1935 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1936 { 1937 uint32_t tmp; 1938 1939 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 1940 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1941 addr[0] = (tmp & 0xff); 1942 addr[1] = (tmp >> 8) & 0xff; 1943 addr[2] = (tmp >> 16) & 0xff; 1944 addr[3] = (tmp >> 24) & 0xff; 1945 1946 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1947 addr[4] = (tmp & 0xff); 1948 addr[5] = (tmp >> 8) & 0xff; 1949 1950 } else { 1951 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1952 addr[0] = (tmp >> 8) & 0xff; 1953 addr[1] = (tmp & 0xff); 1954 1955 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1956 addr[2] = (tmp >> 24) & 0xff; 1957 addr[3] = (tmp >> 16) & 0xff; 1958 addr[4] = (tmp >> 8) & 0xff; 1959 addr[5] = (tmp & 0xff); 1960 } 1961 } 1962 1963 void 1964 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1965 { 1966 NFE_WRITE(sc, NFE_MACADDR_LO, 1967 addr[5] << 8 | addr[4]); 1968 NFE_WRITE(sc, NFE_MACADDR_HI, 1969 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1970 } 1971 1972 void 1973 nfe_tick(void *arg) 1974 { 1975 struct nfe_softc *sc = arg; 1976 int s; 1977 1978 s = splnet(); 1979 mii_tick(&sc->sc_mii); 1980 splx(s); 1981 1982 callout_schedule(&sc->sc_tick_ch, hz); 1983 } 1984 1985 void 1986 nfe_poweron(device_t self) 1987 { 1988 struct nfe_softc *sc = device_private(self); 1989 1990 if ((sc->sc_flags & NFE_PWR_MGMT) != 0) { 1991 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 1992 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 1993 DELAY(100); 1994 NFE_WRITE(sc, NFE_MAC_RESET, 0); 1995 DELAY(100); 1996 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 1997 NFE_WRITE(sc, NFE_PWR2_CTL, 1998 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_WAKEUP_MASK); 1999 } 2000 } 2001 2002 bool 2003 nfe_resume(device_t dv, const pmf_qual_t *qual) 2004 { 2005 nfe_poweron(dv); 2006 2007 return true; 2008 } 2009
Indexes created Tue Sep 30 07:10:03 GMT 2025