if_nfe.c revision 1.69
1 /* $NetBSD: if_nfe.c,v 1.69 2019/05/23 10:51:39 msaitoh Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.77 2008/02/05 16:52:50 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006, 2007 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.69 2019/05/23 10:51:39 msaitoh Exp $"); 25 26 #include "opt_inet.h" 27 #include "vlan.h" 28 29 #include <sys/param.h> 30 #include <sys/endian.h> 31 #include <sys/systm.h> 32 #include <sys/types.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/mutex.h> 36 #include <sys/queue.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/callout.h> 40 #include <sys/socket.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #include <net/bpf.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_nfereg.h> 72 #include <dev/pci/if_nfevar.h> 73 74 static int nfe_ifflags_cb(struct ethercom *); 75 76 int nfe_match(device_t, cfdata_t, void *); 77 void nfe_attach(device_t, device_t, void *); 78 int nfe_detach(device_t, int); 79 void nfe_power(int, void *); 80 void nfe_miibus_statchg(struct ifnet *); 81 int nfe_miibus_readreg(device_t, int, int, uint16_t *); 82 int nfe_miibus_writereg(device_t, int, int, uint16_t); 83 int nfe_intr(void *); 84 int nfe_ioctl(struct ifnet *, u_long, void *); 85 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 86 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 87 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 88 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 89 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 90 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 91 void nfe_rxeof(struct nfe_softc *); 92 void nfe_txeof(struct nfe_softc *); 93 int nfe_encap(struct nfe_softc *, struct mbuf *); 94 void nfe_start(struct ifnet *); 95 void nfe_watchdog(struct ifnet *); 96 int nfe_init(struct ifnet *); 97 void nfe_stop(struct ifnet *, int); 98 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 99 void nfe_jfree(struct mbuf *, void *, size_t, void *); 100 int nfe_jpool_alloc(struct nfe_softc *); 101 void nfe_jpool_free(struct nfe_softc *); 102 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 105 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 108 void nfe_setmulti(struct nfe_softc *); 109 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 110 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 111 void nfe_tick(void *); 112 void nfe_poweron(device_t); 113 bool nfe_resume(device_t, const pmf_qual_t *); 114 115 CFATTACH_DECL_NEW(nfe, sizeof(struct nfe_softc), 116 nfe_match, nfe_attach, nfe_detach, NULL); 117 118 /* #define NFE_NO_JUMBO */ 119 120 #ifdef NFE_DEBUG 121 int nfedebug = 0; 122 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 123 #define DPRINTFN(n, x) do { if (nfedebug >= (n)) printf x; } while (0) 124 #else 125 #define DPRINTF(x) 126 #define DPRINTFN(n, x) 127 #endif 128 129 /* deal with naming differences */ 130 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 134 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 135 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 136 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 137 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 140 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 141 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 142 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 145 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 146 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 147 148 #ifdef _LP64 149 #define __LP64__ 1 150 #endif 151 152 const struct nfe_product { 153 pci_vendor_id_t vendor; 154 pci_product_id_t product; 155 } nfe_devices[] = { 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 183 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 184 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 185 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 186 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 }, 187 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1 }, 188 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2 }, 189 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3 }, 190 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4 }, 191 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1 }, 192 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2 }, 193 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3 }, 194 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4 } 195 }; 196 197 int 198 nfe_match(device_t dev, cfdata_t match, void *aux) 199 { 200 struct pci_attach_args *pa = aux; 201 const struct nfe_product *np; 202 int i; 203 204 for (i = 0; i < __arraycount(nfe_devices); i++) { 205 np = &nfe_devices[i]; 206 if (PCI_VENDOR(pa->pa_id) == np->vendor && 207 PCI_PRODUCT(pa->pa_id) == np->product) 208 return 1; 209 } 210 return 0; 211 } 212 213 void 214 nfe_attach(device_t parent, device_t self, void *aux) 215 { 216 struct nfe_softc *sc = device_private(self); 217 struct pci_attach_args *pa = aux; 218 pci_chipset_tag_t pc = pa->pa_pc; 219 pci_intr_handle_t ih; 220 const char *intrstr; 221 struct ifnet *ifp; 222 struct mii_data * const mii = &sc->sc_mii; 223 pcireg_t memtype, csr; 224 int mii_flags = 0; 225 char intrbuf[PCI_INTRSTR_LEN]; 226 227 sc->sc_dev = self; 228 sc->sc_pc = pa->pa_pc; 229 pci_aprint_devinfo(pa, NULL); 230 231 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 232 switch (memtype) { 233 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 234 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 235 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 236 &sc->sc_memh, NULL, &sc->sc_mems) == 0) 237 break; 238 /* FALLTHROUGH */ 239 default: 240 aprint_error_dev(self, "could not map mem space\n"); 241 return; 242 } 243 244 if (pci_intr_map(pa, &ih) != 0) { 245 aprint_error_dev(self, "could not map interrupt\n"); 246 goto fail; 247 } 248 249 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 250 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, nfe_intr, sc, 251 device_xname(self)); 252 if (sc->sc_ih == NULL) { 253 aprint_error_dev(self, "could not establish interrupt"); 254 if (intrstr != NULL) 255 aprint_error(" at %s", intrstr); 256 aprint_error("\n"); 257 goto fail; 258 } 259 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 260 261 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 262 csr |= PCI_COMMAND_MASTER_ENABLE; 263 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 264 265 sc->sc_flags = 0; 266 267 switch (PCI_PRODUCT(pa->pa_id)) { 268 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 269 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 270 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 271 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 272 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 273 break; 274 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 275 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 276 sc->sc_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT; 277 break; 278 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 279 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 280 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 281 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 282 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 283 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 284 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 285 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 286 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 287 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 288 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 289 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 290 sc->sc_flags |= NFE_40BIT_ADDR | NFE_CORRECT_MACADDR | 291 NFE_PWR_MGMT; 292 break; 293 case PCI_PRODUCT_NVIDIA_MCP77_LAN1: 294 case PCI_PRODUCT_NVIDIA_MCP77_LAN2: 295 case PCI_PRODUCT_NVIDIA_MCP77_LAN3: 296 case PCI_PRODUCT_NVIDIA_MCP77_LAN4: 297 sc->sc_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | 298 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 299 break; 300 case PCI_PRODUCT_NVIDIA_MCP79_LAN1: 301 case PCI_PRODUCT_NVIDIA_MCP79_LAN2: 302 case PCI_PRODUCT_NVIDIA_MCP79_LAN3: 303 case PCI_PRODUCT_NVIDIA_MCP79_LAN4: 304 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 305 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 306 break; 307 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 308 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 309 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 310 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 311 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 312 break; 313 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 314 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 315 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 316 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 317 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 318 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 319 mii_flags = MIIF_DOPAUSE; 320 break; 321 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 322 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 323 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 324 NFE_HW_VLAN | NFE_PWR_MGMT; 325 break; 326 } 327 328 if (pci_dma64_available(pa) && (sc->sc_flags & NFE_40BIT_ADDR) != 0) 329 sc->sc_dmat = pa->pa_dmat64; 330 else 331 sc->sc_dmat = pa->pa_dmat; 332 333 nfe_poweron(self); 334 335 #ifndef NFE_NO_JUMBO 336 /* enable jumbo frames for adapters that support it */ 337 if (sc->sc_flags & NFE_JUMBO_SUP) 338 sc->sc_flags |= NFE_USE_JUMBO; 339 #endif 340 341 /* Check for reversed ethernet address */ 342 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 343 sc->sc_flags |= NFE_CORRECT_MACADDR; 344 345 nfe_get_macaddr(sc, sc->sc_enaddr); 346 aprint_normal_dev(self, "Ethernet address %s\n", 347 ether_sprintf(sc->sc_enaddr)); 348 349 /* 350 * Allocate Tx and Rx rings. 351 */ 352 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 353 aprint_error_dev(self, "could not allocate Tx ring\n"); 354 goto fail; 355 } 356 357 mutex_init(&sc->rxq.mtx, MUTEX_DEFAULT, IPL_NET); 358 359 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 360 aprint_error_dev(self, "could not allocate Rx ring\n"); 361 nfe_free_tx_ring(sc, &sc->txq); 362 goto fail; 363 } 364 365 ifp = &sc->sc_ethercom.ec_if; 366 ifp->if_softc = sc; 367 ifp->if_mtu = ETHERMTU; 368 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 369 ifp->if_ioctl = nfe_ioctl; 370 ifp->if_start = nfe_start; 371 ifp->if_stop = nfe_stop; 372 ifp->if_watchdog = nfe_watchdog; 373 ifp->if_init = nfe_init; 374 ifp->if_baudrate = IF_Gbps(1); 375 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 376 IFQ_SET_READY(&ifp->if_snd); 377 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 378 379 if (sc->sc_flags & NFE_USE_JUMBO) 380 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 381 382 #if NVLAN > 0 383 if (sc->sc_flags & NFE_HW_VLAN) 384 sc->sc_ethercom.ec_capabilities |= 385 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 386 #endif 387 if (sc->sc_flags & NFE_HW_CSUM) { 388 ifp->if_capabilities |= 389 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 390 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 391 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 392 } 393 394 mii->mii_ifp = ifp; 395 mii->mii_readreg = nfe_miibus_readreg; 396 mii->mii_writereg = nfe_miibus_writereg; 397 mii->mii_statchg = nfe_miibus_statchg; 398 399 sc->sc_ethercom.ec_mii = mii; 400 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 401 402 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 0, mii_flags); 403 404 if (LIST_FIRST(&mii->mii_phys) == NULL) { 405 aprint_error_dev(self, "no PHY found!\n"); 406 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 407 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 408 } else 409 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 410 411 if_attach(ifp); 412 if_deferred_start_init(ifp, NULL); 413 ether_ifattach(ifp, sc->sc_enaddr); 414 ether_set_ifflags_cb(&sc->sc_ethercom, nfe_ifflags_cb); 415 416 callout_init(&sc->sc_tick_ch, 0); 417 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 418 419 if (pmf_device_register(self, NULL, nfe_resume)) 420 pmf_class_network_register(self, ifp); 421 else 422 aprint_error_dev(self, "couldn't establish power handler\n"); 423 424 return; 425 426 fail: 427 if (sc->sc_ih != NULL) { 428 pci_intr_disestablish(pc, sc->sc_ih); 429 sc->sc_ih = NULL; 430 } 431 if (sc->sc_mems != 0) { 432 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 433 sc->sc_mems = 0; 434 } 435 } 436 437 int 438 nfe_detach(device_t self, int flags) 439 { 440 struct nfe_softc *sc = device_private(self); 441 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 442 int s; 443 444 s = splnet(); 445 446 nfe_stop(ifp, 1); 447 448 pmf_device_deregister(self); 449 callout_destroy(&sc->sc_tick_ch); 450 ether_ifdetach(ifp); 451 if_detach(ifp); 452 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 453 454 nfe_free_rx_ring(sc, &sc->rxq); 455 mutex_destroy(&sc->rxq.mtx); 456 nfe_free_tx_ring(sc, &sc->txq); 457 458 if (sc->sc_ih != NULL) { 459 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 460 sc->sc_ih = NULL; 461 } 462 463 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 464 nfe_set_macaddr(sc, sc->sc_enaddr); 465 } else { 466 NFE_WRITE(sc, NFE_MACADDR_LO, 467 sc->sc_enaddr[0] << 8 | sc->sc_enaddr[1]); 468 NFE_WRITE(sc, NFE_MACADDR_HI, 469 sc->sc_enaddr[2] << 24 | sc->sc_enaddr[3] << 16 | 470 sc->sc_enaddr[4] << 8 | sc->sc_enaddr[5]); 471 } 472 473 if (sc->sc_mems != 0) { 474 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 475 sc->sc_mems = 0; 476 } 477 478 splx(s); 479 480 return 0; 481 } 482 483 void 484 nfe_miibus_statchg(struct ifnet *ifp) 485 { 486 struct nfe_softc *sc = ifp->if_softc; 487 struct mii_data *mii = &sc->sc_mii; 488 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 489 490 phy = NFE_READ(sc, NFE_PHY_IFACE); 491 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 492 493 seed = NFE_READ(sc, NFE_RNDSEED); 494 seed &= ~NFE_SEED_MASK; 495 496 if ((mii->mii_media_active & IFM_HDX) != 0) { 497 phy |= NFE_PHY_HDX; /* half-duplex */ 498 misc |= NFE_MISC1_HDX; 499 } 500 501 switch (IFM_SUBTYPE(mii->mii_media_active)) { 502 case IFM_1000_T: /* full-duplex only */ 503 link |= NFE_MEDIA_1000T; 504 seed |= NFE_SEED_1000T; 505 phy |= NFE_PHY_1000T; 506 break; 507 case IFM_100_TX: 508 link |= NFE_MEDIA_100TX; 509 seed |= NFE_SEED_100TX; 510 phy |= NFE_PHY_100TX; 511 break; 512 case IFM_10_T: 513 link |= NFE_MEDIA_10T; 514 seed |= NFE_SEED_10T; 515 break; 516 } 517 518 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 519 520 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 521 NFE_WRITE(sc, NFE_MISC1, misc); 522 NFE_WRITE(sc, NFE_LINKSPEED, link); 523 } 524 525 int 526 nfe_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 527 { 528 struct nfe_softc *sc = device_private(dev); 529 uint32_t data; 530 int ntries; 531 532 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 533 534 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 535 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 536 DELAY(100); 537 } 538 539 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 540 541 for (ntries = 0; ntries < 1000; ntries++) { 542 DELAY(100); 543 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 544 break; 545 } 546 if (ntries == 1000) { 547 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 548 device_xname(sc->sc_dev))); 549 return ETIMEDOUT; 550 } 551 552 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 553 DPRINTFN(2, ("%s: could not read PHY\n", 554 device_xname(sc->sc_dev))); 555 return -1; 556 } 557 558 data = NFE_READ(sc, NFE_PHY_DATA); 559 if (data != 0xffffffff && data != 0) 560 sc->mii_phyaddr = phy; 561 562 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x data 0x%x\n", 563 device_xname(sc->sc_dev), phy, reg, data)); 564 565 *val = data & 0x0000ffff; 566 return 0; 567 } 568 569 int 570 nfe_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 571 { 572 struct nfe_softc *sc = device_private(dev); 573 uint32_t ctl; 574 int ntries; 575 576 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 577 578 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 579 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 580 DELAY(100); 581 } 582 583 NFE_WRITE(sc, NFE_PHY_DATA, val); 584 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 585 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 586 587 for (ntries = 0; ntries < 1000; ntries++) { 588 DELAY(100); 589 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 590 break; 591 } 592 if (ntries == 1000) { 593 #ifdef NFE_DEBUG 594 if (nfedebug >= 2) 595 printf("could not write to PHY\n"); 596 #endif 597 return ETIMEDOUT; 598 } 599 return 0; 600 } 601 602 int 603 nfe_intr(void *arg) 604 { 605 struct nfe_softc *sc = arg; 606 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 607 uint32_t r; 608 int handled; 609 610 if ((ifp->if_flags & IFF_UP) == 0) 611 return 0; 612 613 handled = 0; 614 615 for (;;) { 616 r = NFE_READ(sc, NFE_IRQ_STATUS); 617 if ((r & NFE_IRQ_WANTED) == 0) 618 break; 619 620 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 621 handled = 1; 622 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 623 624 if ((r & (NFE_IRQ_RXERR |NFE_IRQ_RX_NOBUF |NFE_IRQ_RX)) != 0) { 625 /* check Rx ring */ 626 nfe_rxeof(sc); 627 } 628 if ((r & (NFE_IRQ_TXERR|NFE_IRQ_TXERR2|NFE_IRQ_TX_DONE)) != 0) { 629 /* check Tx ring */ 630 nfe_txeof(sc); 631 } 632 if ((r & NFE_IRQ_LINK) != 0) { 633 NFE_READ(sc, NFE_PHY_STATUS); 634 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 635 DPRINTF(("%s: link state changed\n", 636 device_xname(sc->sc_dev))); 637 } 638 } 639 640 if (handled) 641 if_schedule_deferred_start(ifp); 642 643 return handled; 644 } 645 646 static int 647 nfe_ifflags_cb(struct ethercom *ec) 648 { 649 struct ifnet *ifp = &ec->ec_if; 650 struct nfe_softc *sc = ifp->if_softc; 651 int change = ifp->if_flags ^ sc->sc_if_flags; 652 653 /* 654 * If only the PROMISC flag changes, then 655 * don't do a full re-init of the chip, just update 656 * the Rx filter. 657 */ 658 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 659 return ENETRESET; 660 else if ((change & IFF_PROMISC) != 0) 661 nfe_setmulti(sc); 662 663 return 0; 664 } 665 666 int 667 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 668 { 669 struct nfe_softc *sc = ifp->if_softc; 670 struct ifaddr *ifa = (struct ifaddr *)data; 671 int s, error = 0; 672 673 s = splnet(); 674 675 switch (cmd) { 676 case SIOCINITIFADDR: 677 ifp->if_flags |= IFF_UP; 678 nfe_init(ifp); 679 switch (ifa->ifa_addr->sa_family) { 680 #ifdef INET 681 case AF_INET: 682 arp_ifinit(ifp, ifa); 683 break; 684 #endif 685 default: 686 break; 687 } 688 break; 689 default: 690 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 691 break; 692 693 error = 0; 694 695 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 696 ; 697 else if (ifp->if_flags & IFF_RUNNING) 698 nfe_setmulti(sc); 699 break; 700 } 701 sc->sc_if_flags = ifp->if_flags; 702 703 splx(s); 704 705 return error; 706 } 707 708 void 709 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 710 { 711 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 712 (char *)desc32 - (char *)sc->txq.desc32, 713 sizeof (struct nfe_desc32), ops); 714 } 715 716 void 717 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 718 { 719 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 720 (char *)desc64 - (char *)sc->txq.desc64, 721 sizeof (struct nfe_desc64), ops); 722 } 723 724 void 725 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 726 { 727 if (end > start) { 728 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 729 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 730 (char *)&sc->txq.desc32[end] - 731 (char *)&sc->txq.desc32[start], ops); 732 return; 733 } 734 /* sync from 'start' to end of ring */ 735 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 736 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 737 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 738 (char *)&sc->txq.desc32[start], ops); 739 740 /* sync from start of ring to 'end' */ 741 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 742 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 743 } 744 745 void 746 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 747 { 748 if (end > start) { 749 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 750 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 751 (char *)&sc->txq.desc64[end] - 752 (char *)&sc->txq.desc64[start], ops); 753 return; 754 } 755 /* sync from 'start' to end of ring */ 756 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 757 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 758 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 759 (char *)&sc->txq.desc64[start], ops); 760 761 /* sync from start of ring to 'end' */ 762 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 763 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 764 } 765 766 void 767 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 768 { 769 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 770 (char *)desc32 - (char *)sc->rxq.desc32, 771 sizeof (struct nfe_desc32), ops); 772 } 773 774 void 775 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 776 { 777 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 778 (char *)desc64 - (char *)sc->rxq.desc64, 779 sizeof (struct nfe_desc64), ops); 780 } 781 782 void 783 nfe_rxeof(struct nfe_softc *sc) 784 { 785 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 786 struct nfe_desc32 *desc32; 787 struct nfe_desc64 *desc64; 788 struct nfe_rx_data *data; 789 struct nfe_jbuf *jbuf; 790 struct mbuf *m, *mnew; 791 bus_addr_t physaddr; 792 uint16_t flags; 793 int error, len, i; 794 795 desc32 = NULL; 796 desc64 = NULL; 797 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 798 data = &sc->rxq.data[i]; 799 800 if (sc->sc_flags & NFE_40BIT_ADDR) { 801 desc64 = &sc->rxq.desc64[i]; 802 nfe_rxdesc64_sync(sc, desc64, 803 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 804 805 flags = le16toh(desc64->flags); 806 len = le16toh(desc64->length) & 0x3fff; 807 } else { 808 desc32 = &sc->rxq.desc32[i]; 809 nfe_rxdesc32_sync(sc, desc32, 810 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 811 812 flags = le16toh(desc32->flags); 813 len = le16toh(desc32->length) & 0x3fff; 814 } 815 816 if ((flags & NFE_RX_READY) != 0) 817 break; 818 819 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 820 if ((flags & NFE_RX_VALID_V1) == 0) 821 goto skip; 822 823 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 824 flags &= ~NFE_RX_ERROR; 825 len--; /* fix buffer length */ 826 } 827 } else { 828 if ((flags & NFE_RX_VALID_V2) == 0) 829 goto skip; 830 831 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 832 flags &= ~NFE_RX_ERROR; 833 len--; /* fix buffer length */ 834 } 835 } 836 837 if (flags & NFE_RX_ERROR) { 838 ifp->if_ierrors++; 839 goto skip; 840 } 841 842 /* 843 * Try to allocate a new mbuf for this ring element and load 844 * it before processing the current mbuf. If the ring element 845 * cannot be loaded, drop the received packet and reuse the 846 * old mbuf. In the unlikely case that the old mbuf can't be 847 * reloaded either, explicitly panic. 848 */ 849 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 850 if (mnew == NULL) { 851 ifp->if_ierrors++; 852 goto skip; 853 } 854 855 if (sc->sc_flags & NFE_USE_JUMBO) { 856 physaddr = 857 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 858 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 859 if (len > MCLBYTES) { 860 m_freem(mnew); 861 ifp->if_ierrors++; 862 goto skip1; 863 } 864 MCLGET(mnew, M_DONTWAIT); 865 if ((mnew->m_flags & M_EXT) == 0) { 866 m_freem(mnew); 867 ifp->if_ierrors++; 868 goto skip1; 869 } 870 871 (void)memcpy(mtod(mnew, void *), 872 mtod(data->m, const void *), len); 873 m = mnew; 874 goto mbufcopied; 875 } else { 876 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 877 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 878 mtod(data->m, char *) - (char *)sc->rxq.jpool, 879 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 880 881 physaddr = jbuf->physaddr; 882 } 883 } else { 884 MCLGET(mnew, M_DONTWAIT); 885 if ((mnew->m_flags & M_EXT) == 0) { 886 m_freem(mnew); 887 ifp->if_ierrors++; 888 goto skip; 889 } 890 891 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 892 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 893 bus_dmamap_unload(sc->sc_dmat, data->map); 894 895 error = bus_dmamap_load(sc->sc_dmat, data->map, 896 mtod(mnew, void *), MCLBYTES, NULL, 897 BUS_DMA_READ | BUS_DMA_NOWAIT); 898 if (error != 0) { 899 m_freem(mnew); 900 901 /* try to reload the old mbuf */ 902 error = bus_dmamap_load(sc->sc_dmat, data->map, 903 mtod(data->m, void *), MCLBYTES, NULL, 904 BUS_DMA_READ | BUS_DMA_NOWAIT); 905 if (error != 0) { 906 /* very unlikely that it will fail.. */ 907 panic("%s: could not load old rx mbuf", 908 device_xname(sc->sc_dev)); 909 } 910 ifp->if_ierrors++; 911 goto skip; 912 } 913 physaddr = data->map->dm_segs[0].ds_addr; 914 } 915 916 /* 917 * New mbuf successfully loaded, update Rx ring and continue 918 * processing. 919 */ 920 m = data->m; 921 data->m = mnew; 922 923 mbufcopied: 924 /* finalize mbuf */ 925 m->m_pkthdr.len = m->m_len = len; 926 m_set_rcvif(m, ifp); 927 928 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 929 /* 930 * XXX 931 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 932 */ 933 if (flags & NFE_RX_IP_CSUMOK) { 934 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 935 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 936 device_xname(sc->sc_dev))); 937 } 938 /* 939 * XXX 940 * no way to check M_CSUM_TCP_UDP_BAD or 941 * other protocols? 942 */ 943 if (flags & NFE_RX_UDP_CSUMOK) { 944 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 945 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 946 device_xname(sc->sc_dev))); 947 } else if (flags & NFE_RX_TCP_CSUMOK) { 948 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 949 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 950 device_xname(sc->sc_dev))); 951 } 952 } 953 if_percpuq_enqueue(ifp->if_percpuq, m); 954 955 skip1: 956 /* update mapping address in h/w descriptor */ 957 if (sc->sc_flags & NFE_40BIT_ADDR) { 958 #if defined(__LP64__) 959 desc64->physaddr[0] = htole32(physaddr >> 32); 960 #endif 961 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 962 } else { 963 desc32->physaddr = htole32(physaddr); 964 } 965 966 skip: 967 if (sc->sc_flags & NFE_40BIT_ADDR) { 968 desc64->length = htole16(sc->rxq.bufsz); 969 desc64->flags = htole16(NFE_RX_READY); 970 971 nfe_rxdesc64_sync(sc, desc64, 972 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 973 } else { 974 desc32->length = htole16(sc->rxq.bufsz); 975 desc32->flags = htole16(NFE_RX_READY); 976 977 nfe_rxdesc32_sync(sc, desc32, 978 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 979 } 980 } 981 /* update current RX pointer */ 982 sc->rxq.cur = i; 983 } 984 985 void 986 nfe_txeof(struct nfe_softc *sc) 987 { 988 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 989 struct nfe_desc32 *desc32; 990 struct nfe_desc64 *desc64; 991 struct nfe_tx_data *data = NULL; 992 int i; 993 uint16_t flags; 994 char buf[128]; 995 996 for (i = sc->txq.next; 997 sc->txq.queued > 0; 998 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 999 if (sc->sc_flags & NFE_40BIT_ADDR) { 1000 desc64 = &sc->txq.desc64[i]; 1001 nfe_txdesc64_sync(sc, desc64, 1002 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1003 1004 flags = le16toh(desc64->flags); 1005 } else { 1006 desc32 = &sc->txq.desc32[i]; 1007 nfe_txdesc32_sync(sc, desc32, 1008 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1009 1010 flags = le16toh(desc32->flags); 1011 } 1012 1013 if ((flags & NFE_TX_VALID) != 0) 1014 break; 1015 1016 data = &sc->txq.data[i]; 1017 1018 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 1019 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 1020 data->m == NULL) 1021 continue; 1022 1023 if ((flags & NFE_TX_ERROR_V1) != 0) { 1024 snprintb(buf, sizeof(buf), NFE_V1_TXERR, flags); 1025 aprint_error_dev(sc->sc_dev, "tx v1 error %s\n", 1026 buf); 1027 ifp->if_oerrors++; 1028 } else 1029 ifp->if_opackets++; 1030 } else { 1031 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 1032 data->m == NULL) 1033 continue; 1034 1035 if ((flags & NFE_TX_ERROR_V2) != 0) { 1036 snprintb(buf, sizeof(buf), NFE_V2_TXERR, flags); 1037 aprint_error_dev(sc->sc_dev, "tx v2 error %s\n", 1038 buf); 1039 ifp->if_oerrors++; 1040 } else 1041 ifp->if_opackets++; 1042 } 1043 1044 if (data->m == NULL) { /* should not get there */ 1045 aprint_error_dev(sc->sc_dev, 1046 "last fragment bit w/o associated mbuf!\n"); 1047 continue; 1048 } 1049 1050 /* last fragment of the mbuf chain transmitted */ 1051 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1052 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1053 bus_dmamap_unload(sc->sc_dmat, data->active); 1054 m_freem(data->m); 1055 data->m = NULL; 1056 } 1057 1058 sc->txq.next = i; 1059 1060 if (sc->txq.queued < NFE_TX_RING_COUNT) { 1061 /* at least one slot freed */ 1062 ifp->if_flags &= ~IFF_OACTIVE; 1063 } 1064 1065 if (sc->txq.queued == 0) { 1066 /* all queued packets are sent */ 1067 ifp->if_timer = 0; 1068 } 1069 } 1070 1071 int 1072 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 1073 { 1074 struct nfe_desc32 *desc32; 1075 struct nfe_desc64 *desc64; 1076 struct nfe_tx_data *data; 1077 bus_dmamap_t map; 1078 uint16_t flags, csumflags; 1079 #if NVLAN > 0 1080 uint32_t vtag = 0; 1081 #endif 1082 int error, i, first; 1083 1084 desc32 = NULL; 1085 desc64 = NULL; 1086 data = NULL; 1087 1088 flags = 0; 1089 csumflags = 0; 1090 first = sc->txq.cur; 1091 1092 map = sc->txq.data[first].map; 1093 1094 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1095 if (error != 0) { 1096 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1097 error); 1098 return error; 1099 } 1100 1101 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1102 bus_dmamap_unload(sc->sc_dmat, map); 1103 return ENOBUFS; 1104 } 1105 1106 #if NVLAN > 0 1107 /* setup h/w VLAN tagging */ 1108 if (vlan_has_tag(m0)) 1109 vtag = NFE_TX_VTAG | vlan_get_tag(m0); 1110 #endif 1111 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1112 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1113 csumflags |= NFE_TX_IP_CSUM; 1114 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1115 csumflags |= NFE_TX_TCP_UDP_CSUM; 1116 } 1117 1118 for (i = 0; i < map->dm_nsegs; i++) { 1119 data = &sc->txq.data[sc->txq.cur]; 1120 1121 if (sc->sc_flags & NFE_40BIT_ADDR) { 1122 desc64 = &sc->txq.desc64[sc->txq.cur]; 1123 #if defined(__LP64__) 1124 desc64->physaddr[0] = 1125 htole32(map->dm_segs[i].ds_addr >> 32); 1126 #endif 1127 desc64->physaddr[1] = 1128 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1129 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1130 desc64->flags = htole16(flags); 1131 desc64->vtag = 0; 1132 } else { 1133 desc32 = &sc->txq.desc32[sc->txq.cur]; 1134 1135 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1136 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1137 desc32->flags = htole16(flags); 1138 } 1139 1140 /* 1141 * Setting of the valid bit in the first descriptor is 1142 * deferred until the whole chain is fully setup. 1143 */ 1144 flags |= NFE_TX_VALID; 1145 1146 sc->txq.queued++; 1147 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1148 } 1149 1150 /* the whole mbuf chain has been setup */ 1151 if (sc->sc_flags & NFE_40BIT_ADDR) { 1152 /* fix last descriptor */ 1153 flags |= NFE_TX_LASTFRAG_V2; 1154 desc64->flags = htole16(flags); 1155 1156 /* Checksum flags and vtag belong to the first fragment only. */ 1157 #if NVLAN > 0 1158 sc->txq.desc64[first].vtag = htole32(vtag); 1159 #endif 1160 sc->txq.desc64[first].flags |= htole16(csumflags); 1161 1162 /* finally, set the valid bit in the first descriptor */ 1163 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1164 } else { 1165 /* fix last descriptor */ 1166 if (sc->sc_flags & NFE_JUMBO_SUP) 1167 flags |= NFE_TX_LASTFRAG_V2; 1168 else 1169 flags |= NFE_TX_LASTFRAG_V1; 1170 desc32->flags = htole16(flags); 1171 1172 /* Checksum flags belong to the first fragment only. */ 1173 sc->txq.desc32[first].flags |= htole16(csumflags); 1174 1175 /* finally, set the valid bit in the first descriptor */ 1176 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1177 } 1178 1179 data->m = m0; 1180 data->active = map; 1181 1182 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1183 BUS_DMASYNC_PREWRITE); 1184 1185 return 0; 1186 } 1187 1188 void 1189 nfe_start(struct ifnet *ifp) 1190 { 1191 struct nfe_softc *sc = ifp->if_softc; 1192 int old = sc->txq.queued; 1193 struct mbuf *m0; 1194 1195 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1196 return; 1197 1198 for (;;) { 1199 IFQ_POLL(&ifp->if_snd, m0); 1200 if (m0 == NULL) 1201 break; 1202 1203 if (nfe_encap(sc, m0) != 0) { 1204 ifp->if_flags |= IFF_OACTIVE; 1205 break; 1206 } 1207 1208 /* packet put in h/w queue, remove from s/w queue */ 1209 IFQ_DEQUEUE(&ifp->if_snd, m0); 1210 1211 bpf_mtap(ifp, m0, BPF_D_OUT); 1212 } 1213 1214 if (sc->txq.queued != old) { 1215 /* packets are queued */ 1216 if (sc->sc_flags & NFE_40BIT_ADDR) 1217 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1218 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1219 else 1220 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1221 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1222 /* kick Tx */ 1223 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1224 1225 /* 1226 * Set a timeout in case the chip goes out to lunch. 1227 */ 1228 ifp->if_timer = 5; 1229 } 1230 } 1231 1232 void 1233 nfe_watchdog(struct ifnet *ifp) 1234 { 1235 struct nfe_softc *sc = ifp->if_softc; 1236 1237 aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1238 1239 ifp->if_flags &= ~IFF_RUNNING; 1240 nfe_init(ifp); 1241 1242 ifp->if_oerrors++; 1243 } 1244 1245 int 1246 nfe_init(struct ifnet *ifp) 1247 { 1248 struct nfe_softc *sc = ifp->if_softc; 1249 uint32_t tmp; 1250 int rc = 0, s; 1251 1252 if (ifp->if_flags & IFF_RUNNING) 1253 return 0; 1254 1255 nfe_stop(ifp, 0); 1256 1257 NFE_WRITE(sc, NFE_TX_UNK, 0); 1258 NFE_WRITE(sc, NFE_STATUS, 0); 1259 1260 sc->rxtxctl = NFE_RXTX_BIT2; 1261 if (sc->sc_flags & NFE_40BIT_ADDR) 1262 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1263 else if (sc->sc_flags & NFE_JUMBO_SUP) 1264 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1265 if (sc->sc_flags & NFE_HW_CSUM) 1266 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1267 #if NVLAN > 0 1268 /* 1269 * Although the adapter is capable of stripping VLAN tags from received 1270 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1271 * purpose. This will be done in software by our network stack. 1272 */ 1273 if (sc->sc_flags & NFE_HW_VLAN) 1274 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1275 #endif 1276 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1277 DELAY(10); 1278 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1279 1280 #if NVLAN 1281 if (sc->sc_flags & NFE_HW_VLAN) 1282 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1283 #endif 1284 1285 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1286 1287 /* set MAC address */ 1288 nfe_set_macaddr(sc, sc->sc_enaddr); 1289 1290 /* tell MAC where rings are in memory */ 1291 #ifdef __LP64__ 1292 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1293 #endif 1294 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1295 #ifdef __LP64__ 1296 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1297 #endif 1298 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1299 1300 NFE_WRITE(sc, NFE_RING_SIZE, 1301 (NFE_RX_RING_COUNT - 1) << 16 | 1302 (NFE_TX_RING_COUNT - 1)); 1303 1304 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1305 1306 /* force MAC to wakeup */ 1307 tmp = NFE_READ(sc, NFE_PWR_STATE); 1308 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1309 DELAY(10); 1310 tmp = NFE_READ(sc, NFE_PWR_STATE); 1311 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1312 1313 s = splnet(); 1314 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1315 nfe_intr(sc); /* XXX clear IRQ status registers */ 1316 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1317 splx(s); 1318 1319 #if 1 1320 /* configure interrupts coalescing/mitigation */ 1321 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1322 #else 1323 /* no interrupt mitigation: one interrupt per packet */ 1324 NFE_WRITE(sc, NFE_IMTIMER, 970); 1325 #endif 1326 1327 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1328 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1329 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1330 1331 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1332 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1333 1334 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1335 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_ENABLE); 1336 1337 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1338 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1339 DELAY(10); 1340 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1341 1342 /* set Rx filter */ 1343 nfe_setmulti(sc); 1344 1345 if ((rc = ether_mediachange(ifp)) != 0) 1346 goto out; 1347 1348 nfe_tick(sc); 1349 1350 /* enable Rx */ 1351 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1352 1353 /* enable Tx */ 1354 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1355 1356 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1357 1358 /* enable interrupts */ 1359 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1360 1361 callout_schedule(&sc->sc_tick_ch, hz); 1362 1363 ifp->if_flags |= IFF_RUNNING; 1364 ifp->if_flags &= ~IFF_OACTIVE; 1365 1366 out: 1367 return rc; 1368 } 1369 1370 void 1371 nfe_stop(struct ifnet *ifp, int disable) 1372 { 1373 struct nfe_softc *sc = ifp->if_softc; 1374 1375 callout_stop(&sc->sc_tick_ch); 1376 1377 ifp->if_timer = 0; 1378 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1379 1380 mii_down(&sc->sc_mii); 1381 1382 /* abort Tx */ 1383 NFE_WRITE(sc, NFE_TX_CTL, 0); 1384 1385 /* disable Rx */ 1386 NFE_WRITE(sc, NFE_RX_CTL, 0); 1387 1388 /* disable interrupts */ 1389 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1390 1391 /* reset Tx and Rx rings */ 1392 nfe_reset_tx_ring(sc, &sc->txq); 1393 nfe_reset_rx_ring(sc, &sc->rxq); 1394 } 1395 1396 int 1397 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1398 { 1399 struct nfe_desc32 *desc32; 1400 struct nfe_desc64 *desc64; 1401 struct nfe_rx_data *data; 1402 struct nfe_jbuf *jbuf; 1403 void **desc; 1404 bus_addr_t physaddr; 1405 int i, nsegs, error, descsize; 1406 1407 if (sc->sc_flags & NFE_40BIT_ADDR) { 1408 desc = (void **)&ring->desc64; 1409 descsize = sizeof (struct nfe_desc64); 1410 } else { 1411 desc = (void **)&ring->desc32; 1412 descsize = sizeof (struct nfe_desc32); 1413 } 1414 1415 ring->cur = ring->next = 0; 1416 ring->bufsz = MCLBYTES; 1417 1418 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1419 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1420 if (error != 0) { 1421 aprint_error_dev(sc->sc_dev, 1422 "could not create desc DMA map\n"); 1423 ring->map = NULL; 1424 goto fail; 1425 } 1426 1427 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1428 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1429 if (error != 0) { 1430 aprint_error_dev(sc->sc_dev, 1431 "could not allocate DMA memory\n"); 1432 goto fail; 1433 } 1434 1435 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1436 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1437 if (error != 0) { 1438 aprint_error_dev(sc->sc_dev, 1439 "could not map desc DMA memory\n"); 1440 goto fail; 1441 } 1442 1443 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1444 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1445 if (error != 0) { 1446 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1447 goto fail; 1448 } 1449 1450 memset(*desc, 0, NFE_RX_RING_COUNT * descsize); 1451 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1452 1453 if (sc->sc_flags & NFE_USE_JUMBO) { 1454 ring->bufsz = NFE_JBYTES; 1455 if ((error = nfe_jpool_alloc(sc)) != 0) { 1456 aprint_error_dev(sc->sc_dev, 1457 "could not allocate jumbo frames\n"); 1458 goto fail; 1459 } 1460 } 1461 1462 /* 1463 * Pre-allocate Rx buffers and populate Rx ring. 1464 */ 1465 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1466 data = &sc->rxq.data[i]; 1467 1468 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1469 if (data->m == NULL) { 1470 aprint_error_dev(sc->sc_dev, 1471 "could not allocate rx mbuf\n"); 1472 error = ENOMEM; 1473 goto fail; 1474 } 1475 1476 if (sc->sc_flags & NFE_USE_JUMBO) { 1477 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1478 aprint_error_dev(sc->sc_dev, 1479 "could not allocate jumbo buffer\n"); 1480 goto fail; 1481 } 1482 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1483 sc); 1484 1485 physaddr = jbuf->physaddr; 1486 } else { 1487 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1488 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1489 if (error != 0) { 1490 aprint_error_dev(sc->sc_dev, 1491 "could not create DMA map\n"); 1492 data->map = NULL; 1493 goto fail; 1494 } 1495 MCLGET(data->m, M_DONTWAIT); 1496 if (!(data->m->m_flags & M_EXT)) { 1497 aprint_error_dev(sc->sc_dev, 1498 "could not allocate mbuf cluster\n"); 1499 error = ENOMEM; 1500 goto fail; 1501 } 1502 1503 error = bus_dmamap_load(sc->sc_dmat, data->map, 1504 mtod(data->m, void *), MCLBYTES, NULL, 1505 BUS_DMA_READ | BUS_DMA_NOWAIT); 1506 if (error != 0) { 1507 aprint_error_dev(sc->sc_dev, 1508 "could not load rx buf DMA map"); 1509 goto fail; 1510 } 1511 physaddr = data->map->dm_segs[0].ds_addr; 1512 } 1513 1514 if (sc->sc_flags & NFE_40BIT_ADDR) { 1515 desc64 = &sc->rxq.desc64[i]; 1516 #if defined(__LP64__) 1517 desc64->physaddr[0] = htole32(physaddr >> 32); 1518 #endif 1519 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1520 desc64->length = htole16(sc->rxq.bufsz); 1521 desc64->flags = htole16(NFE_RX_READY); 1522 } else { 1523 desc32 = &sc->rxq.desc32[i]; 1524 desc32->physaddr = htole32(physaddr); 1525 desc32->length = htole16(sc->rxq.bufsz); 1526 desc32->flags = htole16(NFE_RX_READY); 1527 } 1528 } 1529 1530 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1531 BUS_DMASYNC_PREWRITE); 1532 1533 return 0; 1534 1535 fail: nfe_free_rx_ring(sc, ring); 1536 return error; 1537 } 1538 1539 void 1540 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1541 { 1542 int i; 1543 1544 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1545 if (sc->sc_flags & NFE_40BIT_ADDR) { 1546 ring->desc64[i].length = htole16(ring->bufsz); 1547 ring->desc64[i].flags = htole16(NFE_RX_READY); 1548 } else { 1549 ring->desc32[i].length = htole16(ring->bufsz); 1550 ring->desc32[i].flags = htole16(NFE_RX_READY); 1551 } 1552 } 1553 1554 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1555 BUS_DMASYNC_PREWRITE); 1556 1557 ring->cur = ring->next = 0; 1558 } 1559 1560 void 1561 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1562 { 1563 struct nfe_rx_data *data; 1564 void *desc; 1565 int i, descsize; 1566 1567 if (sc->sc_flags & NFE_40BIT_ADDR) { 1568 desc = ring->desc64; 1569 descsize = sizeof (struct nfe_desc64); 1570 } else { 1571 desc = ring->desc32; 1572 descsize = sizeof (struct nfe_desc32); 1573 } 1574 1575 if (desc != NULL) { 1576 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1577 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1578 bus_dmamap_unload(sc->sc_dmat, ring->map); 1579 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1580 NFE_RX_RING_COUNT * descsize); 1581 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1582 } 1583 1584 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1585 data = &ring->data[i]; 1586 1587 if (data->map != NULL) { 1588 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1589 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1590 bus_dmamap_unload(sc->sc_dmat, data->map); 1591 bus_dmamap_destroy(sc->sc_dmat, data->map); 1592 } 1593 if (data->m != NULL) 1594 m_freem(data->m); 1595 } 1596 1597 nfe_jpool_free(sc); 1598 } 1599 1600 struct nfe_jbuf * 1601 nfe_jalloc(struct nfe_softc *sc, int i) 1602 { 1603 struct nfe_jbuf *jbuf; 1604 1605 mutex_enter(&sc->rxq.mtx); 1606 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1607 if (jbuf != NULL) 1608 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1609 mutex_exit(&sc->rxq.mtx); 1610 if (jbuf == NULL) 1611 return NULL; 1612 sc->rxq.jbufmap[i] = 1613 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1614 return jbuf; 1615 } 1616 1617 /* 1618 * This is called automatically by the network stack when the mbuf is freed. 1619 * Caution must be taken that the NIC might be reset by the time the mbuf is 1620 * freed. 1621 */ 1622 void 1623 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1624 { 1625 struct nfe_softc *sc = arg; 1626 struct nfe_jbuf *jbuf; 1627 int i; 1628 1629 /* find the jbuf from the base pointer */ 1630 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1631 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1632 aprint_error_dev(sc->sc_dev, 1633 "request to free a buffer (%p) not managed by us\n", buf); 1634 return; 1635 } 1636 jbuf = &sc->rxq.jbuf[i]; 1637 1638 /* ..and put it back in the free list */ 1639 mutex_enter(&sc->rxq.mtx); 1640 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1641 mutex_exit(&sc->rxq.mtx); 1642 1643 if (m != NULL) 1644 pool_cache_put(mb_cache, m); 1645 } 1646 1647 int 1648 nfe_jpool_alloc(struct nfe_softc *sc) 1649 { 1650 struct nfe_rx_ring *ring = &sc->rxq; 1651 struct nfe_jbuf *jbuf; 1652 bus_addr_t physaddr; 1653 char *buf; 1654 int i, nsegs, error; 1655 1656 /* 1657 * Allocate a big chunk of DMA'able memory. 1658 */ 1659 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1660 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1661 if (error != 0) { 1662 aprint_error_dev(sc->sc_dev, 1663 "could not create jumbo DMA map\n"); 1664 ring->jmap = NULL; 1665 goto fail; 1666 } 1667 1668 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1669 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1670 if (error != 0) { 1671 aprint_error_dev(sc->sc_dev, 1672 "could not allocate jumbo DMA memory\n"); 1673 goto fail; 1674 } 1675 1676 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1677 &ring->jpool, BUS_DMA_NOWAIT); 1678 if (error != 0) { 1679 aprint_error_dev(sc->sc_dev, 1680 "could not map jumbo DMA memory\n"); 1681 goto fail; 1682 } 1683 1684 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1685 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1686 if (error != 0) { 1687 aprint_error_dev(sc->sc_dev, 1688 "could not load jumbo DMA map\n"); 1689 goto fail; 1690 } 1691 1692 /* ..and split it into 9KB chunks */ 1693 SLIST_INIT(&ring->jfreelist); 1694 1695 buf = ring->jpool; 1696 physaddr = ring->jmap->dm_segs[0].ds_addr; 1697 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1698 jbuf = &ring->jbuf[i]; 1699 1700 jbuf->buf = buf; 1701 jbuf->physaddr = physaddr; 1702 1703 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1704 1705 buf += NFE_JBYTES; 1706 physaddr += NFE_JBYTES; 1707 } 1708 1709 return 0; 1710 1711 fail: nfe_jpool_free(sc); 1712 return error; 1713 } 1714 1715 void 1716 nfe_jpool_free(struct nfe_softc *sc) 1717 { 1718 struct nfe_rx_ring *ring = &sc->rxq; 1719 1720 if (ring->jmap != NULL) { 1721 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1722 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1723 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1724 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1725 ring->jmap = NULL; 1726 } 1727 if (ring->jpool != NULL) { 1728 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1729 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1730 ring->jpool = NULL; 1731 } 1732 } 1733 1734 int 1735 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1736 { 1737 int i, nsegs, error; 1738 void **desc; 1739 int descsize; 1740 1741 if (sc->sc_flags & NFE_40BIT_ADDR) { 1742 desc = (void **)&ring->desc64; 1743 descsize = sizeof (struct nfe_desc64); 1744 } else { 1745 desc = (void **)&ring->desc32; 1746 descsize = sizeof (struct nfe_desc32); 1747 } 1748 1749 ring->queued = 0; 1750 ring->cur = ring->next = 0; 1751 1752 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1753 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1754 1755 if (error != 0) { 1756 aprint_error_dev(sc->sc_dev, 1757 "could not create desc DMA map\n"); 1758 ring->map = NULL; 1759 goto fail; 1760 } 1761 1762 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1763 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1764 if (error != 0) { 1765 aprint_error_dev(sc->sc_dev, 1766 "could not allocate DMA memory\n"); 1767 goto fail; 1768 } 1769 1770 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1771 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1772 if (error != 0) { 1773 aprint_error_dev(sc->sc_dev, 1774 "could not map desc DMA memory\n"); 1775 goto fail; 1776 } 1777 1778 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1779 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1780 if (error != 0) { 1781 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1782 goto fail; 1783 } 1784 1785 memset(*desc, 0, NFE_TX_RING_COUNT * descsize); 1786 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1787 1788 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1789 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1790 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1791 &ring->data[i].map); 1792 if (error != 0) { 1793 aprint_error_dev(sc->sc_dev, 1794 "could not create DMA map\n"); 1795 ring->data[i].map = NULL; 1796 goto fail; 1797 } 1798 } 1799 1800 return 0; 1801 1802 fail: nfe_free_tx_ring(sc, ring); 1803 return error; 1804 } 1805 1806 void 1807 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1808 { 1809 struct nfe_tx_data *data; 1810 int i; 1811 1812 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1813 if (sc->sc_flags & NFE_40BIT_ADDR) 1814 ring->desc64[i].flags = 0; 1815 else 1816 ring->desc32[i].flags = 0; 1817 1818 data = &ring->data[i]; 1819 1820 if (data->m != NULL) { 1821 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1822 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1823 bus_dmamap_unload(sc->sc_dmat, data->active); 1824 m_freem(data->m); 1825 data->m = NULL; 1826 } 1827 } 1828 1829 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1830 BUS_DMASYNC_PREWRITE); 1831 1832 ring->queued = 0; 1833 ring->cur = ring->next = 0; 1834 } 1835 1836 void 1837 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1838 { 1839 struct nfe_tx_data *data; 1840 void *desc; 1841 int i, descsize; 1842 1843 if (sc->sc_flags & NFE_40BIT_ADDR) { 1844 desc = ring->desc64; 1845 descsize = sizeof (struct nfe_desc64); 1846 } else { 1847 desc = ring->desc32; 1848 descsize = sizeof (struct nfe_desc32); 1849 } 1850 1851 if (desc != NULL) { 1852 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1853 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1854 bus_dmamap_unload(sc->sc_dmat, ring->map); 1855 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1856 NFE_TX_RING_COUNT * descsize); 1857 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1858 } 1859 1860 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1861 data = &ring->data[i]; 1862 1863 if (data->m != NULL) { 1864 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1865 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1866 bus_dmamap_unload(sc->sc_dmat, data->active); 1867 m_freem(data->m); 1868 } 1869 } 1870 1871 /* ..and now actually destroy the DMA mappings */ 1872 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1873 data = &ring->data[i]; 1874 if (data->map == NULL) 1875 continue; 1876 bus_dmamap_destroy(sc->sc_dmat, data->map); 1877 } 1878 } 1879 1880 void 1881 nfe_setmulti(struct nfe_softc *sc) 1882 { 1883 struct ethercom *ec = &sc->sc_ethercom; 1884 struct ifnet *ifp = &ec->ec_if; 1885 struct ether_multi *enm; 1886 struct ether_multistep step; 1887 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1888 uint32_t filter = NFE_RXFILTER_MAGIC; 1889 int i; 1890 1891 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1892 memset(addr, 0, ETHER_ADDR_LEN); 1893 memset(mask, 0, ETHER_ADDR_LEN); 1894 goto done; 1895 } 1896 1897 memcpy(addr, etherbroadcastaddr, ETHER_ADDR_LEN); 1898 memcpy(mask, etherbroadcastaddr, ETHER_ADDR_LEN); 1899 1900 ETHER_FIRST_MULTI(step, ec, enm); 1901 while (enm != NULL) { 1902 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1903 ifp->if_flags |= IFF_ALLMULTI; 1904 memset(addr, 0, ETHER_ADDR_LEN); 1905 memset(mask, 0, ETHER_ADDR_LEN); 1906 goto done; 1907 } 1908 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1909 addr[i] &= enm->enm_addrlo[i]; 1910 mask[i] &= ~enm->enm_addrlo[i]; 1911 } 1912 ETHER_NEXT_MULTI(step, enm); 1913 } 1914 for (i = 0; i < ETHER_ADDR_LEN; i++) 1915 mask[i] |= addr[i]; 1916 1917 done: 1918 addr[0] |= 0x01; /* make sure multicast bit is set */ 1919 1920 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1921 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1922 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1923 addr[5] << 8 | addr[4]); 1924 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1925 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1926 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1927 mask[5] << 8 | mask[4]); 1928 1929 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1930 NFE_WRITE(sc, NFE_RXFILTER, filter); 1931 } 1932 1933 void 1934 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1935 { 1936 uint32_t tmp; 1937 1938 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 1939 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1940 addr[0] = (tmp & 0xff); 1941 addr[1] = (tmp >> 8) & 0xff; 1942 addr[2] = (tmp >> 16) & 0xff; 1943 addr[3] = (tmp >> 24) & 0xff; 1944 1945 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1946 addr[4] = (tmp & 0xff); 1947 addr[5] = (tmp >> 8) & 0xff; 1948 1949 } else { 1950 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1951 addr[0] = (tmp >> 8) & 0xff; 1952 addr[1] = (tmp & 0xff); 1953 1954 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1955 addr[2] = (tmp >> 24) & 0xff; 1956 addr[3] = (tmp >> 16) & 0xff; 1957 addr[4] = (tmp >> 8) & 0xff; 1958 addr[5] = (tmp & 0xff); 1959 } 1960 } 1961 1962 void 1963 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1964 { 1965 NFE_WRITE(sc, NFE_MACADDR_LO, 1966 addr[5] << 8 | addr[4]); 1967 NFE_WRITE(sc, NFE_MACADDR_HI, 1968 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1969 } 1970 1971 void 1972 nfe_tick(void *arg) 1973 { 1974 struct nfe_softc *sc = arg; 1975 int s; 1976 1977 s = splnet(); 1978 mii_tick(&sc->sc_mii); 1979 splx(s); 1980 1981 callout_schedule(&sc->sc_tick_ch, hz); 1982 } 1983 1984 void 1985 nfe_poweron(device_t self) 1986 { 1987 struct nfe_softc *sc = device_private(self); 1988 1989 if ((sc->sc_flags & NFE_PWR_MGMT) != 0) { 1990 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 1991 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 1992 DELAY(100); 1993 NFE_WRITE(sc, NFE_MAC_RESET, 0); 1994 DELAY(100); 1995 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 1996 NFE_WRITE(sc, NFE_PWR2_CTL, 1997 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_WAKEUP_MASK); 1998 } 1999 } 2000 2001 bool 2002 nfe_resume(device_t dv, const pmf_qual_t *qual) 2003 { 2004 nfe_poweron(dv); 2005 2006 return true; 2007 } 2008
Indexes created Tue Sep 30 07:10:03 GMT 2025