if_nfe.c revision 1.7.2.1.2.2
1 /* $NetBSD: if_nfe.c,v 1.7.2.1.2.2 2008/06/03 20:47:24 skrll Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.52 2006/03/02 09:04:00 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.7.2.1.2.2 2008/06/03 20:47:24 skrll Exp $"); 25 26 #include "opt_inet.h" 27 #include "bpfilter.h" 28 #include "vlan.h" 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/types.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/queue.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/socket.h> 41 42 #include <machine/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/pci/if_nfereg.h> 74 #include <dev/pci/if_nfevar.h> 75 76 int nfe_match(struct device *, struct cfdata *, void *); 77 void nfe_attach(struct device *, struct device *, void *); 78 void nfe_power(int, void *); 79 void nfe_miibus_statchg(struct device *); 80 int nfe_miibus_readreg(struct device *, int, int); 81 void nfe_miibus_writereg(struct device *, int, int, int); 82 int nfe_intr(void *); 83 int nfe_ioctl(struct ifnet *, u_long, caddr_t); 84 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 85 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 86 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 87 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 88 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 89 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 90 void nfe_rxeof(struct nfe_softc *); 91 void nfe_txeof(struct nfe_softc *); 92 int nfe_encap(struct nfe_softc *, struct mbuf *); 93 void nfe_start(struct ifnet *); 94 void nfe_watchdog(struct ifnet *); 95 int nfe_init(struct ifnet *); 96 void nfe_stop(struct ifnet *, int); 97 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 98 void nfe_jfree(struct mbuf *, caddr_t, size_t, void *); 99 int nfe_jpool_alloc(struct nfe_softc *); 100 void nfe_jpool_free(struct nfe_softc *); 101 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 102 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 105 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 int nfe_ifmedia_upd(struct ifnet *); 108 void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 109 void nfe_setmulti(struct nfe_softc *); 110 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 111 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 112 void nfe_tick(void *); 113 114 CFATTACH_DECL(nfe, sizeof(struct nfe_softc), nfe_match, nfe_attach, NULL, NULL); 115 116 /*#define NFE_NO_JUMBO*/ 117 118 #ifdef NFE_DEBUG 119 int nfedebug = 0; 120 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 121 #define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 122 #else 123 #define DPRINTF(x) 124 #define DPRINTFN(n,x) 125 #endif 126 127 /* deal with naming differences */ 128 129 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 130 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 134 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 135 136 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 137 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 140 141 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 142 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 145 146 #ifdef _LP64 147 #define __LP64__ 1 148 #endif 149 150 const struct nfe_product { 151 pci_vendor_id_t vendor; 152 pci_product_id_t product; 153 } nfe_devices[] = { 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 155 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 183 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 184 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 } 185 }; 186 187 int 188 nfe_match(struct device *dev, struct cfdata *match, void *aux) 189 { 190 struct pci_attach_args *pa = aux; 191 const struct nfe_product *np; 192 int i; 193 194 for (i = 0; i < sizeof(nfe_devices) / sizeof(nfe_devices[0]); i++) { 195 np = &nfe_devices[i]; 196 if (PCI_VENDOR(pa->pa_id) == np->vendor && 197 PCI_PRODUCT(pa->pa_id) == np->product) 198 return 1; 199 } 200 return 0; 201 } 202 203 void 204 nfe_attach(struct device *parent, struct device *self, void *aux) 205 { 206 struct nfe_softc *sc = (struct nfe_softc *)self; 207 struct pci_attach_args *pa = aux; 208 pci_chipset_tag_t pc = pa->pa_pc; 209 pci_intr_handle_t ih; 210 const char *intrstr; 211 struct ifnet *ifp; 212 bus_size_t memsize; 213 pcireg_t memtype; 214 char devinfo[256]; 215 216 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 217 aprint_normal(": %s (rev. 0x%02x)\n", 218 devinfo, PCI_REVISION(pa->pa_class)); 219 220 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 221 switch (memtype) { 222 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 223 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 224 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 225 &sc->sc_memh, NULL, &memsize) == 0) 226 break; 227 /* FALLTHROUGH */ 228 default: 229 printf("%s: could not map mem space\n", sc->sc_dev.dv_xname); 230 return; 231 } 232 233 if (pci_intr_map(pa, &ih) != 0) { 234 printf("%s: could not map interrupt\n", sc->sc_dev.dv_xname); 235 return; 236 } 237 238 intrstr = pci_intr_string(pc, ih); 239 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc); 240 if (sc->sc_ih == NULL) { 241 printf("%s: could not establish interrupt", 242 sc->sc_dev.dv_xname); 243 if (intrstr != NULL) 244 printf(" at %s", intrstr); 245 printf("\n"); 246 return; 247 } 248 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 249 250 sc->sc_dmat = pa->pa_dmat; 251 252 /* Check for reversed ethernet address */ 253 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 254 sc->sc_flags |= NFE_CORRECT_MACADDR; 255 256 nfe_get_macaddr(sc, sc->sc_enaddr); 257 printf("%s: Ethernet address %s\n", 258 sc->sc_dev.dv_xname, ether_sprintf(sc->sc_enaddr)); 259 260 sc->sc_flags = 0; 261 262 switch (PCI_PRODUCT(pa->pa_id)) { 263 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 264 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 265 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 266 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 267 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 268 break; 269 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 270 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 271 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 272 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 273 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 274 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 275 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 276 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 277 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 278 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 279 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 280 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 281 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 282 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 283 sc->sc_flags |= NFE_40BIT_ADDR |NFE_PWR_MGMT; 284 break; 285 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 286 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 287 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 288 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 289 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 290 break; 291 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 292 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 293 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 294 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 295 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 296 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 297 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 298 NFE_HW_VLAN | NFE_PWR_MGMT; 299 break; 300 } 301 302 if ((sc->sc_flags & NFE_PWR_MGMT) != 0) { 303 /* wakeup some newer chips from powerdown mode */ 304 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 305 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 306 DELAY(100); 307 NFE_WRITE(sc, NFE_MAC_RESET, 0); 308 DELAY(100); 309 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 310 NFE_WRITE(sc, NFE_PWR2_CTL, 311 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_WAKEUP_MASK); 312 } 313 314 #ifndef NFE_NO_JUMBO 315 /* enable jumbo frames for adapters that support it */ 316 if (sc->sc_flags & NFE_JUMBO_SUP) 317 sc->sc_flags |= NFE_USE_JUMBO; 318 #endif 319 320 /* 321 * Allocate Tx and Rx rings. 322 */ 323 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 324 printf("%s: could not allocate Tx ring\n", 325 sc->sc_dev.dv_xname); 326 return; 327 } 328 329 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 330 printf("%s: could not allocate Rx ring\n", 331 sc->sc_dev.dv_xname); 332 nfe_free_tx_ring(sc, &sc->txq); 333 return; 334 } 335 336 ifp = &sc->sc_ethercom.ec_if; 337 ifp->if_softc = sc; 338 ifp->if_mtu = ETHERMTU; 339 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 340 ifp->if_ioctl = nfe_ioctl; 341 ifp->if_start = nfe_start; 342 ifp->if_watchdog = nfe_watchdog; 343 ifp->if_init = nfe_init; 344 ifp->if_baudrate = IF_Gbps(1); 345 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 346 IFQ_SET_READY(&ifp->if_snd); 347 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 348 349 #if NVLAN > 0 350 if (sc->sc_flags & NFE_HW_VLAN) 351 sc->sc_ethercom.ec_capabilities |= 352 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 353 #endif 354 if (sc->sc_flags & NFE_HW_CSUM) { 355 ifp->if_capabilities |= 356 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 357 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 358 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 359 } 360 361 sc->sc_mii.mii_ifp = ifp; 362 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 363 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 364 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 365 366 ifmedia_init(&sc->sc_mii.mii_media, 0, nfe_ifmedia_upd, 367 nfe_ifmedia_sts); 368 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 369 MII_OFFSET_ANY, 0); 370 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 371 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 372 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 373 0, NULL); 374 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 375 } else 376 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 377 378 if_attach(ifp); 379 ether_ifattach(ifp, sc->sc_enaddr); 380 381 callout_init(&sc->sc_tick_ch); 382 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 383 384 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 385 nfe_power, sc); 386 } 387 388 void 389 nfe_power(int why, void *arg) 390 { 391 struct nfe_softc *sc = arg; 392 struct ifnet *ifp; 393 394 if (why == PWR_RESUME) { 395 ifp = &sc->sc_ethercom.ec_if; 396 if (ifp->if_flags & IFF_UP) { 397 ifp->if_flags &= ~IFF_RUNNING; 398 nfe_init(ifp); 399 if (ifp->if_flags & IFF_RUNNING) 400 nfe_start(ifp); 401 } 402 } 403 } 404 405 void 406 nfe_miibus_statchg(struct device *dev) 407 { 408 struct nfe_softc *sc = (struct nfe_softc *)dev; 409 struct mii_data *mii = &sc->sc_mii; 410 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 411 412 phy = NFE_READ(sc, NFE_PHY_IFACE); 413 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 414 415 seed = NFE_READ(sc, NFE_RNDSEED); 416 seed &= ~NFE_SEED_MASK; 417 418 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 419 phy |= NFE_PHY_HDX; /* half-duplex */ 420 misc |= NFE_MISC1_HDX; 421 } 422 423 switch (IFM_SUBTYPE(mii->mii_media_active)) { 424 case IFM_1000_T: /* full-duplex only */ 425 link |= NFE_MEDIA_1000T; 426 seed |= NFE_SEED_1000T; 427 phy |= NFE_PHY_1000T; 428 break; 429 case IFM_100_TX: 430 link |= NFE_MEDIA_100TX; 431 seed |= NFE_SEED_100TX; 432 phy |= NFE_PHY_100TX; 433 break; 434 case IFM_10_T: 435 link |= NFE_MEDIA_10T; 436 seed |= NFE_SEED_10T; 437 break; 438 } 439 440 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 441 442 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 443 NFE_WRITE(sc, NFE_MISC1, misc); 444 NFE_WRITE(sc, NFE_LINKSPEED, link); 445 } 446 447 int 448 nfe_miibus_readreg(struct device *dev, int phy, int reg) 449 { 450 struct nfe_softc *sc = (struct nfe_softc *)dev; 451 uint32_t val; 452 int ntries; 453 454 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 455 456 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 457 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 458 DELAY(100); 459 } 460 461 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 462 463 for (ntries = 0; ntries < 1000; ntries++) { 464 DELAY(100); 465 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 466 break; 467 } 468 if (ntries == 1000) { 469 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 470 sc->sc_dev.dv_xname)); 471 return 0; 472 } 473 474 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 475 DPRINTFN(2, ("%s: could not read PHY\n", 476 sc->sc_dev.dv_xname)); 477 return 0; 478 } 479 480 val = NFE_READ(sc, NFE_PHY_DATA); 481 if (val != 0xffffffff && val != 0) 482 sc->mii_phyaddr = phy; 483 484 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 485 sc->sc_dev.dv_xname, phy, reg, val)); 486 487 return val; 488 } 489 490 void 491 nfe_miibus_writereg(struct device *dev, int phy, int reg, int val) 492 { 493 struct nfe_softc *sc = (struct nfe_softc *)dev; 494 uint32_t ctl; 495 int ntries; 496 497 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 498 499 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 500 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 501 DELAY(100); 502 } 503 504 NFE_WRITE(sc, NFE_PHY_DATA, val); 505 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 506 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 507 508 for (ntries = 0; ntries < 1000; ntries++) { 509 DELAY(100); 510 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 511 break; 512 } 513 #ifdef NFE_DEBUG 514 if (nfedebug >= 2 && ntries == 1000) 515 printf("could not write to PHY\n"); 516 #endif 517 } 518 519 int 520 nfe_intr(void *arg) 521 { 522 struct nfe_softc *sc = arg; 523 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 524 uint32_t r; 525 int handled; 526 527 if ((ifp->if_flags & IFF_UP) == 0) 528 return 0; 529 530 handled = 0; 531 532 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 533 534 for (;;) { 535 r = NFE_READ(sc, NFE_IRQ_STATUS); 536 if ((r & NFE_IRQ_WANTED) == 0) 537 break; 538 539 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 540 handled = 1; 541 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 542 543 if ((r & (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX)) 544 != 0) { 545 /* check Rx ring */ 546 nfe_rxeof(sc); 547 } 548 549 if ((r & (NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE)) 550 != 0) { 551 /* check Tx ring */ 552 nfe_txeof(sc); 553 } 554 555 if ((r & NFE_IRQ_LINK) != 0) { 556 NFE_READ(sc, NFE_PHY_STATUS); 557 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 558 DPRINTF(("%s: link state changed\n", 559 sc->sc_dev.dv_xname)); 560 } 561 } 562 563 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 564 565 if (handled && !IF_IS_EMPTY(&ifp->if_snd)) 566 nfe_start(ifp); 567 568 return handled; 569 } 570 571 int 572 nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 573 { 574 struct nfe_softc *sc = ifp->if_softc; 575 struct ifreq *ifr = (struct ifreq *)data; 576 struct ifaddr *ifa = (struct ifaddr *)data; 577 int s, error = 0; 578 579 s = splnet(); 580 581 switch (cmd) { 582 case SIOCSIFADDR: 583 ifp->if_flags |= IFF_UP; 584 nfe_init(ifp); 585 switch (ifa->ifa_addr->sa_family) { 586 #ifdef INET 587 case AF_INET: 588 arp_ifinit(ifp, ifa); 589 break; 590 #endif 591 default: 592 break; 593 } 594 break; 595 case SIOCSIFMTU: 596 if (ifr->ifr_mtu < ETHERMIN || 597 ((sc->sc_flags & NFE_USE_JUMBO) && 598 ifr->ifr_mtu > ETHERMTU_JUMBO) || 599 (!(sc->sc_flags & NFE_USE_JUMBO) && 600 ifr->ifr_mtu > ETHERMTU)) 601 error = EINVAL; 602 else if (ifp->if_mtu != ifr->ifr_mtu) 603 ifp->if_mtu = ifr->ifr_mtu; 604 break; 605 case SIOCSIFFLAGS: 606 if (ifp->if_flags & IFF_UP) { 607 /* 608 * If only the PROMISC or ALLMULTI flag changes, then 609 * don't do a full re-init of the chip, just update 610 * the Rx filter. 611 */ 612 if ((ifp->if_flags & IFF_RUNNING) && 613 ((ifp->if_flags ^ sc->sc_if_flags) & 614 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 615 nfe_setmulti(sc); 616 else 617 nfe_init(ifp); 618 } else { 619 if (ifp->if_flags & IFF_RUNNING) 620 nfe_stop(ifp, 1); 621 } 622 sc->sc_if_flags = ifp->if_flags; 623 break; 624 case SIOCADDMULTI: 625 case SIOCDELMULTI: 626 error = (cmd == SIOCADDMULTI) ? 627 ether_addmulti(ifr, &sc->sc_ethercom) : 628 ether_delmulti(ifr, &sc->sc_ethercom); 629 630 if (error == ENETRESET) { 631 if (ifp->if_flags & IFF_RUNNING) 632 nfe_setmulti(sc); 633 error = 0; 634 } 635 break; 636 case SIOCSIFMEDIA: 637 case SIOCGIFMEDIA: 638 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 639 break; 640 default: 641 error = ether_ioctl(ifp, cmd, data); 642 if (error == ENETRESET) { 643 if (ifp->if_flags & IFF_RUNNING) 644 nfe_setmulti(sc); 645 error = 0; 646 } 647 break; 648 649 } 650 651 splx(s); 652 653 return error; 654 } 655 656 void 657 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 658 { 659 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 660 (caddr_t)desc32 - (caddr_t)sc->txq.desc32, 661 sizeof (struct nfe_desc32), ops); 662 } 663 664 void 665 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 666 { 667 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 668 (caddr_t)desc64 - (caddr_t)sc->txq.desc64, 669 sizeof (struct nfe_desc64), ops); 670 } 671 672 void 673 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 674 { 675 if (end > start) { 676 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 677 (caddr_t)&sc->txq.desc32[start] - (caddr_t)sc->txq.desc32, 678 (caddr_t)&sc->txq.desc32[end] - 679 (caddr_t)&sc->txq.desc32[start], ops); 680 return; 681 } 682 /* sync from 'start' to end of ring */ 683 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 684 (caddr_t)&sc->txq.desc32[start] - (caddr_t)sc->txq.desc32, 685 (caddr_t)&sc->txq.desc32[NFE_TX_RING_COUNT] - 686 (caddr_t)&sc->txq.desc32[start], ops); 687 688 /* sync from start of ring to 'end' */ 689 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 690 (caddr_t)&sc->txq.desc32[end] - (caddr_t)sc->txq.desc32, ops); 691 } 692 693 void 694 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 695 { 696 if (end > start) { 697 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 698 (caddr_t)&sc->txq.desc64[start] - (caddr_t)sc->txq.desc64, 699 (caddr_t)&sc->txq.desc64[end] - 700 (caddr_t)&sc->txq.desc64[start], ops); 701 return; 702 } 703 /* sync from 'start' to end of ring */ 704 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 705 (caddr_t)&sc->txq.desc64[start] - (caddr_t)sc->txq.desc64, 706 (caddr_t)&sc->txq.desc64[NFE_TX_RING_COUNT] - 707 (caddr_t)&sc->txq.desc64[start], ops); 708 709 /* sync from start of ring to 'end' */ 710 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 711 (caddr_t)&sc->txq.desc64[end] - (caddr_t)sc->txq.desc64, ops); 712 } 713 714 void 715 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 716 { 717 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 718 (caddr_t)desc32 - (caddr_t)sc->rxq.desc32, 719 sizeof (struct nfe_desc32), ops); 720 } 721 722 void 723 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 724 { 725 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 726 (caddr_t)desc64 - (caddr_t)sc->rxq.desc64, 727 sizeof (struct nfe_desc64), ops); 728 } 729 730 void 731 nfe_rxeof(struct nfe_softc *sc) 732 { 733 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 734 struct nfe_desc32 *desc32; 735 struct nfe_desc64 *desc64; 736 struct nfe_rx_data *data; 737 struct nfe_jbuf *jbuf; 738 struct mbuf *m, *mnew; 739 bus_addr_t physaddr; 740 uint16_t flags; 741 int error, len, i; 742 743 desc32 = NULL; 744 desc64 = NULL; 745 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 746 data = &sc->rxq.data[i]; 747 748 if (sc->sc_flags & NFE_40BIT_ADDR) { 749 desc64 = &sc->rxq.desc64[i]; 750 nfe_rxdesc64_sync(sc, desc64, 751 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 752 753 flags = le16toh(desc64->flags); 754 len = le16toh(desc64->length) & 0x3fff; 755 } else { 756 desc32 = &sc->rxq.desc32[i]; 757 nfe_rxdesc32_sync(sc, desc32, 758 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 759 760 flags = le16toh(desc32->flags); 761 len = le16toh(desc32->length) & 0x3fff; 762 } 763 764 if ((flags & NFE_RX_READY) != 0) 765 break; 766 767 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 768 if ((flags & NFE_RX_VALID_V1) == 0) 769 goto skip; 770 771 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 772 flags &= ~NFE_RX_ERROR; 773 len--; /* fix buffer length */ 774 } 775 } else { 776 if ((flags & NFE_RX_VALID_V2) == 0) 777 goto skip; 778 779 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 780 flags &= ~NFE_RX_ERROR; 781 len--; /* fix buffer length */ 782 } 783 } 784 785 if (flags & NFE_RX_ERROR) { 786 ifp->if_ierrors++; 787 goto skip; 788 } 789 790 /* 791 * Try to allocate a new mbuf for this ring element and load 792 * it before processing the current mbuf. If the ring element 793 * cannot be loaded, drop the received packet and reuse the 794 * old mbuf. In the unlikely case that the old mbuf can't be 795 * reloaded either, explicitly panic. 796 */ 797 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 798 if (mnew == NULL) { 799 ifp->if_ierrors++; 800 goto skip; 801 } 802 803 if (sc->sc_flags & NFE_USE_JUMBO) { 804 physaddr = 805 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 806 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 807 if (len > MCLBYTES) { 808 m_freem(mnew); 809 ifp->if_ierrors++; 810 goto skip1; 811 } 812 MCLGET(mnew, M_DONTWAIT); 813 if ((mnew->m_flags & M_EXT) == 0) { 814 m_freem(mnew); 815 ifp->if_ierrors++; 816 goto skip1; 817 } 818 819 memcpy(mtod(mnew, void *), 820 mtod(data->m, const void *), len); 821 m = mnew; 822 goto mbufcopied; 823 } else { 824 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 825 826 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 827 mtod(data->m, char *) - (char *)sc->rxq.jpool, 828 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 829 830 physaddr = jbuf->physaddr; 831 } 832 } else { 833 MCLGET(mnew, M_DONTWAIT); 834 if ((mnew->m_flags & M_EXT) == 0) { 835 m_freem(mnew); 836 ifp->if_ierrors++; 837 goto skip; 838 } 839 840 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 841 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 842 bus_dmamap_unload(sc->sc_dmat, data->map); 843 844 error = bus_dmamap_load(sc->sc_dmat, data->map, 845 mtod(mnew, void *), MCLBYTES, NULL, 846 BUS_DMA_READ | BUS_DMA_NOWAIT); 847 if (error != 0) { 848 m_freem(mnew); 849 850 /* try to reload the old mbuf */ 851 error = bus_dmamap_load(sc->sc_dmat, data->map, 852 mtod(data->m, void *), MCLBYTES, NULL, 853 BUS_DMA_READ | BUS_DMA_NOWAIT); 854 if (error != 0) { 855 /* very unlikely that it will fail.. */ 856 panic("%s: could not load old rx mbuf", 857 sc->sc_dev.dv_xname); 858 } 859 ifp->if_ierrors++; 860 goto skip; 861 } 862 physaddr = data->map->dm_segs[0].ds_addr; 863 } 864 865 /* 866 * New mbuf successfully loaded, update Rx ring and continue 867 * processing. 868 */ 869 m = data->m; 870 data->m = mnew; 871 872 mbufcopied: 873 /* finalize mbuf */ 874 m->m_pkthdr.len = m->m_len = len; 875 m->m_pkthdr.rcvif = ifp; 876 877 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 878 /* 879 * XXX 880 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 881 */ 882 if (flags & NFE_RX_IP_CSUMOK) { 883 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 884 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 885 sc->sc_dev.dv_xname)); 886 } 887 /* 888 * XXX 889 * no way to check M_CSUM_TCP_UDP_BAD or 890 * other protocols? 891 */ 892 if (flags & NFE_RX_UDP_CSUMOK) { 893 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 894 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 895 sc->sc_dev.dv_xname)); 896 } else if (flags & NFE_RX_TCP_CSUMOK) { 897 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 898 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 899 sc->sc_dev.dv_xname)); 900 } 901 } 902 903 #if NBPFILTER > 0 904 if (ifp->if_bpf) 905 bpf_mtap(ifp->if_bpf, m); 906 #endif 907 ifp->if_ipackets++; 908 (*ifp->if_input)(ifp, m); 909 910 skip1: 911 /* update mapping address in h/w descriptor */ 912 if (sc->sc_flags & NFE_40BIT_ADDR) { 913 #if defined(__LP64__) 914 desc64->physaddr[0] = htole32(physaddr >> 32); 915 #endif 916 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 917 } else { 918 desc32->physaddr = htole32(physaddr); 919 } 920 921 skip: 922 if (sc->sc_flags & NFE_40BIT_ADDR) { 923 desc64->length = htole16(sc->rxq.bufsz); 924 desc64->flags = htole16(NFE_RX_READY); 925 926 nfe_rxdesc64_sync(sc, desc64, 927 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 928 } else { 929 desc32->length = htole16(sc->rxq.bufsz); 930 desc32->flags = htole16(NFE_RX_READY); 931 932 nfe_rxdesc32_sync(sc, desc32, 933 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 934 } 935 } 936 /* update current RX pointer */ 937 sc->rxq.cur = i; 938 } 939 940 void 941 nfe_txeof(struct nfe_softc *sc) 942 { 943 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 944 struct nfe_desc32 *desc32; 945 struct nfe_desc64 *desc64; 946 struct nfe_tx_data *data = NULL; 947 int i; 948 uint16_t flags; 949 950 for (i = sc->txq.next; 951 sc->txq.queued > 0; 952 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 953 if (sc->sc_flags & NFE_40BIT_ADDR) { 954 desc64 = &sc->txq.desc64[i]; 955 nfe_txdesc64_sync(sc, desc64, 956 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 957 958 flags = le16toh(desc64->flags); 959 } else { 960 desc32 = &sc->txq.desc32[i]; 961 nfe_txdesc32_sync(sc, desc32, 962 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 963 964 flags = le16toh(desc32->flags); 965 } 966 967 if ((flags & NFE_TX_VALID) != 0) 968 break; 969 970 data = &sc->txq.data[i]; 971 972 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 973 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 974 data->m == NULL) 975 continue; 976 977 if ((flags & NFE_TX_ERROR_V1) != 0) { 978 printf("%s: tx v1 error 0x%04x\n", 979 sc->sc_dev.dv_xname, flags); 980 ifp->if_oerrors++; 981 } else 982 ifp->if_opackets++; 983 } else { 984 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 985 data->m == NULL) 986 continue; 987 988 if ((flags & NFE_TX_ERROR_V2) != 0) { 989 printf("%s: tx v2 error 0x%04x\n", 990 sc->sc_dev.dv_xname, flags); 991 ifp->if_oerrors++; 992 } else 993 ifp->if_opackets++; 994 } 995 996 if (data->m == NULL) { /* should not get there */ 997 printf("%s: last fragment bit w/o associated mbuf!\n", 998 sc->sc_dev.dv_xname); 999 continue; 1000 } 1001 1002 /* last fragment of the mbuf chain transmitted */ 1003 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1004 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1005 bus_dmamap_unload(sc->sc_dmat, data->active); 1006 m_freem(data->m); 1007 data->m = NULL; 1008 } 1009 1010 sc->txq.next = i; 1011 1012 if (sc->txq.queued < NFE_TX_RING_COUNT) { 1013 /* at least one slot freed */ 1014 ifp->if_flags &= ~IFF_OACTIVE; 1015 } 1016 1017 if (sc->txq.queued == 0) { 1018 /* all queued packets are sent */ 1019 ifp->if_timer = 0; 1020 } 1021 } 1022 1023 int 1024 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 1025 { 1026 struct nfe_desc32 *desc32; 1027 struct nfe_desc64 *desc64; 1028 struct nfe_tx_data *data; 1029 bus_dmamap_t map; 1030 uint16_t flags, csumflags; 1031 #if NVLAN > 0 1032 struct m_tag *mtag; 1033 uint32_t vtag = 0; 1034 #endif 1035 int error, i, first; 1036 1037 desc32 = NULL; 1038 desc64 = NULL; 1039 data = NULL; 1040 1041 flags = 0; 1042 csumflags = 0; 1043 first = sc->txq.cur; 1044 1045 map = sc->txq.data[first].map; 1046 1047 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1048 if (error != 0) { 1049 printf("%s: could not map mbuf (error %d)\n", 1050 sc->sc_dev.dv_xname, error); 1051 return error; 1052 } 1053 1054 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1055 bus_dmamap_unload(sc->sc_dmat, map); 1056 return ENOBUFS; 1057 } 1058 1059 #if NVLAN > 0 1060 /* setup h/w VLAN tagging */ 1061 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) 1062 vtag = NFE_TX_VTAG | VLAN_TAG_VALUE(mtag); 1063 #endif 1064 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1065 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1066 csumflags |= NFE_TX_IP_CSUM; 1067 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1068 csumflags |= NFE_TX_TCP_UDP_CSUM; 1069 } 1070 1071 for (i = 0; i < map->dm_nsegs; i++) { 1072 data = &sc->txq.data[sc->txq.cur]; 1073 1074 if (sc->sc_flags & NFE_40BIT_ADDR) { 1075 desc64 = &sc->txq.desc64[sc->txq.cur]; 1076 #if defined(__LP64__) 1077 desc64->physaddr[0] = 1078 htole32(map->dm_segs[i].ds_addr >> 32); 1079 #endif 1080 desc64->physaddr[1] = 1081 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1082 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1083 desc64->flags = htole16(flags); 1084 desc64->vtag = 0; 1085 } else { 1086 desc32 = &sc->txq.desc32[sc->txq.cur]; 1087 1088 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1089 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1090 desc32->flags = htole16(flags); 1091 } 1092 1093 /* 1094 * Setting of the valid bit in the first descriptor is 1095 * deferred until the whole chain is fully setup. 1096 */ 1097 flags |= NFE_TX_VALID; 1098 1099 sc->txq.queued++; 1100 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1101 } 1102 1103 /* the whole mbuf chain has been setup */ 1104 if (sc->sc_flags & NFE_40BIT_ADDR) { 1105 /* fix last descriptor */ 1106 flags |= NFE_TX_LASTFRAG_V2; 1107 desc64->flags = htole16(flags); 1108 1109 /* Checksum flags and vtag belong to the first fragment only. */ 1110 #if NVLAN > 0 1111 sc->txq.desc64[first].vtag = htole32(vtag); 1112 #endif 1113 sc->txq.desc64[first].flags |= htole16(csumflags); 1114 1115 /* finally, set the valid bit in the first descriptor */ 1116 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1117 } else { 1118 /* fix last descriptor */ 1119 if (sc->sc_flags & NFE_JUMBO_SUP) 1120 flags |= NFE_TX_LASTFRAG_V2; 1121 else 1122 flags |= NFE_TX_LASTFRAG_V1; 1123 desc32->flags = htole16(flags); 1124 1125 /* Checksum flags belong to the first fragment only. */ 1126 sc->txq.desc32[first].flags |= htole16(csumflags); 1127 1128 /* finally, set the valid bit in the first descriptor */ 1129 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1130 } 1131 1132 data->m = m0; 1133 data->active = map; 1134 1135 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1136 BUS_DMASYNC_PREWRITE); 1137 1138 return 0; 1139 } 1140 1141 void 1142 nfe_start(struct ifnet *ifp) 1143 { 1144 struct nfe_softc *sc = ifp->if_softc; 1145 int old = sc->txq.queued; 1146 struct mbuf *m0; 1147 1148 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 1149 return; 1150 1151 for (;;) { 1152 IFQ_POLL(&ifp->if_snd, m0); 1153 if (m0 == NULL) 1154 break; 1155 1156 if (nfe_encap(sc, m0) != 0) { 1157 ifp->if_flags |= IFF_OACTIVE; 1158 break; 1159 } 1160 1161 /* packet put in h/w queue, remove from s/w queue */ 1162 IFQ_DEQUEUE(&ifp->if_snd, m0); 1163 1164 #if NBPFILTER > 0 1165 if (ifp->if_bpf != NULL) 1166 bpf_mtap(ifp->if_bpf, m0); 1167 #endif 1168 } 1169 1170 if (sc->txq.queued != old) { 1171 /* packets are queued */ 1172 if (sc->sc_flags & NFE_40BIT_ADDR) 1173 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1174 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1175 else 1176 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1177 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1178 /* kick Tx */ 1179 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1180 1181 /* 1182 * Set a timeout in case the chip goes out to lunch. 1183 */ 1184 ifp->if_timer = 5; 1185 } 1186 } 1187 1188 void 1189 nfe_watchdog(struct ifnet *ifp) 1190 { 1191 struct nfe_softc *sc = ifp->if_softc; 1192 1193 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1194 1195 ifp->if_flags &= ~IFF_RUNNING; 1196 nfe_init(ifp); 1197 1198 ifp->if_oerrors++; 1199 } 1200 1201 int 1202 nfe_init(struct ifnet *ifp) 1203 { 1204 struct nfe_softc *sc = ifp->if_softc; 1205 uint32_t tmp; 1206 int s; 1207 1208 if (ifp->if_flags & IFF_RUNNING) 1209 return 0; 1210 1211 nfe_stop(ifp, 0); 1212 1213 NFE_WRITE(sc, NFE_TX_UNK, 0); 1214 NFE_WRITE(sc, NFE_STATUS, 0); 1215 1216 sc->rxtxctl = NFE_RXTX_BIT2; 1217 if (sc->sc_flags & NFE_40BIT_ADDR) 1218 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1219 else if (sc->sc_flags & NFE_JUMBO_SUP) 1220 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1221 if (sc->sc_flags & NFE_HW_CSUM) 1222 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1223 #if NVLAN > 0 1224 /* 1225 * Although the adapter is capable of stripping VLAN tags from received 1226 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1227 * purpose. This will be done in software by our network stack. 1228 */ 1229 if (sc->sc_flags & NFE_HW_VLAN) 1230 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1231 #endif 1232 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1233 DELAY(10); 1234 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1235 1236 #if NVLAN 1237 if (sc->sc_flags & NFE_HW_VLAN) 1238 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1239 #endif 1240 1241 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1242 1243 /* set MAC address */ 1244 nfe_set_macaddr(sc, sc->sc_enaddr); 1245 1246 /* tell MAC where rings are in memory */ 1247 #ifdef __LP64__ 1248 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1249 #endif 1250 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1251 #ifdef __LP64__ 1252 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1253 #endif 1254 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1255 1256 NFE_WRITE(sc, NFE_RING_SIZE, 1257 (NFE_RX_RING_COUNT - 1) << 16 | 1258 (NFE_TX_RING_COUNT - 1)); 1259 1260 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1261 1262 /* force MAC to wakeup */ 1263 tmp = NFE_READ(sc, NFE_PWR_STATE); 1264 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1265 DELAY(10); 1266 tmp = NFE_READ(sc, NFE_PWR_STATE); 1267 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1268 1269 s = splnet(); 1270 nfe_intr(sc); /* XXX clear IRQ status registers */ 1271 splx(s); 1272 1273 #if 1 1274 /* configure interrupts coalescing/mitigation */ 1275 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1276 #else 1277 /* no interrupt mitigation: one interrupt per packet */ 1278 NFE_WRITE(sc, NFE_IMTIMER, 970); 1279 #endif 1280 1281 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1282 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1283 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1284 1285 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1286 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1287 1288 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1289 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC); 1290 1291 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1292 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1293 DELAY(10); 1294 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1295 1296 /* set Rx filter */ 1297 nfe_setmulti(sc); 1298 1299 nfe_ifmedia_upd(ifp); 1300 1301 nfe_tick(sc); 1302 1303 /* enable Rx */ 1304 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1305 1306 /* enable Tx */ 1307 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1308 1309 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1310 1311 /* enable interrupts */ 1312 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1313 1314 callout_schedule(&sc->sc_tick_ch, hz); 1315 1316 ifp->if_flags |= IFF_RUNNING; 1317 ifp->if_flags &= ~IFF_OACTIVE; 1318 1319 return 0; 1320 } 1321 1322 void 1323 nfe_stop(struct ifnet *ifp, int disable) 1324 { 1325 struct nfe_softc *sc = ifp->if_softc; 1326 1327 callout_stop(&sc->sc_tick_ch); 1328 1329 ifp->if_timer = 0; 1330 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1331 1332 mii_down(&sc->sc_mii); 1333 1334 /* abort Tx */ 1335 NFE_WRITE(sc, NFE_TX_CTL, 0); 1336 1337 /* disable Rx */ 1338 NFE_WRITE(sc, NFE_RX_CTL, 0); 1339 1340 /* disable interrupts */ 1341 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1342 1343 /* reset Tx and Rx rings */ 1344 nfe_reset_tx_ring(sc, &sc->txq); 1345 nfe_reset_rx_ring(sc, &sc->rxq); 1346 } 1347 1348 int 1349 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1350 { 1351 struct nfe_desc32 *desc32; 1352 struct nfe_desc64 *desc64; 1353 struct nfe_rx_data *data; 1354 struct nfe_jbuf *jbuf; 1355 void **desc; 1356 bus_addr_t physaddr; 1357 int i, nsegs, error, descsize; 1358 1359 if (sc->sc_flags & NFE_40BIT_ADDR) { 1360 desc = (void **)&ring->desc64; 1361 descsize = sizeof (struct nfe_desc64); 1362 } else { 1363 desc = (void **)&ring->desc32; 1364 descsize = sizeof (struct nfe_desc32); 1365 } 1366 1367 ring->cur = ring->next = 0; 1368 ring->bufsz = MCLBYTES; 1369 1370 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1371 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1372 if (error != 0) { 1373 printf("%s: could not create desc DMA map\n", 1374 sc->sc_dev.dv_xname); 1375 goto fail; 1376 } 1377 1378 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1379 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1380 if (error != 0) { 1381 printf("%s: could not allocate DMA memory\n", 1382 sc->sc_dev.dv_xname); 1383 goto fail; 1384 } 1385 1386 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1387 NFE_RX_RING_COUNT * descsize, (caddr_t *)desc, BUS_DMA_NOWAIT); 1388 if (error != 0) { 1389 printf("%s: could not map desc DMA memory\n", 1390 sc->sc_dev.dv_xname); 1391 goto fail; 1392 } 1393 1394 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1395 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1396 if (error != 0) { 1397 printf("%s: could not load desc DMA map\n", 1398 sc->sc_dev.dv_xname); 1399 goto fail; 1400 } 1401 1402 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1403 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1404 1405 if (sc->sc_flags & NFE_USE_JUMBO) { 1406 ring->bufsz = NFE_JBYTES; 1407 if ((error = nfe_jpool_alloc(sc)) != 0) { 1408 printf("%s: could not allocate jumbo frames\n", 1409 sc->sc_dev.dv_xname); 1410 goto fail; 1411 } 1412 } 1413 1414 /* 1415 * Pre-allocate Rx buffers and populate Rx ring. 1416 */ 1417 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1418 data = &sc->rxq.data[i]; 1419 1420 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1421 if (data->m == NULL) { 1422 printf("%s: could not allocate rx mbuf\n", 1423 sc->sc_dev.dv_xname); 1424 error = ENOMEM; 1425 goto fail; 1426 } 1427 1428 if (sc->sc_flags & NFE_USE_JUMBO) { 1429 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1430 printf("%s: could not allocate jumbo buffer\n", 1431 sc->sc_dev.dv_xname); 1432 goto fail; 1433 } 1434 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1435 sc); 1436 1437 physaddr = jbuf->physaddr; 1438 } else { 1439 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1440 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1441 if (error != 0) { 1442 printf("%s: could not create DMA map\n", 1443 sc->sc_dev.dv_xname); 1444 goto fail; 1445 } 1446 MCLGET(data->m, M_DONTWAIT); 1447 if (!(data->m->m_flags & M_EXT)) { 1448 printf("%s: could not allocate mbuf cluster\n", 1449 sc->sc_dev.dv_xname); 1450 error = ENOMEM; 1451 goto fail; 1452 } 1453 1454 error = bus_dmamap_load(sc->sc_dmat, data->map, 1455 mtod(data->m, void *), MCLBYTES, NULL, 1456 BUS_DMA_READ | BUS_DMA_NOWAIT); 1457 if (error != 0) { 1458 printf("%s: could not load rx buf DMA map", 1459 sc->sc_dev.dv_xname); 1460 goto fail; 1461 } 1462 physaddr = data->map->dm_segs[0].ds_addr; 1463 } 1464 1465 if (sc->sc_flags & NFE_40BIT_ADDR) { 1466 desc64 = &sc->rxq.desc64[i]; 1467 #if defined(__LP64__) 1468 desc64->physaddr[0] = htole32(physaddr >> 32); 1469 #endif 1470 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1471 desc64->length = htole16(sc->rxq.bufsz); 1472 desc64->flags = htole16(NFE_RX_READY); 1473 } else { 1474 desc32 = &sc->rxq.desc32[i]; 1475 desc32->physaddr = htole32(physaddr); 1476 desc32->length = htole16(sc->rxq.bufsz); 1477 desc32->flags = htole16(NFE_RX_READY); 1478 } 1479 } 1480 1481 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1482 BUS_DMASYNC_PREWRITE); 1483 1484 return 0; 1485 1486 fail: nfe_free_rx_ring(sc, ring); 1487 return error; 1488 } 1489 1490 void 1491 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1492 { 1493 int i; 1494 1495 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1496 if (sc->sc_flags & NFE_40BIT_ADDR) { 1497 ring->desc64[i].length = htole16(ring->bufsz); 1498 ring->desc64[i].flags = htole16(NFE_RX_READY); 1499 } else { 1500 ring->desc32[i].length = htole16(ring->bufsz); 1501 ring->desc32[i].flags = htole16(NFE_RX_READY); 1502 } 1503 } 1504 1505 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1506 BUS_DMASYNC_PREWRITE); 1507 1508 ring->cur = ring->next = 0; 1509 } 1510 1511 void 1512 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1513 { 1514 struct nfe_rx_data *data; 1515 void *desc; 1516 int i, descsize; 1517 1518 if (sc->sc_flags & NFE_40BIT_ADDR) { 1519 desc = ring->desc64; 1520 descsize = sizeof (struct nfe_desc64); 1521 } else { 1522 desc = ring->desc32; 1523 descsize = sizeof (struct nfe_desc32); 1524 } 1525 1526 if (desc != NULL) { 1527 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1528 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1529 bus_dmamap_unload(sc->sc_dmat, ring->map); 1530 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)desc, 1531 NFE_RX_RING_COUNT * descsize); 1532 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1533 } 1534 1535 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1536 data = &ring->data[i]; 1537 1538 if (data->map != NULL) { 1539 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1540 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1541 bus_dmamap_unload(sc->sc_dmat, data->map); 1542 bus_dmamap_destroy(sc->sc_dmat, data->map); 1543 } 1544 if (data->m != NULL) 1545 m_freem(data->m); 1546 } 1547 } 1548 1549 struct nfe_jbuf * 1550 nfe_jalloc(struct nfe_softc *sc, int i) 1551 { 1552 struct nfe_jbuf *jbuf; 1553 1554 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1555 if (jbuf == NULL) 1556 return NULL; 1557 sc->rxq.jbufmap[i] = 1558 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1559 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1560 return jbuf; 1561 } 1562 1563 /* 1564 * This is called automatically by the network stack when the mbuf is freed. 1565 * Caution must be taken that the NIC might be reset by the time the mbuf is 1566 * freed. 1567 */ 1568 void 1569 nfe_jfree(struct mbuf *m, caddr_t buf, size_t size, void *arg) 1570 { 1571 struct nfe_softc *sc = arg; 1572 struct nfe_jbuf *jbuf; 1573 int i; 1574 1575 /* find the jbuf from the base pointer */ 1576 i = (buf - sc->rxq.jpool) / NFE_JBYTES; 1577 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1578 printf("%s: request to free a buffer (%p) not managed by us\n", 1579 sc->sc_dev.dv_xname, buf); 1580 return; 1581 } 1582 jbuf = &sc->rxq.jbuf[i]; 1583 1584 /* ..and put it back in the free list */ 1585 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1586 1587 if (m != NULL) 1588 pool_cache_put(&mbpool_cache, m); 1589 } 1590 1591 int 1592 nfe_jpool_alloc(struct nfe_softc *sc) 1593 { 1594 struct nfe_rx_ring *ring = &sc->rxq; 1595 struct nfe_jbuf *jbuf; 1596 bus_addr_t physaddr; 1597 caddr_t buf; 1598 int i, nsegs, error; 1599 1600 /* 1601 * Allocate a big chunk of DMA'able memory. 1602 */ 1603 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1604 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1605 if (error != 0) { 1606 printf("%s: could not create jumbo DMA map\n", 1607 sc->sc_dev.dv_xname); 1608 goto fail; 1609 } 1610 1611 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1612 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1613 if (error != 0) { 1614 printf("%s could not allocate jumbo DMA memory\n", 1615 sc->sc_dev.dv_xname); 1616 goto fail; 1617 } 1618 1619 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1620 &ring->jpool, BUS_DMA_NOWAIT); 1621 if (error != 0) { 1622 printf("%s: could not map jumbo DMA memory\n", 1623 sc->sc_dev.dv_xname); 1624 goto fail; 1625 } 1626 1627 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1628 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1629 if (error != 0) { 1630 printf("%s: could not load jumbo DMA map\n", 1631 sc->sc_dev.dv_xname); 1632 goto fail; 1633 } 1634 1635 /* ..and split it into 9KB chunks */ 1636 SLIST_INIT(&ring->jfreelist); 1637 1638 buf = ring->jpool; 1639 physaddr = ring->jmap->dm_segs[0].ds_addr; 1640 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1641 jbuf = &ring->jbuf[i]; 1642 1643 jbuf->buf = buf; 1644 jbuf->physaddr = physaddr; 1645 1646 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1647 1648 buf += NFE_JBYTES; 1649 physaddr += NFE_JBYTES; 1650 } 1651 1652 return 0; 1653 1654 fail: nfe_jpool_free(sc); 1655 return error; 1656 } 1657 1658 void 1659 nfe_jpool_free(struct nfe_softc *sc) 1660 { 1661 struct nfe_rx_ring *ring = &sc->rxq; 1662 1663 if (ring->jmap != NULL) { 1664 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1665 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1666 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1667 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1668 } 1669 if (ring->jpool != NULL) { 1670 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1671 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1672 } 1673 } 1674 1675 int 1676 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1677 { 1678 int i, nsegs, error; 1679 void **desc; 1680 int descsize; 1681 1682 if (sc->sc_flags & NFE_40BIT_ADDR) { 1683 desc = (void **)&ring->desc64; 1684 descsize = sizeof (struct nfe_desc64); 1685 } else { 1686 desc = (void **)&ring->desc32; 1687 descsize = sizeof (struct nfe_desc32); 1688 } 1689 1690 ring->queued = 0; 1691 ring->cur = ring->next = 0; 1692 1693 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1694 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1695 1696 if (error != 0) { 1697 printf("%s: could not create desc DMA map\n", 1698 sc->sc_dev.dv_xname); 1699 goto fail; 1700 } 1701 1702 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1703 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1704 if (error != 0) { 1705 printf("%s: could not allocate DMA memory\n", 1706 sc->sc_dev.dv_xname); 1707 goto fail; 1708 } 1709 1710 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1711 NFE_TX_RING_COUNT * descsize, (caddr_t *)desc, BUS_DMA_NOWAIT); 1712 if (error != 0) { 1713 printf("%s: could not map desc DMA memory\n", 1714 sc->sc_dev.dv_xname); 1715 goto fail; 1716 } 1717 1718 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1719 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1720 if (error != 0) { 1721 printf("%s: could not load desc DMA map\n", 1722 sc->sc_dev.dv_xname); 1723 goto fail; 1724 } 1725 1726 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1727 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1728 1729 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1730 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1731 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1732 &ring->data[i].map); 1733 if (error != 0) { 1734 printf("%s: could not create DMA map\n", 1735 sc->sc_dev.dv_xname); 1736 goto fail; 1737 } 1738 } 1739 1740 return 0; 1741 1742 fail: nfe_free_tx_ring(sc, ring); 1743 return error; 1744 } 1745 1746 void 1747 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1748 { 1749 struct nfe_tx_data *data; 1750 int i; 1751 1752 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1753 if (sc->sc_flags & NFE_40BIT_ADDR) 1754 ring->desc64[i].flags = 0; 1755 else 1756 ring->desc32[i].flags = 0; 1757 1758 data = &ring->data[i]; 1759 1760 if (data->m != NULL) { 1761 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1762 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1763 bus_dmamap_unload(sc->sc_dmat, data->active); 1764 m_freem(data->m); 1765 data->m = NULL; 1766 } 1767 } 1768 1769 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1770 BUS_DMASYNC_PREWRITE); 1771 1772 ring->queued = 0; 1773 ring->cur = ring->next = 0; 1774 } 1775 1776 void 1777 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1778 { 1779 struct nfe_tx_data *data; 1780 void *desc; 1781 int i, descsize; 1782 1783 if (sc->sc_flags & NFE_40BIT_ADDR) { 1784 desc = ring->desc64; 1785 descsize = sizeof (struct nfe_desc64); 1786 } else { 1787 desc = ring->desc32; 1788 descsize = sizeof (struct nfe_desc32); 1789 } 1790 1791 if (desc != NULL) { 1792 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1793 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1794 bus_dmamap_unload(sc->sc_dmat, ring->map); 1795 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)desc, 1796 NFE_TX_RING_COUNT * descsize); 1797 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1798 } 1799 1800 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1801 data = &ring->data[i]; 1802 1803 if (data->m != NULL) { 1804 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1805 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1806 bus_dmamap_unload(sc->sc_dmat, data->active); 1807 m_freem(data->m); 1808 } 1809 } 1810 1811 /* ..and now actually destroy the DMA mappings */ 1812 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1813 data = &ring->data[i]; 1814 if (data->map == NULL) 1815 continue; 1816 bus_dmamap_destroy(sc->sc_dmat, data->map); 1817 } 1818 } 1819 1820 int 1821 nfe_ifmedia_upd(struct ifnet *ifp) 1822 { 1823 struct nfe_softc *sc = ifp->if_softc; 1824 struct mii_data *mii = &sc->sc_mii; 1825 struct mii_softc *miisc; 1826 1827 if (mii->mii_instance != 0) { 1828 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1829 mii_phy_reset(miisc); 1830 } 1831 return mii_mediachg(mii); 1832 } 1833 1834 void 1835 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1836 { 1837 struct nfe_softc *sc = ifp->if_softc; 1838 struct mii_data *mii = &sc->sc_mii; 1839 1840 mii_pollstat(mii); 1841 ifmr->ifm_status = mii->mii_media_status; 1842 ifmr->ifm_active = mii->mii_media_active; 1843 } 1844 1845 void 1846 nfe_setmulti(struct nfe_softc *sc) 1847 { 1848 struct ethercom *ec = &sc->sc_ethercom; 1849 struct ifnet *ifp = &ec->ec_if; 1850 struct ether_multi *enm; 1851 struct ether_multistep step; 1852 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1853 uint32_t filter = NFE_RXFILTER_MAGIC; 1854 int i; 1855 1856 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1857 bzero(addr, ETHER_ADDR_LEN); 1858 bzero(mask, ETHER_ADDR_LEN); 1859 goto done; 1860 } 1861 1862 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1863 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1864 1865 ETHER_FIRST_MULTI(step, ec, enm); 1866 while (enm != NULL) { 1867 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1868 ifp->if_flags |= IFF_ALLMULTI; 1869 bzero(addr, ETHER_ADDR_LEN); 1870 bzero(mask, ETHER_ADDR_LEN); 1871 goto done; 1872 } 1873 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1874 addr[i] &= enm->enm_addrlo[i]; 1875 mask[i] &= ~enm->enm_addrlo[i]; 1876 } 1877 ETHER_NEXT_MULTI(step, enm); 1878 } 1879 for (i = 0; i < ETHER_ADDR_LEN; i++) 1880 mask[i] |= addr[i]; 1881 1882 done: 1883 addr[0] |= 0x01; /* make sure multicast bit is set */ 1884 1885 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1886 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1887 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1888 addr[5] << 8 | addr[4]); 1889 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1890 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1891 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1892 mask[5] << 8 | mask[4]); 1893 1894 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1895 NFE_WRITE(sc, NFE_RXFILTER, filter); 1896 } 1897 1898 void 1899 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1900 { 1901 uint32_t tmp; 1902 1903 if ((sc->sc_flags & NFE_CORRECT_MACADDR) == 0) { 1904 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1905 addr[0] = (tmp >> 8) & 0xff; 1906 addr[1] = (tmp & 0xff); 1907 1908 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1909 addr[2] = (tmp >> 24) & 0xff; 1910 addr[3] = (tmp >> 16) & 0xff; 1911 addr[4] = (tmp >> 8) & 0xff; 1912 addr[5] = (tmp & 0xff); 1913 } else { 1914 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1915 addr[5] = (tmp >> 8) & 0xff; 1916 addr[4] = (tmp & 0xff); 1917 1918 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1919 addr[3] = (tmp >> 24) & 0xff; 1920 addr[2] = (tmp >> 16) & 0xff; 1921 addr[1] = (tmp >> 8) & 0xff; 1922 addr[0] = (tmp & 0xff); 1923 } 1924 } 1925 1926 void 1927 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1928 { 1929 NFE_WRITE(sc, NFE_MACADDR_LO, 1930 addr[5] << 8 | addr[4]); 1931 NFE_WRITE(sc, NFE_MACADDR_HI, 1932 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1933 } 1934 1935 void 1936 nfe_tick(void *arg) 1937 { 1938 struct nfe_softc *sc = arg; 1939 int s; 1940 1941 s = splnet(); 1942 mii_tick(&sc->sc_mii); 1943 splx(s); 1944 1945 callout_schedule(&sc->sc_tick_ch, hz); 1946 } 1947
Indexes created Mon Oct 13 16:09:52 GMT 2025