if_nfe.c revision 1.72
1 /* $NetBSD: if_nfe.c,v 1.72 2019/09/13 07:55:07 msaitoh Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.77 2008/02/05 16:52:50 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006, 2007 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.72 2019/09/13 07:55:07 msaitoh Exp $"); 25 26 #include "opt_inet.h" 27 #include "vlan.h" 28 29 #include <sys/param.h> 30 #include <sys/endian.h> 31 #include <sys/systm.h> 32 #include <sys/types.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/mutex.h> 36 #include <sys/queue.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/callout.h> 40 #include <sys/socket.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #include <net/bpf.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_nfereg.h> 72 #include <dev/pci/if_nfevar.h> 73 74 static int nfe_ifflags_cb(struct ethercom *); 75 76 int nfe_match(device_t, cfdata_t, void *); 77 void nfe_attach(device_t, device_t, void *); 78 int nfe_detach(device_t, int); 79 void nfe_power(int, void *); 80 void nfe_miibus_statchg(struct ifnet *); 81 int nfe_miibus_readreg(device_t, int, int, uint16_t *); 82 int nfe_miibus_writereg(device_t, int, int, uint16_t); 83 int nfe_intr(void *); 84 int nfe_ioctl(struct ifnet *, u_long, void *); 85 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 86 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 87 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 88 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 89 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 90 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 91 void nfe_rxeof(struct nfe_softc *); 92 void nfe_txeof(struct nfe_softc *); 93 int nfe_encap(struct nfe_softc *, struct mbuf *); 94 void nfe_start(struct ifnet *); 95 void nfe_watchdog(struct ifnet *); 96 int nfe_init(struct ifnet *); 97 void nfe_stop(struct ifnet *, int); 98 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 99 void nfe_jfree(struct mbuf *, void *, size_t, void *); 100 int nfe_jpool_alloc(struct nfe_softc *); 101 void nfe_jpool_free(struct nfe_softc *); 102 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 105 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 108 void nfe_setmulti(struct nfe_softc *); 109 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 110 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 111 void nfe_tick(void *); 112 void nfe_poweron(device_t); 113 bool nfe_resume(device_t, const pmf_qual_t *); 114 115 CFATTACH_DECL_NEW(nfe, sizeof(struct nfe_softc), 116 nfe_match, nfe_attach, nfe_detach, NULL); 117 118 /* #define NFE_NO_JUMBO */ 119 120 #ifdef NFE_DEBUG 121 int nfedebug = 0; 122 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 123 #define DPRINTFN(n, x) do { if (nfedebug >= (n)) printf x; } while (0) 124 #else 125 #define DPRINTF(x) 126 #define DPRINTFN(n, x) 127 #endif 128 129 /* deal with naming differences */ 130 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 134 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 135 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 136 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 137 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 140 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 141 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 142 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 145 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 146 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 147 148 #ifdef _LP64 149 #define __LP64__ 1 150 #endif 151 152 const struct nfe_product { 153 pci_vendor_id_t vendor; 154 pci_product_id_t product; 155 } nfe_devices[] = { 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 183 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 184 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 185 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 186 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 }, 187 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1 }, 188 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2 }, 189 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3 }, 190 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4 }, 191 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1 }, 192 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2 }, 193 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3 }, 194 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4 } 195 }; 196 197 int 198 nfe_match(device_t dev, cfdata_t match, void *aux) 199 { 200 struct pci_attach_args *pa = aux; 201 const struct nfe_product *np; 202 int i; 203 204 for (i = 0; i < __arraycount(nfe_devices); i++) { 205 np = &nfe_devices[i]; 206 if (PCI_VENDOR(pa->pa_id) == np->vendor && 207 PCI_PRODUCT(pa->pa_id) == np->product) 208 return 1; 209 } 210 return 0; 211 } 212 213 void 214 nfe_attach(device_t parent, device_t self, void *aux) 215 { 216 struct nfe_softc *sc = device_private(self); 217 struct pci_attach_args *pa = aux; 218 pci_chipset_tag_t pc = pa->pa_pc; 219 pci_intr_handle_t ih; 220 const char *intrstr; 221 struct ifnet *ifp; 222 struct mii_data * const mii = &sc->sc_mii; 223 pcireg_t memtype, csr; 224 int mii_flags = 0; 225 char intrbuf[PCI_INTRSTR_LEN]; 226 227 sc->sc_dev = self; 228 sc->sc_pc = pa->pa_pc; 229 pci_aprint_devinfo(pa, NULL); 230 231 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 232 switch (memtype) { 233 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 234 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 235 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 236 &sc->sc_memh, NULL, &sc->sc_mems) == 0) 237 break; 238 /* FALLTHROUGH */ 239 default: 240 aprint_error_dev(self, "could not map mem space\n"); 241 return; 242 } 243 244 if (pci_intr_map(pa, &ih) != 0) { 245 aprint_error_dev(self, "could not map interrupt\n"); 246 goto fail; 247 } 248 249 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 250 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, nfe_intr, sc, 251 device_xname(self)); 252 if (sc->sc_ih == NULL) { 253 aprint_error_dev(self, "could not establish interrupt"); 254 if (intrstr != NULL) 255 aprint_error(" at %s", intrstr); 256 aprint_error("\n"); 257 goto fail; 258 } 259 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 260 261 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 262 csr |= PCI_COMMAND_MASTER_ENABLE; 263 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 264 265 sc->sc_flags = 0; 266 267 switch (PCI_PRODUCT(pa->pa_id)) { 268 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 269 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 270 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 271 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 272 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 273 break; 274 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 275 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 276 sc->sc_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT; 277 break; 278 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 279 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 280 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 281 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 282 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 283 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 284 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 285 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 286 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 287 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 288 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 289 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 290 sc->sc_flags |= NFE_40BIT_ADDR | NFE_CORRECT_MACADDR | 291 NFE_PWR_MGMT; 292 break; 293 case PCI_PRODUCT_NVIDIA_MCP77_LAN1: 294 case PCI_PRODUCT_NVIDIA_MCP77_LAN2: 295 case PCI_PRODUCT_NVIDIA_MCP77_LAN3: 296 case PCI_PRODUCT_NVIDIA_MCP77_LAN4: 297 sc->sc_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | 298 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 299 break; 300 case PCI_PRODUCT_NVIDIA_MCP79_LAN1: 301 case PCI_PRODUCT_NVIDIA_MCP79_LAN2: 302 case PCI_PRODUCT_NVIDIA_MCP79_LAN3: 303 case PCI_PRODUCT_NVIDIA_MCP79_LAN4: 304 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 305 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 306 break; 307 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 308 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 309 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 310 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 311 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 312 break; 313 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 314 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 315 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 316 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 317 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 318 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 319 mii_flags = MIIF_DOPAUSE; 320 break; 321 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 322 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 323 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 324 NFE_HW_VLAN | NFE_PWR_MGMT; 325 break; 326 } 327 328 if (pci_dma64_available(pa) && (sc->sc_flags & NFE_40BIT_ADDR) != 0) 329 sc->sc_dmat = pa->pa_dmat64; 330 else 331 sc->sc_dmat = pa->pa_dmat; 332 333 nfe_poweron(self); 334 335 #ifndef NFE_NO_JUMBO 336 /* enable jumbo frames for adapters that support it */ 337 if (sc->sc_flags & NFE_JUMBO_SUP) 338 sc->sc_flags |= NFE_USE_JUMBO; 339 #endif 340 341 /* Check for reversed ethernet address */ 342 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 343 sc->sc_flags |= NFE_CORRECT_MACADDR; 344 345 nfe_get_macaddr(sc, sc->sc_enaddr); 346 aprint_normal_dev(self, "Ethernet address %s\n", 347 ether_sprintf(sc->sc_enaddr)); 348 349 /* 350 * Allocate Tx and Rx rings. 351 */ 352 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 353 aprint_error_dev(self, "could not allocate Tx ring\n"); 354 goto fail; 355 } 356 357 mutex_init(&sc->rxq.mtx, MUTEX_DEFAULT, IPL_NET); 358 359 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 360 aprint_error_dev(self, "could not allocate Rx ring\n"); 361 nfe_free_tx_ring(sc, &sc->txq); 362 goto fail; 363 } 364 365 ifp = &sc->sc_ethercom.ec_if; 366 ifp->if_softc = sc; 367 ifp->if_mtu = ETHERMTU; 368 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 369 ifp->if_ioctl = nfe_ioctl; 370 ifp->if_start = nfe_start; 371 ifp->if_stop = nfe_stop; 372 ifp->if_watchdog = nfe_watchdog; 373 ifp->if_init = nfe_init; 374 ifp->if_baudrate = IF_Gbps(1); 375 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 376 IFQ_SET_READY(&ifp->if_snd); 377 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 378 379 if (sc->sc_flags & NFE_USE_JUMBO) 380 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 381 382 #if NVLAN > 0 383 if (sc->sc_flags & NFE_HW_VLAN) { 384 sc->sc_ethercom.ec_capabilities |= 385 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 386 sc->sc_ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 387 } 388 #endif 389 if (sc->sc_flags & NFE_HW_CSUM) { 390 ifp->if_capabilities |= 391 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 392 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 393 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 394 } 395 396 mii->mii_ifp = ifp; 397 mii->mii_readreg = nfe_miibus_readreg; 398 mii->mii_writereg = nfe_miibus_writereg; 399 mii->mii_statchg = nfe_miibus_statchg; 400 401 sc->sc_ethercom.ec_mii = mii; 402 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 403 404 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 0, mii_flags); 405 406 if (LIST_FIRST(&mii->mii_phys) == NULL) { 407 aprint_error_dev(self, "no PHY found!\n"); 408 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 409 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 410 } else 411 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 412 413 if_attach(ifp); 414 if_deferred_start_init(ifp, NULL); 415 ether_ifattach(ifp, sc->sc_enaddr); 416 ether_set_ifflags_cb(&sc->sc_ethercom, nfe_ifflags_cb); 417 418 callout_init(&sc->sc_tick_ch, 0); 419 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 420 421 if (pmf_device_register(self, NULL, nfe_resume)) 422 pmf_class_network_register(self, ifp); 423 else 424 aprint_error_dev(self, "couldn't establish power handler\n"); 425 426 return; 427 428 fail: 429 if (sc->sc_ih != NULL) { 430 pci_intr_disestablish(pc, sc->sc_ih); 431 sc->sc_ih = NULL; 432 } 433 if (sc->sc_mems != 0) { 434 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 435 sc->sc_mems = 0; 436 } 437 } 438 439 int 440 nfe_detach(device_t self, int flags) 441 { 442 struct nfe_softc *sc = device_private(self); 443 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 444 int s; 445 446 s = splnet(); 447 448 nfe_stop(ifp, 1); 449 450 pmf_device_deregister(self); 451 callout_destroy(&sc->sc_tick_ch); 452 ether_ifdetach(ifp); 453 if_detach(ifp); 454 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 455 456 nfe_free_rx_ring(sc, &sc->rxq); 457 mutex_destroy(&sc->rxq.mtx); 458 nfe_free_tx_ring(sc, &sc->txq); 459 460 if (sc->sc_ih != NULL) { 461 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 462 sc->sc_ih = NULL; 463 } 464 465 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 466 nfe_set_macaddr(sc, sc->sc_enaddr); 467 } else { 468 NFE_WRITE(sc, NFE_MACADDR_LO, 469 sc->sc_enaddr[0] << 8 | sc->sc_enaddr[1]); 470 NFE_WRITE(sc, NFE_MACADDR_HI, 471 sc->sc_enaddr[2] << 24 | sc->sc_enaddr[3] << 16 | 472 sc->sc_enaddr[4] << 8 | sc->sc_enaddr[5]); 473 } 474 475 if (sc->sc_mems != 0) { 476 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 477 sc->sc_mems = 0; 478 } 479 480 splx(s); 481 482 return 0; 483 } 484 485 void 486 nfe_miibus_statchg(struct ifnet *ifp) 487 { 488 struct nfe_softc *sc = ifp->if_softc; 489 struct mii_data *mii = &sc->sc_mii; 490 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 491 492 phy = NFE_READ(sc, NFE_PHY_IFACE); 493 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 494 495 seed = NFE_READ(sc, NFE_RNDSEED); 496 seed &= ~NFE_SEED_MASK; 497 498 if ((mii->mii_media_active & IFM_HDX) != 0) { 499 phy |= NFE_PHY_HDX; /* half-duplex */ 500 misc |= NFE_MISC1_HDX; 501 } 502 503 switch (IFM_SUBTYPE(mii->mii_media_active)) { 504 case IFM_1000_T: /* full-duplex only */ 505 link |= NFE_MEDIA_1000T; 506 seed |= NFE_SEED_1000T; 507 phy |= NFE_PHY_1000T; 508 break; 509 case IFM_100_TX: 510 link |= NFE_MEDIA_100TX; 511 seed |= NFE_SEED_100TX; 512 phy |= NFE_PHY_100TX; 513 break; 514 case IFM_10_T: 515 link |= NFE_MEDIA_10T; 516 seed |= NFE_SEED_10T; 517 break; 518 } 519 520 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 521 522 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 523 NFE_WRITE(sc, NFE_MISC1, misc); 524 NFE_WRITE(sc, NFE_LINKSPEED, link); 525 } 526 527 int 528 nfe_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 529 { 530 struct nfe_softc *sc = device_private(dev); 531 uint32_t data; 532 int ntries; 533 534 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 535 536 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 537 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 538 DELAY(100); 539 } 540 541 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 542 543 for (ntries = 0; ntries < 1000; ntries++) { 544 DELAY(100); 545 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 546 break; 547 } 548 if (ntries == 1000) { 549 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 550 device_xname(sc->sc_dev))); 551 return ETIMEDOUT; 552 } 553 554 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 555 DPRINTFN(2, ("%s: could not read PHY\n", 556 device_xname(sc->sc_dev))); 557 return -1; 558 } 559 560 data = NFE_READ(sc, NFE_PHY_DATA); 561 if (data != 0xffffffff && data != 0) 562 sc->mii_phyaddr = phy; 563 564 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x data 0x%x\n", 565 device_xname(sc->sc_dev), phy, reg, data)); 566 567 *val = data & 0x0000ffff; 568 return 0; 569 } 570 571 int 572 nfe_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 573 { 574 struct nfe_softc *sc = device_private(dev); 575 uint32_t ctl; 576 int ntries; 577 578 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 579 580 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 581 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 582 DELAY(100); 583 } 584 585 NFE_WRITE(sc, NFE_PHY_DATA, val); 586 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 587 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 588 589 for (ntries = 0; ntries < 1000; ntries++) { 590 DELAY(100); 591 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 592 break; 593 } 594 if (ntries == 1000) { 595 #ifdef NFE_DEBUG 596 if (nfedebug >= 2) 597 printf("could not write to PHY\n"); 598 #endif 599 return ETIMEDOUT; 600 } 601 return 0; 602 } 603 604 int 605 nfe_intr(void *arg) 606 { 607 struct nfe_softc *sc = arg; 608 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 609 uint32_t r; 610 int handled; 611 612 if ((ifp->if_flags & IFF_UP) == 0) 613 return 0; 614 615 handled = 0; 616 617 for (;;) { 618 r = NFE_READ(sc, NFE_IRQ_STATUS); 619 if ((r & NFE_IRQ_WANTED) == 0) 620 break; 621 622 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 623 handled = 1; 624 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 625 626 if ((r & (NFE_IRQ_RXERR |NFE_IRQ_RX_NOBUF |NFE_IRQ_RX)) != 0) { 627 /* check Rx ring */ 628 nfe_rxeof(sc); 629 } 630 if ((r & (NFE_IRQ_TXERR|NFE_IRQ_TXERR2|NFE_IRQ_TX_DONE)) != 0) { 631 /* check Tx ring */ 632 nfe_txeof(sc); 633 } 634 if ((r & NFE_IRQ_LINK) != 0) { 635 NFE_READ(sc, NFE_PHY_STATUS); 636 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 637 DPRINTF(("%s: link state changed\n", 638 device_xname(sc->sc_dev))); 639 } 640 } 641 642 if (handled) 643 if_schedule_deferred_start(ifp); 644 645 return handled; 646 } 647 648 static int 649 nfe_ifflags_cb(struct ethercom *ec) 650 { 651 struct ifnet *ifp = &ec->ec_if; 652 struct nfe_softc *sc = ifp->if_softc; 653 u_short change = ifp->if_flags ^ sc->sc_if_flags; 654 655 /* 656 * If only the PROMISC flag changes, then 657 * don't do a full re-init of the chip, just update 658 * the Rx filter. 659 */ 660 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 661 return ENETRESET; 662 else if ((change & IFF_PROMISC) != 0) 663 nfe_setmulti(sc); 664 665 return 0; 666 } 667 668 int 669 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 670 { 671 struct nfe_softc *sc = ifp->if_softc; 672 struct ifaddr *ifa = (struct ifaddr *)data; 673 int s, error = 0; 674 675 s = splnet(); 676 677 switch (cmd) { 678 case SIOCINITIFADDR: 679 ifp->if_flags |= IFF_UP; 680 nfe_init(ifp); 681 switch (ifa->ifa_addr->sa_family) { 682 #ifdef INET 683 case AF_INET: 684 arp_ifinit(ifp, ifa); 685 break; 686 #endif 687 default: 688 break; 689 } 690 break; 691 default: 692 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 693 break; 694 695 error = 0; 696 697 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 698 ; 699 else if (ifp->if_flags & IFF_RUNNING) 700 nfe_setmulti(sc); 701 break; 702 } 703 sc->sc_if_flags = ifp->if_flags; 704 705 splx(s); 706 707 return error; 708 } 709 710 void 711 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 712 { 713 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 714 (char *)desc32 - (char *)sc->txq.desc32, 715 sizeof (struct nfe_desc32), ops); 716 } 717 718 void 719 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 720 { 721 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 722 (char *)desc64 - (char *)sc->txq.desc64, 723 sizeof (struct nfe_desc64), ops); 724 } 725 726 void 727 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 728 { 729 if (end > start) { 730 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 731 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 732 (char *)&sc->txq.desc32[end] - 733 (char *)&sc->txq.desc32[start], ops); 734 return; 735 } 736 /* sync from 'start' to end of ring */ 737 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 738 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 739 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 740 (char *)&sc->txq.desc32[start], ops); 741 742 /* sync from start of ring to 'end' */ 743 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 744 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 745 } 746 747 void 748 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 749 { 750 if (end > start) { 751 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 752 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 753 (char *)&sc->txq.desc64[end] - 754 (char *)&sc->txq.desc64[start], ops); 755 return; 756 } 757 /* sync from 'start' to end of ring */ 758 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 759 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 760 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 761 (char *)&sc->txq.desc64[start], ops); 762 763 /* sync from start of ring to 'end' */ 764 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 765 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 766 } 767 768 void 769 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 770 { 771 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 772 (char *)desc32 - (char *)sc->rxq.desc32, 773 sizeof (struct nfe_desc32), ops); 774 } 775 776 void 777 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 778 { 779 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 780 (char *)desc64 - (char *)sc->rxq.desc64, 781 sizeof (struct nfe_desc64), ops); 782 } 783 784 void 785 nfe_rxeof(struct nfe_softc *sc) 786 { 787 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 788 struct nfe_desc32 *desc32; 789 struct nfe_desc64 *desc64; 790 struct nfe_rx_data *data; 791 struct nfe_jbuf *jbuf; 792 struct mbuf *m, *mnew; 793 bus_addr_t physaddr; 794 uint16_t flags; 795 int error, len, i; 796 797 desc32 = NULL; 798 desc64 = NULL; 799 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 800 data = &sc->rxq.data[i]; 801 802 if (sc->sc_flags & NFE_40BIT_ADDR) { 803 desc64 = &sc->rxq.desc64[i]; 804 nfe_rxdesc64_sync(sc, desc64, 805 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 806 807 flags = le16toh(desc64->flags); 808 len = le16toh(desc64->length) & 0x3fff; 809 } else { 810 desc32 = &sc->rxq.desc32[i]; 811 nfe_rxdesc32_sync(sc, desc32, 812 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 813 814 flags = le16toh(desc32->flags); 815 len = le16toh(desc32->length) & 0x3fff; 816 } 817 818 if ((flags & NFE_RX_READY) != 0) 819 break; 820 821 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 822 if ((flags & NFE_RX_VALID_V1) == 0) 823 goto skip; 824 825 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 826 flags &= ~NFE_RX_ERROR; 827 len--; /* fix buffer length */ 828 } 829 } else { 830 if ((flags & NFE_RX_VALID_V2) == 0) 831 goto skip; 832 833 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 834 flags &= ~NFE_RX_ERROR; 835 len--; /* fix buffer length */ 836 } 837 } 838 839 if (flags & NFE_RX_ERROR) { 840 ifp->if_ierrors++; 841 goto skip; 842 } 843 844 /* 845 * Try to allocate a new mbuf for this ring element and load 846 * it before processing the current mbuf. If the ring element 847 * cannot be loaded, drop the received packet and reuse the 848 * old mbuf. In the unlikely case that the old mbuf can't be 849 * reloaded either, explicitly panic. 850 */ 851 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 852 if (mnew == NULL) { 853 ifp->if_ierrors++; 854 goto skip; 855 } 856 857 if (sc->sc_flags & NFE_USE_JUMBO) { 858 physaddr = 859 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 860 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 861 if (len > MCLBYTES) { 862 m_freem(mnew); 863 ifp->if_ierrors++; 864 goto skip1; 865 } 866 MCLGET(mnew, M_DONTWAIT); 867 if ((mnew->m_flags & M_EXT) == 0) { 868 m_freem(mnew); 869 ifp->if_ierrors++; 870 goto skip1; 871 } 872 873 (void)memcpy(mtod(mnew, void *), 874 mtod(data->m, const void *), len); 875 m = mnew; 876 goto mbufcopied; 877 } else { 878 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 879 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 880 mtod(data->m, char *) - (char *)sc->rxq.jpool, 881 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 882 883 physaddr = jbuf->physaddr; 884 } 885 } else { 886 MCLGET(mnew, M_DONTWAIT); 887 if ((mnew->m_flags & M_EXT) == 0) { 888 m_freem(mnew); 889 ifp->if_ierrors++; 890 goto skip; 891 } 892 893 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 894 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 895 bus_dmamap_unload(sc->sc_dmat, data->map); 896 897 error = bus_dmamap_load(sc->sc_dmat, data->map, 898 mtod(mnew, void *), MCLBYTES, NULL, 899 BUS_DMA_READ | BUS_DMA_NOWAIT); 900 if (error != 0) { 901 m_freem(mnew); 902 903 /* try to reload the old mbuf */ 904 error = bus_dmamap_load(sc->sc_dmat, data->map, 905 mtod(data->m, void *), MCLBYTES, NULL, 906 BUS_DMA_READ | BUS_DMA_NOWAIT); 907 if (error != 0) { 908 /* very unlikely that it will fail.. */ 909 panic("%s: could not load old rx mbuf", 910 device_xname(sc->sc_dev)); 911 } 912 ifp->if_ierrors++; 913 goto skip; 914 } 915 physaddr = data->map->dm_segs[0].ds_addr; 916 } 917 918 /* 919 * New mbuf successfully loaded, update Rx ring and continue 920 * processing. 921 */ 922 m = data->m; 923 data->m = mnew; 924 925 mbufcopied: 926 /* finalize mbuf */ 927 m->m_pkthdr.len = m->m_len = len; 928 m_set_rcvif(m, ifp); 929 930 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 931 /* 932 * XXX 933 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 934 */ 935 if (flags & NFE_RX_IP_CSUMOK) { 936 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 937 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 938 device_xname(sc->sc_dev))); 939 } 940 /* 941 * XXX 942 * no way to check M_CSUM_TCP_UDP_BAD or 943 * other protocols? 944 */ 945 if (flags & NFE_RX_UDP_CSUMOK) { 946 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 947 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 948 device_xname(sc->sc_dev))); 949 } else if (flags & NFE_RX_TCP_CSUMOK) { 950 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 951 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 952 device_xname(sc->sc_dev))); 953 } 954 } 955 if_percpuq_enqueue(ifp->if_percpuq, m); 956 957 skip1: 958 /* update mapping address in h/w descriptor */ 959 if (sc->sc_flags & NFE_40BIT_ADDR) { 960 #if defined(__LP64__) 961 desc64->physaddr[0] = htole32(physaddr >> 32); 962 #endif 963 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 964 } else { 965 desc32->physaddr = htole32(physaddr); 966 } 967 968 skip: 969 if (sc->sc_flags & NFE_40BIT_ADDR) { 970 desc64->length = htole16(sc->rxq.bufsz); 971 desc64->flags = htole16(NFE_RX_READY); 972 973 nfe_rxdesc64_sync(sc, desc64, 974 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 975 } else { 976 desc32->length = htole16(sc->rxq.bufsz); 977 desc32->flags = htole16(NFE_RX_READY); 978 979 nfe_rxdesc32_sync(sc, desc32, 980 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 981 } 982 } 983 /* update current RX pointer */ 984 sc->rxq.cur = i; 985 } 986 987 void 988 nfe_txeof(struct nfe_softc *sc) 989 { 990 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 991 struct nfe_desc32 *desc32; 992 struct nfe_desc64 *desc64; 993 struct nfe_tx_data *data = NULL; 994 int i; 995 uint16_t flags; 996 char buf[128]; 997 998 for (i = sc->txq.next; 999 sc->txq.queued > 0; 1000 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 1001 if (sc->sc_flags & NFE_40BIT_ADDR) { 1002 desc64 = &sc->txq.desc64[i]; 1003 nfe_txdesc64_sync(sc, desc64, 1004 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1005 1006 flags = le16toh(desc64->flags); 1007 } else { 1008 desc32 = &sc->txq.desc32[i]; 1009 nfe_txdesc32_sync(sc, desc32, 1010 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1011 1012 flags = le16toh(desc32->flags); 1013 } 1014 1015 if ((flags & NFE_TX_VALID) != 0) 1016 break; 1017 1018 data = &sc->txq.data[i]; 1019 1020 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 1021 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 1022 data->m == NULL) 1023 continue; 1024 1025 if ((flags & NFE_TX_ERROR_V1) != 0) { 1026 snprintb(buf, sizeof(buf), NFE_V1_TXERR, flags); 1027 aprint_error_dev(sc->sc_dev, "tx v1 error %s\n", 1028 buf); 1029 ifp->if_oerrors++; 1030 } else 1031 ifp->if_opackets++; 1032 } else { 1033 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 1034 data->m == NULL) 1035 continue; 1036 1037 if ((flags & NFE_TX_ERROR_V2) != 0) { 1038 snprintb(buf, sizeof(buf), NFE_V2_TXERR, flags); 1039 aprint_error_dev(sc->sc_dev, "tx v2 error %s\n", 1040 buf); 1041 ifp->if_oerrors++; 1042 } else 1043 ifp->if_opackets++; 1044 } 1045 1046 if (data->m == NULL) { /* should not get there */ 1047 aprint_error_dev(sc->sc_dev, 1048 "last fragment bit w/o associated mbuf!\n"); 1049 continue; 1050 } 1051 1052 /* last fragment of the mbuf chain transmitted */ 1053 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1054 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1055 bus_dmamap_unload(sc->sc_dmat, data->active); 1056 m_freem(data->m); 1057 data->m = NULL; 1058 } 1059 1060 sc->txq.next = i; 1061 1062 if (sc->txq.queued < NFE_TX_RING_COUNT) { 1063 /* at least one slot freed */ 1064 ifp->if_flags &= ~IFF_OACTIVE; 1065 } 1066 1067 if (sc->txq.queued == 0) { 1068 /* all queued packets are sent */ 1069 ifp->if_timer = 0; 1070 } 1071 } 1072 1073 int 1074 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 1075 { 1076 struct nfe_desc32 *desc32; 1077 struct nfe_desc64 *desc64; 1078 struct nfe_tx_data *data; 1079 bus_dmamap_t map; 1080 uint16_t flags, csumflags; 1081 #if NVLAN > 0 1082 uint32_t vtag = 0; 1083 #endif 1084 int error, i, first; 1085 1086 desc32 = NULL; 1087 desc64 = NULL; 1088 data = NULL; 1089 1090 flags = 0; 1091 csumflags = 0; 1092 first = sc->txq.cur; 1093 1094 map = sc->txq.data[first].map; 1095 1096 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1097 if (error != 0) { 1098 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1099 error); 1100 return error; 1101 } 1102 1103 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1104 bus_dmamap_unload(sc->sc_dmat, map); 1105 return ENOBUFS; 1106 } 1107 1108 #if NVLAN > 0 1109 /* setup h/w VLAN tagging */ 1110 if (vlan_has_tag(m0)) 1111 vtag = NFE_TX_VTAG | vlan_get_tag(m0); 1112 #endif 1113 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1114 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1115 csumflags |= NFE_TX_IP_CSUM; 1116 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1117 csumflags |= NFE_TX_TCP_UDP_CSUM; 1118 } 1119 1120 for (i = 0; i < map->dm_nsegs; i++) { 1121 data = &sc->txq.data[sc->txq.cur]; 1122 1123 if (sc->sc_flags & NFE_40BIT_ADDR) { 1124 desc64 = &sc->txq.desc64[sc->txq.cur]; 1125 #if defined(__LP64__) 1126 desc64->physaddr[0] = 1127 htole32(map->dm_segs[i].ds_addr >> 32); 1128 #endif 1129 desc64->physaddr[1] = 1130 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1131 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1132 desc64->flags = htole16(flags); 1133 desc64->vtag = 0; 1134 } else { 1135 desc32 = &sc->txq.desc32[sc->txq.cur]; 1136 1137 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1138 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1139 desc32->flags = htole16(flags); 1140 } 1141 1142 /* 1143 * Setting of the valid bit in the first descriptor is 1144 * deferred until the whole chain is fully setup. 1145 */ 1146 flags |= NFE_TX_VALID; 1147 1148 sc->txq.queued++; 1149 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1150 } 1151 1152 /* the whole mbuf chain has been setup */ 1153 if (sc->sc_flags & NFE_40BIT_ADDR) { 1154 /* fix last descriptor */ 1155 flags |= NFE_TX_LASTFRAG_V2; 1156 desc64->flags = htole16(flags); 1157 1158 /* Checksum flags and vtag belong to the first fragment only. */ 1159 #if NVLAN > 0 1160 sc->txq.desc64[first].vtag = htole32(vtag); 1161 #endif 1162 sc->txq.desc64[first].flags |= htole16(csumflags); 1163 1164 /* finally, set the valid bit in the first descriptor */ 1165 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1166 } else { 1167 /* fix last descriptor */ 1168 if (sc->sc_flags & NFE_JUMBO_SUP) 1169 flags |= NFE_TX_LASTFRAG_V2; 1170 else 1171 flags |= NFE_TX_LASTFRAG_V1; 1172 desc32->flags = htole16(flags); 1173 1174 /* Checksum flags belong to the first fragment only. */ 1175 sc->txq.desc32[first].flags |= htole16(csumflags); 1176 1177 /* finally, set the valid bit in the first descriptor */ 1178 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1179 } 1180 1181 data->m = m0; 1182 data->active = map; 1183 1184 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1185 BUS_DMASYNC_PREWRITE); 1186 1187 return 0; 1188 } 1189 1190 void 1191 nfe_start(struct ifnet *ifp) 1192 { 1193 struct nfe_softc *sc = ifp->if_softc; 1194 int old = sc->txq.queued; 1195 struct mbuf *m0; 1196 1197 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1198 return; 1199 1200 for (;;) { 1201 IFQ_POLL(&ifp->if_snd, m0); 1202 if (m0 == NULL) 1203 break; 1204 1205 if (nfe_encap(sc, m0) != 0) { 1206 ifp->if_flags |= IFF_OACTIVE; 1207 break; 1208 } 1209 1210 /* packet put in h/w queue, remove from s/w queue */ 1211 IFQ_DEQUEUE(&ifp->if_snd, m0); 1212 1213 bpf_mtap(ifp, m0, BPF_D_OUT); 1214 } 1215 1216 if (sc->txq.queued != old) { 1217 /* packets are queued */ 1218 if (sc->sc_flags & NFE_40BIT_ADDR) 1219 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1220 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1221 else 1222 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1223 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1224 /* kick Tx */ 1225 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1226 1227 /* 1228 * Set a timeout in case the chip goes out to lunch. 1229 */ 1230 ifp->if_timer = 5; 1231 } 1232 } 1233 1234 void 1235 nfe_watchdog(struct ifnet *ifp) 1236 { 1237 struct nfe_softc *sc = ifp->if_softc; 1238 1239 aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1240 1241 ifp->if_flags &= ~IFF_RUNNING; 1242 nfe_init(ifp); 1243 1244 ifp->if_oerrors++; 1245 } 1246 1247 int 1248 nfe_init(struct ifnet *ifp) 1249 { 1250 struct nfe_softc *sc = ifp->if_softc; 1251 uint32_t tmp; 1252 int rc = 0, s; 1253 1254 if (ifp->if_flags & IFF_RUNNING) 1255 return 0; 1256 1257 nfe_stop(ifp, 0); 1258 1259 NFE_WRITE(sc, NFE_TX_UNK, 0); 1260 NFE_WRITE(sc, NFE_STATUS, 0); 1261 1262 sc->rxtxctl = NFE_RXTX_BIT2; 1263 if (sc->sc_flags & NFE_40BIT_ADDR) 1264 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1265 else if (sc->sc_flags & NFE_JUMBO_SUP) 1266 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1267 if (sc->sc_flags & NFE_HW_CSUM) 1268 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1269 #if NVLAN > 0 1270 /* 1271 * Although the adapter is capable of stripping VLAN tags from received 1272 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1273 * purpose. This will be done in software by our network stack. 1274 */ 1275 if (sc->sc_flags & NFE_HW_VLAN) 1276 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1277 #endif 1278 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1279 DELAY(10); 1280 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1281 1282 #if NVLAN 1283 if (sc->sc_flags & NFE_HW_VLAN) 1284 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1285 #endif 1286 1287 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1288 1289 /* set MAC address */ 1290 nfe_set_macaddr(sc, sc->sc_enaddr); 1291 1292 /* tell MAC where rings are in memory */ 1293 #ifdef __LP64__ 1294 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1295 #endif 1296 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1297 #ifdef __LP64__ 1298 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1299 #endif 1300 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1301 1302 NFE_WRITE(sc, NFE_RING_SIZE, 1303 (NFE_RX_RING_COUNT - 1) << 16 | 1304 (NFE_TX_RING_COUNT - 1)); 1305 1306 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1307 1308 /* force MAC to wakeup */ 1309 tmp = NFE_READ(sc, NFE_PWR_STATE); 1310 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1311 DELAY(10); 1312 tmp = NFE_READ(sc, NFE_PWR_STATE); 1313 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1314 1315 s = splnet(); 1316 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1317 nfe_intr(sc); /* XXX clear IRQ status registers */ 1318 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1319 splx(s); 1320 1321 #if 1 1322 /* configure interrupts coalescing/mitigation */ 1323 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1324 #else 1325 /* no interrupt mitigation: one interrupt per packet */ 1326 NFE_WRITE(sc, NFE_IMTIMER, 970); 1327 #endif 1328 1329 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1330 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1331 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1332 1333 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1334 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1335 1336 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1337 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_ENABLE); 1338 1339 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1340 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1341 DELAY(10); 1342 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1343 1344 /* set Rx filter */ 1345 nfe_setmulti(sc); 1346 1347 if ((rc = ether_mediachange(ifp)) != 0) 1348 goto out; 1349 1350 nfe_tick(sc); 1351 1352 /* enable Rx */ 1353 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1354 1355 /* enable Tx */ 1356 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1357 1358 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1359 1360 /* enable interrupts */ 1361 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1362 1363 callout_schedule(&sc->sc_tick_ch, hz); 1364 1365 ifp->if_flags |= IFF_RUNNING; 1366 ifp->if_flags &= ~IFF_OACTIVE; 1367 1368 out: 1369 return rc; 1370 } 1371 1372 void 1373 nfe_stop(struct ifnet *ifp, int disable) 1374 { 1375 struct nfe_softc *sc = ifp->if_softc; 1376 1377 callout_stop(&sc->sc_tick_ch); 1378 1379 ifp->if_timer = 0; 1380 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1381 1382 mii_down(&sc->sc_mii); 1383 1384 /* abort Tx */ 1385 NFE_WRITE(sc, NFE_TX_CTL, 0); 1386 1387 /* disable Rx */ 1388 NFE_WRITE(sc, NFE_RX_CTL, 0); 1389 1390 /* disable interrupts */ 1391 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1392 1393 /* reset Tx and Rx rings */ 1394 nfe_reset_tx_ring(sc, &sc->txq); 1395 nfe_reset_rx_ring(sc, &sc->rxq); 1396 } 1397 1398 int 1399 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1400 { 1401 struct nfe_desc32 *desc32; 1402 struct nfe_desc64 *desc64; 1403 struct nfe_rx_data *data; 1404 struct nfe_jbuf *jbuf; 1405 void **desc; 1406 bus_addr_t physaddr; 1407 int i, nsegs, error, descsize; 1408 1409 if (sc->sc_flags & NFE_40BIT_ADDR) { 1410 desc = (void **)&ring->desc64; 1411 descsize = sizeof (struct nfe_desc64); 1412 } else { 1413 desc = (void **)&ring->desc32; 1414 descsize = sizeof (struct nfe_desc32); 1415 } 1416 1417 ring->cur = ring->next = 0; 1418 ring->bufsz = MCLBYTES; 1419 1420 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1421 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1422 if (error != 0) { 1423 aprint_error_dev(sc->sc_dev, 1424 "could not create desc DMA map\n"); 1425 ring->map = NULL; 1426 goto fail; 1427 } 1428 1429 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1430 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1431 if (error != 0) { 1432 aprint_error_dev(sc->sc_dev, 1433 "could not allocate DMA memory\n"); 1434 goto fail; 1435 } 1436 1437 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1438 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1439 if (error != 0) { 1440 aprint_error_dev(sc->sc_dev, 1441 "could not map desc DMA memory\n"); 1442 goto fail; 1443 } 1444 1445 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1446 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1447 if (error != 0) { 1448 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1449 goto fail; 1450 } 1451 1452 memset(*desc, 0, NFE_RX_RING_COUNT * descsize); 1453 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1454 1455 if (sc->sc_flags & NFE_USE_JUMBO) { 1456 ring->bufsz = NFE_JBYTES; 1457 if ((error = nfe_jpool_alloc(sc)) != 0) { 1458 aprint_error_dev(sc->sc_dev, 1459 "could not allocate jumbo frames\n"); 1460 goto fail; 1461 } 1462 } 1463 1464 /* 1465 * Pre-allocate Rx buffers and populate Rx ring. 1466 */ 1467 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1468 data = &sc->rxq.data[i]; 1469 1470 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1471 if (data->m == NULL) { 1472 aprint_error_dev(sc->sc_dev, 1473 "could not allocate rx mbuf\n"); 1474 error = ENOMEM; 1475 goto fail; 1476 } 1477 1478 if (sc->sc_flags & NFE_USE_JUMBO) { 1479 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1480 aprint_error_dev(sc->sc_dev, 1481 "could not allocate jumbo buffer\n"); 1482 goto fail; 1483 } 1484 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1485 sc); 1486 1487 physaddr = jbuf->physaddr; 1488 } else { 1489 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1490 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1491 if (error != 0) { 1492 aprint_error_dev(sc->sc_dev, 1493 "could not create DMA map\n"); 1494 data->map = NULL; 1495 goto fail; 1496 } 1497 MCLGET(data->m, M_DONTWAIT); 1498 if (!(data->m->m_flags & M_EXT)) { 1499 aprint_error_dev(sc->sc_dev, 1500 "could not allocate mbuf cluster\n"); 1501 error = ENOMEM; 1502 goto fail; 1503 } 1504 1505 error = bus_dmamap_load(sc->sc_dmat, data->map, 1506 mtod(data->m, void *), MCLBYTES, NULL, 1507 BUS_DMA_READ | BUS_DMA_NOWAIT); 1508 if (error != 0) { 1509 aprint_error_dev(sc->sc_dev, 1510 "could not load rx buf DMA map"); 1511 goto fail; 1512 } 1513 physaddr = data->map->dm_segs[0].ds_addr; 1514 } 1515 1516 if (sc->sc_flags & NFE_40BIT_ADDR) { 1517 desc64 = &sc->rxq.desc64[i]; 1518 #if defined(__LP64__) 1519 desc64->physaddr[0] = htole32(physaddr >> 32); 1520 #endif 1521 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1522 desc64->length = htole16(sc->rxq.bufsz); 1523 desc64->flags = htole16(NFE_RX_READY); 1524 } else { 1525 desc32 = &sc->rxq.desc32[i]; 1526 desc32->physaddr = htole32(physaddr); 1527 desc32->length = htole16(sc->rxq.bufsz); 1528 desc32->flags = htole16(NFE_RX_READY); 1529 } 1530 } 1531 1532 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1533 BUS_DMASYNC_PREWRITE); 1534 1535 return 0; 1536 1537 fail: nfe_free_rx_ring(sc, ring); 1538 return error; 1539 } 1540 1541 void 1542 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1543 { 1544 int i; 1545 1546 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1547 if (sc->sc_flags & NFE_40BIT_ADDR) { 1548 ring->desc64[i].length = htole16(ring->bufsz); 1549 ring->desc64[i].flags = htole16(NFE_RX_READY); 1550 } else { 1551 ring->desc32[i].length = htole16(ring->bufsz); 1552 ring->desc32[i].flags = htole16(NFE_RX_READY); 1553 } 1554 } 1555 1556 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1557 BUS_DMASYNC_PREWRITE); 1558 1559 ring->cur = ring->next = 0; 1560 } 1561 1562 void 1563 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1564 { 1565 struct nfe_rx_data *data; 1566 void *desc; 1567 int i, descsize; 1568 1569 if (sc->sc_flags & NFE_40BIT_ADDR) { 1570 desc = ring->desc64; 1571 descsize = sizeof (struct nfe_desc64); 1572 } else { 1573 desc = ring->desc32; 1574 descsize = sizeof (struct nfe_desc32); 1575 } 1576 1577 if (desc != NULL) { 1578 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1579 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1580 bus_dmamap_unload(sc->sc_dmat, ring->map); 1581 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1582 NFE_RX_RING_COUNT * descsize); 1583 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1584 } 1585 1586 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1587 data = &ring->data[i]; 1588 1589 if (data->map != NULL) { 1590 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1591 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1592 bus_dmamap_unload(sc->sc_dmat, data->map); 1593 bus_dmamap_destroy(sc->sc_dmat, data->map); 1594 } 1595 if (data->m != NULL) 1596 m_freem(data->m); 1597 } 1598 1599 nfe_jpool_free(sc); 1600 } 1601 1602 struct nfe_jbuf * 1603 nfe_jalloc(struct nfe_softc *sc, int i) 1604 { 1605 struct nfe_jbuf *jbuf; 1606 1607 mutex_enter(&sc->rxq.mtx); 1608 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1609 if (jbuf != NULL) 1610 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1611 mutex_exit(&sc->rxq.mtx); 1612 if (jbuf == NULL) 1613 return NULL; 1614 sc->rxq.jbufmap[i] = 1615 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1616 return jbuf; 1617 } 1618 1619 /* 1620 * This is called automatically by the network stack when the mbuf is freed. 1621 * Caution must be taken that the NIC might be reset by the time the mbuf is 1622 * freed. 1623 */ 1624 void 1625 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1626 { 1627 struct nfe_softc *sc = arg; 1628 struct nfe_jbuf *jbuf; 1629 int i; 1630 1631 /* find the jbuf from the base pointer */ 1632 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1633 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1634 aprint_error_dev(sc->sc_dev, 1635 "request to free a buffer (%p) not managed by us\n", buf); 1636 return; 1637 } 1638 jbuf = &sc->rxq.jbuf[i]; 1639 1640 /* ..and put it back in the free list */ 1641 mutex_enter(&sc->rxq.mtx); 1642 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1643 mutex_exit(&sc->rxq.mtx); 1644 1645 if (m != NULL) 1646 pool_cache_put(mb_cache, m); 1647 } 1648 1649 int 1650 nfe_jpool_alloc(struct nfe_softc *sc) 1651 { 1652 struct nfe_rx_ring *ring = &sc->rxq; 1653 struct nfe_jbuf *jbuf; 1654 bus_addr_t physaddr; 1655 char *buf; 1656 int i, nsegs, error; 1657 1658 /* 1659 * Allocate a big chunk of DMA'able memory. 1660 */ 1661 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1662 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1663 if (error != 0) { 1664 aprint_error_dev(sc->sc_dev, 1665 "could not create jumbo DMA map\n"); 1666 ring->jmap = NULL; 1667 goto fail; 1668 } 1669 1670 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1671 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1672 if (error != 0) { 1673 aprint_error_dev(sc->sc_dev, 1674 "could not allocate jumbo DMA memory\n"); 1675 goto fail; 1676 } 1677 1678 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1679 &ring->jpool, BUS_DMA_NOWAIT); 1680 if (error != 0) { 1681 aprint_error_dev(sc->sc_dev, 1682 "could not map jumbo DMA memory\n"); 1683 goto fail; 1684 } 1685 1686 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1687 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1688 if (error != 0) { 1689 aprint_error_dev(sc->sc_dev, 1690 "could not load jumbo DMA map\n"); 1691 goto fail; 1692 } 1693 1694 /* ..and split it into 9KB chunks */ 1695 SLIST_INIT(&ring->jfreelist); 1696 1697 buf = ring->jpool; 1698 physaddr = ring->jmap->dm_segs[0].ds_addr; 1699 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1700 jbuf = &ring->jbuf[i]; 1701 1702 jbuf->buf = buf; 1703 jbuf->physaddr = physaddr; 1704 1705 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1706 1707 buf += NFE_JBYTES; 1708 physaddr += NFE_JBYTES; 1709 } 1710 1711 return 0; 1712 1713 fail: nfe_jpool_free(sc); 1714 return error; 1715 } 1716 1717 void 1718 nfe_jpool_free(struct nfe_softc *sc) 1719 { 1720 struct nfe_rx_ring *ring = &sc->rxq; 1721 1722 if (ring->jmap != NULL) { 1723 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1724 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1725 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1726 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1727 ring->jmap = NULL; 1728 } 1729 if (ring->jpool != NULL) { 1730 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1731 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1732 ring->jpool = NULL; 1733 } 1734 } 1735 1736 int 1737 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1738 { 1739 int i, nsegs, error; 1740 void **desc; 1741 int descsize; 1742 1743 if (sc->sc_flags & NFE_40BIT_ADDR) { 1744 desc = (void **)&ring->desc64; 1745 descsize = sizeof (struct nfe_desc64); 1746 } else { 1747 desc = (void **)&ring->desc32; 1748 descsize = sizeof (struct nfe_desc32); 1749 } 1750 1751 ring->queued = 0; 1752 ring->cur = ring->next = 0; 1753 1754 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1755 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1756 1757 if (error != 0) { 1758 aprint_error_dev(sc->sc_dev, 1759 "could not create desc DMA map\n"); 1760 ring->map = NULL; 1761 goto fail; 1762 } 1763 1764 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1765 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1766 if (error != 0) { 1767 aprint_error_dev(sc->sc_dev, 1768 "could not allocate DMA memory\n"); 1769 goto fail; 1770 } 1771 1772 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1773 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1774 if (error != 0) { 1775 aprint_error_dev(sc->sc_dev, 1776 "could not map desc DMA memory\n"); 1777 goto fail; 1778 } 1779 1780 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1781 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1782 if (error != 0) { 1783 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1784 goto fail; 1785 } 1786 1787 memset(*desc, 0, NFE_TX_RING_COUNT * descsize); 1788 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1789 1790 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1791 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1792 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1793 &ring->data[i].map); 1794 if (error != 0) { 1795 aprint_error_dev(sc->sc_dev, 1796 "could not create DMA map\n"); 1797 ring->data[i].map = NULL; 1798 goto fail; 1799 } 1800 } 1801 1802 return 0; 1803 1804 fail: nfe_free_tx_ring(sc, ring); 1805 return error; 1806 } 1807 1808 void 1809 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1810 { 1811 struct nfe_tx_data *data; 1812 int i; 1813 1814 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1815 if (sc->sc_flags & NFE_40BIT_ADDR) 1816 ring->desc64[i].flags = 0; 1817 else 1818 ring->desc32[i].flags = 0; 1819 1820 data = &ring->data[i]; 1821 1822 if (data->m != NULL) { 1823 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1824 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1825 bus_dmamap_unload(sc->sc_dmat, data->active); 1826 m_freem(data->m); 1827 data->m = NULL; 1828 } 1829 } 1830 1831 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1832 BUS_DMASYNC_PREWRITE); 1833 1834 ring->queued = 0; 1835 ring->cur = ring->next = 0; 1836 } 1837 1838 void 1839 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1840 { 1841 struct nfe_tx_data *data; 1842 void *desc; 1843 int i, descsize; 1844 1845 if (sc->sc_flags & NFE_40BIT_ADDR) { 1846 desc = ring->desc64; 1847 descsize = sizeof (struct nfe_desc64); 1848 } else { 1849 desc = ring->desc32; 1850 descsize = sizeof (struct nfe_desc32); 1851 } 1852 1853 if (desc != NULL) { 1854 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1855 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1856 bus_dmamap_unload(sc->sc_dmat, ring->map); 1857 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1858 NFE_TX_RING_COUNT * descsize); 1859 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1860 } 1861 1862 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1863 data = &ring->data[i]; 1864 1865 if (data->m != NULL) { 1866 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1867 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1868 bus_dmamap_unload(sc->sc_dmat, data->active); 1869 m_freem(data->m); 1870 } 1871 } 1872 1873 /* ..and now actually destroy the DMA mappings */ 1874 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1875 data = &ring->data[i]; 1876 if (data->map == NULL) 1877 continue; 1878 bus_dmamap_destroy(sc->sc_dmat, data->map); 1879 } 1880 } 1881 1882 void 1883 nfe_setmulti(struct nfe_softc *sc) 1884 { 1885 struct ethercom *ec = &sc->sc_ethercom; 1886 struct ifnet *ifp = &ec->ec_if; 1887 struct ether_multi *enm; 1888 struct ether_multistep step; 1889 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1890 uint32_t filter = NFE_RXFILTER_MAGIC; 1891 int i; 1892 1893 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1894 memset(addr, 0, ETHER_ADDR_LEN); 1895 memset(mask, 0, ETHER_ADDR_LEN); 1896 goto done; 1897 } 1898 1899 memcpy(addr, etherbroadcastaddr, ETHER_ADDR_LEN); 1900 memcpy(mask, etherbroadcastaddr, ETHER_ADDR_LEN); 1901 1902 ETHER_LOCK(ec); 1903 ETHER_FIRST_MULTI(step, ec, enm); 1904 while (enm != NULL) { 1905 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1906 ifp->if_flags |= IFF_ALLMULTI; 1907 memset(addr, 0, ETHER_ADDR_LEN); 1908 memset(mask, 0, ETHER_ADDR_LEN); 1909 ETHER_UNLOCK(ec); 1910 goto done; 1911 } 1912 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1913 addr[i] &= enm->enm_addrlo[i]; 1914 mask[i] &= ~enm->enm_addrlo[i]; 1915 } 1916 ETHER_NEXT_MULTI(step, enm); 1917 } 1918 ETHER_UNLOCK(ec); 1919 for (i = 0; i < ETHER_ADDR_LEN; i++) 1920 mask[i] |= addr[i]; 1921 1922 done: 1923 addr[0] |= 0x01; /* make sure multicast bit is set */ 1924 1925 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1926 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1927 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1928 addr[5] << 8 | addr[4]); 1929 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1930 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1931 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1932 mask[5] << 8 | mask[4]); 1933 1934 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1935 NFE_WRITE(sc, NFE_RXFILTER, filter); 1936 } 1937 1938 void 1939 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1940 { 1941 uint32_t tmp; 1942 1943 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 1944 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1945 addr[0] = (tmp & 0xff); 1946 addr[1] = (tmp >> 8) & 0xff; 1947 addr[2] = (tmp >> 16) & 0xff; 1948 addr[3] = (tmp >> 24) & 0xff; 1949 1950 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1951 addr[4] = (tmp & 0xff); 1952 addr[5] = (tmp >> 8) & 0xff; 1953 1954 } else { 1955 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1956 addr[0] = (tmp >> 8) & 0xff; 1957 addr[1] = (tmp & 0xff); 1958 1959 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1960 addr[2] = (tmp >> 24) & 0xff; 1961 addr[3] = (tmp >> 16) & 0xff; 1962 addr[4] = (tmp >> 8) & 0xff; 1963 addr[5] = (tmp & 0xff); 1964 } 1965 } 1966 1967 void 1968 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1969 { 1970 NFE_WRITE(sc, NFE_MACADDR_LO, 1971 addr[5] << 8 | addr[4]); 1972 NFE_WRITE(sc, NFE_MACADDR_HI, 1973 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1974 } 1975 1976 void 1977 nfe_tick(void *arg) 1978 { 1979 struct nfe_softc *sc = arg; 1980 int s; 1981 1982 s = splnet(); 1983 mii_tick(&sc->sc_mii); 1984 splx(s); 1985 1986 callout_schedule(&sc->sc_tick_ch, hz); 1987 } 1988 1989 void 1990 nfe_poweron(device_t self) 1991 { 1992 struct nfe_softc *sc = device_private(self); 1993 1994 if ((sc->sc_flags & NFE_PWR_MGMT) != 0) { 1995 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 1996 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 1997 DELAY(100); 1998 NFE_WRITE(sc, NFE_MAC_RESET, 0); 1999 DELAY(100); 2000 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 2001 NFE_WRITE(sc, NFE_PWR2_CTL, 2002 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_WAKEUP_MASK); 2003 } 2004 } 2005 2006 bool 2007 nfe_resume(device_t dv, const pmf_qual_t *qual) 2008 { 2009 nfe_poweron(dv); 2010 2011 return true; 2012 } 2013
Indexes created Tue Sep 30 11:09:46 GMT 2025