if_nfe.c revision 1.74
1 /* $NetBSD: if_nfe.c,v 1.74 2020/02/04 05:44:14 thorpej Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.77 2008/02/05 16:52:50 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006, 2007 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.74 2020/02/04 05:44:14 thorpej Exp $"); 25 26 #include "opt_inet.h" 27 #include "vlan.h" 28 29 #include <sys/param.h> 30 #include <sys/endian.h> 31 #include <sys/systm.h> 32 #include <sys/types.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/mutex.h> 36 #include <sys/queue.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/callout.h> 40 #include <sys/socket.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #include <net/bpf.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_nfereg.h> 72 #include <dev/pci/if_nfevar.h> 73 74 static int nfe_ifflags_cb(struct ethercom *); 75 76 int nfe_match(device_t, cfdata_t, void *); 77 void nfe_attach(device_t, device_t, void *); 78 int nfe_detach(device_t, int); 79 void nfe_power(int, void *); 80 void nfe_miibus_statchg(struct ifnet *); 81 int nfe_miibus_readreg(device_t, int, int, uint16_t *); 82 int nfe_miibus_writereg(device_t, int, int, uint16_t); 83 int nfe_intr(void *); 84 int nfe_ioctl(struct ifnet *, u_long, void *); 85 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 86 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 87 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 88 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 89 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 90 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 91 void nfe_rxeof(struct nfe_softc *); 92 void nfe_txeof(struct nfe_softc *); 93 int nfe_encap(struct nfe_softc *, struct mbuf *); 94 void nfe_start(struct ifnet *); 95 void nfe_watchdog(struct ifnet *); 96 int nfe_init(struct ifnet *); 97 void nfe_stop(struct ifnet *, int); 98 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 99 void nfe_jfree(struct mbuf *, void *, size_t, void *); 100 int nfe_jpool_alloc(struct nfe_softc *); 101 void nfe_jpool_free(struct nfe_softc *); 102 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 105 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 108 void nfe_setmulti(struct nfe_softc *); 109 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 110 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 111 void nfe_tick(void *); 112 void nfe_poweron(device_t); 113 bool nfe_resume(device_t, const pmf_qual_t *); 114 115 CFATTACH_DECL_NEW(nfe, sizeof(struct nfe_softc), 116 nfe_match, nfe_attach, nfe_detach, NULL); 117 118 /* #define NFE_NO_JUMBO */ 119 120 #ifdef NFE_DEBUG 121 int nfedebug = 0; 122 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 123 #define DPRINTFN(n, x) do { if (nfedebug >= (n)) printf x; } while (0) 124 #else 125 #define DPRINTF(x) 126 #define DPRINTFN(n, x) 127 #endif 128 129 /* deal with naming differences */ 130 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 134 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 135 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 136 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 137 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 140 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 141 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 142 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 145 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 146 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 147 148 #ifdef _LP64 149 #define __LP64__ 1 150 #endif 151 152 const struct nfe_product { 153 pci_vendor_id_t vendor; 154 pci_product_id_t product; 155 } nfe_devices[] = { 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 183 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 184 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 185 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 186 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 }, 187 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1 }, 188 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2 }, 189 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3 }, 190 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4 }, 191 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1 }, 192 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2 }, 193 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3 }, 194 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4 } 195 }; 196 197 int 198 nfe_match(device_t dev, cfdata_t match, void *aux) 199 { 200 struct pci_attach_args *pa = aux; 201 const struct nfe_product *np; 202 int i; 203 204 for (i = 0; i < __arraycount(nfe_devices); i++) { 205 np = &nfe_devices[i]; 206 if (PCI_VENDOR(pa->pa_id) == np->vendor && 207 PCI_PRODUCT(pa->pa_id) == np->product) 208 return 1; 209 } 210 return 0; 211 } 212 213 void 214 nfe_attach(device_t parent, device_t self, void *aux) 215 { 216 struct nfe_softc *sc = device_private(self); 217 struct pci_attach_args *pa = aux; 218 pci_chipset_tag_t pc = pa->pa_pc; 219 pci_intr_handle_t ih; 220 const char *intrstr; 221 struct ifnet *ifp; 222 struct mii_data * const mii = &sc->sc_mii; 223 pcireg_t memtype, csr; 224 int mii_flags = 0; 225 char intrbuf[PCI_INTRSTR_LEN]; 226 227 sc->sc_dev = self; 228 sc->sc_pc = pa->pa_pc; 229 pci_aprint_devinfo(pa, NULL); 230 231 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 232 switch (memtype) { 233 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 234 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 235 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 236 &sc->sc_memh, NULL, &sc->sc_mems) == 0) 237 break; 238 /* FALLTHROUGH */ 239 default: 240 aprint_error_dev(self, "could not map mem space\n"); 241 return; 242 } 243 244 if (pci_intr_map(pa, &ih) != 0) { 245 aprint_error_dev(self, "could not map interrupt\n"); 246 goto fail; 247 } 248 249 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 250 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, nfe_intr, sc, 251 device_xname(self)); 252 if (sc->sc_ih == NULL) { 253 aprint_error_dev(self, "could not establish interrupt"); 254 if (intrstr != NULL) 255 aprint_error(" at %s", intrstr); 256 aprint_error("\n"); 257 goto fail; 258 } 259 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 260 261 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 262 csr |= PCI_COMMAND_MASTER_ENABLE; 263 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 264 265 sc->sc_flags = 0; 266 267 switch (PCI_PRODUCT(pa->pa_id)) { 268 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 269 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 270 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 271 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 272 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 273 break; 274 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 275 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 276 sc->sc_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT; 277 break; 278 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 279 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 280 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 281 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 282 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 283 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 284 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 285 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 286 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 287 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 288 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 289 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 290 sc->sc_flags |= NFE_40BIT_ADDR | NFE_CORRECT_MACADDR | 291 NFE_PWR_MGMT; 292 break; 293 case PCI_PRODUCT_NVIDIA_MCP77_LAN1: 294 case PCI_PRODUCT_NVIDIA_MCP77_LAN2: 295 case PCI_PRODUCT_NVIDIA_MCP77_LAN3: 296 case PCI_PRODUCT_NVIDIA_MCP77_LAN4: 297 sc->sc_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | 298 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 299 break; 300 case PCI_PRODUCT_NVIDIA_MCP79_LAN1: 301 case PCI_PRODUCT_NVIDIA_MCP79_LAN2: 302 case PCI_PRODUCT_NVIDIA_MCP79_LAN3: 303 case PCI_PRODUCT_NVIDIA_MCP79_LAN4: 304 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 305 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 306 break; 307 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 308 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 309 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 310 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 311 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 312 break; 313 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 314 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 315 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 316 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 317 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 318 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 319 mii_flags = MIIF_DOPAUSE; 320 break; 321 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 322 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 323 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 324 NFE_HW_VLAN | NFE_PWR_MGMT; 325 break; 326 } 327 328 if (pci_dma64_available(pa) && (sc->sc_flags & NFE_40BIT_ADDR) != 0) 329 sc->sc_dmat = pa->pa_dmat64; 330 else 331 sc->sc_dmat = pa->pa_dmat; 332 333 nfe_poweron(self); 334 335 #ifndef NFE_NO_JUMBO 336 /* enable jumbo frames for adapters that support it */ 337 if (sc->sc_flags & NFE_JUMBO_SUP) 338 sc->sc_flags |= NFE_USE_JUMBO; 339 #endif 340 341 /* Check for reversed ethernet address */ 342 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 343 sc->sc_flags |= NFE_CORRECT_MACADDR; 344 345 nfe_get_macaddr(sc, sc->sc_enaddr); 346 aprint_normal_dev(self, "Ethernet address %s\n", 347 ether_sprintf(sc->sc_enaddr)); 348 349 /* 350 * Allocate Tx and Rx rings. 351 */ 352 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 353 aprint_error_dev(self, "could not allocate Tx ring\n"); 354 goto fail; 355 } 356 357 mutex_init(&sc->rxq.mtx, MUTEX_DEFAULT, IPL_NET); 358 359 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 360 aprint_error_dev(self, "could not allocate Rx ring\n"); 361 nfe_free_tx_ring(sc, &sc->txq); 362 goto fail; 363 } 364 365 ifp = &sc->sc_ethercom.ec_if; 366 ifp->if_softc = sc; 367 ifp->if_mtu = ETHERMTU; 368 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 369 ifp->if_ioctl = nfe_ioctl; 370 ifp->if_start = nfe_start; 371 ifp->if_stop = nfe_stop; 372 ifp->if_watchdog = nfe_watchdog; 373 ifp->if_init = nfe_init; 374 ifp->if_baudrate = IF_Gbps(1); 375 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 376 IFQ_SET_READY(&ifp->if_snd); 377 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 378 379 if (sc->sc_flags & NFE_USE_JUMBO) 380 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 381 382 #if NVLAN > 0 383 if (sc->sc_flags & NFE_HW_VLAN) { 384 sc->sc_ethercom.ec_capabilities |= 385 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 386 sc->sc_ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 387 } 388 #endif 389 if (sc->sc_flags & NFE_HW_CSUM) { 390 ifp->if_capabilities |= 391 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 392 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 393 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 394 } 395 396 mii->mii_ifp = ifp; 397 mii->mii_readreg = nfe_miibus_readreg; 398 mii->mii_writereg = nfe_miibus_writereg; 399 mii->mii_statchg = nfe_miibus_statchg; 400 401 sc->sc_ethercom.ec_mii = mii; 402 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 403 404 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 0, mii_flags); 405 406 if (LIST_FIRST(&mii->mii_phys) == NULL) { 407 aprint_error_dev(self, "no PHY found!\n"); 408 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 409 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 410 } else 411 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 412 413 if_attach(ifp); 414 if_deferred_start_init(ifp, NULL); 415 ether_ifattach(ifp, sc->sc_enaddr); 416 ether_set_ifflags_cb(&sc->sc_ethercom, nfe_ifflags_cb); 417 418 callout_init(&sc->sc_tick_ch, 0); 419 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 420 421 if (pmf_device_register(self, NULL, nfe_resume)) 422 pmf_class_network_register(self, ifp); 423 else 424 aprint_error_dev(self, "couldn't establish power handler\n"); 425 426 return; 427 428 fail: 429 if (sc->sc_ih != NULL) { 430 pci_intr_disestablish(pc, sc->sc_ih); 431 sc->sc_ih = NULL; 432 } 433 if (sc->sc_mems != 0) { 434 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 435 sc->sc_mems = 0; 436 } 437 } 438 439 int 440 nfe_detach(device_t self, int flags) 441 { 442 struct nfe_softc *sc = device_private(self); 443 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 444 int s; 445 446 s = splnet(); 447 448 nfe_stop(ifp, 1); 449 450 pmf_device_deregister(self); 451 callout_destroy(&sc->sc_tick_ch); 452 ether_ifdetach(ifp); 453 if_detach(ifp); 454 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 455 ifmedia_fini(&sc->sc_mii.mii_media); 456 457 nfe_free_rx_ring(sc, &sc->rxq); 458 mutex_destroy(&sc->rxq.mtx); 459 nfe_free_tx_ring(sc, &sc->txq); 460 461 if (sc->sc_ih != NULL) { 462 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 463 sc->sc_ih = NULL; 464 } 465 466 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 467 nfe_set_macaddr(sc, sc->sc_enaddr); 468 } else { 469 NFE_WRITE(sc, NFE_MACADDR_LO, 470 sc->sc_enaddr[0] << 8 | sc->sc_enaddr[1]); 471 NFE_WRITE(sc, NFE_MACADDR_HI, 472 sc->sc_enaddr[2] << 24 | sc->sc_enaddr[3] << 16 | 473 sc->sc_enaddr[4] << 8 | sc->sc_enaddr[5]); 474 } 475 476 if (sc->sc_mems != 0) { 477 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 478 sc->sc_mems = 0; 479 } 480 481 splx(s); 482 483 return 0; 484 } 485 486 void 487 nfe_miibus_statchg(struct ifnet *ifp) 488 { 489 struct nfe_softc *sc = ifp->if_softc; 490 struct mii_data *mii = &sc->sc_mii; 491 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 492 493 phy = NFE_READ(sc, NFE_PHY_IFACE); 494 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 495 496 seed = NFE_READ(sc, NFE_RNDSEED); 497 seed &= ~NFE_SEED_MASK; 498 499 if ((mii->mii_media_active & IFM_HDX) != 0) { 500 phy |= NFE_PHY_HDX; /* half-duplex */ 501 misc |= NFE_MISC1_HDX; 502 } 503 504 switch (IFM_SUBTYPE(mii->mii_media_active)) { 505 case IFM_1000_T: /* full-duplex only */ 506 link |= NFE_MEDIA_1000T; 507 seed |= NFE_SEED_1000T; 508 phy |= NFE_PHY_1000T; 509 break; 510 case IFM_100_TX: 511 link |= NFE_MEDIA_100TX; 512 seed |= NFE_SEED_100TX; 513 phy |= NFE_PHY_100TX; 514 break; 515 case IFM_10_T: 516 link |= NFE_MEDIA_10T; 517 seed |= NFE_SEED_10T; 518 break; 519 } 520 521 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 522 523 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 524 NFE_WRITE(sc, NFE_MISC1, misc); 525 NFE_WRITE(sc, NFE_LINKSPEED, link); 526 } 527 528 int 529 nfe_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 530 { 531 struct nfe_softc *sc = device_private(dev); 532 uint32_t data; 533 int ntries; 534 535 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 536 537 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 538 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 539 DELAY(100); 540 } 541 542 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 543 544 for (ntries = 0; ntries < 1000; ntries++) { 545 DELAY(100); 546 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 547 break; 548 } 549 if (ntries == 1000) { 550 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 551 device_xname(sc->sc_dev))); 552 return ETIMEDOUT; 553 } 554 555 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 556 DPRINTFN(2, ("%s: could not read PHY\n", 557 device_xname(sc->sc_dev))); 558 return -1; 559 } 560 561 data = NFE_READ(sc, NFE_PHY_DATA); 562 if (data != 0xffffffff && data != 0) 563 sc->mii_phyaddr = phy; 564 565 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x data 0x%x\n", 566 device_xname(sc->sc_dev), phy, reg, data)); 567 568 *val = data & 0x0000ffff; 569 return 0; 570 } 571 572 int 573 nfe_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 574 { 575 struct nfe_softc *sc = device_private(dev); 576 uint32_t ctl; 577 int ntries; 578 579 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 580 581 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 582 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 583 DELAY(100); 584 } 585 586 NFE_WRITE(sc, NFE_PHY_DATA, val); 587 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 588 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 589 590 for (ntries = 0; ntries < 1000; ntries++) { 591 DELAY(100); 592 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 593 break; 594 } 595 if (ntries == 1000) { 596 #ifdef NFE_DEBUG 597 if (nfedebug >= 2) 598 printf("could not write to PHY\n"); 599 #endif 600 return ETIMEDOUT; 601 } 602 return 0; 603 } 604 605 int 606 nfe_intr(void *arg) 607 { 608 struct nfe_softc *sc = arg; 609 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 610 uint32_t r; 611 int handled; 612 613 if ((ifp->if_flags & IFF_UP) == 0) 614 return 0; 615 616 handled = 0; 617 618 for (;;) { 619 r = NFE_READ(sc, NFE_IRQ_STATUS); 620 if ((r & NFE_IRQ_WANTED) == 0) 621 break; 622 623 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 624 handled = 1; 625 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 626 627 if ((r & (NFE_IRQ_RXERR |NFE_IRQ_RX_NOBUF |NFE_IRQ_RX)) != 0) { 628 /* check Rx ring */ 629 nfe_rxeof(sc); 630 } 631 if ((r & (NFE_IRQ_TXERR|NFE_IRQ_TXERR2|NFE_IRQ_TX_DONE)) != 0) { 632 /* check Tx ring */ 633 nfe_txeof(sc); 634 } 635 if ((r & NFE_IRQ_LINK) != 0) { 636 NFE_READ(sc, NFE_PHY_STATUS); 637 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 638 DPRINTF(("%s: link state changed\n", 639 device_xname(sc->sc_dev))); 640 } 641 } 642 643 if (handled) 644 if_schedule_deferred_start(ifp); 645 646 return handled; 647 } 648 649 static int 650 nfe_ifflags_cb(struct ethercom *ec) 651 { 652 struct ifnet *ifp = &ec->ec_if; 653 struct nfe_softc *sc = ifp->if_softc; 654 u_short change = ifp->if_flags ^ sc->sc_if_flags; 655 656 /* 657 * If only the PROMISC flag changes, then 658 * don't do a full re-init of the chip, just update 659 * the Rx filter. 660 */ 661 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 662 return ENETRESET; 663 else if ((change & IFF_PROMISC) != 0) 664 nfe_setmulti(sc); 665 666 return 0; 667 } 668 669 int 670 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 671 { 672 struct nfe_softc *sc = ifp->if_softc; 673 struct ifaddr *ifa = (struct ifaddr *)data; 674 int s, error = 0; 675 676 s = splnet(); 677 678 switch (cmd) { 679 case SIOCINITIFADDR: 680 ifp->if_flags |= IFF_UP; 681 nfe_init(ifp); 682 switch (ifa->ifa_addr->sa_family) { 683 #ifdef INET 684 case AF_INET: 685 arp_ifinit(ifp, ifa); 686 break; 687 #endif 688 default: 689 break; 690 } 691 break; 692 default: 693 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 694 break; 695 696 error = 0; 697 698 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 699 ; 700 else if (ifp->if_flags & IFF_RUNNING) 701 nfe_setmulti(sc); 702 break; 703 } 704 sc->sc_if_flags = ifp->if_flags; 705 706 splx(s); 707 708 return error; 709 } 710 711 void 712 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 713 { 714 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 715 (char *)desc32 - (char *)sc->txq.desc32, 716 sizeof (struct nfe_desc32), ops); 717 } 718 719 void 720 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 721 { 722 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 723 (char *)desc64 - (char *)sc->txq.desc64, 724 sizeof (struct nfe_desc64), ops); 725 } 726 727 void 728 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 729 { 730 if (end > start) { 731 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 732 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 733 (char *)&sc->txq.desc32[end] - 734 (char *)&sc->txq.desc32[start], ops); 735 return; 736 } 737 /* sync from 'start' to end of ring */ 738 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 739 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 740 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 741 (char *)&sc->txq.desc32[start], ops); 742 743 /* sync from start of ring to 'end' */ 744 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 745 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 746 } 747 748 void 749 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 750 { 751 if (end > start) { 752 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 753 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 754 (char *)&sc->txq.desc64[end] - 755 (char *)&sc->txq.desc64[start], ops); 756 return; 757 } 758 /* sync from 'start' to end of ring */ 759 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 760 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 761 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 762 (char *)&sc->txq.desc64[start], ops); 763 764 /* sync from start of ring to 'end' */ 765 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 766 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 767 } 768 769 void 770 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 771 { 772 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 773 (char *)desc32 - (char *)sc->rxq.desc32, 774 sizeof (struct nfe_desc32), ops); 775 } 776 777 void 778 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 779 { 780 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 781 (char *)desc64 - (char *)sc->rxq.desc64, 782 sizeof (struct nfe_desc64), ops); 783 } 784 785 void 786 nfe_rxeof(struct nfe_softc *sc) 787 { 788 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 789 struct nfe_desc32 *desc32; 790 struct nfe_desc64 *desc64; 791 struct nfe_rx_data *data; 792 struct nfe_jbuf *jbuf; 793 struct mbuf *m, *mnew; 794 bus_addr_t physaddr; 795 uint16_t flags; 796 int error, len, i; 797 798 desc32 = NULL; 799 desc64 = NULL; 800 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 801 data = &sc->rxq.data[i]; 802 803 if (sc->sc_flags & NFE_40BIT_ADDR) { 804 desc64 = &sc->rxq.desc64[i]; 805 nfe_rxdesc64_sync(sc, desc64, 806 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 807 808 flags = le16toh(desc64->flags); 809 len = le16toh(desc64->length) & 0x3fff; 810 } else { 811 desc32 = &sc->rxq.desc32[i]; 812 nfe_rxdesc32_sync(sc, desc32, 813 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 814 815 flags = le16toh(desc32->flags); 816 len = le16toh(desc32->length) & 0x3fff; 817 } 818 819 if ((flags & NFE_RX_READY) != 0) 820 break; 821 822 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 823 if ((flags & NFE_RX_VALID_V1) == 0) 824 goto skip; 825 826 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 827 flags &= ~NFE_RX_ERROR; 828 len--; /* fix buffer length */ 829 } 830 } else { 831 if ((flags & NFE_RX_VALID_V2) == 0) 832 goto skip; 833 834 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 835 flags &= ~NFE_RX_ERROR; 836 len--; /* fix buffer length */ 837 } 838 } 839 840 if (flags & NFE_RX_ERROR) { 841 if_statinc(ifp, if_ierrors); 842 goto skip; 843 } 844 845 /* 846 * Try to allocate a new mbuf for this ring element and load 847 * it before processing the current mbuf. If the ring element 848 * cannot be loaded, drop the received packet and reuse the 849 * old mbuf. In the unlikely case that the old mbuf can't be 850 * reloaded either, explicitly panic. 851 */ 852 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 853 if (mnew == NULL) { 854 if_statinc(ifp, if_ierrors); 855 goto skip; 856 } 857 858 if (sc->sc_flags & NFE_USE_JUMBO) { 859 physaddr = 860 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 861 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 862 if (len > MCLBYTES) { 863 m_freem(mnew); 864 if_statinc(ifp, if_ierrors); 865 goto skip1; 866 } 867 MCLGET(mnew, M_DONTWAIT); 868 if ((mnew->m_flags & M_EXT) == 0) { 869 m_freem(mnew); 870 if_statinc(ifp, if_ierrors); 871 goto skip1; 872 } 873 874 (void)memcpy(mtod(mnew, void *), 875 mtod(data->m, const void *), len); 876 m = mnew; 877 goto mbufcopied; 878 } else { 879 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 880 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 881 mtod(data->m, char *) - (char *)sc->rxq.jpool, 882 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 883 884 physaddr = jbuf->physaddr; 885 } 886 } else { 887 MCLGET(mnew, M_DONTWAIT); 888 if ((mnew->m_flags & M_EXT) == 0) { 889 m_freem(mnew); 890 if_statinc(ifp, if_ierrors); 891 goto skip; 892 } 893 894 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 895 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 896 bus_dmamap_unload(sc->sc_dmat, data->map); 897 898 error = bus_dmamap_load(sc->sc_dmat, data->map, 899 mtod(mnew, void *), MCLBYTES, NULL, 900 BUS_DMA_READ | BUS_DMA_NOWAIT); 901 if (error != 0) { 902 m_freem(mnew); 903 904 /* try to reload the old mbuf */ 905 error = bus_dmamap_load(sc->sc_dmat, data->map, 906 mtod(data->m, void *), MCLBYTES, NULL, 907 BUS_DMA_READ | BUS_DMA_NOWAIT); 908 if (error != 0) { 909 /* very unlikely that it will fail.. */ 910 panic("%s: could not load old rx mbuf", 911 device_xname(sc->sc_dev)); 912 } 913 if_statinc(ifp, if_ierrors); 914 goto skip; 915 } 916 physaddr = data->map->dm_segs[0].ds_addr; 917 } 918 919 /* 920 * New mbuf successfully loaded, update Rx ring and continue 921 * processing. 922 */ 923 m = data->m; 924 data->m = mnew; 925 926 mbufcopied: 927 /* finalize mbuf */ 928 m->m_pkthdr.len = m->m_len = len; 929 m_set_rcvif(m, ifp); 930 931 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 932 /* 933 * XXX 934 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 935 */ 936 if (flags & NFE_RX_IP_CSUMOK) { 937 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 938 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 939 device_xname(sc->sc_dev))); 940 } 941 /* 942 * XXX 943 * no way to check M_CSUM_TCP_UDP_BAD or 944 * other protocols? 945 */ 946 if (flags & NFE_RX_UDP_CSUMOK) { 947 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 948 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 949 device_xname(sc->sc_dev))); 950 } else if (flags & NFE_RX_TCP_CSUMOK) { 951 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 952 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 953 device_xname(sc->sc_dev))); 954 } 955 } 956 if_percpuq_enqueue(ifp->if_percpuq, m); 957 958 skip1: 959 /* update mapping address in h/w descriptor */ 960 if (sc->sc_flags & NFE_40BIT_ADDR) { 961 #if defined(__LP64__) 962 desc64->physaddr[0] = htole32(physaddr >> 32); 963 #endif 964 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 965 } else { 966 desc32->physaddr = htole32(physaddr); 967 } 968 969 skip: 970 if (sc->sc_flags & NFE_40BIT_ADDR) { 971 desc64->length = htole16(sc->rxq.bufsz); 972 desc64->flags = htole16(NFE_RX_READY); 973 974 nfe_rxdesc64_sync(sc, desc64, 975 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 976 } else { 977 desc32->length = htole16(sc->rxq.bufsz); 978 desc32->flags = htole16(NFE_RX_READY); 979 980 nfe_rxdesc32_sync(sc, desc32, 981 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 982 } 983 } 984 /* update current RX pointer */ 985 sc->rxq.cur = i; 986 } 987 988 void 989 nfe_txeof(struct nfe_softc *sc) 990 { 991 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 992 struct nfe_desc32 *desc32; 993 struct nfe_desc64 *desc64; 994 struct nfe_tx_data *data = NULL; 995 int i; 996 uint16_t flags; 997 char buf[128]; 998 999 for (i = sc->txq.next; 1000 sc->txq.queued > 0; 1001 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 1002 if (sc->sc_flags & NFE_40BIT_ADDR) { 1003 desc64 = &sc->txq.desc64[i]; 1004 nfe_txdesc64_sync(sc, desc64, 1005 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1006 1007 flags = le16toh(desc64->flags); 1008 } else { 1009 desc32 = &sc->txq.desc32[i]; 1010 nfe_txdesc32_sync(sc, desc32, 1011 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1012 1013 flags = le16toh(desc32->flags); 1014 } 1015 1016 if ((flags & NFE_TX_VALID) != 0) 1017 break; 1018 1019 data = &sc->txq.data[i]; 1020 1021 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 1022 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 1023 data->m == NULL) 1024 continue; 1025 1026 if ((flags & NFE_TX_ERROR_V1) != 0) { 1027 snprintb(buf, sizeof(buf), NFE_V1_TXERR, flags); 1028 aprint_error_dev(sc->sc_dev, "tx v1 error %s\n", 1029 buf); 1030 if_statinc(ifp, if_oerrors); 1031 } else 1032 if_statinc(ifp, if_opackets); 1033 } else { 1034 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 1035 data->m == NULL) 1036 continue; 1037 1038 if ((flags & NFE_TX_ERROR_V2) != 0) { 1039 snprintb(buf, sizeof(buf), NFE_V2_TXERR, flags); 1040 aprint_error_dev(sc->sc_dev, "tx v2 error %s\n", 1041 buf); 1042 if_statinc(ifp, if_oerrors); 1043 } else 1044 if_statinc(ifp, if_opackets); 1045 } 1046 1047 if (data->m == NULL) { /* should not get there */ 1048 aprint_error_dev(sc->sc_dev, 1049 "last fragment bit w/o associated mbuf!\n"); 1050 continue; 1051 } 1052 1053 /* last fragment of the mbuf chain transmitted */ 1054 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1055 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1056 bus_dmamap_unload(sc->sc_dmat, data->active); 1057 m_freem(data->m); 1058 data->m = NULL; 1059 } 1060 1061 sc->txq.next = i; 1062 1063 if (sc->txq.queued < NFE_TX_RING_COUNT) { 1064 /* at least one slot freed */ 1065 ifp->if_flags &= ~IFF_OACTIVE; 1066 } 1067 1068 if (sc->txq.queued == 0) { 1069 /* all queued packets are sent */ 1070 ifp->if_timer = 0; 1071 } 1072 } 1073 1074 int 1075 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 1076 { 1077 struct nfe_desc32 *desc32; 1078 struct nfe_desc64 *desc64; 1079 struct nfe_tx_data *data; 1080 bus_dmamap_t map; 1081 uint16_t flags, csumflags; 1082 #if NVLAN > 0 1083 uint32_t vtag = 0; 1084 #endif 1085 int error, i, first; 1086 1087 desc32 = NULL; 1088 desc64 = NULL; 1089 data = NULL; 1090 1091 flags = 0; 1092 csumflags = 0; 1093 first = sc->txq.cur; 1094 1095 map = sc->txq.data[first].map; 1096 1097 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1098 if (error != 0) { 1099 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1100 error); 1101 return error; 1102 } 1103 1104 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1105 bus_dmamap_unload(sc->sc_dmat, map); 1106 return ENOBUFS; 1107 } 1108 1109 #if NVLAN > 0 1110 /* setup h/w VLAN tagging */ 1111 if (vlan_has_tag(m0)) 1112 vtag = NFE_TX_VTAG | vlan_get_tag(m0); 1113 #endif 1114 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1115 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1116 csumflags |= NFE_TX_IP_CSUM; 1117 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1118 csumflags |= NFE_TX_TCP_UDP_CSUM; 1119 } 1120 1121 for (i = 0; i < map->dm_nsegs; i++) { 1122 data = &sc->txq.data[sc->txq.cur]; 1123 1124 if (sc->sc_flags & NFE_40BIT_ADDR) { 1125 desc64 = &sc->txq.desc64[sc->txq.cur]; 1126 #if defined(__LP64__) 1127 desc64->physaddr[0] = 1128 htole32(map->dm_segs[i].ds_addr >> 32); 1129 #endif 1130 desc64->physaddr[1] = 1131 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1132 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1133 desc64->flags = htole16(flags); 1134 desc64->vtag = 0; 1135 } else { 1136 desc32 = &sc->txq.desc32[sc->txq.cur]; 1137 1138 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1139 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1140 desc32->flags = htole16(flags); 1141 } 1142 1143 /* 1144 * Setting of the valid bit in the first descriptor is 1145 * deferred until the whole chain is fully setup. 1146 */ 1147 flags |= NFE_TX_VALID; 1148 1149 sc->txq.queued++; 1150 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1151 } 1152 1153 /* the whole mbuf chain has been setup */ 1154 if (sc->sc_flags & NFE_40BIT_ADDR) { 1155 /* fix last descriptor */ 1156 flags |= NFE_TX_LASTFRAG_V2; 1157 desc64->flags = htole16(flags); 1158 1159 /* Checksum flags and vtag belong to the first fragment only. */ 1160 #if NVLAN > 0 1161 sc->txq.desc64[first].vtag = htole32(vtag); 1162 #endif 1163 sc->txq.desc64[first].flags |= htole16(csumflags); 1164 1165 /* finally, set the valid bit in the first descriptor */ 1166 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1167 } else { 1168 /* fix last descriptor */ 1169 if (sc->sc_flags & NFE_JUMBO_SUP) 1170 flags |= NFE_TX_LASTFRAG_V2; 1171 else 1172 flags |= NFE_TX_LASTFRAG_V1; 1173 desc32->flags = htole16(flags); 1174 1175 /* Checksum flags belong to the first fragment only. */ 1176 sc->txq.desc32[first].flags |= htole16(csumflags); 1177 1178 /* finally, set the valid bit in the first descriptor */ 1179 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1180 } 1181 1182 data->m = m0; 1183 data->active = map; 1184 1185 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1186 BUS_DMASYNC_PREWRITE); 1187 1188 return 0; 1189 } 1190 1191 void 1192 nfe_start(struct ifnet *ifp) 1193 { 1194 struct nfe_softc *sc = ifp->if_softc; 1195 int old = sc->txq.queued; 1196 struct mbuf *m0; 1197 1198 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1199 return; 1200 1201 for (;;) { 1202 IFQ_POLL(&ifp->if_snd, m0); 1203 if (m0 == NULL) 1204 break; 1205 1206 if (nfe_encap(sc, m0) != 0) { 1207 ifp->if_flags |= IFF_OACTIVE; 1208 break; 1209 } 1210 1211 /* packet put in h/w queue, remove from s/w queue */ 1212 IFQ_DEQUEUE(&ifp->if_snd, m0); 1213 1214 bpf_mtap(ifp, m0, BPF_D_OUT); 1215 } 1216 1217 if (sc->txq.queued != old) { 1218 /* packets are queued */ 1219 if (sc->sc_flags & NFE_40BIT_ADDR) 1220 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1221 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1222 else 1223 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1224 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1225 /* kick Tx */ 1226 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1227 1228 /* 1229 * Set a timeout in case the chip goes out to lunch. 1230 */ 1231 ifp->if_timer = 5; 1232 } 1233 } 1234 1235 void 1236 nfe_watchdog(struct ifnet *ifp) 1237 { 1238 struct nfe_softc *sc = ifp->if_softc; 1239 1240 aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1241 1242 ifp->if_flags &= ~IFF_RUNNING; 1243 nfe_init(ifp); 1244 1245 if_statinc(ifp, if_oerrors); 1246 } 1247 1248 int 1249 nfe_init(struct ifnet *ifp) 1250 { 1251 struct nfe_softc *sc = ifp->if_softc; 1252 uint32_t tmp; 1253 int rc = 0, s; 1254 1255 if (ifp->if_flags & IFF_RUNNING) 1256 return 0; 1257 1258 nfe_stop(ifp, 0); 1259 1260 NFE_WRITE(sc, NFE_TX_UNK, 0); 1261 NFE_WRITE(sc, NFE_STATUS, 0); 1262 1263 sc->rxtxctl = NFE_RXTX_BIT2; 1264 if (sc->sc_flags & NFE_40BIT_ADDR) 1265 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1266 else if (sc->sc_flags & NFE_JUMBO_SUP) 1267 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1268 if (sc->sc_flags & NFE_HW_CSUM) 1269 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1270 #if NVLAN > 0 1271 /* 1272 * Although the adapter is capable of stripping VLAN tags from received 1273 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1274 * purpose. This will be done in software by our network stack. 1275 */ 1276 if (sc->sc_flags & NFE_HW_VLAN) 1277 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1278 #endif 1279 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1280 DELAY(10); 1281 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1282 1283 #if NVLAN 1284 if (sc->sc_flags & NFE_HW_VLAN) 1285 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1286 #endif 1287 1288 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1289 1290 /* set MAC address */ 1291 nfe_set_macaddr(sc, sc->sc_enaddr); 1292 1293 /* tell MAC where rings are in memory */ 1294 #ifdef __LP64__ 1295 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1296 #endif 1297 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1298 #ifdef __LP64__ 1299 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1300 #endif 1301 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1302 1303 NFE_WRITE(sc, NFE_RING_SIZE, 1304 (NFE_RX_RING_COUNT - 1) << 16 | 1305 (NFE_TX_RING_COUNT - 1)); 1306 1307 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1308 1309 /* force MAC to wakeup */ 1310 tmp = NFE_READ(sc, NFE_PWR_STATE); 1311 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1312 DELAY(10); 1313 tmp = NFE_READ(sc, NFE_PWR_STATE); 1314 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1315 1316 s = splnet(); 1317 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1318 nfe_intr(sc); /* XXX clear IRQ status registers */ 1319 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1320 splx(s); 1321 1322 #if 1 1323 /* configure interrupts coalescing/mitigation */ 1324 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1325 #else 1326 /* no interrupt mitigation: one interrupt per packet */ 1327 NFE_WRITE(sc, NFE_IMTIMER, 970); 1328 #endif 1329 1330 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1331 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1332 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1333 1334 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1335 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1336 1337 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1338 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_ENABLE); 1339 1340 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1341 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1342 DELAY(10); 1343 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1344 1345 /* set Rx filter */ 1346 nfe_setmulti(sc); 1347 1348 if ((rc = ether_mediachange(ifp)) != 0) 1349 goto out; 1350 1351 nfe_tick(sc); 1352 1353 /* enable Rx */ 1354 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1355 1356 /* enable Tx */ 1357 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1358 1359 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1360 1361 /* enable interrupts */ 1362 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1363 1364 callout_schedule(&sc->sc_tick_ch, hz); 1365 1366 ifp->if_flags |= IFF_RUNNING; 1367 ifp->if_flags &= ~IFF_OACTIVE; 1368 1369 out: 1370 return rc; 1371 } 1372 1373 void 1374 nfe_stop(struct ifnet *ifp, int disable) 1375 { 1376 struct nfe_softc *sc = ifp->if_softc; 1377 1378 callout_stop(&sc->sc_tick_ch); 1379 1380 ifp->if_timer = 0; 1381 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1382 1383 mii_down(&sc->sc_mii); 1384 1385 /* abort Tx */ 1386 NFE_WRITE(sc, NFE_TX_CTL, 0); 1387 1388 /* disable Rx */ 1389 NFE_WRITE(sc, NFE_RX_CTL, 0); 1390 1391 /* disable interrupts */ 1392 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1393 1394 /* reset Tx and Rx rings */ 1395 nfe_reset_tx_ring(sc, &sc->txq); 1396 nfe_reset_rx_ring(sc, &sc->rxq); 1397 } 1398 1399 int 1400 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1401 { 1402 struct nfe_desc32 *desc32; 1403 struct nfe_desc64 *desc64; 1404 struct nfe_rx_data *data; 1405 struct nfe_jbuf *jbuf; 1406 void **desc; 1407 bus_addr_t physaddr; 1408 int i, nsegs, error, descsize; 1409 1410 if (sc->sc_flags & NFE_40BIT_ADDR) { 1411 desc = (void **)&ring->desc64; 1412 descsize = sizeof (struct nfe_desc64); 1413 } else { 1414 desc = (void **)&ring->desc32; 1415 descsize = sizeof (struct nfe_desc32); 1416 } 1417 1418 ring->cur = ring->next = 0; 1419 ring->bufsz = MCLBYTES; 1420 1421 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1422 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1423 if (error != 0) { 1424 aprint_error_dev(sc->sc_dev, 1425 "could not create desc DMA map\n"); 1426 ring->map = NULL; 1427 goto fail; 1428 } 1429 1430 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1431 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1432 if (error != 0) { 1433 aprint_error_dev(sc->sc_dev, 1434 "could not allocate DMA memory\n"); 1435 goto fail; 1436 } 1437 1438 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1439 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1440 if (error != 0) { 1441 aprint_error_dev(sc->sc_dev, 1442 "could not map desc DMA memory\n"); 1443 goto fail; 1444 } 1445 1446 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1447 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1448 if (error != 0) { 1449 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1450 goto fail; 1451 } 1452 1453 memset(*desc, 0, NFE_RX_RING_COUNT * descsize); 1454 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1455 1456 if (sc->sc_flags & NFE_USE_JUMBO) { 1457 ring->bufsz = NFE_JBYTES; 1458 if ((error = nfe_jpool_alloc(sc)) != 0) { 1459 aprint_error_dev(sc->sc_dev, 1460 "could not allocate jumbo frames\n"); 1461 goto fail; 1462 } 1463 } 1464 1465 /* 1466 * Pre-allocate Rx buffers and populate Rx ring. 1467 */ 1468 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1469 data = &sc->rxq.data[i]; 1470 1471 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1472 if (data->m == NULL) { 1473 aprint_error_dev(sc->sc_dev, 1474 "could not allocate rx mbuf\n"); 1475 error = ENOMEM; 1476 goto fail; 1477 } 1478 1479 if (sc->sc_flags & NFE_USE_JUMBO) { 1480 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1481 aprint_error_dev(sc->sc_dev, 1482 "could not allocate jumbo buffer\n"); 1483 goto fail; 1484 } 1485 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1486 sc); 1487 1488 physaddr = jbuf->physaddr; 1489 } else { 1490 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1491 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1492 if (error != 0) { 1493 aprint_error_dev(sc->sc_dev, 1494 "could not create DMA map\n"); 1495 data->map = NULL; 1496 goto fail; 1497 } 1498 MCLGET(data->m, M_DONTWAIT); 1499 if (!(data->m->m_flags & M_EXT)) { 1500 aprint_error_dev(sc->sc_dev, 1501 "could not allocate mbuf cluster\n"); 1502 error = ENOMEM; 1503 goto fail; 1504 } 1505 1506 error = bus_dmamap_load(sc->sc_dmat, data->map, 1507 mtod(data->m, void *), MCLBYTES, NULL, 1508 BUS_DMA_READ | BUS_DMA_NOWAIT); 1509 if (error != 0) { 1510 aprint_error_dev(sc->sc_dev, 1511 "could not load rx buf DMA map"); 1512 goto fail; 1513 } 1514 physaddr = data->map->dm_segs[0].ds_addr; 1515 } 1516 1517 if (sc->sc_flags & NFE_40BIT_ADDR) { 1518 desc64 = &sc->rxq.desc64[i]; 1519 #if defined(__LP64__) 1520 desc64->physaddr[0] = htole32(physaddr >> 32); 1521 #endif 1522 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1523 desc64->length = htole16(sc->rxq.bufsz); 1524 desc64->flags = htole16(NFE_RX_READY); 1525 } else { 1526 desc32 = &sc->rxq.desc32[i]; 1527 desc32->physaddr = htole32(physaddr); 1528 desc32->length = htole16(sc->rxq.bufsz); 1529 desc32->flags = htole16(NFE_RX_READY); 1530 } 1531 } 1532 1533 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1534 BUS_DMASYNC_PREWRITE); 1535 1536 return 0; 1537 1538 fail: nfe_free_rx_ring(sc, ring); 1539 return error; 1540 } 1541 1542 void 1543 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1544 { 1545 int i; 1546 1547 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1548 if (sc->sc_flags & NFE_40BIT_ADDR) { 1549 ring->desc64[i].length = htole16(ring->bufsz); 1550 ring->desc64[i].flags = htole16(NFE_RX_READY); 1551 } else { 1552 ring->desc32[i].length = htole16(ring->bufsz); 1553 ring->desc32[i].flags = htole16(NFE_RX_READY); 1554 } 1555 } 1556 1557 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1558 BUS_DMASYNC_PREWRITE); 1559 1560 ring->cur = ring->next = 0; 1561 } 1562 1563 void 1564 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1565 { 1566 struct nfe_rx_data *data; 1567 void *desc; 1568 int i, descsize; 1569 1570 if (sc->sc_flags & NFE_40BIT_ADDR) { 1571 desc = ring->desc64; 1572 descsize = sizeof (struct nfe_desc64); 1573 } else { 1574 desc = ring->desc32; 1575 descsize = sizeof (struct nfe_desc32); 1576 } 1577 1578 if (desc != NULL) { 1579 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1580 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1581 bus_dmamap_unload(sc->sc_dmat, ring->map); 1582 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1583 NFE_RX_RING_COUNT * descsize); 1584 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1585 } 1586 1587 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1588 data = &ring->data[i]; 1589 1590 if (data->map != NULL) { 1591 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1592 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1593 bus_dmamap_unload(sc->sc_dmat, data->map); 1594 bus_dmamap_destroy(sc->sc_dmat, data->map); 1595 } 1596 if (data->m != NULL) 1597 m_freem(data->m); 1598 } 1599 1600 nfe_jpool_free(sc); 1601 } 1602 1603 struct nfe_jbuf * 1604 nfe_jalloc(struct nfe_softc *sc, int i) 1605 { 1606 struct nfe_jbuf *jbuf; 1607 1608 mutex_enter(&sc->rxq.mtx); 1609 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1610 if (jbuf != NULL) 1611 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1612 mutex_exit(&sc->rxq.mtx); 1613 if (jbuf == NULL) 1614 return NULL; 1615 sc->rxq.jbufmap[i] = 1616 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1617 return jbuf; 1618 } 1619 1620 /* 1621 * This is called automatically by the network stack when the mbuf is freed. 1622 * Caution must be taken that the NIC might be reset by the time the mbuf is 1623 * freed. 1624 */ 1625 void 1626 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1627 { 1628 struct nfe_softc *sc = arg; 1629 struct nfe_jbuf *jbuf; 1630 int i; 1631 1632 /* find the jbuf from the base pointer */ 1633 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1634 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1635 aprint_error_dev(sc->sc_dev, 1636 "request to free a buffer (%p) not managed by us\n", buf); 1637 return; 1638 } 1639 jbuf = &sc->rxq.jbuf[i]; 1640 1641 /* ..and put it back in the free list */ 1642 mutex_enter(&sc->rxq.mtx); 1643 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1644 mutex_exit(&sc->rxq.mtx); 1645 1646 if (m != NULL) 1647 pool_cache_put(mb_cache, m); 1648 } 1649 1650 int 1651 nfe_jpool_alloc(struct nfe_softc *sc) 1652 { 1653 struct nfe_rx_ring *ring = &sc->rxq; 1654 struct nfe_jbuf *jbuf; 1655 bus_addr_t physaddr; 1656 char *buf; 1657 int i, nsegs, error; 1658 1659 /* 1660 * Allocate a big chunk of DMA'able memory. 1661 */ 1662 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1663 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1664 if (error != 0) { 1665 aprint_error_dev(sc->sc_dev, 1666 "could not create jumbo DMA map\n"); 1667 ring->jmap = NULL; 1668 goto fail; 1669 } 1670 1671 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1672 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1673 if (error != 0) { 1674 aprint_error_dev(sc->sc_dev, 1675 "could not allocate jumbo DMA memory\n"); 1676 goto fail; 1677 } 1678 1679 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1680 &ring->jpool, BUS_DMA_NOWAIT); 1681 if (error != 0) { 1682 aprint_error_dev(sc->sc_dev, 1683 "could not map jumbo DMA memory\n"); 1684 goto fail; 1685 } 1686 1687 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1688 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1689 if (error != 0) { 1690 aprint_error_dev(sc->sc_dev, 1691 "could not load jumbo DMA map\n"); 1692 goto fail; 1693 } 1694 1695 /* ..and split it into 9KB chunks */ 1696 SLIST_INIT(&ring->jfreelist); 1697 1698 buf = ring->jpool; 1699 physaddr = ring->jmap->dm_segs[0].ds_addr; 1700 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1701 jbuf = &ring->jbuf[i]; 1702 1703 jbuf->buf = buf; 1704 jbuf->physaddr = physaddr; 1705 1706 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1707 1708 buf += NFE_JBYTES; 1709 physaddr += NFE_JBYTES; 1710 } 1711 1712 return 0; 1713 1714 fail: nfe_jpool_free(sc); 1715 return error; 1716 } 1717 1718 void 1719 nfe_jpool_free(struct nfe_softc *sc) 1720 { 1721 struct nfe_rx_ring *ring = &sc->rxq; 1722 1723 if (ring->jmap != NULL) { 1724 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1725 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1726 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1727 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1728 ring->jmap = NULL; 1729 } 1730 if (ring->jpool != NULL) { 1731 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1732 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1733 ring->jpool = NULL; 1734 } 1735 } 1736 1737 int 1738 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1739 { 1740 int i, nsegs, error; 1741 void **desc; 1742 int descsize; 1743 1744 if (sc->sc_flags & NFE_40BIT_ADDR) { 1745 desc = (void **)&ring->desc64; 1746 descsize = sizeof (struct nfe_desc64); 1747 } else { 1748 desc = (void **)&ring->desc32; 1749 descsize = sizeof (struct nfe_desc32); 1750 } 1751 1752 ring->queued = 0; 1753 ring->cur = ring->next = 0; 1754 1755 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1756 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1757 1758 if (error != 0) { 1759 aprint_error_dev(sc->sc_dev, 1760 "could not create desc DMA map\n"); 1761 ring->map = NULL; 1762 goto fail; 1763 } 1764 1765 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1766 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1767 if (error != 0) { 1768 aprint_error_dev(sc->sc_dev, 1769 "could not allocate DMA memory\n"); 1770 goto fail; 1771 } 1772 1773 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1774 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1775 if (error != 0) { 1776 aprint_error_dev(sc->sc_dev, 1777 "could not map desc DMA memory\n"); 1778 goto fail; 1779 } 1780 1781 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1782 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1783 if (error != 0) { 1784 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1785 goto fail; 1786 } 1787 1788 memset(*desc, 0, NFE_TX_RING_COUNT * descsize); 1789 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1790 1791 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1792 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1793 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1794 &ring->data[i].map); 1795 if (error != 0) { 1796 aprint_error_dev(sc->sc_dev, 1797 "could not create DMA map\n"); 1798 ring->data[i].map = NULL; 1799 goto fail; 1800 } 1801 } 1802 1803 return 0; 1804 1805 fail: nfe_free_tx_ring(sc, ring); 1806 return error; 1807 } 1808 1809 void 1810 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1811 { 1812 struct nfe_tx_data *data; 1813 int i; 1814 1815 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1816 if (sc->sc_flags & NFE_40BIT_ADDR) 1817 ring->desc64[i].flags = 0; 1818 else 1819 ring->desc32[i].flags = 0; 1820 1821 data = &ring->data[i]; 1822 1823 if (data->m != NULL) { 1824 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1825 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1826 bus_dmamap_unload(sc->sc_dmat, data->active); 1827 m_freem(data->m); 1828 data->m = NULL; 1829 } 1830 } 1831 1832 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1833 BUS_DMASYNC_PREWRITE); 1834 1835 ring->queued = 0; 1836 ring->cur = ring->next = 0; 1837 } 1838 1839 void 1840 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1841 { 1842 struct nfe_tx_data *data; 1843 void *desc; 1844 int i, descsize; 1845 1846 if (sc->sc_flags & NFE_40BIT_ADDR) { 1847 desc = ring->desc64; 1848 descsize = sizeof (struct nfe_desc64); 1849 } else { 1850 desc = ring->desc32; 1851 descsize = sizeof (struct nfe_desc32); 1852 } 1853 1854 if (desc != NULL) { 1855 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1856 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1857 bus_dmamap_unload(sc->sc_dmat, ring->map); 1858 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1859 NFE_TX_RING_COUNT * descsize); 1860 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1861 } 1862 1863 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1864 data = &ring->data[i]; 1865 1866 if (data->m != NULL) { 1867 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1868 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1869 bus_dmamap_unload(sc->sc_dmat, data->active); 1870 m_freem(data->m); 1871 } 1872 } 1873 1874 /* ..and now actually destroy the DMA mappings */ 1875 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1876 data = &ring->data[i]; 1877 if (data->map == NULL) 1878 continue; 1879 bus_dmamap_destroy(sc->sc_dmat, data->map); 1880 } 1881 } 1882 1883 void 1884 nfe_setmulti(struct nfe_softc *sc) 1885 { 1886 struct ethercom *ec = &sc->sc_ethercom; 1887 struct ifnet *ifp = &ec->ec_if; 1888 struct ether_multi *enm; 1889 struct ether_multistep step; 1890 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1891 uint32_t filter = NFE_RXFILTER_MAGIC; 1892 int i; 1893 1894 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1895 memset(addr, 0, ETHER_ADDR_LEN); 1896 memset(mask, 0, ETHER_ADDR_LEN); 1897 goto done; 1898 } 1899 1900 memcpy(addr, etherbroadcastaddr, ETHER_ADDR_LEN); 1901 memcpy(mask, etherbroadcastaddr, ETHER_ADDR_LEN); 1902 1903 ETHER_LOCK(ec); 1904 ETHER_FIRST_MULTI(step, ec, enm); 1905 while (enm != NULL) { 1906 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1907 ifp->if_flags |= IFF_ALLMULTI; 1908 memset(addr, 0, ETHER_ADDR_LEN); 1909 memset(mask, 0, ETHER_ADDR_LEN); 1910 ETHER_UNLOCK(ec); 1911 goto done; 1912 } 1913 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1914 addr[i] &= enm->enm_addrlo[i]; 1915 mask[i] &= ~enm->enm_addrlo[i]; 1916 } 1917 ETHER_NEXT_MULTI(step, enm); 1918 } 1919 ETHER_UNLOCK(ec); 1920 for (i = 0; i < ETHER_ADDR_LEN; i++) 1921 mask[i] |= addr[i]; 1922 1923 done: 1924 addr[0] |= 0x01; /* make sure multicast bit is set */ 1925 1926 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1927 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1928 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1929 addr[5] << 8 | addr[4]); 1930 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1931 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1932 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1933 mask[5] << 8 | mask[4]); 1934 1935 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1936 NFE_WRITE(sc, NFE_RXFILTER, filter); 1937 } 1938 1939 void 1940 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1941 { 1942 uint32_t tmp; 1943 1944 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 1945 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1946 addr[0] = (tmp & 0xff); 1947 addr[1] = (tmp >> 8) & 0xff; 1948 addr[2] = (tmp >> 16) & 0xff; 1949 addr[3] = (tmp >> 24) & 0xff; 1950 1951 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1952 addr[4] = (tmp & 0xff); 1953 addr[5] = (tmp >> 8) & 0xff; 1954 1955 } else { 1956 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1957 addr[0] = (tmp >> 8) & 0xff; 1958 addr[1] = (tmp & 0xff); 1959 1960 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1961 addr[2] = (tmp >> 24) & 0xff; 1962 addr[3] = (tmp >> 16) & 0xff; 1963 addr[4] = (tmp >> 8) & 0xff; 1964 addr[5] = (tmp & 0xff); 1965 } 1966 } 1967 1968 void 1969 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1970 { 1971 NFE_WRITE(sc, NFE_MACADDR_LO, 1972 addr[5] << 8 | addr[4]); 1973 NFE_WRITE(sc, NFE_MACADDR_HI, 1974 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1975 } 1976 1977 void 1978 nfe_tick(void *arg) 1979 { 1980 struct nfe_softc *sc = arg; 1981 int s; 1982 1983 s = splnet(); 1984 mii_tick(&sc->sc_mii); 1985 splx(s); 1986 1987 callout_schedule(&sc->sc_tick_ch, hz); 1988 } 1989 1990 void 1991 nfe_poweron(device_t self) 1992 { 1993 struct nfe_softc *sc = device_private(self); 1994 1995 if ((sc->sc_flags & NFE_PWR_MGMT) != 0) { 1996 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 1997 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 1998 DELAY(100); 1999 NFE_WRITE(sc, NFE_MAC_RESET, 0); 2000 DELAY(100); 2001 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 2002 NFE_WRITE(sc, NFE_PWR2_CTL, 2003 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_WAKEUP_MASK); 2004 } 2005 } 2006 2007 bool 2008 nfe_resume(device_t dv, const pmf_qual_t *qual) 2009 { 2010 nfe_poweron(dv); 2011 2012 return true; 2013 } 2014
Indexes created Tue Sep 30 07:10:03 GMT 2025