if_nfe.c revision 1.75
1 /* $NetBSD: if_nfe.c,v 1.75 2020/03/01 15:43:58 thorpej Exp $ */ 2 /* $OpenBSD: if_nfe.c,v 1.77 2008/02/05 16:52:50 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006, 2007 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.75 2020/03/01 15:43:58 thorpej Exp $"); 25 26 #include "opt_inet.h" 27 #include "vlan.h" 28 29 #include <sys/param.h> 30 #include <sys/endian.h> 31 #include <sys/systm.h> 32 #include <sys/types.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/mutex.h> 36 #include <sys/queue.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/callout.h> 40 #include <sys/socket.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 #include <net/if_arp.h> 49 50 #ifdef INET 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #if NVLAN > 0 59 #include <net/if_types.h> 60 #endif 61 62 #include <net/bpf.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_nfereg.h> 72 #include <dev/pci/if_nfevar.h> 73 74 static int nfe_ifflags_cb(struct ethercom *); 75 76 int nfe_match(device_t, cfdata_t, void *); 77 void nfe_attach(device_t, device_t, void *); 78 int nfe_detach(device_t, int); 79 void nfe_power(int, void *); 80 void nfe_miibus_statchg(struct ifnet *); 81 int nfe_miibus_readreg(device_t, int, int, uint16_t *); 82 int nfe_miibus_writereg(device_t, int, int, uint16_t); 83 int nfe_intr(void *); 84 int nfe_ioctl(struct ifnet *, u_long, void *); 85 void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 86 void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 87 void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 88 void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 89 void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 90 void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 91 void nfe_rxeof(struct nfe_softc *); 92 void nfe_txeof(struct nfe_softc *); 93 int nfe_encap(struct nfe_softc *, struct mbuf *); 94 void nfe_start(struct ifnet *); 95 void nfe_watchdog(struct ifnet *); 96 int nfe_init(struct ifnet *); 97 void nfe_stop(struct ifnet *, int); 98 struct nfe_jbuf *nfe_jalloc(struct nfe_softc *, int); 99 void nfe_jfree(struct mbuf *, void *, size_t, void *); 100 int nfe_jpool_alloc(struct nfe_softc *); 101 void nfe_jpool_free(struct nfe_softc *); 102 int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 103 void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 104 void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 105 int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 106 void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 107 void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 108 void nfe_setmulti(struct nfe_softc *); 109 void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 110 void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 111 void nfe_tick(void *); 112 void nfe_poweron(device_t); 113 bool nfe_resume(device_t, const pmf_qual_t *); 114 115 CFATTACH_DECL_NEW(nfe, sizeof(struct nfe_softc), 116 nfe_match, nfe_attach, nfe_detach, NULL); 117 118 /* #define NFE_NO_JUMBO */ 119 120 #ifdef NFE_DEBUG 121 int nfedebug = 0; 122 #define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 123 #define DPRINTFN(n, x) do { if (nfedebug >= (n)) printf x; } while (0) 124 #else 125 #define DPRINTF(x) 126 #define DPRINTFN(n, x) 127 #endif 128 129 /* deal with naming differences */ 130 131 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 \ 132 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 133 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 \ 134 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 135 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 \ 136 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 137 138 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 \ 139 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 140 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 \ 141 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 142 143 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 \ 144 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 145 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 \ 146 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 147 148 const struct nfe_product { 149 pci_vendor_id_t vendor; 150 pci_product_id_t product; 151 } nfe_devices[] = { 152 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 153 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 155 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 157 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 159 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 161 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 163 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 165 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 167 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 169 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 171 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 172 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 173 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 174 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 175 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 176 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 177 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 178 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 179 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 180 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 181 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 182 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 }, 183 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1 }, 184 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2 }, 185 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3 }, 186 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4 }, 187 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1 }, 188 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2 }, 189 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3 }, 190 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4 } 191 }; 192 193 int 194 nfe_match(device_t dev, cfdata_t match, void *aux) 195 { 196 struct pci_attach_args *pa = aux; 197 const struct nfe_product *np; 198 int i; 199 200 for (i = 0; i < __arraycount(nfe_devices); i++) { 201 np = &nfe_devices[i]; 202 if (PCI_VENDOR(pa->pa_id) == np->vendor && 203 PCI_PRODUCT(pa->pa_id) == np->product) 204 return 1; 205 } 206 return 0; 207 } 208 209 void 210 nfe_attach(device_t parent, device_t self, void *aux) 211 { 212 struct nfe_softc *sc = device_private(self); 213 struct pci_attach_args *pa = aux; 214 pci_chipset_tag_t pc = pa->pa_pc; 215 pci_intr_handle_t ih; 216 const char *intrstr; 217 struct ifnet *ifp; 218 struct mii_data * const mii = &sc->sc_mii; 219 pcireg_t memtype, csr; 220 int mii_flags = 0; 221 char intrbuf[PCI_INTRSTR_LEN]; 222 223 sc->sc_dev = self; 224 sc->sc_pc = pa->pa_pc; 225 pci_aprint_devinfo(pa, NULL); 226 227 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 228 switch (memtype) { 229 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 230 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 231 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 232 &sc->sc_memh, NULL, &sc->sc_mems) == 0) 233 break; 234 /* FALLTHROUGH */ 235 default: 236 aprint_error_dev(self, "could not map mem space\n"); 237 return; 238 } 239 240 if (pci_intr_map(pa, &ih) != 0) { 241 aprint_error_dev(self, "could not map interrupt\n"); 242 goto fail; 243 } 244 245 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 246 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, nfe_intr, sc, 247 device_xname(self)); 248 if (sc->sc_ih == NULL) { 249 aprint_error_dev(self, "could not establish interrupt"); 250 if (intrstr != NULL) 251 aprint_error(" at %s", intrstr); 252 aprint_error("\n"); 253 goto fail; 254 } 255 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 256 257 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 258 csr |= PCI_COMMAND_MASTER_ENABLE; 259 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 260 261 sc->sc_flags = 0; 262 263 switch (PCI_PRODUCT(pa->pa_id)) { 264 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 265 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 266 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 267 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 268 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 269 break; 270 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 271 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 272 sc->sc_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT; 273 break; 274 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 275 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 276 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 277 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 278 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 279 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 280 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 281 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 282 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 283 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 284 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 285 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 286 sc->sc_flags |= NFE_40BIT_ADDR | NFE_CORRECT_MACADDR | 287 NFE_PWR_MGMT; 288 break; 289 case PCI_PRODUCT_NVIDIA_MCP77_LAN1: 290 case PCI_PRODUCT_NVIDIA_MCP77_LAN2: 291 case PCI_PRODUCT_NVIDIA_MCP77_LAN3: 292 case PCI_PRODUCT_NVIDIA_MCP77_LAN4: 293 sc->sc_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | 294 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 295 break; 296 case PCI_PRODUCT_NVIDIA_MCP79_LAN1: 297 case PCI_PRODUCT_NVIDIA_MCP79_LAN2: 298 case PCI_PRODUCT_NVIDIA_MCP79_LAN3: 299 case PCI_PRODUCT_NVIDIA_MCP79_LAN4: 300 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 301 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 302 break; 303 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 304 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 305 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 306 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 307 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 308 break; 309 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 310 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 311 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 312 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 313 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 314 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 315 mii_flags = MIIF_DOPAUSE; 316 break; 317 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 318 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 319 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 320 NFE_HW_VLAN | NFE_PWR_MGMT; 321 break; 322 } 323 324 if (pci_dma64_available(pa) && (sc->sc_flags & NFE_40BIT_ADDR) != 0) { 325 if (bus_dmatag_subregion(pa->pa_dmat64, 326 0, 327 (1ULL << 40), 328 &sc->sc_dmat, 329 BUS_DMA_WAITOK) != 0) { 330 aprint_error_dev(self, 331 "unable to create 40-bit DMA tag\n"); 332 sc->sc_dmat = pa->pa_dmat64; 333 } else 334 sc->sc_dmat_needs_free = true; 335 } else 336 sc->sc_dmat = pa->pa_dmat; 337 338 nfe_poweron(self); 339 340 #ifndef NFE_NO_JUMBO 341 /* enable jumbo frames for adapters that support it */ 342 if (sc->sc_flags & NFE_JUMBO_SUP) 343 sc->sc_flags |= NFE_USE_JUMBO; 344 #endif 345 346 /* Check for reversed ethernet address */ 347 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 348 sc->sc_flags |= NFE_CORRECT_MACADDR; 349 350 nfe_get_macaddr(sc, sc->sc_enaddr); 351 aprint_normal_dev(self, "Ethernet address %s\n", 352 ether_sprintf(sc->sc_enaddr)); 353 354 /* 355 * Allocate Tx and Rx rings. 356 */ 357 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 358 aprint_error_dev(self, "could not allocate Tx ring\n"); 359 goto fail; 360 } 361 362 mutex_init(&sc->rxq.mtx, MUTEX_DEFAULT, IPL_NET); 363 364 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 365 aprint_error_dev(self, "could not allocate Rx ring\n"); 366 nfe_free_tx_ring(sc, &sc->txq); 367 goto fail; 368 } 369 370 ifp = &sc->sc_ethercom.ec_if; 371 ifp->if_softc = sc; 372 ifp->if_mtu = ETHERMTU; 373 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 374 ifp->if_ioctl = nfe_ioctl; 375 ifp->if_start = nfe_start; 376 ifp->if_stop = nfe_stop; 377 ifp->if_watchdog = nfe_watchdog; 378 ifp->if_init = nfe_init; 379 ifp->if_baudrate = IF_Gbps(1); 380 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 381 IFQ_SET_READY(&ifp->if_snd); 382 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 383 384 if (sc->sc_flags & NFE_USE_JUMBO) 385 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 386 387 #if NVLAN > 0 388 if (sc->sc_flags & NFE_HW_VLAN) { 389 sc->sc_ethercom.ec_capabilities |= 390 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 391 sc->sc_ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 392 } 393 #endif 394 if (sc->sc_flags & NFE_HW_CSUM) { 395 ifp->if_capabilities |= 396 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 397 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 398 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 399 } 400 401 mii->mii_ifp = ifp; 402 mii->mii_readreg = nfe_miibus_readreg; 403 mii->mii_writereg = nfe_miibus_writereg; 404 mii->mii_statchg = nfe_miibus_statchg; 405 406 sc->sc_ethercom.ec_mii = mii; 407 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 408 409 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 0, mii_flags); 410 411 if (LIST_FIRST(&mii->mii_phys) == NULL) { 412 aprint_error_dev(self, "no PHY found!\n"); 413 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 414 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 415 } else 416 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 417 418 if_attach(ifp); 419 if_deferred_start_init(ifp, NULL); 420 ether_ifattach(ifp, sc->sc_enaddr); 421 ether_set_ifflags_cb(&sc->sc_ethercom, nfe_ifflags_cb); 422 423 callout_init(&sc->sc_tick_ch, 0); 424 callout_setfunc(&sc->sc_tick_ch, nfe_tick, sc); 425 426 if (pmf_device_register(self, NULL, nfe_resume)) 427 pmf_class_network_register(self, ifp); 428 else 429 aprint_error_dev(self, "couldn't establish power handler\n"); 430 431 return; 432 433 fail: 434 if (sc->sc_ih != NULL) { 435 pci_intr_disestablish(pc, sc->sc_ih); 436 sc->sc_ih = NULL; 437 } 438 if (sc->sc_mems != 0) { 439 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 440 sc->sc_mems = 0; 441 } 442 } 443 444 int 445 nfe_detach(device_t self, int flags) 446 { 447 struct nfe_softc *sc = device_private(self); 448 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 449 int s; 450 451 s = splnet(); 452 453 nfe_stop(ifp, 1); 454 455 pmf_device_deregister(self); 456 callout_destroy(&sc->sc_tick_ch); 457 ether_ifdetach(ifp); 458 if_detach(ifp); 459 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 460 ifmedia_fini(&sc->sc_mii.mii_media); 461 462 nfe_free_rx_ring(sc, &sc->rxq); 463 mutex_destroy(&sc->rxq.mtx); 464 nfe_free_tx_ring(sc, &sc->txq); 465 466 if (sc->sc_dmat_needs_free) 467 bus_dmatag_destroy(sc->sc_dmat); 468 469 if (sc->sc_ih != NULL) { 470 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 471 sc->sc_ih = NULL; 472 } 473 474 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 475 nfe_set_macaddr(sc, sc->sc_enaddr); 476 } else { 477 NFE_WRITE(sc, NFE_MACADDR_LO, 478 sc->sc_enaddr[0] << 8 | sc->sc_enaddr[1]); 479 NFE_WRITE(sc, NFE_MACADDR_HI, 480 sc->sc_enaddr[2] << 24 | sc->sc_enaddr[3] << 16 | 481 sc->sc_enaddr[4] << 8 | sc->sc_enaddr[5]); 482 } 483 484 if (sc->sc_mems != 0) { 485 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 486 sc->sc_mems = 0; 487 } 488 489 splx(s); 490 491 return 0; 492 } 493 494 void 495 nfe_miibus_statchg(struct ifnet *ifp) 496 { 497 struct nfe_softc *sc = ifp->if_softc; 498 struct mii_data *mii = &sc->sc_mii; 499 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 500 501 phy = NFE_READ(sc, NFE_PHY_IFACE); 502 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 503 504 seed = NFE_READ(sc, NFE_RNDSEED); 505 seed &= ~NFE_SEED_MASK; 506 507 if ((mii->mii_media_active & IFM_HDX) != 0) { 508 phy |= NFE_PHY_HDX; /* half-duplex */ 509 misc |= NFE_MISC1_HDX; 510 } 511 512 switch (IFM_SUBTYPE(mii->mii_media_active)) { 513 case IFM_1000_T: /* full-duplex only */ 514 link |= NFE_MEDIA_1000T; 515 seed |= NFE_SEED_1000T; 516 phy |= NFE_PHY_1000T; 517 break; 518 case IFM_100_TX: 519 link |= NFE_MEDIA_100TX; 520 seed |= NFE_SEED_100TX; 521 phy |= NFE_PHY_100TX; 522 break; 523 case IFM_10_T: 524 link |= NFE_MEDIA_10T; 525 seed |= NFE_SEED_10T; 526 break; 527 } 528 529 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 530 531 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 532 NFE_WRITE(sc, NFE_MISC1, misc); 533 NFE_WRITE(sc, NFE_LINKSPEED, link); 534 } 535 536 int 537 nfe_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 538 { 539 struct nfe_softc *sc = device_private(dev); 540 uint32_t data; 541 int ntries; 542 543 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 544 545 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 546 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 547 DELAY(100); 548 } 549 550 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 551 552 for (ntries = 0; ntries < 1000; ntries++) { 553 DELAY(100); 554 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 555 break; 556 } 557 if (ntries == 1000) { 558 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 559 device_xname(sc->sc_dev))); 560 return ETIMEDOUT; 561 } 562 563 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 564 DPRINTFN(2, ("%s: could not read PHY\n", 565 device_xname(sc->sc_dev))); 566 return -1; 567 } 568 569 data = NFE_READ(sc, NFE_PHY_DATA); 570 if (data != 0xffffffff && data != 0) 571 sc->mii_phyaddr = phy; 572 573 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x data 0x%x\n", 574 device_xname(sc->sc_dev), phy, reg, data)); 575 576 *val = data & 0x0000ffff; 577 return 0; 578 } 579 580 int 581 nfe_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 582 { 583 struct nfe_softc *sc = device_private(dev); 584 uint32_t ctl; 585 int ntries; 586 587 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 588 589 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 590 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 591 DELAY(100); 592 } 593 594 NFE_WRITE(sc, NFE_PHY_DATA, val); 595 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 596 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 597 598 for (ntries = 0; ntries < 1000; ntries++) { 599 DELAY(100); 600 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 601 break; 602 } 603 if (ntries == 1000) { 604 #ifdef NFE_DEBUG 605 if (nfedebug >= 2) 606 printf("could not write to PHY\n"); 607 #endif 608 return ETIMEDOUT; 609 } 610 return 0; 611 } 612 613 int 614 nfe_intr(void *arg) 615 { 616 struct nfe_softc *sc = arg; 617 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 618 uint32_t r; 619 int handled; 620 621 if ((ifp->if_flags & IFF_UP) == 0) 622 return 0; 623 624 handled = 0; 625 626 for (;;) { 627 r = NFE_READ(sc, NFE_IRQ_STATUS); 628 if ((r & NFE_IRQ_WANTED) == 0) 629 break; 630 631 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 632 handled = 1; 633 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 634 635 if ((r & (NFE_IRQ_RXERR |NFE_IRQ_RX_NOBUF |NFE_IRQ_RX)) != 0) { 636 /* check Rx ring */ 637 nfe_rxeof(sc); 638 } 639 if ((r & (NFE_IRQ_TXERR|NFE_IRQ_TXERR2|NFE_IRQ_TX_DONE)) != 0) { 640 /* check Tx ring */ 641 nfe_txeof(sc); 642 } 643 if ((r & NFE_IRQ_LINK) != 0) { 644 NFE_READ(sc, NFE_PHY_STATUS); 645 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 646 DPRINTF(("%s: link state changed\n", 647 device_xname(sc->sc_dev))); 648 } 649 } 650 651 if (handled) 652 if_schedule_deferred_start(ifp); 653 654 return handled; 655 } 656 657 static int 658 nfe_ifflags_cb(struct ethercom *ec) 659 { 660 struct ifnet *ifp = &ec->ec_if; 661 struct nfe_softc *sc = ifp->if_softc; 662 u_short change = ifp->if_flags ^ sc->sc_if_flags; 663 664 /* 665 * If only the PROMISC flag changes, then 666 * don't do a full re-init of the chip, just update 667 * the Rx filter. 668 */ 669 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 670 return ENETRESET; 671 else if ((change & IFF_PROMISC) != 0) 672 nfe_setmulti(sc); 673 674 return 0; 675 } 676 677 int 678 nfe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 679 { 680 struct nfe_softc *sc = ifp->if_softc; 681 struct ifaddr *ifa = (struct ifaddr *)data; 682 int s, error = 0; 683 684 s = splnet(); 685 686 switch (cmd) { 687 case SIOCINITIFADDR: 688 ifp->if_flags |= IFF_UP; 689 nfe_init(ifp); 690 switch (ifa->ifa_addr->sa_family) { 691 #ifdef INET 692 case AF_INET: 693 arp_ifinit(ifp, ifa); 694 break; 695 #endif 696 default: 697 break; 698 } 699 break; 700 default: 701 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 702 break; 703 704 error = 0; 705 706 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 707 ; 708 else if (ifp->if_flags & IFF_RUNNING) 709 nfe_setmulti(sc); 710 break; 711 } 712 sc->sc_if_flags = ifp->if_flags; 713 714 splx(s); 715 716 return error; 717 } 718 719 void 720 nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 721 { 722 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 723 (char *)desc32 - (char *)sc->txq.desc32, 724 sizeof (struct nfe_desc32), ops); 725 } 726 727 void 728 nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 729 { 730 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 731 (char *)desc64 - (char *)sc->txq.desc64, 732 sizeof (struct nfe_desc64), ops); 733 } 734 735 void 736 nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 737 { 738 if (end > start) { 739 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 740 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 741 (char *)&sc->txq.desc32[end] - 742 (char *)&sc->txq.desc32[start], ops); 743 return; 744 } 745 /* sync from 'start' to end of ring */ 746 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 747 (char *)&sc->txq.desc32[start] - (char *)sc->txq.desc32, 748 (char *)&sc->txq.desc32[NFE_TX_RING_COUNT] - 749 (char *)&sc->txq.desc32[start], ops); 750 751 /* sync from start of ring to 'end' */ 752 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 753 (char *)&sc->txq.desc32[end] - (char *)sc->txq.desc32, ops); 754 } 755 756 void 757 nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 758 { 759 if (end > start) { 760 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 761 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 762 (char *)&sc->txq.desc64[end] - 763 (char *)&sc->txq.desc64[start], ops); 764 return; 765 } 766 /* sync from 'start' to end of ring */ 767 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 768 (char *)&sc->txq.desc64[start] - (char *)sc->txq.desc64, 769 (char *)&sc->txq.desc64[NFE_TX_RING_COUNT] - 770 (char *)&sc->txq.desc64[start], ops); 771 772 /* sync from start of ring to 'end' */ 773 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 774 (char *)&sc->txq.desc64[end] - (char *)sc->txq.desc64, ops); 775 } 776 777 void 778 nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 779 { 780 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 781 (char *)desc32 - (char *)sc->rxq.desc32, 782 sizeof (struct nfe_desc32), ops); 783 } 784 785 void 786 nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 787 { 788 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 789 (char *)desc64 - (char *)sc->rxq.desc64, 790 sizeof (struct nfe_desc64), ops); 791 } 792 793 void 794 nfe_rxeof(struct nfe_softc *sc) 795 { 796 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 797 struct nfe_desc32 *desc32; 798 struct nfe_desc64 *desc64; 799 struct nfe_rx_data *data; 800 struct nfe_jbuf *jbuf; 801 struct mbuf *m, *mnew; 802 bus_addr_t physaddr; 803 uint16_t flags; 804 int error, len, i; 805 806 desc32 = NULL; 807 desc64 = NULL; 808 for (i = sc->rxq.cur;; i = NFE_RX_NEXTDESC(i)) { 809 data = &sc->rxq.data[i]; 810 811 if (sc->sc_flags & NFE_40BIT_ADDR) { 812 desc64 = &sc->rxq.desc64[i]; 813 nfe_rxdesc64_sync(sc, desc64, 814 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 815 816 flags = le16toh(desc64->flags); 817 len = le16toh(desc64->length) & 0x3fff; 818 } else { 819 desc32 = &sc->rxq.desc32[i]; 820 nfe_rxdesc32_sync(sc, desc32, 821 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 822 823 flags = le16toh(desc32->flags); 824 len = le16toh(desc32->length) & 0x3fff; 825 } 826 827 if ((flags & NFE_RX_READY) != 0) 828 break; 829 830 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 831 if ((flags & NFE_RX_VALID_V1) == 0) 832 goto skip; 833 834 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 835 flags &= ~NFE_RX_ERROR; 836 len--; /* fix buffer length */ 837 } 838 } else { 839 if ((flags & NFE_RX_VALID_V2) == 0) 840 goto skip; 841 842 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 843 flags &= ~NFE_RX_ERROR; 844 len--; /* fix buffer length */ 845 } 846 } 847 848 if (flags & NFE_RX_ERROR) { 849 if_statinc(ifp, if_ierrors); 850 goto skip; 851 } 852 853 /* 854 * Try to allocate a new mbuf for this ring element and load 855 * it before processing the current mbuf. If the ring element 856 * cannot be loaded, drop the received packet and reuse the 857 * old mbuf. In the unlikely case that the old mbuf can't be 858 * reloaded either, explicitly panic. 859 */ 860 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 861 if (mnew == NULL) { 862 if_statinc(ifp, if_ierrors); 863 goto skip; 864 } 865 866 if (sc->sc_flags & NFE_USE_JUMBO) { 867 physaddr = 868 sc->rxq.jbuf[sc->rxq.jbufmap[i]].physaddr; 869 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 870 if (len > MCLBYTES) { 871 m_freem(mnew); 872 if_statinc(ifp, if_ierrors); 873 goto skip1; 874 } 875 MCLGET(mnew, M_DONTWAIT); 876 if ((mnew->m_flags & M_EXT) == 0) { 877 m_freem(mnew); 878 if_statinc(ifp, if_ierrors); 879 goto skip1; 880 } 881 882 (void)memcpy(mtod(mnew, void *), 883 mtod(data->m, const void *), len); 884 m = mnew; 885 goto mbufcopied; 886 } else { 887 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 888 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 889 mtod(data->m, char *) - (char *)sc->rxq.jpool, 890 NFE_JBYTES, BUS_DMASYNC_POSTREAD); 891 892 physaddr = jbuf->physaddr; 893 } 894 } else { 895 MCLGET(mnew, M_DONTWAIT); 896 if ((mnew->m_flags & M_EXT) == 0) { 897 m_freem(mnew); 898 if_statinc(ifp, if_ierrors); 899 goto skip; 900 } 901 902 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 903 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 904 bus_dmamap_unload(sc->sc_dmat, data->map); 905 906 error = bus_dmamap_load(sc->sc_dmat, data->map, 907 mtod(mnew, void *), MCLBYTES, NULL, 908 BUS_DMA_READ | BUS_DMA_NOWAIT); 909 if (error != 0) { 910 m_freem(mnew); 911 912 /* try to reload the old mbuf */ 913 error = bus_dmamap_load(sc->sc_dmat, data->map, 914 mtod(data->m, void *), MCLBYTES, NULL, 915 BUS_DMA_READ | BUS_DMA_NOWAIT); 916 if (error != 0) { 917 /* very unlikely that it will fail.. */ 918 panic("%s: could not load old rx mbuf", 919 device_xname(sc->sc_dev)); 920 } 921 if_statinc(ifp, if_ierrors); 922 goto skip; 923 } 924 physaddr = data->map->dm_segs[0].ds_addr; 925 } 926 927 /* 928 * New mbuf successfully loaded, update Rx ring and continue 929 * processing. 930 */ 931 m = data->m; 932 data->m = mnew; 933 934 mbufcopied: 935 /* finalize mbuf */ 936 m->m_pkthdr.len = m->m_len = len; 937 m_set_rcvif(m, ifp); 938 939 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 940 /* 941 * XXX 942 * no way to check M_CSUM_IPv4_BAD or non-IPv4 packets? 943 */ 944 if (flags & NFE_RX_IP_CSUMOK) { 945 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 946 DPRINTFN(3, ("%s: ip4csum-rx ok\n", 947 device_xname(sc->sc_dev))); 948 } 949 /* 950 * XXX 951 * no way to check M_CSUM_TCP_UDP_BAD or 952 * other protocols? 953 */ 954 if (flags & NFE_RX_UDP_CSUMOK) { 955 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 956 DPRINTFN(3, ("%s: udp4csum-rx ok\n", 957 device_xname(sc->sc_dev))); 958 } else if (flags & NFE_RX_TCP_CSUMOK) { 959 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 960 DPRINTFN(3, ("%s: tcp4csum-rx ok\n", 961 device_xname(sc->sc_dev))); 962 } 963 } 964 if_percpuq_enqueue(ifp->if_percpuq, m); 965 966 skip1: 967 /* update mapping address in h/w descriptor */ 968 if (sc->sc_flags & NFE_40BIT_ADDR) { 969 desc64->physaddr[0] = 970 htole32(((uint64_t)physaddr) >> 32); 971 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 972 } else { 973 desc32->physaddr = htole32(physaddr); 974 } 975 976 skip: 977 if (sc->sc_flags & NFE_40BIT_ADDR) { 978 desc64->length = htole16(sc->rxq.bufsz); 979 desc64->flags = htole16(NFE_RX_READY); 980 981 nfe_rxdesc64_sync(sc, desc64, 982 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 983 } else { 984 desc32->length = htole16(sc->rxq.bufsz); 985 desc32->flags = htole16(NFE_RX_READY); 986 987 nfe_rxdesc32_sync(sc, desc32, 988 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 989 } 990 } 991 /* update current RX pointer */ 992 sc->rxq.cur = i; 993 } 994 995 void 996 nfe_txeof(struct nfe_softc *sc) 997 { 998 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 999 struct nfe_desc32 *desc32; 1000 struct nfe_desc64 *desc64; 1001 struct nfe_tx_data *data = NULL; 1002 int i; 1003 uint16_t flags; 1004 char buf[128]; 1005 1006 for (i = sc->txq.next; 1007 sc->txq.queued > 0; 1008 i = NFE_TX_NEXTDESC(i), sc->txq.queued--) { 1009 if (sc->sc_flags & NFE_40BIT_ADDR) { 1010 desc64 = &sc->txq.desc64[i]; 1011 nfe_txdesc64_sync(sc, desc64, 1012 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1013 1014 flags = le16toh(desc64->flags); 1015 } else { 1016 desc32 = &sc->txq.desc32[i]; 1017 nfe_txdesc32_sync(sc, desc32, 1018 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1019 1020 flags = le16toh(desc32->flags); 1021 } 1022 1023 if ((flags & NFE_TX_VALID) != 0) 1024 break; 1025 1026 data = &sc->txq.data[i]; 1027 1028 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 1029 if ((flags & NFE_TX_LASTFRAG_V1) == 0 && 1030 data->m == NULL) 1031 continue; 1032 1033 if ((flags & NFE_TX_ERROR_V1) != 0) { 1034 snprintb(buf, sizeof(buf), NFE_V1_TXERR, flags); 1035 aprint_error_dev(sc->sc_dev, "tx v1 error %s\n", 1036 buf); 1037 if_statinc(ifp, if_oerrors); 1038 } else 1039 if_statinc(ifp, if_opackets); 1040 } else { 1041 if ((flags & NFE_TX_LASTFRAG_V2) == 0 && 1042 data->m == NULL) 1043 continue; 1044 1045 if ((flags & NFE_TX_ERROR_V2) != 0) { 1046 snprintb(buf, sizeof(buf), NFE_V2_TXERR, flags); 1047 aprint_error_dev(sc->sc_dev, "tx v2 error %s\n", 1048 buf); 1049 if_statinc(ifp, if_oerrors); 1050 } else 1051 if_statinc(ifp, if_opackets); 1052 } 1053 1054 if (data->m == NULL) { /* should not get there */ 1055 aprint_error_dev(sc->sc_dev, 1056 "last fragment bit w/o associated mbuf!\n"); 1057 continue; 1058 } 1059 1060 /* last fragment of the mbuf chain transmitted */ 1061 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1062 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1063 bus_dmamap_unload(sc->sc_dmat, data->active); 1064 m_freem(data->m); 1065 data->m = NULL; 1066 } 1067 1068 sc->txq.next = i; 1069 1070 if (sc->txq.queued < NFE_TX_RING_COUNT) { 1071 /* at least one slot freed */ 1072 ifp->if_flags &= ~IFF_OACTIVE; 1073 } 1074 1075 if (sc->txq.queued == 0) { 1076 /* all queued packets are sent */ 1077 ifp->if_timer = 0; 1078 } 1079 } 1080 1081 int 1082 nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 1083 { 1084 struct nfe_desc32 *desc32; 1085 struct nfe_desc64 *desc64; 1086 struct nfe_tx_data *data; 1087 bus_dmamap_t map; 1088 uint16_t flags, csumflags; 1089 #if NVLAN > 0 1090 uint32_t vtag = 0; 1091 #endif 1092 int error, i, first; 1093 1094 desc32 = NULL; 1095 desc64 = NULL; 1096 data = NULL; 1097 1098 flags = 0; 1099 csumflags = 0; 1100 first = sc->txq.cur; 1101 1102 map = sc->txq.data[first].map; 1103 1104 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 1105 if (error != 0) { 1106 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1107 error); 1108 return error; 1109 } 1110 1111 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 1112 bus_dmamap_unload(sc->sc_dmat, map); 1113 return ENOBUFS; 1114 } 1115 1116 #if NVLAN > 0 1117 /* setup h/w VLAN tagging */ 1118 if (vlan_has_tag(m0)) 1119 vtag = NFE_TX_VTAG | vlan_get_tag(m0); 1120 #endif 1121 if ((sc->sc_flags & NFE_HW_CSUM) != 0) { 1122 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 1123 csumflags |= NFE_TX_IP_CSUM; 1124 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1125 csumflags |= NFE_TX_TCP_UDP_CSUM; 1126 } 1127 1128 for (i = 0; i < map->dm_nsegs; i++) { 1129 data = &sc->txq.data[sc->txq.cur]; 1130 1131 if (sc->sc_flags & NFE_40BIT_ADDR) { 1132 desc64 = &sc->txq.desc64[sc->txq.cur]; 1133 desc64->physaddr[0] = 1134 htole32(((uint64_t)map->dm_segs[i].ds_addr) >> 32); 1135 desc64->physaddr[1] = 1136 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 1137 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 1138 desc64->flags = htole16(flags); 1139 desc64->vtag = 0; 1140 } else { 1141 desc32 = &sc->txq.desc32[sc->txq.cur]; 1142 1143 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 1144 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 1145 desc32->flags = htole16(flags); 1146 } 1147 1148 /* 1149 * Setting of the valid bit in the first descriptor is 1150 * deferred until the whole chain is fully setup. 1151 */ 1152 flags |= NFE_TX_VALID; 1153 1154 sc->txq.queued++; 1155 sc->txq.cur = NFE_TX_NEXTDESC(sc->txq.cur); 1156 } 1157 1158 /* the whole mbuf chain has been setup */ 1159 if (sc->sc_flags & NFE_40BIT_ADDR) { 1160 /* fix last descriptor */ 1161 flags |= NFE_TX_LASTFRAG_V2; 1162 desc64->flags = htole16(flags); 1163 1164 /* Checksum flags and vtag belong to the first fragment only. */ 1165 #if NVLAN > 0 1166 sc->txq.desc64[first].vtag = htole32(vtag); 1167 #endif 1168 sc->txq.desc64[first].flags |= htole16(csumflags); 1169 1170 /* finally, set the valid bit in the first descriptor */ 1171 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 1172 } else { 1173 /* fix last descriptor */ 1174 if (sc->sc_flags & NFE_JUMBO_SUP) 1175 flags |= NFE_TX_LASTFRAG_V2; 1176 else 1177 flags |= NFE_TX_LASTFRAG_V1; 1178 desc32->flags = htole16(flags); 1179 1180 /* Checksum flags belong to the first fragment only. */ 1181 sc->txq.desc32[first].flags |= htole16(csumflags); 1182 1183 /* finally, set the valid bit in the first descriptor */ 1184 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 1185 } 1186 1187 data->m = m0; 1188 data->active = map; 1189 1190 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1191 BUS_DMASYNC_PREWRITE); 1192 1193 return 0; 1194 } 1195 1196 void 1197 nfe_start(struct ifnet *ifp) 1198 { 1199 struct nfe_softc *sc = ifp->if_softc; 1200 int old = sc->txq.queued; 1201 struct mbuf *m0; 1202 1203 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1204 return; 1205 1206 for (;;) { 1207 IFQ_POLL(&ifp->if_snd, m0); 1208 if (m0 == NULL) 1209 break; 1210 1211 if (nfe_encap(sc, m0) != 0) { 1212 ifp->if_flags |= IFF_OACTIVE; 1213 break; 1214 } 1215 1216 /* packet put in h/w queue, remove from s/w queue */ 1217 IFQ_DEQUEUE(&ifp->if_snd, m0); 1218 1219 bpf_mtap(ifp, m0, BPF_D_OUT); 1220 } 1221 1222 if (sc->txq.queued != old) { 1223 /* packets are queued */ 1224 if (sc->sc_flags & NFE_40BIT_ADDR) 1225 nfe_txdesc64_rsync(sc, old, sc->txq.cur, 1226 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1227 else 1228 nfe_txdesc32_rsync(sc, old, sc->txq.cur, 1229 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1230 /* kick Tx */ 1231 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1232 1233 /* 1234 * Set a timeout in case the chip goes out to lunch. 1235 */ 1236 ifp->if_timer = 5; 1237 } 1238 } 1239 1240 void 1241 nfe_watchdog(struct ifnet *ifp) 1242 { 1243 struct nfe_softc *sc = ifp->if_softc; 1244 1245 aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1246 1247 ifp->if_flags &= ~IFF_RUNNING; 1248 nfe_init(ifp); 1249 1250 if_statinc(ifp, if_oerrors); 1251 } 1252 1253 int 1254 nfe_init(struct ifnet *ifp) 1255 { 1256 struct nfe_softc *sc = ifp->if_softc; 1257 uint32_t tmp; 1258 int rc = 0, s; 1259 1260 if (ifp->if_flags & IFF_RUNNING) 1261 return 0; 1262 1263 nfe_stop(ifp, 0); 1264 1265 NFE_WRITE(sc, NFE_TX_UNK, 0); 1266 NFE_WRITE(sc, NFE_STATUS, 0); 1267 1268 sc->rxtxctl = NFE_RXTX_BIT2; 1269 if (sc->sc_flags & NFE_40BIT_ADDR) 1270 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1271 else if (sc->sc_flags & NFE_JUMBO_SUP) 1272 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1273 if (sc->sc_flags & NFE_HW_CSUM) 1274 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1275 #if NVLAN > 0 1276 /* 1277 * Although the adapter is capable of stripping VLAN tags from received 1278 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1279 * purpose. This will be done in software by our network stack. 1280 */ 1281 if (sc->sc_flags & NFE_HW_VLAN) 1282 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1283 #endif 1284 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1285 DELAY(10); 1286 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1287 1288 #if NVLAN 1289 if (sc->sc_flags & NFE_HW_VLAN) 1290 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1291 #endif 1292 1293 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1294 1295 /* set MAC address */ 1296 nfe_set_macaddr(sc, sc->sc_enaddr); 1297 1298 /* tell MAC where rings are in memory */ 1299 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, ((uint64_t)sc->rxq.physaddr) >> 32); 1300 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1301 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, ((uint64_t)sc->txq.physaddr) >> 32); 1302 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1303 1304 NFE_WRITE(sc, NFE_RING_SIZE, 1305 (NFE_RX_RING_COUNT - 1) << 16 | 1306 (NFE_TX_RING_COUNT - 1)); 1307 1308 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1309 1310 /* force MAC to wakeup */ 1311 tmp = NFE_READ(sc, NFE_PWR_STATE); 1312 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1313 DELAY(10); 1314 tmp = NFE_READ(sc, NFE_PWR_STATE); 1315 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1316 1317 s = splnet(); 1318 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1319 nfe_intr(sc); /* XXX clear IRQ status registers */ 1320 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1321 splx(s); 1322 1323 #if 1 1324 /* configure interrupts coalescing/mitigation */ 1325 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1326 #else 1327 /* no interrupt mitigation: one interrupt per packet */ 1328 NFE_WRITE(sc, NFE_IMTIMER, 970); 1329 #endif 1330 1331 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1332 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1333 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1334 1335 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1336 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1337 1338 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1339 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_ENABLE); 1340 1341 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1342 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1343 DELAY(10); 1344 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1345 1346 /* set Rx filter */ 1347 nfe_setmulti(sc); 1348 1349 if ((rc = ether_mediachange(ifp)) != 0) 1350 goto out; 1351 1352 nfe_tick(sc); 1353 1354 /* enable Rx */ 1355 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1356 1357 /* enable Tx */ 1358 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1359 1360 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1361 1362 /* enable interrupts */ 1363 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1364 1365 callout_schedule(&sc->sc_tick_ch, hz); 1366 1367 ifp->if_flags |= IFF_RUNNING; 1368 ifp->if_flags &= ~IFF_OACTIVE; 1369 1370 out: 1371 return rc; 1372 } 1373 1374 void 1375 nfe_stop(struct ifnet *ifp, int disable) 1376 { 1377 struct nfe_softc *sc = ifp->if_softc; 1378 1379 callout_stop(&sc->sc_tick_ch); 1380 1381 ifp->if_timer = 0; 1382 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1383 1384 mii_down(&sc->sc_mii); 1385 1386 /* abort Tx */ 1387 NFE_WRITE(sc, NFE_TX_CTL, 0); 1388 1389 /* disable Rx */ 1390 NFE_WRITE(sc, NFE_RX_CTL, 0); 1391 1392 /* disable interrupts */ 1393 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1394 1395 /* reset Tx and Rx rings */ 1396 nfe_reset_tx_ring(sc, &sc->txq); 1397 nfe_reset_rx_ring(sc, &sc->rxq); 1398 } 1399 1400 int 1401 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1402 { 1403 struct nfe_desc32 *desc32; 1404 struct nfe_desc64 *desc64; 1405 struct nfe_rx_data *data; 1406 struct nfe_jbuf *jbuf; 1407 void **desc; 1408 bus_addr_t physaddr; 1409 int i, nsegs, error, descsize; 1410 1411 if (sc->sc_flags & NFE_40BIT_ADDR) { 1412 desc = (void **)&ring->desc64; 1413 descsize = sizeof (struct nfe_desc64); 1414 } else { 1415 desc = (void **)&ring->desc32; 1416 descsize = sizeof (struct nfe_desc32); 1417 } 1418 1419 ring->cur = ring->next = 0; 1420 ring->bufsz = MCLBYTES; 1421 1422 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1423 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1424 if (error != 0) { 1425 aprint_error_dev(sc->sc_dev, 1426 "could not create desc DMA map\n"); 1427 ring->map = NULL; 1428 goto fail; 1429 } 1430 1431 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1432 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1433 if (error != 0) { 1434 aprint_error_dev(sc->sc_dev, 1435 "could not allocate DMA memory\n"); 1436 goto fail; 1437 } 1438 1439 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1440 NFE_RX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1441 if (error != 0) { 1442 aprint_error_dev(sc->sc_dev, 1443 "could not map desc DMA memory\n"); 1444 goto fail; 1445 } 1446 1447 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1448 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1449 if (error != 0) { 1450 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1451 goto fail; 1452 } 1453 1454 memset(*desc, 0, NFE_RX_RING_COUNT * descsize); 1455 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1456 1457 if (sc->sc_flags & NFE_USE_JUMBO) { 1458 ring->bufsz = NFE_JBYTES; 1459 if ((error = nfe_jpool_alloc(sc)) != 0) { 1460 aprint_error_dev(sc->sc_dev, 1461 "could not allocate jumbo frames\n"); 1462 goto fail; 1463 } 1464 } 1465 1466 /* 1467 * Pre-allocate Rx buffers and populate Rx ring. 1468 */ 1469 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1470 data = &sc->rxq.data[i]; 1471 1472 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1473 if (data->m == NULL) { 1474 aprint_error_dev(sc->sc_dev, 1475 "could not allocate rx mbuf\n"); 1476 error = ENOMEM; 1477 goto fail; 1478 } 1479 1480 if (sc->sc_flags & NFE_USE_JUMBO) { 1481 if ((jbuf = nfe_jalloc(sc, i)) == NULL) { 1482 aprint_error_dev(sc->sc_dev, 1483 "could not allocate jumbo buffer\n"); 1484 goto fail; 1485 } 1486 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1487 sc); 1488 1489 physaddr = jbuf->physaddr; 1490 } else { 1491 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1492 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1493 if (error != 0) { 1494 aprint_error_dev(sc->sc_dev, 1495 "could not create DMA map\n"); 1496 data->map = NULL; 1497 goto fail; 1498 } 1499 MCLGET(data->m, M_DONTWAIT); 1500 if (!(data->m->m_flags & M_EXT)) { 1501 aprint_error_dev(sc->sc_dev, 1502 "could not allocate mbuf cluster\n"); 1503 error = ENOMEM; 1504 goto fail; 1505 } 1506 1507 error = bus_dmamap_load(sc->sc_dmat, data->map, 1508 mtod(data->m, void *), MCLBYTES, NULL, 1509 BUS_DMA_READ | BUS_DMA_NOWAIT); 1510 if (error != 0) { 1511 aprint_error_dev(sc->sc_dev, 1512 "could not load rx buf DMA map"); 1513 goto fail; 1514 } 1515 physaddr = data->map->dm_segs[0].ds_addr; 1516 } 1517 1518 if (sc->sc_flags & NFE_40BIT_ADDR) { 1519 desc64 = &sc->rxq.desc64[i]; 1520 desc64->physaddr[0] = 1521 htole32(((uint64_t)physaddr) >> 32); 1522 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1523 desc64->length = htole16(sc->rxq.bufsz); 1524 desc64->flags = htole16(NFE_RX_READY); 1525 } else { 1526 desc32 = &sc->rxq.desc32[i]; 1527 desc32->physaddr = htole32(physaddr); 1528 desc32->length = htole16(sc->rxq.bufsz); 1529 desc32->flags = htole16(NFE_RX_READY); 1530 } 1531 } 1532 1533 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1534 BUS_DMASYNC_PREWRITE); 1535 1536 return 0; 1537 1538 fail: nfe_free_rx_ring(sc, ring); 1539 return error; 1540 } 1541 1542 void 1543 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1544 { 1545 int i; 1546 1547 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1548 if (sc->sc_flags & NFE_40BIT_ADDR) { 1549 ring->desc64[i].length = htole16(ring->bufsz); 1550 ring->desc64[i].flags = htole16(NFE_RX_READY); 1551 } else { 1552 ring->desc32[i].length = htole16(ring->bufsz); 1553 ring->desc32[i].flags = htole16(NFE_RX_READY); 1554 } 1555 } 1556 1557 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1558 BUS_DMASYNC_PREWRITE); 1559 1560 ring->cur = ring->next = 0; 1561 } 1562 1563 void 1564 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1565 { 1566 struct nfe_rx_data *data; 1567 void *desc; 1568 int i, descsize; 1569 1570 if (sc->sc_flags & NFE_40BIT_ADDR) { 1571 desc = ring->desc64; 1572 descsize = sizeof (struct nfe_desc64); 1573 } else { 1574 desc = ring->desc32; 1575 descsize = sizeof (struct nfe_desc32); 1576 } 1577 1578 if (desc != NULL) { 1579 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1580 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1581 bus_dmamap_unload(sc->sc_dmat, ring->map); 1582 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1583 NFE_RX_RING_COUNT * descsize); 1584 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1585 } 1586 1587 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1588 data = &ring->data[i]; 1589 1590 if (data->map != NULL) { 1591 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1592 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1593 bus_dmamap_unload(sc->sc_dmat, data->map); 1594 bus_dmamap_destroy(sc->sc_dmat, data->map); 1595 } 1596 if (data->m != NULL) 1597 m_freem(data->m); 1598 } 1599 1600 nfe_jpool_free(sc); 1601 } 1602 1603 struct nfe_jbuf * 1604 nfe_jalloc(struct nfe_softc *sc, int i) 1605 { 1606 struct nfe_jbuf *jbuf; 1607 1608 mutex_enter(&sc->rxq.mtx); 1609 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1610 if (jbuf != NULL) 1611 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1612 mutex_exit(&sc->rxq.mtx); 1613 if (jbuf == NULL) 1614 return NULL; 1615 sc->rxq.jbufmap[i] = 1616 ((char *)jbuf->buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1617 return jbuf; 1618 } 1619 1620 /* 1621 * This is called automatically by the network stack when the mbuf is freed. 1622 * Caution must be taken that the NIC might be reset by the time the mbuf is 1623 * freed. 1624 */ 1625 void 1626 nfe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1627 { 1628 struct nfe_softc *sc = arg; 1629 struct nfe_jbuf *jbuf; 1630 int i; 1631 1632 /* find the jbuf from the base pointer */ 1633 i = ((char *)buf - (char *)sc->rxq.jpool) / NFE_JBYTES; 1634 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1635 aprint_error_dev(sc->sc_dev, 1636 "request to free a buffer (%p) not managed by us\n", buf); 1637 return; 1638 } 1639 jbuf = &sc->rxq.jbuf[i]; 1640 1641 /* ..and put it back in the free list */ 1642 mutex_enter(&sc->rxq.mtx); 1643 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1644 mutex_exit(&sc->rxq.mtx); 1645 1646 if (m != NULL) 1647 pool_cache_put(mb_cache, m); 1648 } 1649 1650 int 1651 nfe_jpool_alloc(struct nfe_softc *sc) 1652 { 1653 struct nfe_rx_ring *ring = &sc->rxq; 1654 struct nfe_jbuf *jbuf; 1655 bus_addr_t physaddr; 1656 char *buf; 1657 int i, nsegs, error; 1658 1659 /* 1660 * Allocate a big chunk of DMA'able memory. 1661 */ 1662 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1663 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1664 if (error != 0) { 1665 aprint_error_dev(sc->sc_dev, 1666 "could not create jumbo DMA map\n"); 1667 ring->jmap = NULL; 1668 goto fail; 1669 } 1670 1671 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1672 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1673 if (error != 0) { 1674 aprint_error_dev(sc->sc_dev, 1675 "could not allocate jumbo DMA memory\n"); 1676 goto fail; 1677 } 1678 1679 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1680 &ring->jpool, BUS_DMA_NOWAIT); 1681 if (error != 0) { 1682 aprint_error_dev(sc->sc_dev, 1683 "could not map jumbo DMA memory\n"); 1684 goto fail; 1685 } 1686 1687 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1688 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1689 if (error != 0) { 1690 aprint_error_dev(sc->sc_dev, 1691 "could not load jumbo DMA map\n"); 1692 goto fail; 1693 } 1694 1695 /* ..and split it into 9KB chunks */ 1696 SLIST_INIT(&ring->jfreelist); 1697 1698 buf = ring->jpool; 1699 physaddr = ring->jmap->dm_segs[0].ds_addr; 1700 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1701 jbuf = &ring->jbuf[i]; 1702 1703 jbuf->buf = buf; 1704 jbuf->physaddr = physaddr; 1705 1706 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1707 1708 buf += NFE_JBYTES; 1709 physaddr += NFE_JBYTES; 1710 } 1711 1712 return 0; 1713 1714 fail: nfe_jpool_free(sc); 1715 return error; 1716 } 1717 1718 void 1719 nfe_jpool_free(struct nfe_softc *sc) 1720 { 1721 struct nfe_rx_ring *ring = &sc->rxq; 1722 1723 if (ring->jmap != NULL) { 1724 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1725 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1726 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1727 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1728 ring->jmap = NULL; 1729 } 1730 if (ring->jpool != NULL) { 1731 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1732 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1733 ring->jpool = NULL; 1734 } 1735 } 1736 1737 int 1738 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1739 { 1740 int i, nsegs, error; 1741 void **desc; 1742 int descsize; 1743 1744 if (sc->sc_flags & NFE_40BIT_ADDR) { 1745 desc = (void **)&ring->desc64; 1746 descsize = sizeof (struct nfe_desc64); 1747 } else { 1748 desc = (void **)&ring->desc32; 1749 descsize = sizeof (struct nfe_desc32); 1750 } 1751 1752 ring->queued = 0; 1753 ring->cur = ring->next = 0; 1754 1755 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1756 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1757 1758 if (error != 0) { 1759 aprint_error_dev(sc->sc_dev, 1760 "could not create desc DMA map\n"); 1761 ring->map = NULL; 1762 goto fail; 1763 } 1764 1765 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1766 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1767 if (error != 0) { 1768 aprint_error_dev(sc->sc_dev, 1769 "could not allocate DMA memory\n"); 1770 goto fail; 1771 } 1772 1773 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1774 NFE_TX_RING_COUNT * descsize, (void **)desc, BUS_DMA_NOWAIT); 1775 if (error != 0) { 1776 aprint_error_dev(sc->sc_dev, 1777 "could not map desc DMA memory\n"); 1778 goto fail; 1779 } 1780 1781 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1782 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1783 if (error != 0) { 1784 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 1785 goto fail; 1786 } 1787 1788 memset(*desc, 0, NFE_TX_RING_COUNT * descsize); 1789 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1790 1791 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1792 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1793 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1794 &ring->data[i].map); 1795 if (error != 0) { 1796 aprint_error_dev(sc->sc_dev, 1797 "could not create DMA map\n"); 1798 ring->data[i].map = NULL; 1799 goto fail; 1800 } 1801 } 1802 1803 return 0; 1804 1805 fail: nfe_free_tx_ring(sc, ring); 1806 return error; 1807 } 1808 1809 void 1810 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1811 { 1812 struct nfe_tx_data *data; 1813 int i; 1814 1815 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1816 if (sc->sc_flags & NFE_40BIT_ADDR) 1817 ring->desc64[i].flags = 0; 1818 else 1819 ring->desc32[i].flags = 0; 1820 1821 data = &ring->data[i]; 1822 1823 if (data->m != NULL) { 1824 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1825 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1826 bus_dmamap_unload(sc->sc_dmat, data->active); 1827 m_freem(data->m); 1828 data->m = NULL; 1829 } 1830 } 1831 1832 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1833 BUS_DMASYNC_PREWRITE); 1834 1835 ring->queued = 0; 1836 ring->cur = ring->next = 0; 1837 } 1838 1839 void 1840 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1841 { 1842 struct nfe_tx_data *data; 1843 void *desc; 1844 int i, descsize; 1845 1846 if (sc->sc_flags & NFE_40BIT_ADDR) { 1847 desc = ring->desc64; 1848 descsize = sizeof (struct nfe_desc64); 1849 } else { 1850 desc = ring->desc32; 1851 descsize = sizeof (struct nfe_desc32); 1852 } 1853 1854 if (desc != NULL) { 1855 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1856 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1857 bus_dmamap_unload(sc->sc_dmat, ring->map); 1858 bus_dmamem_unmap(sc->sc_dmat, (void *)desc, 1859 NFE_TX_RING_COUNT * descsize); 1860 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1861 } 1862 1863 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1864 data = &ring->data[i]; 1865 1866 if (data->m != NULL) { 1867 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1868 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1869 bus_dmamap_unload(sc->sc_dmat, data->active); 1870 m_freem(data->m); 1871 } 1872 } 1873 1874 /* ..and now actually destroy the DMA mappings */ 1875 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1876 data = &ring->data[i]; 1877 if (data->map == NULL) 1878 continue; 1879 bus_dmamap_destroy(sc->sc_dmat, data->map); 1880 } 1881 } 1882 1883 void 1884 nfe_setmulti(struct nfe_softc *sc) 1885 { 1886 struct ethercom *ec = &sc->sc_ethercom; 1887 struct ifnet *ifp = &ec->ec_if; 1888 struct ether_multi *enm; 1889 struct ether_multistep step; 1890 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1891 uint32_t filter = NFE_RXFILTER_MAGIC; 1892 int i; 1893 1894 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1895 memset(addr, 0, ETHER_ADDR_LEN); 1896 memset(mask, 0, ETHER_ADDR_LEN); 1897 goto done; 1898 } 1899 1900 memcpy(addr, etherbroadcastaddr, ETHER_ADDR_LEN); 1901 memcpy(mask, etherbroadcastaddr, ETHER_ADDR_LEN); 1902 1903 ETHER_LOCK(ec); 1904 ETHER_FIRST_MULTI(step, ec, enm); 1905 while (enm != NULL) { 1906 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1907 ifp->if_flags |= IFF_ALLMULTI; 1908 memset(addr, 0, ETHER_ADDR_LEN); 1909 memset(mask, 0, ETHER_ADDR_LEN); 1910 ETHER_UNLOCK(ec); 1911 goto done; 1912 } 1913 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1914 addr[i] &= enm->enm_addrlo[i]; 1915 mask[i] &= ~enm->enm_addrlo[i]; 1916 } 1917 ETHER_NEXT_MULTI(step, enm); 1918 } 1919 ETHER_UNLOCK(ec); 1920 for (i = 0; i < ETHER_ADDR_LEN; i++) 1921 mask[i] |= addr[i]; 1922 1923 done: 1924 addr[0] |= 0x01; /* make sure multicast bit is set */ 1925 1926 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1927 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1928 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1929 addr[5] << 8 | addr[4]); 1930 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1931 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1932 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1933 mask[5] << 8 | mask[4]); 1934 1935 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1936 NFE_WRITE(sc, NFE_RXFILTER, filter); 1937 } 1938 1939 void 1940 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1941 { 1942 uint32_t tmp; 1943 1944 if ((sc->sc_flags & NFE_CORRECT_MACADDR) != 0) { 1945 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1946 addr[0] = (tmp & 0xff); 1947 addr[1] = (tmp >> 8) & 0xff; 1948 addr[2] = (tmp >> 16) & 0xff; 1949 addr[3] = (tmp >> 24) & 0xff; 1950 1951 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1952 addr[4] = (tmp & 0xff); 1953 addr[5] = (tmp >> 8) & 0xff; 1954 1955 } else { 1956 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1957 addr[0] = (tmp >> 8) & 0xff; 1958 addr[1] = (tmp & 0xff); 1959 1960 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1961 addr[2] = (tmp >> 24) & 0xff; 1962 addr[3] = (tmp >> 16) & 0xff; 1963 addr[4] = (tmp >> 8) & 0xff; 1964 addr[5] = (tmp & 0xff); 1965 } 1966 } 1967 1968 void 1969 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1970 { 1971 NFE_WRITE(sc, NFE_MACADDR_LO, 1972 addr[5] << 8 | addr[4]); 1973 NFE_WRITE(sc, NFE_MACADDR_HI, 1974 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1975 } 1976 1977 void 1978 nfe_tick(void *arg) 1979 { 1980 struct nfe_softc *sc = arg; 1981 int s; 1982 1983 s = splnet(); 1984 mii_tick(&sc->sc_mii); 1985 splx(s); 1986 1987 callout_schedule(&sc->sc_tick_ch, hz); 1988 } 1989 1990 void 1991 nfe_poweron(device_t self) 1992 { 1993 struct nfe_softc *sc = device_private(self); 1994 1995 if ((sc->sc_flags & NFE_PWR_MGMT) != 0) { 1996 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 1997 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 1998 DELAY(100); 1999 NFE_WRITE(sc, NFE_MAC_RESET, 0); 2000 DELAY(100); 2001 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 2002 NFE_WRITE(sc, NFE_PWR2_CTL, 2003 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_WAKEUP_MASK); 2004 } 2005 } 2006 2007 bool 2008 nfe_resume(device_t dv, const pmf_qual_t *qual) 2009 { 2010 nfe_poweron(dv); 2011 2012 return true; 2013 } 2014
Indexes created Tue Sep 30 10:09:55 GMT 2025