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if_nfereg.h revision 1.6.6.1
      1  1.6.6.1      mjf /*	$NetBSD: if_nfereg.h,v 1.6.6.1 2008/06/02 13:23:39 mjf Exp $	*/
      2  1.6.6.1      mjf /*	$OpenBSD: if_nfereg.h,v 1.22 2007/12/05 08:30:33 jsg Exp $	*/
      3      1.1      chs 
      4      1.1      chs /*-
      5      1.1      chs  * Copyright (c) 2005 Jonathan Gray <jsg (at) openbsd.org>
      6      1.1      chs  *
      7      1.1      chs  * Permission to use, copy, modify, and distribute this software for any
      8      1.1      chs  * purpose with or without fee is hereby granted, provided that the above
      9      1.1      chs  * copyright notice and this permission notice appear in all copies.
     10      1.1      chs  *
     11      1.1      chs  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
     12      1.1      chs  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
     13      1.1      chs  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
     14      1.1      chs  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
     15      1.1      chs  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
     16      1.1      chs  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
     17      1.1      chs  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
     18      1.1      chs  */
     19      1.1      chs 
     20      1.1      chs #define NFE_PCI_BA		0x10
     21      1.1      chs 
     22      1.1      chs #define NFE_RX_RING_COUNT	128
     23  1.6.6.1      mjf #define NFE_TX_RING_COUNT	256
     24      1.1      chs 
     25      1.4  tsutsui #define NFE_RX_NEXTDESC(x)	(((x) + 1) & (NFE_RX_RING_COUNT - 1))
     26      1.4  tsutsui #define NFE_TX_NEXTDESC(x)	(((x) + 1) & (NFE_TX_RING_COUNT - 1))
     27      1.4  tsutsui 
     28      1.1      chs #define	ETHER_ALIGN		2
     29  1.6.6.1      mjf 
     30  1.6.6.1      mjf #define NFE_JUMBO_FRAMELEN	9018
     31  1.6.6.1      mjf #define NFE_JUMBO_MTU		(NFE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
     32  1.6.6.1      mjf 
     33  1.6.6.1      mjf #define NFE_JBYTES		(NFE_JUMBO_FRAMELEN + ETHER_ALIGN)
     34      1.1      chs #define NFE_JPOOL_COUNT		(NFE_RX_RING_COUNT + 64)
     35      1.1      chs #define NFE_JPOOL_SIZE		(NFE_JPOOL_COUNT * NFE_JBYTES)
     36      1.1      chs 
     37      1.1      chs #define NFE_MAX_SCATTER		(NFE_TX_RING_COUNT - 2)
     38      1.1      chs 
     39      1.1      chs #define NFE_IRQ_STATUS		0x000
     40      1.1      chs #define NFE_IRQ_MASK		0x004
     41      1.1      chs #define NFE_SETUP_R6		0x008
     42      1.1      chs #define NFE_IMTIMER		0x00c
     43      1.6  tsutsui #define NFE_MAC_RESET		0x03c
     44      1.1      chs #define NFE_MISC1		0x080
     45      1.1      chs #define NFE_TX_CTL		0x084
     46      1.1      chs #define NFE_TX_STATUS		0x088
     47      1.1      chs #define NFE_RXFILTER		0x08c
     48      1.1      chs #define NFE_RXBUFSZ		0x090
     49      1.1      chs #define NFE_RX_CTL		0x094
     50      1.1      chs #define NFE_RX_STATUS		0x098
     51      1.1      chs #define NFE_RNDSEED		0x09c
     52      1.1      chs #define NFE_SETUP_R1		0x0a0
     53      1.1      chs #define NFE_SETUP_R2		0x0a4
     54      1.1      chs #define NFE_MACADDR_HI		0x0a8
     55      1.1      chs #define NFE_MACADDR_LO		0x0ac
     56      1.1      chs #define NFE_MULTIADDR_HI	0x0b0
     57      1.1      chs #define NFE_MULTIADDR_LO	0x0b4
     58      1.1      chs #define NFE_MULTIMASK_HI	0x0b8
     59      1.1      chs #define NFE_MULTIMASK_LO	0x0bc
     60      1.1      chs #define NFE_PHY_IFACE		0x0c0
     61      1.1      chs #define NFE_TX_RING_ADDR_LO	0x100
     62      1.1      chs #define NFE_RX_RING_ADDR_LO	0x104
     63      1.1      chs #define NFE_RING_SIZE		0x108
     64      1.1      chs #define NFE_TX_UNK		0x10c
     65      1.1      chs #define NFE_LINKSPEED		0x110
     66      1.1      chs #define NFE_SETUP_R5		0x130
     67      1.1      chs #define NFE_SETUP_R3		0x13C
     68      1.1      chs #define NFE_SETUP_R7		0x140
     69      1.1      chs #define NFE_RXTX_CTL		0x144
     70      1.1      chs #define NFE_TX_RING_ADDR_HI	0x148
     71      1.1      chs #define NFE_RX_RING_ADDR_HI	0x14c
     72      1.1      chs #define NFE_PHY_STATUS		0x180
     73      1.1      chs #define NFE_SETUP_R4		0x184
     74      1.1      chs #define NFE_STATUS		0x188
     75      1.1      chs #define NFE_PHY_SPEED		0x18c
     76      1.1      chs #define NFE_PHY_CTL		0x190
     77      1.1      chs #define NFE_PHY_DATA		0x194
     78      1.1      chs #define NFE_WOL_CTL		0x200
     79      1.1      chs #define NFE_PATTERN_CRC		0x204
     80      1.1      chs #define NFE_PATTERN_MASK	0x208
     81      1.1      chs #define NFE_PWR_CAP		0x268
     82      1.1      chs #define NFE_PWR_STATE		0x26c
     83      1.1      chs #define NFE_VTAG_CTL		0x300
     84      1.6  tsutsui #define NFE_PWR2_CTL		0x600
     85      1.1      chs 
     86      1.1      chs #define NFE_PHY_ERROR		0x00001
     87      1.1      chs #define NFE_PHY_WRITE		0x00400
     88      1.1      chs #define NFE_PHY_BUSY		0x08000
     89      1.1      chs #define NFE_PHYADD_SHIFT	5
     90      1.1      chs 
     91      1.6  tsutsui #define NFE_MAC_RESET_MAGIC	0x00f3
     92      1.6  tsutsui 
     93      1.1      chs #define NFE_STATUS_MAGIC	0x140000
     94      1.1      chs 
     95      1.5  tsutsui #define NFE_MAC_ADDR_INORDER	0x8000
     96      1.5  tsutsui 
     97      1.1      chs #define NFE_R1_MAGIC		0x16070f
     98      1.1      chs #define NFE_R2_MAGIC		0x16
     99      1.1      chs #define NFE_R4_MAGIC		0x08
    100      1.1      chs #define NFE_R6_MAGIC		0x03
    101  1.6.6.1      mjf #define NFE_WOL_ENABLE		0x1111
    102      1.1      chs #define NFE_RX_START		0x01
    103      1.1      chs #define NFE_TX_START		0x01
    104      1.1      chs 
    105      1.1      chs #define NFE_IRQ_RXERR		0x0001
    106      1.1      chs #define NFE_IRQ_RX		0x0002
    107      1.1      chs #define NFE_IRQ_RX_NOBUF	0x0004
    108      1.1      chs #define NFE_IRQ_TXERR		0x0008
    109      1.1      chs #define NFE_IRQ_TX_DONE		0x0010
    110      1.1      chs #define NFE_IRQ_TIMER		0x0020
    111      1.1      chs #define NFE_IRQ_LINK		0x0040
    112      1.1      chs #define NFE_IRQ_TXERR2		0x0080
    113      1.1      chs #define NFE_IRQ_TX1		0x0100
    114      1.1      chs 
    115      1.1      chs #define NFE_IRQ_WANTED							\
    116      1.1      chs 	(NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX |		\
    117      1.1      chs 	 NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE |		\
    118      1.1      chs 	 NFE_IRQ_LINK)
    119      1.1      chs 
    120      1.1      chs #define NFE_RXTX_KICKTX		0x0001
    121      1.1      chs #define NFE_RXTX_BIT1		0x0002
    122      1.1      chs #define NFE_RXTX_BIT2		0x0004
    123      1.1      chs #define NFE_RXTX_RESET		0x0010
    124      1.1      chs #define NFE_RXTX_VTAG_STRIP	0x0040
    125      1.1      chs #define NFE_RXTX_VTAG_INSERT	0x0080
    126      1.1      chs #define NFE_RXTX_RXCSUM		0x0400
    127      1.1      chs #define NFE_RXTX_V2MAGIC	0x2100
    128      1.1      chs #define NFE_RXTX_V3MAGIC	0x2200
    129      1.1      chs #define NFE_RXFILTER_MAGIC	0x007f0008
    130      1.1      chs #define NFE_U2M			(1 << 5)
    131      1.1      chs #define NFE_PROMISC		(1 << 7)
    132      1.1      chs 
    133      1.1      chs /* default interrupt moderation timer of 128us */
    134      1.1      chs #define NFE_IM_DEFAULT	((128 * 100) / 1024)
    135      1.1      chs 
    136      1.1      chs #define NFE_VTAG_ENABLE		(1 << 13)
    137      1.1      chs 
    138      1.1      chs #define NFE_PWR_VALID		(1 << 8)
    139      1.1      chs #define NFE_PWR_WAKEUP		(1 << 15)
    140      1.6  tsutsui #define NFE_PWR2_WAKEUP_MASK	0x0f11
    141      1.1      chs 
    142      1.1      chs #define NFE_MEDIA_SET		0x10000
    143      1.1      chs #define	NFE_MEDIA_1000T		0x00032
    144      1.1      chs #define NFE_MEDIA_100TX		0x00064
    145      1.1      chs #define NFE_MEDIA_10T		0x003e8
    146      1.1      chs 
    147      1.1      chs #define NFE_PHY_100TX		(1 << 0)
    148      1.1      chs #define NFE_PHY_1000T		(1 << 1)
    149      1.1      chs #define NFE_PHY_HDX		(1 << 8)
    150      1.1      chs 
    151      1.1      chs #define NFE_MISC1_MAGIC		0x003b0f3c
    152      1.1      chs #define NFE_MISC1_HDX		(1 << 1)
    153      1.1      chs 
    154      1.1      chs #define NFE_SEED_MASK		0x0003ff00
    155      1.1      chs #define NFE_SEED_10T		0x00007f00
    156      1.1      chs #define NFE_SEED_100TX		0x00002d00
    157      1.1      chs #define NFE_SEED_1000T		0x00007400
    158      1.1      chs 
    159      1.1      chs /* Rx/Tx descriptor */
    160      1.1      chs struct nfe_desc32 {
    161      1.4  tsutsui 	volatile uint32_t	physaddr;
    162      1.4  tsutsui 	volatile uint16_t	length;
    163      1.4  tsutsui 	volatile uint16_t	flags;
    164      1.1      chs #define NFE_RX_FIXME_V1		0x6004
    165      1.1      chs #define NFE_RX_VALID_V1		(1 << 0)
    166      1.1      chs #define NFE_TX_ERROR_V1		0x7808
    167      1.1      chs #define NFE_TX_LASTFRAG_V1	(1 << 0)
    168      1.1      chs } __packed;
    169      1.1      chs 
    170  1.6.6.1      mjf #define NFE_V1_TXERR	"\020"	\
    171  1.6.6.1      mjf 	"\14TXERROR\13UNDERFLOW\12LATECOLLISION\11LOSTCARRIER\10DEFERRED" \
    172  1.6.6.1      mjf 	"\08FORCEDINT\03RETRY\00LASTPACKET"
    173  1.6.6.1      mjf 
    174      1.1      chs /* V2 Rx/Tx descriptor */
    175      1.1      chs struct nfe_desc64 {
    176      1.4  tsutsui 	volatile uint32_t	physaddr[2];
    177      1.4  tsutsui 	volatile uint32_t	vtag;
    178      1.1      chs #define NFE_RX_VTAG		(1 << 16)
    179      1.1      chs #define NFE_TX_VTAG		(1 << 18)
    180      1.4  tsutsui 	volatile uint16_t	length;
    181      1.4  tsutsui 	volatile uint16_t	flags;
    182      1.1      chs #define NFE_RX_FIXME_V2		0x4300
    183      1.1      chs #define NFE_RX_VALID_V2		(1 << 13)
    184      1.1      chs #define NFE_TX_ERROR_V2		0x5c04
    185      1.1      chs #define NFE_TX_LASTFRAG_V2	(1 << 13)
    186      1.1      chs } __packed;
    187      1.1      chs 
    188  1.6.6.1      mjf #define NFE_V2_TXERR	"\020"	\
    189  1.6.6.1      mjf 	"\14FORCEDINT\13LASTPACKET\12UNDERFLOW\10LOSTCARRIER\09DEFERRED\02RETRY"
    190  1.6.6.1      mjf 
    191      1.1      chs /* flags common to V1/V2 descriptors */
    192  1.6.6.1      mjf #define NFE_RX_UDP_CSUMOK	(1 << 10)
    193  1.6.6.1      mjf #define NFE_RX_TCP_CSUMOK	(1 << 11)
    194  1.6.6.1      mjf #define NFE_RX_IP_CSUMOK	(1 << 12)
    195      1.1      chs #define NFE_RX_ERROR		(1 << 14)
    196      1.1      chs #define NFE_RX_READY		(1 << 15)
    197  1.6.6.1      mjf #define NFE_TX_TCP_UDP_CSUM	(1 << 10)
    198  1.6.6.1      mjf #define NFE_TX_IP_CSUM		(1 << 11)
    199      1.1      chs #define NFE_TX_VALID		(1 << 15)
    200      1.1      chs 
    201      1.1      chs #define NFE_READ(sc, reg) \
    202      1.1      chs 	bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (reg))
    203      1.1      chs 
    204      1.1      chs #define NFE_WRITE(sc, reg, val) \
    205      1.1      chs 	bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (reg), (val))
    206