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if_ntwoc_pcireg.h revision 1.1 
      1 /*	$Id: if_ntwoc_pcireg.h,v 1.1 1998/07/26 03:28:28 explorer Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1998 Vixie Enterprises
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  *
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  * 3. Neither the name of Vixie Enterprises nor the names
     17  *    of its contributors may be used to endorse or promote products derived
     18  *    from this software without specific prior written permission.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY VIXIE ENTERPRISES AND
     21  * CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
     22  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     24  * DISCLAIMED.  IN NO EVENT SHALL VIXIE ENTERPRISES OR
     25  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     26  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
     27  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
     28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
     29  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
     31  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     32  * SUCH DAMAGE.
     33  *
     34  * This software has been written for Vixie Enterprises by Michael Graff
     35  * <explorer (at) flame.org>.  To learn more about Vixie Enterprises, see
     36  * ``http://www.vix.com''.
     37  */
     38 
     39 #ifndef _IF_NTWOC_PCIREG_H_
     40 #define _IF_NTWOC_PCIREG_H_
     41 
     42 /*
     43  * ASIC register offsets
     44  */
     45 
     46 /*
     47  * This register is in the SCA namespace, but is NOT really an SCA register.
     48  * It contains information about the daughter cards, and provides a method
     49  * to configure them.
     50  */
     51 #define NTWOC_FECR	0x200
     52 
     53 /*
     54  * definition of the NTWO_FECR register
     55  */
     56 #define NTWOC_FECR_ID0		0x0e00	/* mask of daughter card on port 0 */
     57 #define NTWOC_FECR_ID0_SHIFT	     9
     58 #define NTWOC_FECR_ID1		0xe000  /* mask of daughter card on port 1 */
     59 #define NTWOC_FECR_ID1_SHIFT	    13
     60 
     61 #define NTWOC_FECR_DTR1		0x0080	/* DTR output for port 1 */
     62 #define NTWOC_FECR_DTR0		0x0040	/* DTR output for port 0 */
     63 #define NTWOC_FECR_DSR1		0x1000	/* DSR input for port 1 */
     64 #define NTWOC_FECR_DSR0		0x0100	/* DSR input for port 0 */
     65 #define NTWOC_FECR_TE1		0x0008	/* tristate enable port 1 */
     66 #define NTWOC_FECR_TE0		0x0004	/* tristate enable port 0 */
     67 #define NTWOC_FECR_ETC1		0x0002	/* output clock port 1 */
     68 #define NTWOC_FECR_ETC0		0x0001	/* output clock port 0 */
     69 
     70 /*
     71  * Daughter card for port.
     72  */
     73 #define NTWOC_FE_ID_V35		0x00
     74 #define NTWOC_FE_ID_X01		0x01	/* unused? */
     75 #define NTWOC_FE_ID_TEST	0x02
     76 #define NTWOC_FE_ID_X03		0x03	/* unused? */
     77 #define NTWOC_FE_ID_RS232	0x04
     78 #define NTWOC_FE_ID_X05		0x05	/* was hssi, now unused? */
     79 #define NTWOC_FE_ID_RS422	0x06
     80 #define NTWOC_FE_ID_NONE	0x07	/* empty, no card present */
     81 
     82 /*
     83  * ASIC Control defininitions
     84  */
     85 
     86 /* Front End (Modem,etc) Control Register */
     87 
     88 #define  ASIC_MODEM   0x200   /* ASIC modem control register Offset */
     89 
     90 /* ASIC front end control register bits */
     91 #define  ASIC_DSR1       0x1000    /* DSR signal input port 1 */
     92 #define  ASIC_DSR0        0x100    /* DSR signal input port 0 */
     93 #define  ASIC_DTR1         0x80    /* DTR signal output port 1 */
     94 #define  ASIC_DTR0         0x40    /* DTR signal output port 0 */
     95 #define  ASIC_TE1           0x8    /* RS422 TX,enable port 1 */
     96 #define  ASIC_TE0           0x4    /* RS422 TX,enable port 0 */
     97 #define  ASIC_ETC1          0x2    /* ETC Clock out port 1 */
     98 #define  ASIC_ETC0          0x1    /* ETC Clock out port 0 */
     99 
    100 #endif /* _IF_NTWOC_PCIREG_H_ */
    101