if_pcn.c revision 1.26
1 /* $NetBSD: if_pcn.c,v 1.26 2005/05/07 09:15:44 is Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the AMD PCnet-PCI series of Ethernet 40 * chips: 41 * 42 * * Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 43 * Local Bus 44 * 45 * * Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 46 * for PCI Local Bus 47 * 48 * * Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 49 * Ethernet Controller for PCI Local Bus 50 * 51 * * Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 52 * with OnNow Support 53 * 54 * * Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 55 * Ethernet Controller with Integrated PHY 56 * 57 * This also supports the virtual PCnet-PCI Ethernet interface found 58 * in VMware. 59 * 60 * TODO: 61 * 62 * * Split this into bus-specific and bus-independent portions. 63 * The core could also be used for the ILACC (Am79900) 32-bit 64 * Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE). 65 */ 66 67 #include "opt_pcn.h" 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: if_pcn.c,v 1.26 2005/05/07 09:15:44 is Exp $"); 71 72 #include "bpfilter.h" 73 #include "rnd.h" 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/callout.h> 78 #include <sys/mbuf.h> 79 #include <sys/malloc.h> 80 #include <sys/kernel.h> 81 #include <sys/socket.h> 82 #include <sys/ioctl.h> 83 #include <sys/errno.h> 84 #include <sys/device.h> 85 #include <sys/queue.h> 86 87 #if NRND > 0 88 #include <sys/rnd.h> 89 #endif 90 91 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 92 93 #include <net/if.h> 94 #include <net/if_dl.h> 95 #include <net/if_media.h> 96 #include <net/if_ether.h> 97 98 #if NBPFILTER > 0 99 #include <net/bpf.h> 100 #endif 101 102 #include <machine/bus.h> 103 #include <machine/intr.h> 104 #include <machine/endian.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 109 #include <dev/ic/am79900reg.h> 110 #include <dev/ic/lancereg.h> 111 112 #include <dev/pci/pcireg.h> 113 #include <dev/pci/pcivar.h> 114 #include <dev/pci/pcidevs.h> 115 116 #include <dev/pci/if_pcnreg.h> 117 118 /* 119 * Transmit descriptor list size. This is arbitrary, but allocate 120 * enough descriptors for 128 pending transmissions, and 4 segments 121 * per packet. This MUST work out to a power of 2. 122 * 123 * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL! 124 * 125 * So we play a little trick here. We give each packet up to 16 126 * DMA segments, but only allocate the max of 512 descriptors. The 127 * transmit logic can deal with this, we just are hoping to sneak by. 128 */ 129 #define PCN_NTXSEGS 16 130 131 #define PCN_TXQUEUELEN 128 132 #define PCN_TXQUEUELEN_MASK (PCN_TXQUEUELEN - 1) 133 #define PCN_NTXDESC 512 134 #define PCN_NTXDESC_MASK (PCN_NTXDESC - 1) 135 #define PCN_NEXTTX(x) (((x) + 1) & PCN_NTXDESC_MASK) 136 #define PCN_NEXTTXS(x) (((x) + 1) & PCN_TXQUEUELEN_MASK) 137 138 /* Tx interrupt every N + 1 packets. */ 139 #define PCN_TXINTR_MASK 7 140 141 /* 142 * Receive descriptor list size. We have one Rx buffer per incoming 143 * packet, so this logic is a little simpler. 144 */ 145 #define PCN_NRXDESC 128 146 #define PCN_NRXDESC_MASK (PCN_NRXDESC - 1) 147 #define PCN_NEXTRX(x) (((x) + 1) & PCN_NRXDESC_MASK) 148 149 /* 150 * Control structures are DMA'd to the PCnet chip. We allocate them in 151 * a single clump that maps to a single DMA segment to make several things 152 * easier. 153 */ 154 struct pcn_control_data { 155 /* The transmit descriptors. */ 156 struct letmd pcd_txdescs[PCN_NTXDESC]; 157 158 /* The receive descriptors. */ 159 struct lermd pcd_rxdescs[PCN_NRXDESC]; 160 161 /* The init block. */ 162 struct leinit pcd_initblock; 163 }; 164 165 #define PCN_CDOFF(x) offsetof(struct pcn_control_data, x) 166 #define PCN_CDTXOFF(x) PCN_CDOFF(pcd_txdescs[(x)]) 167 #define PCN_CDRXOFF(x) PCN_CDOFF(pcd_rxdescs[(x)]) 168 #define PCN_CDINITOFF PCN_CDOFF(pcd_initblock) 169 170 /* 171 * Software state for transmit jobs. 172 */ 173 struct pcn_txsoft { 174 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 175 bus_dmamap_t txs_dmamap; /* our DMA map */ 176 int txs_firstdesc; /* first descriptor in packet */ 177 int txs_lastdesc; /* last descriptor in packet */ 178 }; 179 180 /* 181 * Software state for receive jobs. 182 */ 183 struct pcn_rxsoft { 184 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 185 bus_dmamap_t rxs_dmamap; /* our DMA map */ 186 }; 187 188 /* 189 * Description of Rx FIFO watermarks for various revisions. 190 */ 191 static const char * const pcn_79c970_rcvfw[] = { 192 "16 bytes", 193 "64 bytes", 194 "128 bytes", 195 NULL, 196 }; 197 198 static const char * const pcn_79c971_rcvfw[] = { 199 "16 bytes", 200 "64 bytes", 201 "112 bytes", 202 NULL, 203 }; 204 205 /* 206 * Description of Tx start points for various revisions. 207 */ 208 static const char * const pcn_79c970_xmtsp[] = { 209 "8 bytes", 210 "64 bytes", 211 "128 bytes", 212 "248 bytes", 213 }; 214 215 static const char * const pcn_79c971_xmtsp[] = { 216 "20 bytes", 217 "64 bytes", 218 "128 bytes", 219 "248 bytes", 220 }; 221 222 static const char * const pcn_79c971_xmtsp_sram[] = { 223 "44 bytes", 224 "64 bytes", 225 "128 bytes", 226 "store-and-forward", 227 }; 228 229 /* 230 * Description of Tx FIFO watermarks for various revisions. 231 */ 232 static const char * const pcn_79c970_xmtfw[] = { 233 "16 bytes", 234 "64 bytes", 235 "128 bytes", 236 NULL, 237 }; 238 239 static const char * const pcn_79c971_xmtfw[] = { 240 "16 bytes", 241 "64 bytes", 242 "108 bytes", 243 NULL, 244 }; 245 246 /* 247 * Software state per device. 248 */ 249 struct pcn_softc { 250 struct device sc_dev; /* generic device information */ 251 bus_space_tag_t sc_st; /* bus space tag */ 252 bus_space_handle_t sc_sh; /* bus space handle */ 253 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 254 struct ethercom sc_ethercom; /* Ethernet common data */ 255 void *sc_sdhook; /* shutdown hook */ 256 257 /* Points to our media routines, etc. */ 258 const struct pcn_variant *sc_variant; 259 260 void *sc_ih; /* interrupt cookie */ 261 262 struct mii_data sc_mii; /* MII/media information */ 263 264 struct callout sc_tick_ch; /* tick callout */ 265 266 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 267 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 268 269 /* Software state for transmit and receive descriptors. */ 270 struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN]; 271 struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC]; 272 273 /* Control data structures */ 274 struct pcn_control_data *sc_control_data; 275 #define sc_txdescs sc_control_data->pcd_txdescs 276 #define sc_rxdescs sc_control_data->pcd_rxdescs 277 #define sc_initblock sc_control_data->pcd_initblock 278 279 #ifdef PCN_EVENT_COUNTERS 280 /* Event counters. */ 281 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 282 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 283 struct evcnt sc_ev_txintr; /* Tx interrupts */ 284 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 285 struct evcnt sc_ev_babl; /* BABL in pcn_intr() */ 286 struct evcnt sc_ev_miss; /* MISS in pcn_intr() */ 287 struct evcnt sc_ev_merr; /* MERR in pcn_intr() */ 288 289 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 290 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 291 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 292 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 293 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 294 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 295 struct evcnt sc_ev_txcopy; /* Tx copies required */ 296 #endif /* PCN_EVENT_COUNTERS */ 297 298 const char * const *sc_rcvfw_desc; /* Rx FIFO watermark info */ 299 int sc_rcvfw; 300 301 const char * const *sc_xmtsp_desc; /* Tx start point info */ 302 int sc_xmtsp; 303 304 const char * const *sc_xmtfw_desc; /* Tx FIFO watermark info */ 305 int sc_xmtfw; 306 307 int sc_flags; /* misc. flags; see below */ 308 int sc_swstyle; /* the software style in use */ 309 310 int sc_txfree; /* number of free Tx descriptors */ 311 int sc_txnext; /* next ready Tx descriptor */ 312 313 int sc_txsfree; /* number of free Tx jobs */ 314 int sc_txsnext; /* next free Tx job */ 315 int sc_txsdirty; /* dirty Tx jobs */ 316 317 int sc_rxptr; /* next ready Rx descriptor/job */ 318 319 uint32_t sc_csr5; /* prototype CSR5 register */ 320 uint32_t sc_mode; /* prototype MODE register */ 321 322 #if NRND > 0 323 rndsource_element_t rnd_source; /* random source */ 324 #endif 325 }; 326 327 /* sc_flags */ 328 #define PCN_F_HAS_MII 0x0001 /* has MII */ 329 330 #ifdef PCN_EVENT_COUNTERS 331 #define PCN_EVCNT_INCR(ev) (ev)->ev_count++ 332 #else 333 #define PCN_EVCNT_INCR(ev) /* nothing */ 334 #endif 335 336 #define PCN_CDTXADDR(sc, x) ((sc)->sc_cddma + PCN_CDTXOFF((x))) 337 #define PCN_CDRXADDR(sc, x) ((sc)->sc_cddma + PCN_CDRXOFF((x))) 338 #define PCN_CDINITADDR(sc) ((sc)->sc_cddma + PCN_CDINITOFF) 339 340 #define PCN_CDTXSYNC(sc, x, n, ops) \ 341 do { \ 342 int __x, __n; \ 343 \ 344 __x = (x); \ 345 __n = (n); \ 346 \ 347 /* If it will wrap around, sync to the end of the ring. */ \ 348 if ((__x + __n) > PCN_NTXDESC) { \ 349 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 350 PCN_CDTXOFF(__x), sizeof(struct letmd) * \ 351 (PCN_NTXDESC - __x), (ops)); \ 352 __n -= (PCN_NTXDESC - __x); \ 353 __x = 0; \ 354 } \ 355 \ 356 /* Now sync whatever is left. */ \ 357 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 358 PCN_CDTXOFF(__x), sizeof(struct letmd) * __n, (ops)); \ 359 } while (/*CONSTCOND*/0) 360 361 #define PCN_CDRXSYNC(sc, x, ops) \ 362 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 363 PCN_CDRXOFF((x)), sizeof(struct lermd), (ops)) 364 365 #define PCN_CDINITSYNC(sc, ops) \ 366 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 367 PCN_CDINITOFF, sizeof(struct leinit), (ops)) 368 369 #define PCN_INIT_RXDESC(sc, x) \ 370 do { \ 371 struct pcn_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 372 struct lermd *__rmd = &(sc)->sc_rxdescs[(x)]; \ 373 struct mbuf *__m = __rxs->rxs_mbuf; \ 374 \ 375 /* \ 376 * Note: We scoot the packet forward 2 bytes in the buffer \ 377 * so that the payload after the Ethernet header is aligned \ 378 * to a 4-byte boundary. \ 379 */ \ 380 __m->m_data = __m->m_ext.ext_buf + 2; \ 381 \ 382 if ((sc)->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { \ 383 __rmd->rmd2 = \ 384 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 385 __rmd->rmd0 = 0; \ 386 } else { \ 387 __rmd->rmd2 = 0; \ 388 __rmd->rmd0 = \ 389 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 390 } \ 391 __rmd->rmd1 = htole32(LE_R1_OWN|LE_R1_ONES| \ 392 (LE_BCNT(MCLBYTES - 2) & LE_R1_BCNT_MASK)); \ 393 PCN_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);\ 394 } while(/*CONSTCOND*/0) 395 396 static void pcn_start(struct ifnet *); 397 static void pcn_watchdog(struct ifnet *); 398 static int pcn_ioctl(struct ifnet *, u_long, caddr_t); 399 static int pcn_init(struct ifnet *); 400 static void pcn_stop(struct ifnet *, int); 401 402 static void pcn_shutdown(void *); 403 404 static void pcn_reset(struct pcn_softc *); 405 static void pcn_rxdrain(struct pcn_softc *); 406 static int pcn_add_rxbuf(struct pcn_softc *, int); 407 static void pcn_tick(void *); 408 409 static void pcn_spnd(struct pcn_softc *); 410 411 static void pcn_set_filter(struct pcn_softc *); 412 413 static int pcn_intr(void *); 414 static void pcn_txintr(struct pcn_softc *); 415 static int pcn_rxintr(struct pcn_softc *); 416 417 static int pcn_mii_readreg(struct device *, int, int); 418 static void pcn_mii_writereg(struct device *, int, int, int); 419 static void pcn_mii_statchg(struct device *); 420 421 static void pcn_79c970_mediainit(struct pcn_softc *); 422 static int pcn_79c970_mediachange(struct ifnet *); 423 static void pcn_79c970_mediastatus(struct ifnet *, struct ifmediareq *); 424 425 static void pcn_79c971_mediainit(struct pcn_softc *); 426 static int pcn_79c971_mediachange(struct ifnet *); 427 static void pcn_79c971_mediastatus(struct ifnet *, struct ifmediareq *); 428 429 /* 430 * Description of a PCnet-PCI variant. Used to select media access 431 * method, mostly, and to print a nice description of the chip. 432 */ 433 static const struct pcn_variant { 434 const char *pcv_desc; 435 void (*pcv_mediainit)(struct pcn_softc *); 436 uint16_t pcv_chipid; 437 } pcn_variants[] = { 438 { "Am79c970 PCnet-PCI", 439 pcn_79c970_mediainit, 440 PARTID_Am79c970 }, 441 442 { "Am79c970A PCnet-PCI II", 443 pcn_79c970_mediainit, 444 PARTID_Am79c970A }, 445 446 { "Am79c971 PCnet-FAST", 447 pcn_79c971_mediainit, 448 PARTID_Am79c971 }, 449 450 { "Am79c972 PCnet-FAST+", 451 pcn_79c971_mediainit, 452 PARTID_Am79c972 }, 453 454 { "Am79c973 PCnet-FAST III", 455 pcn_79c971_mediainit, 456 PARTID_Am79c973 }, 457 458 { "Am79c975 PCnet-FAST III", 459 pcn_79c971_mediainit, 460 PARTID_Am79c975 }, 461 462 { "Unknown PCnet-PCI variant", 463 pcn_79c971_mediainit, 464 0 }, 465 }; 466 467 int pcn_copy_small = 0; 468 469 static int pcn_match(struct device *, struct cfdata *, void *); 470 static void pcn_attach(struct device *, struct device *, void *); 471 472 CFATTACH_DECL(pcn, sizeof(struct pcn_softc), 473 pcn_match, pcn_attach, NULL, NULL); 474 475 /* 476 * Routines to read and write the PCnet-PCI CSR/BCR space. 477 */ 478 479 static __inline uint32_t 480 pcn_csr_read(struct pcn_softc *sc, int reg) 481 { 482 483 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 484 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RDP)); 485 } 486 487 static __inline void 488 pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val) 489 { 490 491 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 492 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val); 493 } 494 495 static __inline uint32_t 496 pcn_bcr_read(struct pcn_softc *sc, int reg) 497 { 498 499 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 500 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_BDP)); 501 } 502 503 static __inline void 504 pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val) 505 { 506 507 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 508 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val); 509 } 510 511 static const struct pcn_variant * 512 pcn_lookup_variant(uint16_t chipid) 513 { 514 const struct pcn_variant *pcv; 515 516 for (pcv = pcn_variants; pcv->pcv_chipid != 0; pcv++) { 517 if (chipid == pcv->pcv_chipid) 518 return (pcv); 519 } 520 521 /* 522 * This covers unknown chips, which we simply treat like 523 * a generic PCnet-FAST. 524 */ 525 return (pcv); 526 } 527 528 static int 529 pcn_match(struct device *parent, struct cfdata *cf, void *aux) 530 { 531 struct pci_attach_args *pa = aux; 532 533 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 534 return (0); 535 536 switch (PCI_PRODUCT(pa->pa_id)) { 537 case PCI_PRODUCT_AMD_PCNET_PCI: 538 /* Beat if_le_pci.c */ 539 return (10); 540 } 541 542 return (0); 543 } 544 545 static void 546 pcn_attach(struct device *parent, struct device *self, void *aux) 547 { 548 struct pcn_softc *sc = (struct pcn_softc *) self; 549 struct pci_attach_args *pa = aux; 550 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 551 pci_chipset_tag_t pc = pa->pa_pc; 552 pci_intr_handle_t ih; 553 const char *intrstr = NULL; 554 bus_space_tag_t iot, memt; 555 bus_space_handle_t ioh, memh; 556 bus_dma_segment_t seg; 557 int ioh_valid, memh_valid; 558 int i, rseg, error; 559 pcireg_t pmode; 560 uint32_t chipid, reg; 561 uint8_t enaddr[ETHER_ADDR_LEN]; 562 int pmreg; 563 564 callout_init(&sc->sc_tick_ch); 565 566 printf(": AMD PCnet-PCI Ethernet\n"); 567 568 /* 569 * Map the device. 570 */ 571 ioh_valid = (pci_mapreg_map(pa, PCN_PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 572 &iot, &ioh, NULL, NULL) == 0); 573 memh_valid = (pci_mapreg_map(pa, PCN_PCI_CBMEM, 574 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 575 &memt, &memh, NULL, NULL) == 0); 576 577 if (memh_valid) { 578 sc->sc_st = memt; 579 sc->sc_sh = memh; 580 } else if (ioh_valid) { 581 sc->sc_st = iot; 582 sc->sc_sh = ioh; 583 } else { 584 printf("%s: unable to map device registers\n", 585 sc->sc_dev.dv_xname); 586 return; 587 } 588 589 sc->sc_dmat = pa->pa_dmat; 590 591 /* Make sure bus mastering is enabled. */ 592 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 593 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 594 PCI_COMMAND_MASTER_ENABLE); 595 596 /* Get it out of power save mode, if needed. */ 597 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 598 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 599 PCI_PMCSR_STATE_MASK; 600 if (pmode == PCI_PMCSR_STATE_D3) { 601 /* 602 * The card has lost all configuration data in 603 * this state, so punt. 604 */ 605 printf("%s: unable to wake from power state D3\n", 606 sc->sc_dev.dv_xname); 607 return; 608 } 609 if (pmode != PCI_PMCSR_STATE_D0) { 610 printf("%s: waking up from power date D%d\n", 611 sc->sc_dev.dv_xname, pmode); 612 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 613 PCI_PMCSR_STATE_D0); 614 } 615 } 616 617 /* 618 * Reset the chip to a known state. This also puts the 619 * chip into 32-bit mode. 620 */ 621 pcn_reset(sc); 622 623 #if !defined(PCN_NO_PROM) 624 625 /* 626 * Read the Ethernet address from the EEPROM. 627 */ 628 for (i = 0; i < ETHER_ADDR_LEN; i++) 629 enaddr[i] = bus_space_read_1(sc->sc_st, sc->sc_sh, 630 PCN32_APROM + i); 631 #else 632 /* 633 * The PROM is not used; instead we assume that the MAC address 634 * has been programmed into the device's physical address 635 * registers by the boot firmware 636 */ 637 638 for (i=0; i < 3; i++) { 639 uint32_t val; 640 val = pcn_csr_read(sc, LE_CSR12 + i); 641 enaddr[2*i] = val & 0x0ff; 642 enaddr[2*i+1] = (val >> 8) & 0x0ff; 643 } 644 #endif 645 646 /* 647 * Now that the device is mapped, attempt to figure out what 648 * kind of chip we have. Note that IDL has all 32 bits of 649 * the chip ID when we're in 32-bit mode. 650 */ 651 chipid = pcn_csr_read(sc, LE_CSR88); 652 sc->sc_variant = pcn_lookup_variant(CHIPID_PARTID(chipid)); 653 654 printf("%s: %s rev %d, Ethernet address %s\n", 655 sc->sc_dev.dv_xname, sc->sc_variant->pcv_desc, CHIPID_VER(chipid), 656 ether_sprintf(enaddr)); 657 658 /* 659 * Map and establish our interrupt. 660 */ 661 if (pci_intr_map(pa, &ih)) { 662 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 663 return; 664 } 665 intrstr = pci_intr_string(pc, ih); 666 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, pcn_intr, sc); 667 if (sc->sc_ih == NULL) { 668 printf("%s: unable to establish interrupt", 669 sc->sc_dev.dv_xname); 670 if (intrstr != NULL) 671 printf(" at %s", intrstr); 672 printf("\n"); 673 return; 674 } 675 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 676 677 /* 678 * Allocate the control data structures, and create and load the 679 * DMA map for it. 680 */ 681 if ((error = bus_dmamem_alloc(sc->sc_dmat, 682 sizeof(struct pcn_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 683 0)) != 0) { 684 printf("%s: unable to allocate control data, error = %d\n", 685 sc->sc_dev.dv_xname, error); 686 goto fail_0; 687 } 688 689 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 690 sizeof(struct pcn_control_data), (caddr_t *)&sc->sc_control_data, 691 BUS_DMA_COHERENT)) != 0) { 692 printf("%s: unable to map control data, error = %d\n", 693 sc->sc_dev.dv_xname, error); 694 goto fail_1; 695 } 696 697 if ((error = bus_dmamap_create(sc->sc_dmat, 698 sizeof(struct pcn_control_data), 1, 699 sizeof(struct pcn_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 700 printf("%s: unable to create control data DMA map, " 701 "error = %d\n", sc->sc_dev.dv_xname, error); 702 goto fail_2; 703 } 704 705 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 706 sc->sc_control_data, sizeof(struct pcn_control_data), NULL, 707 0)) != 0) { 708 printf("%s: unable to load control data DMA map, error = %d\n", 709 sc->sc_dev.dv_xname, error); 710 goto fail_3; 711 } 712 713 /* Create the transmit buffer DMA maps. */ 714 for (i = 0; i < PCN_TXQUEUELEN; i++) { 715 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 716 PCN_NTXSEGS, MCLBYTES, 0, 0, 717 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 718 printf("%s: unable to create tx DMA map %d, " 719 "error = %d\n", sc->sc_dev.dv_xname, i, error); 720 goto fail_4; 721 } 722 } 723 724 /* Create the receive buffer DMA maps. */ 725 for (i = 0; i < PCN_NRXDESC; i++) { 726 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 727 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 728 printf("%s: unable to create rx DMA map %d, " 729 "error = %d\n", sc->sc_dev.dv_xname, i, error); 730 goto fail_5; 731 } 732 sc->sc_rxsoft[i].rxs_mbuf = NULL; 733 } 734 735 /* Initialize our media structures. */ 736 (*sc->sc_variant->pcv_mediainit)(sc); 737 738 /* 739 * Initialize FIFO watermark info. 740 */ 741 switch (sc->sc_variant->pcv_chipid) { 742 case PARTID_Am79c970: 743 case PARTID_Am79c970A: 744 sc->sc_rcvfw_desc = pcn_79c970_rcvfw; 745 sc->sc_xmtsp_desc = pcn_79c970_xmtsp; 746 sc->sc_xmtfw_desc = pcn_79c970_xmtfw; 747 break; 748 749 default: 750 sc->sc_rcvfw_desc = pcn_79c971_rcvfw; 751 /* 752 * Read BCR25 to determine how much SRAM is 753 * on the board. If > 0, then we the chip 754 * uses different Start Point thresholds. 755 * 756 * Note BCR25 and BCR26 are loaded from the 757 * EEPROM on RST, and unaffected by S_RESET, 758 * so we don't really have to worry about 759 * them except for this. 760 */ 761 reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff; 762 if (reg != 0) 763 sc->sc_xmtsp_desc = pcn_79c971_xmtsp_sram; 764 else 765 sc->sc_xmtsp_desc = pcn_79c971_xmtsp; 766 sc->sc_xmtfw_desc = pcn_79c971_xmtfw; 767 break; 768 } 769 770 /* 771 * Set up defaults -- see the tables above for what these 772 * values mean. 773 * 774 * XXX How should we tune RCVFW and XMTFW? 775 */ 776 sc->sc_rcvfw = 1; /* minimum for full-duplex */ 777 sc->sc_xmtsp = 1; 778 sc->sc_xmtfw = 0; 779 780 ifp = &sc->sc_ethercom.ec_if; 781 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 782 ifp->if_softc = sc; 783 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 784 ifp->if_ioctl = pcn_ioctl; 785 ifp->if_start = pcn_start; 786 ifp->if_watchdog = pcn_watchdog; 787 ifp->if_init = pcn_init; 788 ifp->if_stop = pcn_stop; 789 IFQ_SET_READY(&ifp->if_snd); 790 791 /* Attach the interface. */ 792 if_attach(ifp); 793 ether_ifattach(ifp, enaddr); 794 #if NRND > 0 795 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 796 RND_TYPE_NET, 0); 797 #endif 798 799 #ifdef PCN_EVENT_COUNTERS 800 /* Attach event counters. */ 801 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 802 NULL, sc->sc_dev.dv_xname, "txsstall"); 803 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 804 NULL, sc->sc_dev.dv_xname, "txdstall"); 805 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 806 NULL, sc->sc_dev.dv_xname, "txintr"); 807 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 808 NULL, sc->sc_dev.dv_xname, "rxintr"); 809 evcnt_attach_dynamic(&sc->sc_ev_babl, EVCNT_TYPE_MISC, 810 NULL, sc->sc_dev.dv_xname, "babl"); 811 evcnt_attach_dynamic(&sc->sc_ev_miss, EVCNT_TYPE_MISC, 812 NULL, sc->sc_dev.dv_xname, "miss"); 813 evcnt_attach_dynamic(&sc->sc_ev_merr, EVCNT_TYPE_MISC, 814 NULL, sc->sc_dev.dv_xname, "merr"); 815 816 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 817 NULL, sc->sc_dev.dv_xname, "txseg1"); 818 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 819 NULL, sc->sc_dev.dv_xname, "txseg2"); 820 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 821 NULL, sc->sc_dev.dv_xname, "txseg3"); 822 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 823 NULL, sc->sc_dev.dv_xname, "txseg4"); 824 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 825 NULL, sc->sc_dev.dv_xname, "txseg5"); 826 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 827 NULL, sc->sc_dev.dv_xname, "txsegmore"); 828 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 829 NULL, sc->sc_dev.dv_xname, "txcopy"); 830 #endif /* PCN_EVENT_COUNTERS */ 831 832 /* Make sure the interface is shutdown during reboot. */ 833 sc->sc_sdhook = shutdownhook_establish(pcn_shutdown, sc); 834 if (sc->sc_sdhook == NULL) 835 printf("%s: WARNING: unable to establish shutdown hook\n", 836 sc->sc_dev.dv_xname); 837 return; 838 839 /* 840 * Free any resources we've allocated during the failed attach 841 * attempt. Do this in reverse order and fall through. 842 */ 843 fail_5: 844 for (i = 0; i < PCN_NRXDESC; i++) { 845 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 846 bus_dmamap_destroy(sc->sc_dmat, 847 sc->sc_rxsoft[i].rxs_dmamap); 848 } 849 fail_4: 850 for (i = 0; i < PCN_TXQUEUELEN; i++) { 851 if (sc->sc_txsoft[i].txs_dmamap != NULL) 852 bus_dmamap_destroy(sc->sc_dmat, 853 sc->sc_txsoft[i].txs_dmamap); 854 } 855 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 856 fail_3: 857 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 858 fail_2: 859 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 860 sizeof(struct pcn_control_data)); 861 fail_1: 862 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 863 fail_0: 864 return; 865 } 866 867 /* 868 * pcn_shutdown: 869 * 870 * Make sure the interface is stopped at reboot time. 871 */ 872 static void 873 pcn_shutdown(void *arg) 874 { 875 struct pcn_softc *sc = arg; 876 877 pcn_stop(&sc->sc_ethercom.ec_if, 1); 878 } 879 880 /* 881 * pcn_start: [ifnet interface function] 882 * 883 * Start packet transmission on the interface. 884 */ 885 static void 886 pcn_start(struct ifnet *ifp) 887 { 888 struct pcn_softc *sc = ifp->if_softc; 889 struct mbuf *m0, *m; 890 struct pcn_txsoft *txs; 891 bus_dmamap_t dmamap; 892 int error, nexttx, lasttx = -1, ofree, seg; 893 894 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 895 return; 896 897 /* 898 * Remember the previous number of free descriptors and 899 * the first descriptor we'll use. 900 */ 901 ofree = sc->sc_txfree; 902 903 /* 904 * Loop through the send queue, setting up transmit descriptors 905 * until we drain the queue, or use up all available transmit 906 * descriptors. 907 */ 908 for (;;) { 909 /* Grab a packet off the queue. */ 910 IFQ_POLL(&ifp->if_snd, m0); 911 if (m0 == NULL) 912 break; 913 m = NULL; 914 915 /* Get a work queue entry. */ 916 if (sc->sc_txsfree == 0) { 917 PCN_EVCNT_INCR(&sc->sc_ev_txsstall); 918 break; 919 } 920 921 txs = &sc->sc_txsoft[sc->sc_txsnext]; 922 dmamap = txs->txs_dmamap; 923 924 /* 925 * Load the DMA map. If this fails, the packet either 926 * didn't fit in the alloted number of segments, or we 927 * were short on resources. In this case, we'll copy 928 * and try again. 929 */ 930 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 931 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 932 PCN_EVCNT_INCR(&sc->sc_ev_txcopy); 933 MGETHDR(m, M_DONTWAIT, MT_DATA); 934 if (m == NULL) { 935 printf("%s: unable to allocate Tx mbuf\n", 936 sc->sc_dev.dv_xname); 937 break; 938 } 939 if (m0->m_pkthdr.len > MHLEN) { 940 MCLGET(m, M_DONTWAIT); 941 if ((m->m_flags & M_EXT) == 0) { 942 printf("%s: unable to allocate Tx " 943 "cluster\n", sc->sc_dev.dv_xname); 944 m_freem(m); 945 break; 946 } 947 } 948 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 949 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 950 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 951 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 952 if (error) { 953 printf("%s: unable to load Tx buffer, " 954 "error = %d\n", sc->sc_dev.dv_xname, error); 955 break; 956 } 957 } 958 959 /* 960 * Ensure we have enough descriptors free to describe 961 * the packet. Note, we always reserve one descriptor 962 * at the end of the ring as a termination point, to 963 * prevent wrap-around. 964 */ 965 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 966 /* 967 * Not enough free descriptors to transmit this 968 * packet. We haven't committed anything yet, 969 * so just unload the DMA map, put the packet 970 * back on the queue, and punt. Notify the upper 971 * layer that there are not more slots left. 972 * 973 * XXX We could allocate an mbuf and copy, but 974 * XXX is it worth it? 975 */ 976 ifp->if_flags |= IFF_OACTIVE; 977 bus_dmamap_unload(sc->sc_dmat, dmamap); 978 if (m != NULL) 979 m_freem(m); 980 PCN_EVCNT_INCR(&sc->sc_ev_txdstall); 981 break; 982 } 983 984 IFQ_DEQUEUE(&ifp->if_snd, m0); 985 if (m != NULL) { 986 m_freem(m0); 987 m0 = m; 988 } 989 990 /* 991 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 992 */ 993 994 /* Sync the DMA map. */ 995 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 996 BUS_DMASYNC_PREWRITE); 997 998 #ifdef PCN_EVENT_COUNTERS 999 switch (dmamap->dm_nsegs) { 1000 case 1: 1001 PCN_EVCNT_INCR(&sc->sc_ev_txseg1); 1002 break; 1003 case 2: 1004 PCN_EVCNT_INCR(&sc->sc_ev_txseg2); 1005 break; 1006 case 3: 1007 PCN_EVCNT_INCR(&sc->sc_ev_txseg3); 1008 break; 1009 case 4: 1010 PCN_EVCNT_INCR(&sc->sc_ev_txseg4); 1011 break; 1012 case 5: 1013 PCN_EVCNT_INCR(&sc->sc_ev_txseg5); 1014 break; 1015 default: 1016 PCN_EVCNT_INCR(&sc->sc_ev_txsegmore); 1017 break; 1018 } 1019 #endif /* PCN_EVENT_COUNTERS */ 1020 1021 /* 1022 * Initialize the transmit descriptors. 1023 */ 1024 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { 1025 for (nexttx = sc->sc_txnext, seg = 0; 1026 seg < dmamap->dm_nsegs; 1027 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1028 /* 1029 * If this is the first descriptor we're 1030 * enqueueing, don't set the OWN bit just 1031 * yet. That could cause a race condition. 1032 * We'll do it below. 1033 */ 1034 sc->sc_txdescs[nexttx].tmd0 = 0; 1035 sc->sc_txdescs[nexttx].tmd2 = 1036 htole32(dmamap->dm_segs[seg].ds_addr); 1037 sc->sc_txdescs[nexttx].tmd1 = 1038 htole32(LE_T1_ONES | 1039 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1040 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1041 LE_T1_BCNT_MASK)); 1042 lasttx = nexttx; 1043 } 1044 } else { 1045 for (nexttx = sc->sc_txnext, seg = 0; 1046 seg < dmamap->dm_nsegs; 1047 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1048 /* 1049 * If this is the first descriptor we're 1050 * enqueueing, don't set the OWN bit just 1051 * yet. That could cause a race condition. 1052 * We'll do it below. 1053 */ 1054 sc->sc_txdescs[nexttx].tmd0 = 1055 htole32(dmamap->dm_segs[seg].ds_addr); 1056 sc->sc_txdescs[nexttx].tmd2 = 0; 1057 sc->sc_txdescs[nexttx].tmd1 = 1058 htole32(LE_T1_ONES | 1059 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1060 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1061 LE_T1_BCNT_MASK)); 1062 lasttx = nexttx; 1063 } 1064 } 1065 1066 KASSERT(lasttx != -1); 1067 /* Interrupt on the packet, if appropriate. */ 1068 if ((sc->sc_txsnext & PCN_TXINTR_MASK) == 0) 1069 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT); 1070 1071 /* Set `start of packet' and `end of packet' appropriately. */ 1072 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP); 1073 sc->sc_txdescs[sc->sc_txnext].tmd1 |= 1074 htole32(LE_T1_OWN|LE_T1_STP); 1075 1076 /* Sync the descriptors we're using. */ 1077 PCN_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1078 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1079 1080 /* Kick the transmitter. */ 1081 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_TDMD); 1082 1083 /* 1084 * Store a pointer to the packet so we can free it later, 1085 * and remember what txdirty will be once the packet is 1086 * done. 1087 */ 1088 txs->txs_mbuf = m0; 1089 txs->txs_firstdesc = sc->sc_txnext; 1090 txs->txs_lastdesc = lasttx; 1091 1092 /* Advance the tx pointer. */ 1093 sc->sc_txfree -= dmamap->dm_nsegs; 1094 sc->sc_txnext = nexttx; 1095 1096 sc->sc_txsfree--; 1097 sc->sc_txsnext = PCN_NEXTTXS(sc->sc_txsnext); 1098 1099 #if NBPFILTER > 0 1100 /* Pass the packet to any BPF listeners. */ 1101 if (ifp->if_bpf) 1102 bpf_mtap(ifp->if_bpf, m0); 1103 #endif /* NBPFILTER > 0 */ 1104 } 1105 1106 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1107 /* No more slots left; notify upper layer. */ 1108 ifp->if_flags |= IFF_OACTIVE; 1109 } 1110 1111 if (sc->sc_txfree != ofree) { 1112 /* Set a watchdog timer in case the chip flakes out. */ 1113 ifp->if_timer = 5; 1114 } 1115 } 1116 1117 /* 1118 * pcn_watchdog: [ifnet interface function] 1119 * 1120 * Watchdog timer handler. 1121 */ 1122 static void 1123 pcn_watchdog(struct ifnet *ifp) 1124 { 1125 struct pcn_softc *sc = ifp->if_softc; 1126 1127 /* 1128 * Since we're not interrupting every packet, sweep 1129 * up before we report an error. 1130 */ 1131 pcn_txintr(sc); 1132 1133 if (sc->sc_txfree != PCN_NTXDESC) { 1134 printf("%s: device timeout (txfree %d txsfree %d)\n", 1135 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree); 1136 ifp->if_oerrors++; 1137 1138 /* Reset the interface. */ 1139 (void) pcn_init(ifp); 1140 } 1141 1142 /* Try to get more packets going. */ 1143 pcn_start(ifp); 1144 } 1145 1146 /* 1147 * pcn_ioctl: [ifnet interface function] 1148 * 1149 * Handle control requests from the operator. 1150 */ 1151 static int 1152 pcn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1153 { 1154 struct pcn_softc *sc = ifp->if_softc; 1155 struct ifreq *ifr = (struct ifreq *) data; 1156 int s, error; 1157 1158 s = splnet(); 1159 1160 switch (cmd) { 1161 case SIOCSIFMEDIA: 1162 case SIOCGIFMEDIA: 1163 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1164 break; 1165 1166 default: 1167 error = ether_ioctl(ifp, cmd, data); 1168 if (error == ENETRESET) { 1169 /* 1170 * Multicast list has changed; set the hardware filter 1171 * accordingly. 1172 */ 1173 if (ifp->if_flags & IFF_RUNNING) 1174 error = pcn_init(ifp); 1175 else 1176 error = 0; 1177 } 1178 break; 1179 } 1180 1181 /* Try to get more packets going. */ 1182 pcn_start(ifp); 1183 1184 splx(s); 1185 return (error); 1186 } 1187 1188 /* 1189 * pcn_intr: 1190 * 1191 * Interrupt service routine. 1192 */ 1193 static int 1194 pcn_intr(void *arg) 1195 { 1196 struct pcn_softc *sc = arg; 1197 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1198 uint32_t csr0; 1199 int wantinit, handled = 0; 1200 1201 for (wantinit = 0; wantinit == 0;) { 1202 csr0 = pcn_csr_read(sc, LE_CSR0); 1203 if ((csr0 & LE_C0_INTR) == 0) 1204 break; 1205 1206 #if NRND > 0 1207 if (RND_ENABLED(&sc->rnd_source)) 1208 rnd_add_uint32(&sc->rnd_source, csr0); 1209 #endif 1210 1211 /* ACK the bits and re-enable interrupts. */ 1212 pcn_csr_write(sc, LE_CSR0, csr0 & 1213 (LE_C0_INEA|LE_C0_BABL|LE_C0_MISS|LE_C0_MERR|LE_C0_RINT| 1214 LE_C0_TINT|LE_C0_IDON)); 1215 1216 handled = 1; 1217 1218 if (csr0 & LE_C0_RINT) { 1219 PCN_EVCNT_INCR(&sc->sc_ev_rxintr); 1220 wantinit = pcn_rxintr(sc); 1221 } 1222 1223 if (csr0 & LE_C0_TINT) { 1224 PCN_EVCNT_INCR(&sc->sc_ev_txintr); 1225 pcn_txintr(sc); 1226 } 1227 1228 if (csr0 & LE_C0_ERR) { 1229 if (csr0 & LE_C0_BABL) { 1230 PCN_EVCNT_INCR(&sc->sc_ev_babl); 1231 ifp->if_oerrors++; 1232 } 1233 if (csr0 & LE_C0_MISS) { 1234 PCN_EVCNT_INCR(&sc->sc_ev_miss); 1235 ifp->if_ierrors++; 1236 } 1237 if (csr0 & LE_C0_MERR) { 1238 PCN_EVCNT_INCR(&sc->sc_ev_merr); 1239 printf("%s: memory error\n", 1240 sc->sc_dev.dv_xname); 1241 wantinit = 1; 1242 break; 1243 } 1244 } 1245 1246 if ((csr0 & LE_C0_RXON) == 0) { 1247 printf("%s: receiver disabled\n", 1248 sc->sc_dev.dv_xname); 1249 ifp->if_ierrors++; 1250 wantinit = 1; 1251 } 1252 1253 if ((csr0 & LE_C0_TXON) == 0) { 1254 printf("%s: transmitter disabled\n", 1255 sc->sc_dev.dv_xname); 1256 ifp->if_oerrors++; 1257 wantinit = 1; 1258 } 1259 } 1260 1261 if (handled) { 1262 if (wantinit) 1263 pcn_init(ifp); 1264 1265 /* Try to get more packets going. */ 1266 pcn_start(ifp); 1267 } 1268 1269 return (handled); 1270 } 1271 1272 /* 1273 * pcn_spnd: 1274 * 1275 * Suspend the chip. 1276 */ 1277 static void 1278 pcn_spnd(struct pcn_softc *sc) 1279 { 1280 int i; 1281 1282 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5 | LE_C5_SPND); 1283 1284 for (i = 0; i < 10000; i++) { 1285 if (pcn_csr_read(sc, LE_CSR5) & LE_C5_SPND) 1286 return; 1287 delay(5); 1288 } 1289 1290 printf("%s: WARNING: chip failed to enter suspended state\n", 1291 sc->sc_dev.dv_xname); 1292 } 1293 1294 /* 1295 * pcn_txintr: 1296 * 1297 * Helper; handle transmit interrupts. 1298 */ 1299 static void 1300 pcn_txintr(struct pcn_softc *sc) 1301 { 1302 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1303 struct pcn_txsoft *txs; 1304 uint32_t tmd1, tmd2, tmd; 1305 int i, j; 1306 1307 ifp->if_flags &= ~IFF_OACTIVE; 1308 1309 /* 1310 * Go through our Tx list and free mbufs for those 1311 * frames which have been transmitted. 1312 */ 1313 for (i = sc->sc_txsdirty; sc->sc_txsfree != PCN_TXQUEUELEN; 1314 i = PCN_NEXTTXS(i), sc->sc_txsfree++) { 1315 txs = &sc->sc_txsoft[i]; 1316 1317 PCN_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1318 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1319 1320 tmd1 = le32toh(sc->sc_txdescs[txs->txs_lastdesc].tmd1); 1321 if (tmd1 & LE_T1_OWN) 1322 break; 1323 1324 /* 1325 * Slightly annoying -- we have to loop through the 1326 * descriptors we've used looking for ERR, since it 1327 * can appear on any descriptor in the chain. 1328 */ 1329 for (j = txs->txs_firstdesc;; j = PCN_NEXTTX(j)) { 1330 tmd = le32toh(sc->sc_txdescs[j].tmd1); 1331 if (tmd & LE_T1_ERR) { 1332 ifp->if_oerrors++; 1333 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1334 tmd2 = le32toh(sc->sc_txdescs[j].tmd0); 1335 else 1336 tmd2 = le32toh(sc->sc_txdescs[j].tmd2); 1337 if (tmd2 & LE_T2_UFLO) { 1338 if (sc->sc_xmtsp < LE_C80_XMTSP_MAX) { 1339 sc->sc_xmtsp++; 1340 printf("%s: transmit " 1341 "underrun; new threshold: " 1342 "%s\n", 1343 sc->sc_dev.dv_xname, 1344 sc->sc_xmtsp_desc[ 1345 sc->sc_xmtsp]); 1346 pcn_spnd(sc); 1347 pcn_csr_write(sc, LE_CSR80, 1348 LE_C80_RCVFW(sc->sc_rcvfw) | 1349 LE_C80_XMTSP(sc->sc_xmtsp) | 1350 LE_C80_XMTFW(sc->sc_xmtfw)); 1351 pcn_csr_write(sc, LE_CSR5, 1352 sc->sc_csr5); 1353 } else { 1354 printf("%s: transmit " 1355 "underrun\n", 1356 sc->sc_dev.dv_xname); 1357 } 1358 } else if (tmd2 & LE_T2_BUFF) { 1359 printf("%s: transmit buffer error\n", 1360 sc->sc_dev.dv_xname); 1361 } 1362 if (tmd2 & LE_T2_LCOL) 1363 ifp->if_collisions++; 1364 if (tmd2 & LE_T2_RTRY) 1365 ifp->if_collisions += 16; 1366 goto next_packet; 1367 } 1368 if (j == txs->txs_lastdesc) 1369 break; 1370 } 1371 if (tmd1 & LE_T1_ONE) 1372 ifp->if_collisions++; 1373 else if (tmd & LE_T1_MORE) { 1374 /* Real number is unknown. */ 1375 ifp->if_collisions += 2; 1376 } 1377 ifp->if_opackets++; 1378 next_packet: 1379 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1380 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1381 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1382 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1383 m_freem(txs->txs_mbuf); 1384 txs->txs_mbuf = NULL; 1385 } 1386 1387 /* Update the dirty transmit buffer pointer. */ 1388 sc->sc_txsdirty = i; 1389 1390 /* 1391 * If there are no more pending transmissions, cancel the watchdog 1392 * timer. 1393 */ 1394 if (sc->sc_txsfree == PCN_TXQUEUELEN) 1395 ifp->if_timer = 0; 1396 } 1397 1398 /* 1399 * pcn_rxintr: 1400 * 1401 * Helper; handle receive interrupts. 1402 */ 1403 static int 1404 pcn_rxintr(struct pcn_softc *sc) 1405 { 1406 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1407 struct pcn_rxsoft *rxs; 1408 struct mbuf *m; 1409 uint32_t rmd1; 1410 int i, len; 1411 1412 for (i = sc->sc_rxptr;; i = PCN_NEXTRX(i)) { 1413 rxs = &sc->sc_rxsoft[i]; 1414 1415 PCN_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1416 1417 rmd1 = le32toh(sc->sc_rxdescs[i].rmd1); 1418 1419 if (rmd1 & LE_R1_OWN) 1420 break; 1421 1422 /* 1423 * Check for errors and make sure the packet fit into 1424 * a single buffer. We have structured this block of 1425 * code the way it is in order to compress it into 1426 * one test in the common case (no error). 1427 */ 1428 if (__predict_false((rmd1 & (LE_R1_STP|LE_R1_ENP|LE_R1_ERR)) != 1429 (LE_R1_STP|LE_R1_ENP))) { 1430 /* Make sure the packet is in a single buffer. */ 1431 if ((rmd1 & (LE_R1_STP|LE_R1_ENP)) != 1432 (LE_R1_STP|LE_R1_ENP)) { 1433 printf("%s: packet spilled into next buffer\n", 1434 sc->sc_dev.dv_xname); 1435 return (1); /* pcn_intr() will re-init */ 1436 } 1437 1438 /* 1439 * If the packet had an error, simple recycle the 1440 * buffer. 1441 */ 1442 if (rmd1 & LE_R1_ERR) { 1443 ifp->if_ierrors++; 1444 /* 1445 * If we got an overflow error, chances 1446 * are there will be a CRC error. In 1447 * this case, just print the overflow 1448 * error, and skip the others. 1449 */ 1450 if (rmd1 & LE_R1_OFLO) 1451 printf("%s: overflow error\n", 1452 sc->sc_dev.dv_xname); 1453 else { 1454 #define PRINTIT(x, str) \ 1455 if (rmd1 & (x)) \ 1456 printf("%s: %s\n", \ 1457 sc->sc_dev.dv_xname, str); 1458 PRINTIT(LE_R1_FRAM, "framing error"); 1459 PRINTIT(LE_R1_CRC, "CRC error"); 1460 PRINTIT(LE_R1_BUFF, "buffer error"); 1461 } 1462 #undef PRINTIT 1463 PCN_INIT_RXDESC(sc, i); 1464 continue; 1465 } 1466 } 1467 1468 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1469 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1470 1471 /* 1472 * No errors; receive the packet. 1473 */ 1474 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1475 len = le32toh(sc->sc_rxdescs[i].rmd0) & LE_R1_BCNT_MASK; 1476 else 1477 len = le32toh(sc->sc_rxdescs[i].rmd2) & LE_R1_BCNT_MASK; 1478 1479 /* 1480 * The LANCE family includes the CRC with every packet; 1481 * trim it off here. 1482 */ 1483 len -= ETHER_CRC_LEN; 1484 1485 /* 1486 * If the packet is small enough to fit in a 1487 * single header mbuf, allocate one and copy 1488 * the data into it. This greatly reduces 1489 * memory consumption when we receive lots 1490 * of small packets. 1491 * 1492 * Otherwise, we add a new buffer to the receive 1493 * chain. If this fails, we drop the packet and 1494 * recycle the old buffer. 1495 */ 1496 if (pcn_copy_small != 0 && len <= (MHLEN - 2)) { 1497 MGETHDR(m, M_DONTWAIT, MT_DATA); 1498 if (m == NULL) 1499 goto dropit; 1500 m->m_data += 2; 1501 memcpy(mtod(m, caddr_t), 1502 mtod(rxs->rxs_mbuf, caddr_t), len); 1503 PCN_INIT_RXDESC(sc, i); 1504 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1505 rxs->rxs_dmamap->dm_mapsize, 1506 BUS_DMASYNC_PREREAD); 1507 } else { 1508 m = rxs->rxs_mbuf; 1509 if (pcn_add_rxbuf(sc, i) != 0) { 1510 dropit: 1511 ifp->if_ierrors++; 1512 PCN_INIT_RXDESC(sc, i); 1513 bus_dmamap_sync(sc->sc_dmat, 1514 rxs->rxs_dmamap, 0, 1515 rxs->rxs_dmamap->dm_mapsize, 1516 BUS_DMASYNC_PREREAD); 1517 continue; 1518 } 1519 } 1520 1521 m->m_pkthdr.rcvif = ifp; 1522 m->m_pkthdr.len = m->m_len = len; 1523 1524 #if NBPFILTER > 0 1525 /* Pass this up to any BPF listeners. */ 1526 if (ifp->if_bpf) 1527 bpf_mtap(ifp->if_bpf, m); 1528 #endif /* NBPFILTER > 0 */ 1529 1530 /* Pass it on. */ 1531 (*ifp->if_input)(ifp, m); 1532 ifp->if_ipackets++; 1533 } 1534 1535 /* Update the receive pointer. */ 1536 sc->sc_rxptr = i; 1537 return (0); 1538 } 1539 1540 /* 1541 * pcn_tick: 1542 * 1543 * One second timer, used to tick the MII. 1544 */ 1545 static void 1546 pcn_tick(void *arg) 1547 { 1548 struct pcn_softc *sc = arg; 1549 int s; 1550 1551 s = splnet(); 1552 mii_tick(&sc->sc_mii); 1553 splx(s); 1554 1555 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1556 } 1557 1558 /* 1559 * pcn_reset: 1560 * 1561 * Perform a soft reset on the PCnet-PCI. 1562 */ 1563 static void 1564 pcn_reset(struct pcn_softc *sc) 1565 { 1566 1567 /* 1568 * The PCnet-PCI chip is reset by reading from the 1569 * RESET register. Note that while the NE2100 LANCE 1570 * boards require a write after the read, the PCnet-PCI 1571 * chips do not require this. 1572 * 1573 * Since we don't know if we're in 16-bit or 32-bit 1574 * mode right now, issue both (it's safe) in the 1575 * hopes that one will succeed. 1576 */ 1577 (void) bus_space_read_2(sc->sc_st, sc->sc_sh, PCN16_RESET); 1578 (void) bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RESET); 1579 1580 /* Wait 1ms for it to finish. */ 1581 delay(1000); 1582 1583 /* 1584 * Select 32-bit I/O mode by issuing a 32-bit write to the 1585 * RDP. Since the RAP is 0 after a reset, writing a 0 1586 * to RDP is safe (since it simply clears CSR0). 1587 */ 1588 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, 0); 1589 } 1590 1591 /* 1592 * pcn_init: [ifnet interface function] 1593 * 1594 * Initialize the interface. Must be called at splnet(). 1595 */ 1596 static int 1597 pcn_init(struct ifnet *ifp) 1598 { 1599 struct pcn_softc *sc = ifp->if_softc; 1600 struct pcn_rxsoft *rxs; 1601 uint8_t *enaddr = LLADDR(ifp->if_sadl); 1602 int i, error = 0; 1603 uint32_t reg; 1604 1605 /* Cancel any pending I/O. */ 1606 pcn_stop(ifp, 0); 1607 1608 /* Reset the chip to a known state. */ 1609 pcn_reset(sc); 1610 1611 /* 1612 * On the Am79c970, select SSTYLE 2, and SSTYLE 3 on everything 1613 * else. 1614 * 1615 * XXX It'd be really nice to use SSTYLE 2 on all the chips, 1616 * because the structure layout is compatible with ILACC, 1617 * but the burst mode is only available in SSTYLE 3, and 1618 * burst mode should provide some performance enhancement. 1619 */ 1620 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970) 1621 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI2; 1622 else 1623 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI3; 1624 pcn_bcr_write(sc, LE_BCR20, sc->sc_swstyle); 1625 1626 /* Initialize the transmit descriptor ring. */ 1627 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1628 PCN_CDTXSYNC(sc, 0, PCN_NTXDESC, 1629 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1630 sc->sc_txfree = PCN_NTXDESC; 1631 sc->sc_txnext = 0; 1632 1633 /* Initialize the transmit job descriptors. */ 1634 for (i = 0; i < PCN_TXQUEUELEN; i++) 1635 sc->sc_txsoft[i].txs_mbuf = NULL; 1636 sc->sc_txsfree = PCN_TXQUEUELEN; 1637 sc->sc_txsnext = 0; 1638 sc->sc_txsdirty = 0; 1639 1640 /* 1641 * Initialize the receive descriptor and receive job 1642 * descriptor rings. 1643 */ 1644 for (i = 0; i < PCN_NRXDESC; i++) { 1645 rxs = &sc->sc_rxsoft[i]; 1646 if (rxs->rxs_mbuf == NULL) { 1647 if ((error = pcn_add_rxbuf(sc, i)) != 0) { 1648 printf("%s: unable to allocate or map rx " 1649 "buffer %d, error = %d\n", 1650 sc->sc_dev.dv_xname, i, error); 1651 /* 1652 * XXX Should attempt to run with fewer receive 1653 * XXX buffers instead of just failing. 1654 */ 1655 pcn_rxdrain(sc); 1656 goto out; 1657 } 1658 } else 1659 PCN_INIT_RXDESC(sc, i); 1660 } 1661 sc->sc_rxptr = 0; 1662 1663 /* Initialize MODE for the initialization block. */ 1664 sc->sc_mode = 0; 1665 if (ifp->if_flags & IFF_PROMISC) 1666 sc->sc_mode |= LE_C15_PROM; 1667 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1668 sc->sc_mode |= LE_C15_DRCVBC; 1669 1670 /* 1671 * If we have MII, simply select MII in the MODE register, 1672 * and clear ASEL. Otherwise, let ASEL stand (for now), 1673 * and leave PORTSEL alone (it is ignored with ASEL is set). 1674 */ 1675 if (sc->sc_flags & PCN_F_HAS_MII) { 1676 pcn_bcr_write(sc, LE_BCR2, 1677 pcn_bcr_read(sc, LE_BCR2) & ~LE_B2_ASEL); 1678 sc->sc_mode |= LE_C15_PORTSEL(PORTSEL_MII); 1679 1680 /* 1681 * Disable MII auto-negotiation. We handle that in 1682 * our own MII layer. 1683 */ 1684 pcn_bcr_write(sc, LE_BCR32, 1685 pcn_bcr_read(sc, LE_BCR32) | LE_B32_DANAS); 1686 } 1687 1688 /* 1689 * Set the Tx and Rx descriptor ring addresses in the init 1690 * block, the TLEN and RLEN other fields of the init block 1691 * MODE register. 1692 */ 1693 sc->sc_initblock.init_rdra = htole32(PCN_CDRXADDR(sc, 0)); 1694 sc->sc_initblock.init_tdra = htole32(PCN_CDTXADDR(sc, 0)); 1695 sc->sc_initblock.init_mode = htole32(sc->sc_mode | 1696 ((ffs(PCN_NTXDESC) - 1) << 28) | 1697 ((ffs(PCN_NRXDESC) - 1) << 20)); 1698 1699 /* Set the station address in the init block. */ 1700 sc->sc_initblock.init_padr[0] = htole32(enaddr[0] | 1701 (enaddr[1] << 8) | (enaddr[2] << 16) | (enaddr[3] << 24)); 1702 sc->sc_initblock.init_padr[1] = htole32(enaddr[4] | 1703 (enaddr[5] << 8)); 1704 1705 /* Set the multicast filter in the init block. */ 1706 pcn_set_filter(sc); 1707 1708 /* Initialize CSR3. */ 1709 pcn_csr_write(sc, LE_CSR3, LE_C3_MISSM|LE_C3_IDONM|LE_C3_DXSUFLO); 1710 1711 /* Initialize CSR4. */ 1712 pcn_csr_write(sc, LE_CSR4, LE_C4_DMAPLUS|LE_C4_APAD_XMT| 1713 LE_C4_MFCOM|LE_C4_RCVCCOM|LE_C4_TXSTRTM); 1714 1715 /* Initialize CSR5. */ 1716 sc->sc_csr5 = LE_C5_LTINTEN|LE_C5_SINTE; 1717 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5); 1718 1719 /* 1720 * If we have an Am79c971 or greater, initialize CSR7. 1721 * 1722 * XXX Might be nice to use the MII auto-poll interrupt someday. 1723 */ 1724 switch (sc->sc_variant->pcv_chipid) { 1725 case PARTID_Am79c970: 1726 case PARTID_Am79c970A: 1727 /* Not available on these chips. */ 1728 break; 1729 1730 default: 1731 pcn_csr_write(sc, LE_CSR7, LE_C7_FASTSPNDE); 1732 break; 1733 } 1734 1735 /* 1736 * On the Am79c970A and greater, initialize BCR18 to 1737 * enable burst mode. 1738 * 1739 * Also enable the "no underflow" option on the Am79c971 and 1740 * higher, which prevents the chip from generating transmit 1741 * underflows, yet sill provides decent performance. Note if 1742 * chip is not connected to external SRAM, then we still have 1743 * to handle underflow errors (the NOUFLO bit is ignored in 1744 * that case). 1745 */ 1746 reg = pcn_bcr_read(sc, LE_BCR18); 1747 switch (sc->sc_variant->pcv_chipid) { 1748 case PARTID_Am79c970: 1749 break; 1750 1751 case PARTID_Am79c970A: 1752 reg |= LE_B18_BREADE|LE_B18_BWRITE; 1753 break; 1754 1755 default: 1756 reg |= LE_B18_BREADE|LE_B18_BWRITE|LE_B18_NOUFLO; 1757 break; 1758 } 1759 pcn_bcr_write(sc, LE_BCR18, reg); 1760 1761 /* 1762 * Initialize CSR80 (FIFO thresholds for Tx and Rx). 1763 */ 1764 pcn_csr_write(sc, LE_CSR80, LE_C80_RCVFW(sc->sc_rcvfw) | 1765 LE_C80_XMTSP(sc->sc_xmtsp) | LE_C80_XMTFW(sc->sc_xmtfw)); 1766 1767 /* 1768 * Send the init block to the chip, and wait for it 1769 * to be processed. 1770 */ 1771 PCN_CDINITSYNC(sc, BUS_DMASYNC_PREWRITE); 1772 pcn_csr_write(sc, LE_CSR1, PCN_CDINITADDR(sc) & 0xffff); 1773 pcn_csr_write(sc, LE_CSR2, (PCN_CDINITADDR(sc) >> 16) & 0xffff); 1774 pcn_csr_write(sc, LE_CSR0, LE_C0_INIT); 1775 delay(100); 1776 for (i = 0; i < 10000; i++) { 1777 if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON) 1778 break; 1779 delay(10); 1780 } 1781 PCN_CDINITSYNC(sc, BUS_DMASYNC_POSTWRITE); 1782 if (i == 10000) { 1783 printf("%s: timeout processing init block\n", 1784 sc->sc_dev.dv_xname); 1785 error = EIO; 1786 goto out; 1787 } 1788 1789 /* Set the media. */ 1790 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 1791 1792 /* Enable interrupts and external activity (and ACK IDON). */ 1793 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_STRT|LE_C0_IDON); 1794 1795 if (sc->sc_flags & PCN_F_HAS_MII) { 1796 /* Start the one second MII clock. */ 1797 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1798 } 1799 1800 /* ...all done! */ 1801 ifp->if_flags |= IFF_RUNNING; 1802 ifp->if_flags &= ~IFF_OACTIVE; 1803 1804 out: 1805 if (error) 1806 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1807 return (error); 1808 } 1809 1810 /* 1811 * pcn_rxdrain: 1812 * 1813 * Drain the receive queue. 1814 */ 1815 static void 1816 pcn_rxdrain(struct pcn_softc *sc) 1817 { 1818 struct pcn_rxsoft *rxs; 1819 int i; 1820 1821 for (i = 0; i < PCN_NRXDESC; i++) { 1822 rxs = &sc->sc_rxsoft[i]; 1823 if (rxs->rxs_mbuf != NULL) { 1824 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1825 m_freem(rxs->rxs_mbuf); 1826 rxs->rxs_mbuf = NULL; 1827 } 1828 } 1829 } 1830 1831 /* 1832 * pcn_stop: [ifnet interface function] 1833 * 1834 * Stop transmission on the interface. 1835 */ 1836 static void 1837 pcn_stop(struct ifnet *ifp, int disable) 1838 { 1839 struct pcn_softc *sc = ifp->if_softc; 1840 struct pcn_txsoft *txs; 1841 int i; 1842 1843 if (sc->sc_flags & PCN_F_HAS_MII) { 1844 /* Stop the one second clock. */ 1845 callout_stop(&sc->sc_tick_ch); 1846 1847 /* Down the MII. */ 1848 mii_down(&sc->sc_mii); 1849 } 1850 1851 /* Stop the chip. */ 1852 pcn_csr_write(sc, LE_CSR0, LE_C0_STOP); 1853 1854 /* Release any queued transmit buffers. */ 1855 for (i = 0; i < PCN_TXQUEUELEN; i++) { 1856 txs = &sc->sc_txsoft[i]; 1857 if (txs->txs_mbuf != NULL) { 1858 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1859 m_freem(txs->txs_mbuf); 1860 txs->txs_mbuf = NULL; 1861 } 1862 } 1863 1864 if (disable) 1865 pcn_rxdrain(sc); 1866 1867 /* Mark the interface as down and cancel the watchdog timer. */ 1868 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1869 ifp->if_timer = 0; 1870 } 1871 1872 /* 1873 * pcn_add_rxbuf: 1874 * 1875 * Add a receive buffer to the indicated descriptor. 1876 */ 1877 static int 1878 pcn_add_rxbuf(struct pcn_softc *sc, int idx) 1879 { 1880 struct pcn_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1881 struct mbuf *m; 1882 int error; 1883 1884 MGETHDR(m, M_DONTWAIT, MT_DATA); 1885 if (m == NULL) 1886 return (ENOBUFS); 1887 1888 MCLGET(m, M_DONTWAIT); 1889 if ((m->m_flags & M_EXT) == 0) { 1890 m_freem(m); 1891 return (ENOBUFS); 1892 } 1893 1894 if (rxs->rxs_mbuf != NULL) 1895 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1896 1897 rxs->rxs_mbuf = m; 1898 1899 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1900 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1901 BUS_DMA_READ|BUS_DMA_NOWAIT); 1902 if (error) { 1903 printf("%s: can't load rx DMA map %d, error = %d\n", 1904 sc->sc_dev.dv_xname, idx, error); 1905 panic("pcn_add_rxbuf"); 1906 } 1907 1908 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1909 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1910 1911 PCN_INIT_RXDESC(sc, idx); 1912 1913 return (0); 1914 } 1915 1916 /* 1917 * pcn_set_filter: 1918 * 1919 * Set up the receive filter. 1920 */ 1921 static void 1922 pcn_set_filter(struct pcn_softc *sc) 1923 { 1924 struct ethercom *ec = &sc->sc_ethercom; 1925 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1926 struct ether_multi *enm; 1927 struct ether_multistep step; 1928 uint32_t crc; 1929 1930 /* 1931 * Set up the multicast address filter by passing all multicast 1932 * addresses through a CRC generator, and then using the high 1933 * order 6 bits as an index into the 64-bit logical address 1934 * filter. The high order bits select the word, while the rest 1935 * of the bits select the bit within the word. 1936 */ 1937 1938 if (ifp->if_flags & IFF_PROMISC) 1939 goto allmulti; 1940 1941 sc->sc_initblock.init_ladrf[0] = 1942 sc->sc_initblock.init_ladrf[1] = 1943 sc->sc_initblock.init_ladrf[2] = 1944 sc->sc_initblock.init_ladrf[3] = 0; 1945 1946 ETHER_FIRST_MULTI(step, ec, enm); 1947 while (enm != NULL) { 1948 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1949 /* 1950 * We must listen to a range of multicast addresses. 1951 * For now, just accept all multicasts, rather than 1952 * trying to set only those filter bits needed to match 1953 * the range. (At this time, the only use of address 1954 * ranges is for IP multicast routing, for which the 1955 * range is big enough to require all bits set.) 1956 */ 1957 goto allmulti; 1958 } 1959 1960 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1961 1962 /* Just want the 6 most significant bits. */ 1963 crc >>= 26; 1964 1965 /* Set the corresponding bit in the filter. */ 1966 sc->sc_initblock.init_ladrf[crc >> 4] |= 1967 htole16(1 << (crc & 0xf)); 1968 1969 ETHER_NEXT_MULTI(step, enm); 1970 } 1971 1972 ifp->if_flags &= ~IFF_ALLMULTI; 1973 return; 1974 1975 allmulti: 1976 ifp->if_flags |= IFF_ALLMULTI; 1977 sc->sc_initblock.init_ladrf[0] = 1978 sc->sc_initblock.init_ladrf[1] = 1979 sc->sc_initblock.init_ladrf[2] = 1980 sc->sc_initblock.init_ladrf[3] = 0xffff; 1981 } 1982 1983 /* 1984 * pcn_79c970_mediainit: 1985 * 1986 * Initialize media for the Am79c970. 1987 */ 1988 static void 1989 pcn_79c970_mediainit(struct pcn_softc *sc) 1990 { 1991 const char *sep = ""; 1992 1993 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, pcn_79c970_mediachange, 1994 pcn_79c970_mediastatus); 1995 1996 #define ADD(str, m, d) \ 1997 do { \ 1998 printf("%s%s", sep, str); \ 1999 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(m), (d), NULL); \ 2000 sep = ", "; \ 2001 } while (/*CONSTCOND*/0) 2002 2003 printf("%s: ", sc->sc_dev.dv_xname); 2004 ADD("10base5", IFM_10_5, PORTSEL_AUI); 2005 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2006 ADD("10base5-FDX", IFM_10_5|IFM_FDX, PORTSEL_AUI); 2007 ADD("10baseT", IFM_10_T, PORTSEL_10T); 2008 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2009 ADD("10baseT-FDX", IFM_10_T|IFM_FDX, PORTSEL_10T); 2010 ADD("auto", IFM_AUTO, 0); 2011 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2012 ADD("auto-FDX", IFM_AUTO|IFM_FDX, 0); 2013 printf("\n"); 2014 2015 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2016 } 2017 2018 /* 2019 * pcn_79c970_mediastatus: [ifmedia interface function] 2020 * 2021 * Get the current interface media status (Am79c970 version). 2022 */ 2023 static void 2024 pcn_79c970_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2025 { 2026 struct pcn_softc *sc = ifp->if_softc; 2027 2028 /* 2029 * The currently selected media is always the active media. 2030 * Note: We have no way to determine what media the AUTO 2031 * process picked. 2032 */ 2033 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_media; 2034 } 2035 2036 /* 2037 * pcn_79c970_mediachange: [ifmedia interface function] 2038 * 2039 * Set hardware to newly-selected media (Am79c970 version). 2040 */ 2041 static int 2042 pcn_79c970_mediachange(struct ifnet *ifp) 2043 { 2044 struct pcn_softc *sc = ifp->if_softc; 2045 uint32_t reg; 2046 2047 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_AUTO) { 2048 /* 2049 * CSR15:PORTSEL doesn't matter. Just set BCR2:ASEL. 2050 */ 2051 reg = pcn_bcr_read(sc, LE_BCR2); 2052 reg |= LE_B2_ASEL; 2053 pcn_bcr_write(sc, LE_BCR2, reg); 2054 } else { 2055 /* 2056 * Clear BCR2:ASEL and set the new CSR15:PORTSEL value. 2057 */ 2058 reg = pcn_bcr_read(sc, LE_BCR2); 2059 reg &= ~LE_B2_ASEL; 2060 pcn_bcr_write(sc, LE_BCR2, reg); 2061 2062 reg = pcn_csr_read(sc, LE_CSR15); 2063 reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) | 2064 LE_C15_PORTSEL(sc->sc_mii.mii_media.ifm_cur->ifm_data); 2065 pcn_csr_write(sc, LE_CSR15, reg); 2066 } 2067 2068 if ((sc->sc_mii.mii_media.ifm_media & IFM_FDX) != 0) { 2069 reg = LE_B9_FDEN; 2070 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_10_5) 2071 reg |= LE_B9_AUIFD; 2072 pcn_bcr_write(sc, LE_BCR9, reg); 2073 } else 2074 pcn_bcr_write(sc, LE_BCR9, 0); 2075 2076 return (0); 2077 } 2078 2079 /* 2080 * pcn_79c971_mediainit: 2081 * 2082 * Initialize media for the Am79c971. 2083 */ 2084 static void 2085 pcn_79c971_mediainit(struct pcn_softc *sc) 2086 { 2087 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2088 2089 /* We have MII. */ 2090 sc->sc_flags |= PCN_F_HAS_MII; 2091 2092 /* 2093 * The built-in 10BASE-T interface is mapped to the MII 2094 * on the PCNet-FAST. Unfortunately, there's no EEPROM 2095 * word that tells us which PHY to use. 2096 * This driver used to ignore all but the first PHY to 2097 * answer, but this code was removed to support multiple 2098 * external PHYs. As the default instance will be the first 2099 * one to answer, no harm is done by letting the possibly 2100 * non-connected internal PHY show up. 2101 */ 2102 2103 /* Initialize our media structures and probe the MII. */ 2104 sc->sc_mii.mii_ifp = ifp; 2105 sc->sc_mii.mii_readreg = pcn_mii_readreg; 2106 sc->sc_mii.mii_writereg = pcn_mii_writereg; 2107 sc->sc_mii.mii_statchg = pcn_mii_statchg; 2108 ifmedia_init(&sc->sc_mii.mii_media, 0, pcn_79c971_mediachange, 2109 pcn_79c971_mediastatus); 2110 2111 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 2112 MII_OFFSET_ANY, 0); 2113 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 2114 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 2115 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 2116 } else 2117 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2118 } 2119 2120 /* 2121 * pcn_79c971_mediastatus: [ifmedia interface function] 2122 * 2123 * Get the current interface media status (Am79c971 version). 2124 */ 2125 static void 2126 pcn_79c971_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2127 { 2128 struct pcn_softc *sc = ifp->if_softc; 2129 2130 mii_pollstat(&sc->sc_mii); 2131 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2132 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2133 } 2134 2135 /* 2136 * pcn_79c971_mediachange: [ifmedia interface function] 2137 * 2138 * Set hardware to newly-selected media (Am79c971 version). 2139 */ 2140 static int 2141 pcn_79c971_mediachange(struct ifnet *ifp) 2142 { 2143 struct pcn_softc *sc = ifp->if_softc; 2144 2145 if (ifp->if_flags & IFF_UP) 2146 mii_mediachg(&sc->sc_mii); 2147 return (0); 2148 } 2149 2150 /* 2151 * pcn_mii_readreg: [mii interface function] 2152 * 2153 * Read a PHY register on the MII. 2154 */ 2155 static int 2156 pcn_mii_readreg(struct device *self, int phy, int reg) 2157 { 2158 struct pcn_softc *sc = (void *) self; 2159 uint32_t rv; 2160 2161 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2162 rv = pcn_bcr_read(sc, LE_BCR34) & LE_B34_MIIMD; 2163 if (rv == 0xffff) 2164 return (0); 2165 2166 return (rv); 2167 } 2168 2169 /* 2170 * pcn_mii_writereg: [mii interface function] 2171 * 2172 * Write a PHY register on the MII. 2173 */ 2174 static void 2175 pcn_mii_writereg(struct device *self, int phy, int reg, int val) 2176 { 2177 struct pcn_softc *sc = (void *) self; 2178 2179 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2180 pcn_bcr_write(sc, LE_BCR34, val); 2181 } 2182 2183 /* 2184 * pcn_mii_statchg: [mii interface function] 2185 * 2186 * Callback from MII layer when media changes. 2187 */ 2188 static void 2189 pcn_mii_statchg(struct device *self) 2190 { 2191 struct pcn_softc *sc = (void *) self; 2192 2193 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2194 pcn_bcr_write(sc, LE_BCR9, LE_B9_FDEN); 2195 else 2196 pcn_bcr_write(sc, LE_BCR9, 0); 2197 } 2198
Indexes created Fri Sep 26 20:09:58 GMT 2025